CY7C168A-25 [CYPRESS]
4Kx4 RAM; 4Kx4 RAM
| 型号： | CY7C168A-25 |
| 厂家： | 
CYPRESS |
| 描述： | 4Kx4 RAM |
| 文件： | 总9页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C168A
4Kx4 RAM
Features
Functional Description
The CY7C168A is a high-performance CMOS static RAM or-
ganized as 4096 by 4 bits. Easy memory expansion is provided
by an active LOW Chip Enable (CE) and three-state drivers.
The CY7C168A has an automatic power-down feature, reduc-
ing the power consumption by 77% when deselected.
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— t = 15 ns
AA
• Low active power
— 633 mW
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
four data input/output pins (I/O through I/O ) is written into the
0
3
• Low standby power
— 110 mW
memory location specified on the address pins (A through
0
A
).
11
• TTL-compatible inputs and outputs
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the location specified on the
address pins will appear on the four data input/output pins
• V of 2.2V
IH
• Capable ofwithstanding greaterthan 2001V electrostat-
ic discharge
(I/O through I/O ).
0
3
The input/output pins remain in a high-impedance state when
Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
V
A
20
19
18
17
16
A
1
2
3
4
4
5
CC
3
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
2
6
7
8
9
1
0
5
7C168A
\
INPUTBUFFER
15
14
13
12
11
6
0
1
2
3
7
A
10
A
A
1
0
8
A
11
CE
I/O
0
9
A
2
I/O
1
10
128 x 128
ARRAY
WE
GND
C168A-2
A
3
A
4
I/O
2
A
A
6
5
I/O
3
CE
POWER
DOWN
COLUMN
DECODER
(7C168A)
WE
A
7
A
8
A A
A
10 11
9
C168A-1
Selection Guide
7C168A-15
7C168A-20
7C168A-25
7C168A-35
7C168A-45
Maximum Access Time (ns)
15
115
-
20
90
25
90
35
90
45
90
Maximum Operating
Current (mA)
Commercial
Military
100
100
100
100
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 3, 2000
CY7C168A
Output Current into Outputs (Low) .............................. 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential
(Pin 20 to Pin 10)................................................ −0.5V to +7.0V
Range
Temperature
V
CC
Commercial
0°C to +70°C
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State.................................................... −0.5V to +7.0V
[1]
Military
−55°C to +125°C
DC Input Voltage .................................................−3.0V to +7.0V
[2]
Electrical Characteristics Over the Operating Range
7C168A-15
7C168A-20
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
V
V
2.4
2.4
OH
CC
CC
OH
V
= Min., I = 8.0 mA
0.4
0.4
V
OL
OL
V
2.2
−0.5
−10
−10
V
2.2
−0.5
−10
−10
V
V
IH
IL
CC
CC
[3]
V
Input LOW Voltage
0.8
+10
+10
0.8
V
I
I
Input Load Current
GND < V < V
CC
+10
+10
µA
µA
IX
I
Output Leakage
Current
GND < V < V
,
OZ
OS
CC
O
CC
Output Disabled
I
I
Output Short
Circuit Current
V
= Max., V
= GND
−350
−350
mA
mA
CC
OUT
[4]
V
Operating
V
I
= Max.,
Com’l
Mil
115
-
90
100
40
CC
CC
Supply Current
= 0 mA
OUT
I
I
Automatic CE
Power-Down Current
Max. V
CE > V
,
CC
Com’l
Mil
40
-
mA
mA
SB1
SB2
IH
40
Automatic CE
Power-Down Current
Max. V
CE > V − 0.3V
,
Com’l
Mil
20
-
20
CC
CC
20
Notes:
1. A is the “instant on” case temperature.
T
2. See the last page of this specification for Group A subgroup testing information.
3. VIL min. = −3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C168A
[2]
Electrical Characteristics Over the Operating Range (continued)
7C168A-25
7C168A-35
7C168A-45
Parameter
Description
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min.
Max.
Min.
Max. Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
2.4
2.4
2.4
V
OH
CC
CC
OH
V
= Min., I = 8.0 mA
0.4
0.4
0.4
V
V
OL
OL
V
V
2.2
−0.5
−10
−10
V
2.2
−0.5
−10
−50
V
2.2
−0.5
−10
−50
V
CC
IH
IL
CC
CC
[3]
Input LOW Voltage
0.8
+10
+10
0.8
10
50
0.8
V
I
I
Input Load Current
GND < V < V
CC
10
50
µA
µA
IX
I
Output Leakage
Current
GND < V < V
O CC
Output Disabled
OZ
OS
CC
I
I
Output Short
Circuit Current
V
= Max., V = GND
OUT
−350
−350
−350
mA
mA
CC
[4]
V
Operating
Supply Current
V
I
= Max.,
Com’l
90
100
20
90
100
20
90
100
20
CC
CC
= 0 mA
OUT
Mil
I
I
Automatic CE
Power-Down Current
Max. V
CE > V
,
Com’l
Mil
mA
mA
SB1
CC
IH
20
20
20
Automatic CE
Power-Down Current
Max. V
CE > VCC − 0.3 V
,
Com’l
Mil
20
20
20
SB2
CC
20
20
20
Capacitance[5]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
10
Unit
C
C
Input Capacitance
Output Capacitance
pF
pF
IN
A
V
= 5.0V
CC
10
OUT
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481
R1 481
Ω
Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
R2
255
R2
255
10%
30 pF
5 pF
Ω
Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C168A-4
C168A-3
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
3
CY7C168A
[2,6]
Switching Characteristics Over the Operating Range
7C168A-15 7C168A-20 7C168A-25 7C168A-35 7C168A-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
15
5
20
5
25
5
35
5
45
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
15
15
8
20
20
8
25
25
10
20
35
35
15
20
45
45
15
25
AA
Output Hold from Address Change
Power Supply Current
OHA
ACE
LZCE
HZCE
PU
[7]
CE LOW to Low Z
5
5
5
5
5
[7, 8]
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power-Down
Read Command Set-Up
0
0
0
0
0
15
20
PD
0
0
0
0
0
0
0
0
0
0
RCS
RCH
Read Command Hold
[9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
0
20
15
15
0
20
20
20
0
25
25
25
0
40
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
0
0
SA
12
10
0
15
10
0
15
10
0
20
15
0
20
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7]
WE HIGH to Low Z
7
7
7
5
5
LZWE
HZWE
[7, 8]
WE LOW to High Z
5
5
5
5
10
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C168A-5
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
I
7. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady state voltage with specified loading in part
(b) of AC Test Loads and Waveforms.
8. tHZCE and tHZWE are tested with CL = 5 pF as in part (a) of Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. Both signal must be LOW to initiate a write and either signal can terminate a
write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = V .
IL
4
CY7C168A
Switching Waveforms (continued)
[10, 12]
Read Cycle
t
RC
CE
t
ACE
t
LZCE
t
HZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PD
t
PU
ICC
ISB
V
CC
50%
SUPPLY
50%
CURRENT
WE
t
RCH
t
RCS
C168A-6
[9]
Write CycleNo. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
[9, 13]
C168A-7
Write Cycle No. 2 (CS Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
IN
t
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
DATA I/O
Notes:
C168A-8
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
5
CY7C168A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
I
CC
1.0
0.8
I
CC
1.0
0.8
0.6
V
= 5.0V
V
= 5.0V
IN
CC
0.6
0.4
60
T = 25°C
A
T = 25°C
A
40
V
V
IN
= 5.0V
= 5.0V
CC
0.4
0.2
0.0
20
0
0.2
0.0
I
SB
I
SB
55
25
125
0.0
1.0
2.0
3.0
4.0
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
40
T = 25°C
A
V
= 5.0V
CC
T = 25°C
A
V
CC
= 5.0V
0.8
0.6
20
0
0.9
0.8
0.0
1.0
2.0
3.0
4.0
55
25
125
−
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs.CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.1
1.0
0.9
0.8
1.0
0.5
10.0
5.0
V
= 4.5V
CC
T = 25°C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
6
CY7C168A
Ordering Information
Speed
(ns)
I
Package
Name
Operating
Range
CC
(mA)
Ordering Code
Package Type
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
15
115 CY7C168A-15PC
CY7C168A-15VC
P5
V5
P5
V5
D6
P5
V5
D6
P5
V5
D6
P5
V5
D6
Commercial
20
90
CY7C168A-20PC
CY7C168A-20VC
CY7C168A-20DMB
CY7C168A-25PC
CY7C168A-25VC
CY7C168A-25DMB
CY7C168A-35PC
CY7C168A-35VC
CY7C168A-35DMB
CY7C168A-45PC
CY7C168A-45VC
CY7C168A-45DMB
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Commercial
20-Lead (300-Mil) CerDIP
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Military
25
35
45
70
Commercial
80
70
20-Lead (300-Mil) CerDIP
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Military
Commercial
20-Lead (300-Mil) CerDIP
20-Lead (300-Mil) Molded DIP
20-Lead Molded SOJ
Military
70
Commercial
20-Lead (300-Mil) CerDIP
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
Parameter
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
READ CYCLE
V
OH
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
RC
V
OL
AA
V
IH
OHA
ACE
RCS
RCH
V Max.
IL
I
I
I
I
I
IX
OZ
CC
SB1
SB2
WRITE CYCLE
t
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
SCE
AW
HA
Document #: 38-00095-E
SA
PWE
SD
HD
7
CY7C168A
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D-8 Config. A
51-80029
20-Lead (300-Mil) Molded DIP P5
51-85011-A
8
CY7C168A
Package Diagrams (continued)
20-Lead (300-Mil) Molded SOJ V5
51-85029-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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