CY7C182-35VC [CYPRESS]
8Kx9 Static RAM; 8Kx9静态RAM
| 型号： | CY7C182-35VC |
| 厂家： | 
CYPRESS |
| 描述： | 8Kx9 Static RAM |
| 文件： | 总6页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C182
8Kx9 Static RAM
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
Features
• High speed
— t = 25 ns
AA
• x9 organization is ideal for cache memory applications
• CMOS for optimum speed/power
• Low active power
an active-LOW Chip Enable (CE ), an active HIGH Chip En-
1
able (CE ), an active-LOW Output Enable (OE), and three-
2
state drivers.
— 770 mW
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE in-
puts are both LOW, data on the nine data input/output pins
• Low standby power
1
— 195 mW
(I/O through I/O ) is written into the memory location ad-
0
8
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CE , CE , OE options
dressed by the address present on the address pins (A
0
through A ). Reading the device is accomplished by selecting
12
the device and enabling the outputs, (CE and OE active LOW
1
1
2
and CE active HIGH), while (WE) remains inactive or HIGH.
2
Functional Description
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
DIP/SOJ
Top View
A
A
A
A
A
A
V
CC
4
5
6
7
8
9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
CE
2
I/O
0
3
2
INPUT BUFFER
A
3
4
I/O
1
A
2
5
A
1
6
I/O
2
A
1
A
OE
10
7
A
2
A
A
A
0
11
12
8
I/O
3
A
3
CE
I/O
I/O
I/O
I/O
I/O
9
1
8
7
6
5
4
A
256 x 32 x 9
ARRAY
4
I/O
I/O
I/O
I/O
10
11
12
13
14
0
1
2
3
A
5
I/O
4
A
6
A
7
I/O
5
A
8
GND
I/O
6
C182–2
POWER
DOWN
CE
I/O
7
1
COLUMN
DECODER
CE
2
WE
I/O
8
OE
C182–1
Selection Guide
7C182-25
7C182-35
7C182-45
Maximum Access Time (ns)
25
140
35
35
140
35
45
140
35
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 4, 1999
CY7C182
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015.2)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
Ambient
Temperature
[1]
Supply Voltage to Ground Potential ..............−0.5V to +7.0V
Range
V
CC
DC Voltage Applied to Outputs
in High Z State .................................................−0.5V to +7.0V
Commercial
0°C to + 70°C
5V ± 10%
[1]
[1]
DC Input Voltage ..............................................−0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C182-25, 35, 45
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Max.
Unit
V
V
V
Min., I = −4.0 mA.
OH
2.4
V
V
OH
CC
CC
V
Min., I = 8.0 mA
0.4
OL
OL
V
2.2
−0.5
−10
V
V
IH
IL
CC
[1]
V
Input LOW Voltage
0.8
V
I
Input Load Current
GND < V < V ,
CC
+10
µA
IX
IN
GND < V
< V
,
OUT
CC
Output Disabled
I
I
Output Leakage Current
Output Short Circuit
Current
V
V
= Max., V
= Max., V
= GND
−10
+10
µA
OZ
CC
CC
OUT
OUT
= GND
−300
mA
OS
[2]
I
V
Operating Circuit
V
Max., Output Current = 0 mA,
140
35
mA
mA
mA
CC
CC
CC
Current
f = Max., V = V or GND
IN CC
Automatic Power-Down
Current — TTL Inputs
Max V , CE > V , CE < V ,
CC 1 IH 2
V
IL
> V or V < V , f = f
IN IH IN IL MAX
Automatic Power-Down
Max V , CE > V − 0.3V, CE < 0.3V,
20
CC
1
CC
2
Current — CMOS Inputs
V
> V − 0.3V or V < 0.3V, f = 0
IN
CC
IN
Capacitance[3]
Parameter
Description
Output Capacitance
Input Capacitance
Test Conditions
Max.
10
Unit
pF
C
T = 25°C, f = 1 MHz,
A
OUT
V
= 5.0V
CC
C
10
pF
IN
Note:
1.
V
IL (min.) = −3.0V for pulse durations of less than 20 ns.
2. Duration of the short circuit should not exceed 30 seconds. Not more than one output should be shorted at one time.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481
R1 481
Ω
Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
90%
10%
10%
R2
255
R2
255
30pF
5 pF
Ω
Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C182–3
C182–4
(a)
(b)
Equivalentto:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
2
CY7C182
Switching Characteristics Over the Operating Range
7C182-25
Min. Max.
7C182-35
Min. Max.
7C182-45
Min. Max.
Parameter
Description
Unit
[4]
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
25
3
35
3
45
3
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
25
35
45
AA
Data Hold from Address Change
OHA
ACE1
ACE2
LZCE1
LZCE2
HZCE1
HZCE2
PU
CE Access Time
25
25
35
35
45
45
1
CE Access Time
2
CE LOW to Low Z
5
5
5
5
5
5
1
CE HIGH to Low Z
2
[5]
CE HIGH to High Z
18
18
20
20
25
25
1
[5]
CE LOW to High Z
2
CE LOW to Power-Up
0
3
0
3
0
3
ns
ns
ns
ns
ns
1
CE HIGH to Power-Down
20
18
20
20
25
20
PD
1
OE Access Time
OE LOW to Low Z
DOE
LZOE
HZOE
[5]
OE HIGH to High Z
18
20
25
[6]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
25
0
35
0
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Address Set-Up Time
Address Valid to End of Write
Data Set-Up Time
SA
20
15
20
20
20
0
30
20
30
30
25
0
40
25
40
40
30
0
AW
SD
CE LOW to Write End
SCE1
SCE2
PWE
HA
1
CE HIGH to Write End
2
WE Pulse Width
Address Hold from End of Write
Data Hold Time
0
0
0
HD
[7]
Write HIGH to Low Z
3
3
3
LZWE
HZWE
[5, 7, 8]
Write LOW to High Z
13
15
20
Notes:
4. WE is HIGH for read cycle.
5. tHZCE and tHZWE are specified with CL = 5 pF. Transition is measured ± 500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write
and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
7. At any given temperature and voltage condition, tLZWE is less than tHZWE for any given device. These parameters are sampled and not 100% tested.
8. Address valid prior to or coincident with CE transition LOW and CE2 transition HIGH.
3
CY7C182
Switching Waveforms
[4, 9]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C182–5
[4, 10]
Read Cycle No. 2
t
RC
CE
1
t
t
CE
ACE1
ACE2
2
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
V
CC
SUPPLY
CURRENT
50%
50%
ISB
C182–6
[6]
Write Cycle No.1 (WE Controlled)
t
WC
ADDRESS
t
t
SCE1
SCE2
CS
1
CS
2
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA I/O
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
C182–7
Notes:
9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
10. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
4
CY7C182
Switching Waveforms (continued)
[6, 10]
Write Cycle No.2 (CE Controlled)
t
WC
ADDRESS
CE
1
t
SCE1
t
SA
t
SCE2
CE
2
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C182–8
Truth Table
CE
H
L
CE
X
OE
X
WE
X
Data In
Data Out
Mode
Deselect/Power-Down
Read
1
2
Z
Z
Z
Valid
Z
H
L
H
L
H
X
L
Valid
Z
Write
L
H
H
X
H
Z
Output Disable
Deselect
X
L
X
Z
Z
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
25
CY7C182−25PC
CY7C182−25VC
CY7C182−35PC
CY7C182−35VC
CY7C182−45PC
CY7C182−45VC
P21
V21
P21
V21
P21
V21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
Commercial
Commercial
35
45
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Document #: 38-00110-F
5
CY7C182
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-B
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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