CY7C186-25PC [CYPRESS]
8Kx8 Static RAM; 8Kx8静态RAM
| 型号： | CY7C186-25PC |
| 厂家： | 
CYPRESS |
| 描述： | 8Kx8 Static RAM |
| 文件： | 总9页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
86
CY7C186
8Kx8 Static RAM
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. The device has an automatic power-down
feature (CE1), reducing the power consumption by over 80%
when deselected. The CY7C186 is in a 600-mil-wide PDIP
package and a 32-pin TSOP (std. pinout).
Features
• High speed
— 20 ns
• Low active power
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE1 and WE in-
puts are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
— 605 mW
• Low standby power
— 110 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE
features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C186 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Pin Configuration
LogicBlock Diagram
DIP
Top View
V
CC
WE
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
4
2
A5
A6
A7
3
CE2
I/O
A3
4
0
A2
5
INPUT BUFFER
A
A1
8
6
I/O
1
A9
OE
7
A0
A
10
8
A
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A
11
9
I/O
1
2
A
12
I/O0
I/O
10
11
12
13
14
A
2
A
I/O
3
3
A
256 x 32 x 8
ARRAY
I/O12
4
A
GND
5
I/O
A
4
6
A
7
I/O
A
5
8
I/O
6
POWER
DOWN
CE
CE
1
2
I/O
COLUMN DECODER
7
WE
OE
Selection Guide[1]
7C186-20
20
7C186-25
25
7C186-35
35
Maximum Access Time (ns)
Maximum Operating Current (mA)
110
100
100
Maximum Standby Current (mA)
20/15
20/15
20/15
Notes:
1. For military specifications, see the CY7C186A datasheet.
Cypress Semiconductor Corporation
Document #: 38-05280 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised March 22, 2002
CY7C186
Pin Configurations (continued)
TSOP
Top View
A
CE
I/O
OE
32
21
30
0
1
A
1
2
3
A
2
7
6
5
4
A
I/O
3
4
5
29
28
CE
I/O
2
I/O
WE
27
26
25
6
7
V
I/O
CC
3
NC
NC
8
NC
NC
24
9
NC
GND
10
11
12
23
22
A
I/O
4
5
6
7
8
9
2
1
0
A
I/O
21
20
A
13
14
15
16
I/O
A
A
19
18
17
12
A
A
11
A
A
10
C186-3
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Latch-Up Current.................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Ambient
Temperature
DC Voltage Applied to Outputs
Range
VCC
in High Z State[2]............................................ –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage[2] ........................................ –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C186-20
7C186-25,35
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
Test Conditions
Min. Max.
Min.
Max.
Unit
VCC = Min., IOH = –4.0 mA
2.4
0.4
2.4
V
V
VOL
VIH
VIL
IIX
VCC = Min., IOL = 8.0 mA
0.4
VCC
0.8
2.2
–0.5
–5
VCC
0.8
2.2
–0.5
–5
V
V
GND < VI < VCC
+5
+5
µA
µA
mA
IOZ
IOS
Output Leakage Current GND < VI < VCC, Output Disabled
–5
+5
–5
+5
Output Short
VCC = Max.,
VOUT = GND
–300
–300
Circuit Current[3]
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA
110
20
100
20
mA
mA
mA
ISB1
ISB2
Automatic CE1
Power-Down Current
Max. VCC, CE1 > VIH,
Min. Duty Cycle=100%
Automatic CE1
Power-Down Current
Max. VCC, CE1 > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
15
15
Capacitance[4]
Parameter
CIN
Description
Test Conditions
Max.
Unit
pF
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
7
7
COUT
pF
Notes:
2. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05280 Rev. **
Page 2 of 9
CY7C186
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
OUTPUT
5V
OUTPUT
ALL INPUT PULSES
3.0V
GND
90%
10%
90%
30 pF
5 pF
R2
255Ω
R2
255Ω
10%
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
≤ 5 ns
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[5]
7C186-20
7C186-25
7C186-35
Min. Max.
Parameter
READ CYCLE
tRC
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
20
5
25
5
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6]
CE1 LOW to Low Z[7]
CE2 HIGH to Low Z
20
25
35
tOHA
tACE1
20
20
9
25
25
12
35
35
15
tACE2
tDOE
tLZOE
3
3
3
tHZOE
8
10
10
tLZCE1
tLZCE2
tHZCE
5
3
5
3
5
3
CE1 HIGH to High Z[6, 7]
CE2 LOW to High Z
8
10
20
10
20
tPU
CE1 LOW to Power-Up
0
0
0
ns
ns
tPD
CE1 HIGH to Power-Down
20
WRITE CYCLE[8]
tWC
Write Cycle Time
20
15
15
15
0
25
20
20
20
0
35
20
20
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE1
tSCE2
tAW
CE1 LOW to Write End
CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
15
10
0
15
10
0
20
12
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[6]
tHD
tHZWE
7
7
8
tLZWE
WE HIGH to Low Z
5
5
5
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
6. tHZOE, HZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
I
t
7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All signals must be active to initiate a write, and any
signal can terminate a write by going inactive. The data input set-up and hold timing should be referenced to the trailing edge of the signal that terminates the
write.
Document #: 38-05280 Rev. **
Page 3 of 9
CY7C186
Switching Waveforms
Read Cycle No. 1[9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[10, 11]
t
CE
RC
1
CE
t
t
2
ACE
OE
t
t
HZOE
DOE
t
HZCE
HIGH
LZOE
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
ISB
V
CC
50%
50%
SUPPLY
CURRENT
Write Cycle No. 1 (WE Controlled)[11, 12]
t
WC
ADDRESS
t
CE
SCEI
1
t
t
HA
AW
t
CE
2
SCE2
t
t
PWE
SA
WE
OE
t
t
HD
SD
DATA VALID
DATA I/O
NOTE 13
IN
t
HZOE
Notes:
9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL
.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05280 Rev. **
Page 4 of 9
CY7C186
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[11,12,14]
t
WC
ADDRESS
t
t
CE
SCE1
1
t
SA
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 14]
t
WC
ADDRESS
t
CE
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
t
WE
PWE
t
t
SD
HD
DATA I/O
NOTE 13
DATA VALID
IN
t
t
LZWE
HZWE
Notes:
14. If CE1 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05280 Rev. **
Page 5 of 9
CY7C186
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
0.8
1.2
I
I
CC
CC
1.0
0.8
0.6
0.4
V
CC
=5.0V
0.6
0.4
60
T =25°C
A
40
V
V
IN
=5.0V
=5.0V
CC
0.2
0.0
20
0
I
SB
0.2
0.0
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLYVOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
= 5.0V
1.2
1.0
T = 25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLYVOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
CC
=0.5V
1.0
0.5
0.0
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLYVOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05280 Rev. **
Page 6 of 9
CY7C186
Truth Table
CE1 CE2 WE OE Input/Output
Mode
Deselect/Power-Down
Deselect
H
X
L
L
L
X
L
X
X
H
L
X
X
L
High Z
High Z
Data Out
Data In
High Z
H
H
H
Read
X
H
Write
H
Deselect
Address Designators
Address
Name
Address
Function
DIP Pin
Number
TSOP Pin
Number
A4
A5
X3
X4
X5
X6
X7
Y1
Y4
Y3
Y0
Y2
X0
X1
X2
2
3
11
12
13
14
15
16
17
18
19
32
2
A6
4
A7
5
A8
6
A9
7
A10
A11
A12
A0
8
9
10
21
23
24
25
A1
A2
3
A3
4
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C186-20PC
CY7C186-20ZC
CY7C186-25PC
CY7C186-35PC
Name
Package Type
20
P15
28-Lead (600-Mil) Molded DIP
32-Lead Thin Small Outline Package
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
Commercial
Z32
25
35
P15
Commercial
Commercial
P15
Document #: 38-05280 Rev. **
Page 7 of 9
CY7C186
Package Diagrams
28-Lead (600-Mil) Molded DIP P15
51-85017-A
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
51-85056-*D
Document #: 38-05280 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C186
Document Title: CY7C186 8Kx8 Static RAM
Document Number: 38-05280
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
114447
3/26/02
DSG
Change from Spec number: 38-00240 to 38-05280
Document #: 38-05280 Rev. **
Page 9 of 9
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