CY7C199-10ZC [CYPRESS]
32K x 8 Static RAM; 32K x 8静态RAM
| 型号： | CY7C199-10ZC |
| 厂家： | 
CYPRESS |
| 描述： | 32K x 8 Static RAM |
| 文件： | 总13页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C199
32K x 8 Static RAM
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
Features
• High speed
— 10 ns
• Fast tDOE
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
LCC
Top View
Top View
A
A
V
CC
28
27
26
1
2
3
4
5
6
5
WE
6
3
2 1 2827
26
A
A
A
4
7
4
A
4
A
8
8
A
3
25
24
5
6
7
8
25
24
23
22
21
20
19
18
A
A
9
3
A
9
A
2
A
1
A
A
10
11
12
13
14
2
A
10
A
11
23
22
A
A
A
A
A
1
OE
7
OE
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
I/O
I/O
I/O
A
21
20
19
18
17
16
15
A
12
13
14
0
0
1
2
3
4
5
6
8
9
10
11
12
13
0
10
11
12
CE
I/O
I/O
INPUT BUFFER
CE
I/O
I/O
I/O
I/O
I/O
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617
A
1
A
2
I/O
I/O
A
GND
3
14
3
A
4
1024 x 32 x 8
ARRAY
22
A
OE
A
5
21
A
0
A
23
24
1
6
A
20
CE
I/O
I/O
A
A
A
7
A
2
3
4
19
18
17
16
7
6
8
A
25
26
27
28
1
9
I/O
I/O
I/O
GND
I/O
5
4
3
TSOP I
Top View
(not to scale)
WE
V
CC
A
15
14
13
CE
WE
5
6
7
POWER
DOWN
COLUMN
DECODER
A
A
A
2
3
2
12
11
I/O
I/O
A
1
0
14
I/O
4
5
7
8
9
OE
A
10
9
A
6
7
10
A
A
13
12
A
11
8
Selection Guide
7C199 7C199
7C199 7C199 7C199 7C199 7C199 7C199
-8
-10
10
-12
12
-15
15
-20
20
-25
25
-35
35
-45
45
Unit
ns
Maximum Access Time
8
Maximum Operating Current
120
110
90
0.5
0.05
160
90
10
155
90
10
150
90
10
150
80
10
140
70
10
140
mA
L
L
Maximum CMOS Standby Current
0.5
10
mA
0.05
0.05
0.05
0.05
0.05
Shaded area contains advance information.
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 7, 2003
CY7C199
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Range
Commercial
Industrial
Military
Ambient Temperature[2]
VCC
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
–40°C to +85°C
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
–55°C to +125°C
Electrical Characteristics Over the Operating Range (-8, -10, -12, -15)[3]
7C199-8
7C199-10
7C199-12
7C199-15
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH=–4.0 mA
VCC = Min., IOL=8.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.4
2.4
2.4
2.4
V
V
V
VOL
0.4
2.2 VCC 2.2 VCC 2.2 VCC 2.2 VCC
+0.3V +0.3V +0.3V +0.3V
–0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8
0.4
0.4
0.4
VIH
VIL
IIX
Input LOW Voltage
Input Load Current
V
GND < VI < VCC
–5
–5
+5
+5
–5
–5
+5
+5
–5
–5
+5
+5
–5
–5
+5
+5
µA
µA
IOZ
Output Leakage Current GND < VO < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l
L
120
110
85
160
85
155 mA
100 mA
180 mA
Mil
ISB1
Automatic CE
Power-down Current— VIH, VIN > VIH or
TTL Inputs
Max. VCC, CE >
Com’l
L
5
5
5
30
5
30
5
mA
mA
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current— CE > VCC – 0.3V
CMOS Inputs
Max. VCC
,
Com’l
L
0.5
0.5
10
10
mA
0.05
0.05
0.05
0.05 mA
15 mA
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Mil
[3]
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45)
7C199-20 7C199-25 7C199-35
7C199-45
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VCC = Min., IOH = –4.0 mA 2.4
2.4
2.4
2.4
2.2
V
V
V
VOL
VCC = Min., IOL = 8.0 mA
0.4
2.2 VCC 2.2 VCC 2.2 VCC
+0.3V +0.3V +0.3V
–0.5 0.8 -0.5 0.8 -0.5 0.8
0.4
0.4
0.4
VIH
VCC
+0.3V
VIL
IIX
Input LOW Voltage
Input Load Current
-0.5
–5
0.8
+5
+5
V
GND < VI < VCC
–5
–5
+5
+5
–5
–5
+5
+5
–5
–5
+5
+5
µA
µA
IOZ
Output Leakage Current GND < VI < VCC, Output
Disabled
–5
ICC
VCC Operating Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l
L
150
90
150
80
140
70
140 mA
70 mA
Mil
170
150
150
150 mA
Shaded area contains advance information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Document #: 38-05160 Rev. *A
Page 2 of 13
CY7C199
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45) (continued)[3]
7C199-20 7C199-25 7C199-35
7C199-45
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
ISB1
Automatic CE
Power-down Current—
TTL Inputs
Max. VCC,CE> VIH, Com’l
30
5
30
5
25
5
25
5
mA
mA
VIN > VIHorVIN< VIL,
L
f = fMAX
ISB2
Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC
CE > VCC – 0.3V
IN > VCC – 0.3V or
,
Com’l
L
10
0.05
15
10
0.05
15
10
0.05
15
10
mA
0.05 µA
V
Mil
15
mA
VIN < 0.3V, f=0
Capacitance[4 ]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
8
COUT
pF
AC Test Loads and Waveforms[5]
R1 481Ω
R1 481Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
R2
255 Ω
R2
255Ω
30 pF
5 pF
≤t
≤t
r
r
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167 Ω
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L-version only)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions[6]
Min.
Max.
Unit
V
2.0
Com’l
VCC = VDR = 2.0V, CE > VCC
0.3V, VIN > VCC –0.3V or VIN
0.3V
–
<
µA
µA
ns
Com’l L
10
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[5]
tR
200
µs
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds
6. No input may exceed VCC + 0.5V.
Document #: 38-05160 Rev. *A
Page 3 of 13
CY7C199
[3, 7]
Switching Characteristics Over the Operating Range (-8, -10, -12, -15)
7C199-8
7C199-10
7C199-12
Min. Max.
7C199-15
Min. Max.
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
10
3
Max.
Unit
Read Cycle Time
8
3
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8,9]
CE LOW to Power-up
CE HIGH to Power-down
8
10
12
15
tOHA
tACE
8
10
5
12
5
15
7
tDOE
4.5
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
0
3
0
5
4
8
5
5
5
5
7
7
tPD
10
12
15
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
8
7
7
0
0
7
5
0
10
7
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
9
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9]
5
8
9
tHD
0
0
0
tHZWE
tLZWE
5
6
7
7
WE HIGH to Low-Z[8]
3
3
3
3
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20 7C199-25
Min. Max.
7C199-35
7C199-45
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
20
3
25
3
35
3
45
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
20
25
35
45
tOHA
tACE
20
9
25
10
35
16
45
16
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
tHZCE
tPU
9
9
11
11
15
15
15
15
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05160 Rev. *A
Page 4 of 13
CY7C199
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20 7C199-25
Min. Max. Min. Max.
20 20
7C199-35
Min. Max.
20
7C199-45
Min. Max.
25
Parameter
tPD
Description
Unit
CE HIGH to Power-down
ns
Write Cycle[10,11]
tWC
tSCE
tAW
Write Cycle Time
20
15
15
0
25
18
20
0
35
22
30
0
45
22
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
0
tPWE
tSD
15
10
0
18
10
0
22
15
0
22
15
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9]
tHD
tHZWE
tLZWE
10
11
15
15
WE HIGH to Low-Z[8]
3
3
3
3
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [13, 14]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05160 Rev. *A
Page 5 of 13
CY7C199
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
IN
DATA I/O
t
HZOE
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
t
t
LZWE
HZWE
Notes:
15. Data I/O is high impedance if OE = VIH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05160 Rev. *A
Page 6 of 13
CY7C199
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY
VOLTAGE
120
100
80
1.4
1.2
1.4
1.2
1.0
0.8
0.6
I
CC
I
CC
1.0
0.8
0.6
V
CC
=5.0V
60
T =25°C
A
V
IN
=5.0V
T =25°C
A
40
V
V
IN
=5.0V
=5.0V
0.4
CC
0.4
20
0
0.2
0.0
0.2
0.0
I
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICALPOWER-ON CURRENT
vs.SUPPLY VOLTAGE
TYPICAL ACCESS TIMECHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
IN
=0.5V
V
=4.5V
1.0
0.5
10.0
5.0
CC
T =25°C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High Z
)
L
L
X
Write
)
L
H
H
Deselect, Output disabled
)
Document #: 38-05160 Rev. *A
Page 7 of 13
CY7C199
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
28-Lead Molded SOJ
8
CY7C199-8VC
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
P21
V21
Z28
P21
V21
Z28
V21
Z28
V21
Z28
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
Commercial
Commercial
Industrial
CY7C199-8ZC
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
CY7C199L-8VC
CY7C199L-8ZC
CY7C199-10VC
CY7C199-10ZC
CY7C199L-10VC
CY7C199L-10ZC
CY7C199-10VI
CY7C199-10ZI
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
10
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
CY7C199L-10VI
CY7C199L-10ZI
CY7C199-12PC
CY7C199-12VC
CY7C199-12ZC
CY7C199L-12PC
CY7C199L-12VC
CY7C199L-12ZC
CY7C199-12VI
CY7C199-12ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
12
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
CY7C199L-12VI
CY7C199L-12ZI
CY7C199-15PC
CY7C199-15VC
CY7C199-15ZC
CY7C199L-15PC
CY7C199L-15VC
CY7C199L-15ZC
CY7C199-15VI
CY7C199-15ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
15
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199-15DMB
CY7C199-15LMB
CY7C199L-15DMB
CY7C199L-15LMB
CY7C199-20PC
CY7C199-20VC
CY7C199-20ZC
CY7C199L-20PC
CY7C199L-20VC
CY7C199L-20ZC
CY7C199-20VI
CY7C199-20ZI
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
20
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199-20DMB
CY7C199-20LMB
CY7C199L-20DMB
CY7C199L-20LMB
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains advance information. Contact your Cypress sales representative for availability
Document #: 38-05160 Rev. *A
Page 8 of 13
CY7C199
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C199-25PC
Package Type
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
25
P21
S21
V21
Z28
S21
V21
Z28
D22
L54
P21
S21
V21
Z28
S21
V21
Z28
D22
L54
D22
L54
Commercial
CY7C199-25SC
CY7C199-25VC
CY7C199-25ZC
CY7C199-25SI
CY7C199-25VI
CY7C199-25ZI
CY7C199-25DMB
CY7C199-25LMB
CY7C199-35PC
CY7C199-35SC
CY7C199-35VC
CY7C199-35ZC
CY7C199-35SI
CY7C199-35VI
CY7C199-35ZI
CY7C199-35DMB
CY7C199-35LMB
CY7C199-45DMB
CY7C199-45LMB
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOIC
Industrial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
35
Commercial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOIC
Industrial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Military
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
45
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains advance information. Contact your Cypress sales representative for availability
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
Parameter
Read Cycle
tRC
tAA
Subgroups
VOH
VOL
VIH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
VIL Max.
IIX
tOHA
tACE
tDOE
Write Cycle
tWC
IOZ
ICC
ISB1
ISB2
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tAA
tAW
tHA
tSA
tPWE
tSD
tHD
Document #: 38-05160 Rev. *A
Page 9 of 13
CY7C199
Package Diagrams
28-pin (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032-**
28-pin Rectangular Leadless Chip Carrier L54
MIL-STD-1835C-11A
51-80067-**
Document #: 38-05160 Rev. *A
Page 10 of 13
CY7C199
Package Diagrams (continued)
28-pin (300-Mil) Molded DIP P21
51-85014-B
28-pin (300-Mil) Molded SOIC S21
51-85026-A
Document #: 38-05160 Rev. *A
Page 11 of 13
CY7C199
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ V21
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05160 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C199
Document History Page
Document Title: CY7C199 32K x 8 Static RAM
Document Number: 38-05160
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109971
121730
Description of Change
Change from Spec number: 38-00239 to 38-05160
Updated Product Offering table.
10/28/01
01/09/02
SZV
DFP
*A
Document #: 38-05160 Rev. *A
Page 13 of 13
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