CY7C199BL-10ZI [CYPRESS]
32K x 8 Static RAM; 32K x 8静态RAM型号: | CY7C199BL-10ZI |
厂家: | CYPRESS |
描述: | 32K x 8 Static RAM |
文件: | 总15页 (文件大小:258K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
CY7C199B
32K x 8 Static RAM
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199B is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
Features
• High speed
— 10 ns
• Fast t
DOE
An active LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
• CMOS for optimum speed/power
• Low active power
are both LOW, data on the eight data input/output pins (I/O
0
— 495 mW (max, 10 ns “L” version)
• Low standby power
through I/O ) is written into the memory location addressed by
7
the address present on the address pins (A through A ).
0
14
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199B is a high-performance CMOS static RAM or-
ganized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
LCC
Top View
A
A
V
CC
28
27
26
5
1
2
3
4
5
6
WE
6
3
2 1 2827
26
A
A
A
4
7
4
A
4
A
8
8
A
3
25
24
5
6
7
8
25
24
23
22
21
20
19
18
A
A
9
3
A
9
A
2
A
A
10
11
12
2
A
10
A
11
23
22
A
1
A
A
A
A
A
1
OE
7
OE
9
13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
I/O
I/O
I/O
A
21
20
19
18
17
16
15
12
13
14
A
0
0
1
2
3
4
5
6
0
8
9
10
11
12
13
10
11
12
CE
I/O
I/O
INPUT BUFFER
CE
I/O
I/O
I/O
I/O
I/O
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617
A
1
C199–3
A
2
I/O
I/O
A
3
GND
14
3
A
4
C199B–2
1024 x 32 x 8
ARRAY
A
5
22
OE
A
A
A
0
21
6
23
24
1
A
20
CE
I/O
I/O
6
I/O
I/O
I/O
GND
7
A
A
A
A
2
3
4
19
18
17
16
8
A
7
25
26
27
28
1
9
5
TSOP I
Top View
(not to scale)
WE
4
3
CE
V
CC
A
A
15
14
13
POWER
DOWN
WE
COLUMN
DECODER
5
6
7
2
3
I/O
2
A
A
A
I/O
7
12
11
I/O
I/O
A
1
0
OE
4
5
8
9
C199B–1
10
9
14
A
6
7
10
A
A
13
12
A
11
8
C199–4
Selection Guide
199B-8
199B-10
10
199B-12
12
199B-15
15
199B-20
20
199B-25
25
199B-35
35
199B-45
45
Maximum Access Time (ns)
Maximum Operating
8
120
110
160
90
155
90
150
90
150
80
140
70
140
Current (mA)
L
90
Maximum CMOS
0.5
0.5
10
10
10
10
10
10
Standby Current (mA)
L
0.05
0.05
0.05
0.05
0.05
0.05
Shaded area contains advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 13, 2000
PRELIMINARY
CY7C199B
DC Voltage Applied to Outputs
in High Z State ................................... –0.5V to V + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
[1]
CC
[1]
DC Input Voltage ................................ –0.5V to V + 0.5V
CC
Storage Temperature .................................–65°C to +150°C
Output Current into Outputs (LOW)............................. 20 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +7.0V
Latch-Up Current.................................................... >200 mA
Operating Range
[2]
Range
Commercial
Industrial
Military
Ambient Temperature
0°C to +70°C
V
CC
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C
[3]
Electrical Characteristics Over the Operating Range
7C199B-8
7C199B-10
7C199B-12
7C199B-15
Parameter
Description
Test Conditions
= Min., I =–4.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
Output HIGH
Voltage
V
V
2.4
2.4
2.4
2.4
V
V
OH
OL
IH
CC
CC
OH
Output LOW
Voltage
= Min., I =8.0 mA
0.4
0.4
0.4
0.4
OL
Input HIGH
Voltage
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
V
CC
CC
CC
CC
Input LOW
Voltage
0.8
+5
0.8
+5
+5
0.8
0.8
+5
+5
V
IL
I
I
I
Input Load
Current
GND < V < V
CC
+5
+5
µA
µA
IX
I
Output Leakage GND < V < V ,
CC
Current
–5
+5
–5
–5
–5
OZ
CC
O
Output Disabled
V
Operating
V
= Max.,
= 0 mA,
Com’l
L
120
110
85
160
85
155
100
180
30
mA
mA
mA
mA
mA
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
Mil
I
I
Automatic CE
Power-Down
Current— TTL
Inputs
Max. V
CE > V
,
CC
Com’l
L
5
5
5
30
5
SB1
SB2
,
IH
5
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
Automatic CE
Power-Down
Current— CMOS
Inputs
Max. V
CE > V – 0.3V
,
Com’l
L
0.5
0.5
10
10
0.05
15
mA
mA
mA
CC
CC
0.05
0.05
0.05
V
> V – 0.3V
IN
CC
Mil
or V < 0.3V, f = 0
IN
Shaded area contains advance information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. See the last page of this specification for Group A subgroup testing information.
2
PRELIMINARY
CY7C199B
[3]
Electrical Characteristics Over the Operating Range (continued)
7C199B-20
7C199B-25
7C199B-35
7C199B-45
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max.
Min.
Max. Unit
V
V
V
V
Output HIGH
Voltage
V
V
= Min., I =–4.0 mA 2.4
2.4
2.4
2.4
V
OH
OL
IH
CC
CC
OH
Output LOW
Voltage
= Min., I =8.0 mA
0.4
0.4
0.4
0.4
V
V
OL
Input HIGH
Voltage
2.2
–0.5
–5
V
2.2
-0.5
–5
V
2.2
-0.5
–5
V
2.2
-0.5
–5
V
CC
+0.3V
CC
CC
CC
+0.3V
+0.3V
+0.3V
Input LOW
Voltage
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
V
IL
I
I
I
Input Load
Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage GND < V < V ,
CC
Current
–5
–5
–5
–5
OZ
CC
I
Output Disabled
V
Operating
V
= Max.,
= 0 mA,
Com’l
L
150
90
170
30
5
150
80
140
70
140
70
mA
mA
mA
mA
mA
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
Mil
150
30
150
25
150
25
I
I
Automatic CE
Power-Down
Current—
Max. V , CE> V , Com’l
SB1
SB2
CC
IH
IH
V
> V
IN
L
5
5
5
or V < V , f = f
IN
IL
MAX
TTL Inputs
Automatic CE
Power-Down
Current—
Max. V
CE > V – 0.3V
,
Com’l
L
10
0.05
15
10
0.05
15
10
0.05
15
10
0.05
15
mA
µA
CC
CC
CC
V
> V – 0.3V or
IN
CMOS Inputs
V
< 0.3V, f=0
Mil
mA
IN
]
Capacitance[4]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
8
8
IN
A
V
= 5.0V
CC
pF
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
PRELIMINARY
CY7C199B
AC Test Loads and Waveforms
R1 481
R1 481
Ω
Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
t
≤
t
≤
r
r
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C199B–5
C199B–6
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L version only)
[5]
Parameter
Description
for Data Retention
CC
Conditions
Min.
Max.
Unit
V
V
V
2.0
DR
I
Data Retention Current
Com’l
V
= V = 2.0V,
µA
µA
ns
CCDR
CC
DR
CE > V – 0.3V,
CC
Com’l L
10
V
> V – 0.3V or
IN
CC
V
< 0.3V
[4]
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
CDR
200
µs
R
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
C199B–7
Note:
5. No input may exceed VCC + 0.5V.
4
PRELIMINARY
CY7C199B
[3, 6]
Switching Characteristics Over the Operating Range
7C199B-8
Min. Max.
7C199B-10
7C199B-12
7C199B-15
Parameter
Description
Min.
Max.
Min.
12
3
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
8
3
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
8
10
12
15
AA
Data Hold from Address Change
CE LOW to Data Valid
3
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
8
10
5
12
5
15
7
OE LOW to Data Valid
4.5
[7]
OE LOW to Low Z
0
3
0
0
3
0
0
3
0
0
3
0
[7, 8]
OE HIGH to High Z
5
4
8
5
5
5
5
7
7
[7]
CE LOW to Low Z
[7,8]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
15
PD
[9, 10]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
8
7
7
0
0
7
5
0
10
7
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
9
0
0
HA
0
0
0
SA
7
8
9
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
8
9
0
0
0
HD
[8]
WE LOW to High Z
5
6
7
7
HZWE
LZWE
[7]
WE HIGH to Low Z
3
3
3
3
Shaded area contains advance information.
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WEcontrolled, OE LOW) is the sum of tHZWE and tSD
.
5
PRELIMINARY
CY7C199B
[3,6]
Switching Characteristics Over the Operating Range
(continued)
7C199B-25
7C199B-20
7C199B-35
7C199B-45
Parameter
Description
Min.
20
Max.
Min.
Max.
Min.
35
3
Max.
Min.
45
3
Max.
Unit
READ CYCLE
t
t
t
Read Cycle Time
25
ns
ns
ns
RC
Address to Data Valid
20
25
35
45
AA
Data Hold from Address
Change
3
3
OHA
t
t
t
t
t
t
t
t
CE LOW to Data Valid
OE LOW to Data Valid
20
9
25
10
35
16
45
16
ns
ns
ns
ns
ns
ns
ns
ns
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[7]
OE LOW to Low Z
0
3
0
0
3
0
0
3
0
0
3
0
[7, 8]
OE HIGH to High Z
9
9
11
11
20
15
15
20
15
15
25
[7]
CE LOW to Low Z
[7, 8]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
20
PD
[9,10]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
15
15
0
25
18
20
0
35
22
30
0
45
22
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
0
SA
15
10
0
18
10
0
22
15
0
22
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[8]
WE LOW to High Z
10
11
15
15
HZWE
LZWE
[7]
WE HIGH to Low Z
3
3
3
3
Switching Waveforms
[11, 12]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C199B–8
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
6
PRELIMINARY
CY7C199B
Switching Waveforms (continued)
[12, 13]
Read Cycle No. 2
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
C199B–9
[9, 14, 15]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
IN
DATA I/O
t
HZOE
C199B–10
[9, 14, 15]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA
VALID
IN
C199B–11
Notes:
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH
.
15. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
7
PRELIMINARY
CY7C199B
Switching Waveforms (continued)
[10, 15]
Write Cycle No. 3 (WE Controlled OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
t
t
LZWE
HZWE
C199B–12
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY
VOLTAGE
120
100
80
1.4
1.2
1.4
1.2
1.0
0.8
0.6
I
CC
I
CC
1.0
0.8
0.6
V
CC
=5.0V
60
T =25 C
°
A
V
IN
=5.0V
T =25 C
°
A
40
V
V
IN
=5.0V
=5.0V
0.4
CC
0.4
20
0
0.2
0.0
0.2
0.0
I
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
°
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25 C
°
A
V
CC
=5.0V
T =25 C
°
V
CC
=5.0V
A
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
OUTPUT VOLTAGE (V)
°
SUPPLY VOLTAGE (V)
8
PRELIMINARY
CY7C199B
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs.SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
°
=0.5V
CC
T =25 C
A
V
IN
V
=4.5V
°
1.0
0.5
10.0
5.0
CC
T =25 C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
L
WE
OE
X
Inputs/Outputs
High Z
Mode
Power
X
H
L
Deselect/Power-Down
Read
Standby (I
)
SB
L
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
X
Write
)
CC
L
H
H
Deselect, Output Disabled
)
CC
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C199B-8VC
Package Type
28-Lead Molded SOJ
8
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
P21
V21
Z28
P21
V21
Z28
V21
Z28
V21
Z28
Commercial
Commercial
Industrial
CY7C199B-8ZC
CY7C199BL-8VC
CY7C199BL-8ZC
CY7C199B-10VC
CY7C199B-10ZC
CY7C199BL-10VC
CY7C199BL-10ZC
CY7C199B-10VI
CY7C199B-10ZI
CY7C199BL-10VI
CY7C199BL-10ZI
CY7C199B-12PC
CY7C199B-12VC
CY7C199B-12ZC
CY7C199BL-12PC
CY7C199BL-12VC
CY7C199BL-12ZC
CY7C199B-12VI
CY7C199B-12ZI
CY7C199BL-12VI
CY7C199BL-12ZI
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
10
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
12
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
Shaded area contains advance information. Contact your Cypress sales representative for availability
9
PRELIMINARY
CY7C199B
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C199B-15PC
Package Type
15
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
S21
V21
Z28
Z28
D22
L54
P21
S21
V21
Z28
D22
L54
D22
L54
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
CY7C199B-15VC
CY7C199B-15ZC
CY7C199BL-15PC
CY7C199BL-15VC
CY7C199BL-15ZC
CY7C199B-15VI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
CY7C199B-15ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199B-15DMB
CY7C199B-15LMB
CY7C199BL-15DMB
CY7C199BL-15LMB
CY7C199B-20PC
CY7C199B-20VC
CY7C199B-20ZC
CY7C199BL-20PC
CY7C199BL-20VC
CY7C199BL-20ZC
CY7C199B-20VI
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
20
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
CY7C199B-20ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199B-20DMB
CY7C199B-20LMB
CY7C199BL-20DMB
CY7C199BL-20LMB
CY7C199B-25PC
CY7C199B-25SC
CY7C199B-25VC
CY7C199B-25ZC
CY7C199BL-25ZI
CY7C199B-25DMB
CY7C199B-25LMB
CY7C199B-35PC
CY7C199B-35SC
CY7C199B-35VC
CY7C199B-35ZC
CY7C199B-35DMB
CY7C199B-35LMB
CY7C199B-45DMB
CY7C199B-45LMB
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
25
Commercial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Industrial
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
35
45
Commercial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Military
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains advance information. Contact your Cypress sales representative for availability
10
PRELIMINARY
CY7C199B
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
V
V
V
V
1, 2, 3
OH
OL
IH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Max.
IL
I
I
I
I
I
IX
OZ
CC
SB1
SB2
Switching Characteristics
Parameter
Subgroups
READ CYCLE
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
RC
AA
OHA
ACE
DOE
WRITE CYCLE
t
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
AA
AW
HA
SA
PWE
SD
HD
Document #: 38-00941-**
11
PRELIMINARY
CY7C199B
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
12
PRELIMINARY
CY7C199B
Package Diagrams (continued)
28-Pin Rectangular Leadless Chip Carrier L54
MIL-STD-1835C-11A
51-80067
28-Lead (300-Mil) Molded DIP P21
51-85014-B
13
PRELIMINARY
CY7C199B
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
14
CY7C199B
PRELIMINARY
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
51-85071-F
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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