CY7C2245KV18-450BZXI [CYPRESS]
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165;
| 型号： | CY7C2245KV18-450BZXI |
| 厂家： | 
CYPRESS |
| 描述： | QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C2245KV18
36-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.0 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.0 Cycles:
CY7C2245KV18 – 1 M × 36
■ 450 MHz clock for high bandwidth
Functional Description
■ Four-word burst for reducing address bus frequency
The CY7C2245KV18 is 1.8 V synchronous pipelined SRAM,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 36-bit
words (CY7C2245KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn-arounds”.
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-die termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
These devices have an on-die termination feature supported for
D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen
DOFF is asserted LOW
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Available in × 36 configurations
■ Full data coherency, providing most current data
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
[1]
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum operating frequency
450 MHz Unit
450
MHz
mA
Maximum operating current
× 36
1020
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-87885 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 8, 2014
CY7C2245KV18
Logic Block Diagram – CY7C2245KV18
36
D
[35:0]
Write Write Write Write
Reg
Reg Reg Reg
18
Address
Register
A
(17:0)
18
Address
Register
A
(17:0)
RPS
K
Control
Logic
CLK
Gen.
K
DOFF
Read Data Reg.
CQ
CQ
144
72
V
REF
36
36
36
36
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
36
72
Q
[35:0]
[3:0]
QVLD
Document Number: 001-87885 Rev. *A
Page 2 of 28
CY7C2245KV18
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................7
Byte Write Operations .................................................7
Concurrent Transactions .............................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
Valid Data Indicator (QVLD) ........................................7
On-Die Termination (ODT) ..........................................7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................9
Write Cycle Descriptions ...............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port .......................................................11
Performing a TAP Reset ...........................................11
TAP Registers ...........................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Electrical Characteristics ......................................14
TAP AC Switching Characteristics ...............................15
TAP Timing and Test Conditions ..................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Power Up Sequence in QDR II+ SRAM .........................19
Power Up Sequence .................................................19
PLL Constraints .........................................................19
Maximum Ratings ...........................................................20
Operating Range .............................................................20
Neutron Soft Error Immunity .........................................20
Electrical Characteristics ...............................................20
DC Electrical Characteristics .....................................20
AC Electrical Characteristics .....................................21
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................21
Switching Characteristics ..............................................22
Switching Waveforms ....................................................23
Read/Write/Deselect Sequence ................................23
Ordering Information ......................................................24
Ordering Code Definitions .........................................24
Package Diagram ............................................................25
Acronyms ........................................................................26
Document Conventions .................................................26
Units of Measure .......................................................26
Document History Page .................................................27
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC® Solutions ......................................................28
Cypress Developer Community .................................28
Technical Support .....................................................28
Document Number: 001-87885 Rev. *A
Page 3 of 28
CY7C2245KV18
Pin Configurations
The pin configuration for CY7C2245KV18 follow. [2]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C2245KV18 (1 M × 36)
1
2
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
10
NC/144M
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
CQ
NC/288M NC/72M
WPS
A
RPS
A
A
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
K
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
D15
D6
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
D9
A
QVLD
ODT
A
D0
A
A
A
A
A
TMS
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-87885 Rev. *A
Page 4 of 28
CY7C2245KV18
Pin Definitions
Pin Name
I/O
Pin Description
Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
D[x:0]
Input-
synchronous CY7C2245KV18 D[35:0]
WPS
Input-
Write port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a
synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]
.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte write select 0, 1, 2 and 3 active LOW. Sampled on the rising edge of the K and K clocks when
synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C2245KV18 BWS0 controls D[8:0], BWS1 controls D[17:9]
,
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device
.
A
Input-
Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 1 M × 36 (4 arrays each of 256 K × 36) for CY7C2245KV18. Therefore, only 18 address
inputs for CY7C2245KV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
RPS
Outputs-
Data output signals. These pins drive out the requested data when the read operation is active. Valid
synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tri-stated.
CY7C2245KV18 Q[35:0]
Input-
Read port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a
synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output Valid output indicator. The Q valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
ODT [3]
On-die
On-die termination input. This pin is used for on-die termination of the input signals. ODT range
termination selection is made during power up initialization. A LOW on this pin selects a low range that follows
input pin
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0]
.
CQ
CQ
ZQ
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 22.
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 22.
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Note
3. On-die termination (ODT) feature is supported for D
, BWS
, and K/K inputs.
[x:0]
[x:0]
Document Number: 001-87885 Rev. *A
Page 5 of 28
CY7C2245KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
DOFF
Input
PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with QDR I timing.
TDO
Output
Input
Input
Input
N/A
TDO pin for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
Input-
reference measurement points.
VDD
VSS
Power supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power supply Power supply inputs for the outputs of the device.
Read Operations
Functional Overview
The CY7C2245KV18 is organized internally as four arrays of
256 K × 36. Accesses are completed in a burst of four sequential
36-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 36-bit word of data is driven onto the
Q[35:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 36-bit data word is driven
onto the Q[35:0]. This process continues until all four 36-bit data
words have been driven out onto Q[35:0]. The requested data is
valid 0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 36-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
The CY7C2245KV18 is synchronous pipelined burst SRAM
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 36-bit data transfers in the case of
CY7C2245KV18, in two clock cycles.
These devices operate with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to VSS then device behaves in QDR I mode with a read latency
of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
When the read port is deselected, the CY7C2245KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C2245KV18 is described in the following sections.
Document Number: 001-87885 Rev. *A
Page 6 of 28
CY7C2245KV18
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[35:0] is latched and stored into
the lower 36-bit write data register, provided BWS[3:0] are
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[35:0] is also stored
into the write data register, provided BWS[3:0] are asserted
active. This process continues for one more cycle until four 36-bit
words (a total of 144 bits) of data are stored in the SRAM. The
144 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 36 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the QDR II+. The timing
for the echo clocks is shown in the Switching Characteristics on
page 22.
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C2245KV18. A
write operation is initiated as described in the section Write
Operations on page 7. The bytes that are written are determined
by BWS0, BWS1, BWS2 and BWS3 which are sampled with each
set of 36-bit data words. Asserting the appropriate byte write
select input during the data portion of a write latches the data
being presented and writes it into the device. Deasserting the
byte write select input during the data portion of a write enables
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify read, modify, or write opera-
tions to a byte write operation.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
On-Die Termination (ODT)
These devices have an on-die termination feature for data inputs
(D[x:0]), byte write selects (BWS[x:0]), and input clocks (K and K).
The termination resistors are integrated within the chip. The ODT
range selection is enabled through ball R6 (ODT pin). The ODT
termination tracks value of RQ where RQ is the resistor tied to
the ZQ pin. ODT range selection is made during power-up
initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied
to ZQ pin)A HIGH on this pin selects a high range that follows
RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied
to ZQ pin). When left floating, a high range termination value is
selected by default. For a detailed description on the ODT
implementation, refer to the application note, On-Die Termination
for QDRII+/DDRII+ SRAMs.
Concurrent Transactions
The read and write ports on the CY7C2245KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations can not be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in
alternating read or write operations being initiated, with the first
access being a read.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power-up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Depth Expansion
The CY7C2245KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
Document Number: 001-87885 Rev. *A
Page 7 of 28
CY7C2245KV18
Application Example
Figure 2 shows two QDR II+ used in an application.
Figure 2. Application Example (Width Expansion)
ZQ
CQ/CQ
Q[x:0]
ZQ
SRAM#1
SRAM#2
CQ/CQ
RQ
Q[x:0]
RQ
D[x:0]
D[x:0]
A
RPS WPS BWS
K
K
A
RPS WPS BWS
K
K
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
Document Number: 001-87885 Rev. *A
Page 8 of 28
CY7C2245KV18
Truth Table
The truth table for CY7C2245KV18 follows. [4, 5, 6, 7, 8, 9]
Operation
Write cycle:
K
RPS WPS
DQ
DQ
DQ
DQ
L–H
H [10] L [11] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read cycle:
(2.0 cycle latency)
L–H
L [11]
X
Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)
Load address on the rising
edge of K; wait two cycles;
read data on two consec-
utive K and K rising edges.
NOP: No Operation
L–H
H
X
H
X
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped
Stopped
Previous state
Previous state
Previous state
Previous state
Notes
4. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, represents rising edge.
5. Device powers up deselected with the outputs in a tri-state condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and thirdclock cycles respectively succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. Ensure that when clock is stopped K = K = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
11. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 001-87885 Rev. *A
Page 9 of 28
CY7C2245KV18
Write Cycle Descriptions
The write cycle description table for CY7C2245KV18 follows. [12, 13]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
12. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
13. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a
0
1
2
3
write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-87885 Rev. *A
Page 10 of 28
CY7C2245KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 14. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
This SRAM incorporates a serial boundary scan test access port
(TAP) in the FBGA package. This part is fully compliant with IEEE
Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-87885 Rev. *A
Page 11 of 28
CY7C2245KV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-87885 Rev. *A
Page 12 of 28
CY7C2245KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [14]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
1
SHIFT-DR
1
SHIFT-IR
1
1
0
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
14. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-87885 Rev. *A
Page 13 of 28
CY7C2245KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
Circuitry
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [15, 16, 17]
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
IOH =2.0 mA
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
–0.3
–5
0.35 × VDD
5
V
IX
Input and output load current
GND VI VDD
A
Notes
15. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20.
16. Overshoot: V < V + 0.35 V (Pulse width less than t /2), Undershoot: V /2).
> -0.3 V (Pulse width less than t
CYC
IH(AC)
DDQ
CYC
IL(AC)
17. All voltage referenced to ground.
Document Number: 001-87885 Rev. *A
Page 14 of 28
CY7C2245KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [18, 19]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Output Times
tTDOV
tTDOX
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
Notes
18. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
19. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-87885 Rev. *A
Page 15 of 28
CY7C2245KV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [20]
Figure 3. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
0.9V
1.8V
50
TDO
0V
Z = 50
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
20. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-87885 Rev. *A
Page 16 of 28
CY7C2245KV18
Identification Register Definitions
Value
CY7C2245KV18
000
Instruction Field
Description
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
Version number.
11010010001100111
00000110100
Defines the type of SRAM.
Allows unique identification of SRAM
vendor.
ID register presence (0)
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-87885 Rev. *A
Page 17 of 28
CY7C2245KV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
Bit #
84
Bump ID
1J
1
6P
5B
5A
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
4A
87
3J
4
7N
5C
4B
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
3A
90
2L
7
8P
2A
91
3L
8
9R
1A
92
1M
1L
9
11P
10P
10N
9P
2B
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
3B
94
3N
1C
1B
95
3M
1N
96
10M
11N
9M
9D
3D
3C
1D
2C
3E
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
2D
2E
3R
4R
10L
11K
10K
9J
1E
4P
8B
2F
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-87885 Rev. *A
Page 18 of 28
CY7C2245KV18
PLL Constraints
Power Up Sequence in QDR II+ SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (all other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Figure 4. Power Up Waveforms
K
K
Unstable Clock
> 20μs Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-87885 Rev. *A
Page 19 of 28
CY7C2245KV18
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature (TA)
[22]
[22]
Range
VDD
VDDQ
Industrial
–40 °C to +85 °C
1.8 ± 0.1 V 1.4 V to
VDD
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Neutron Soft Error Immunity
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in high Z ........–0.5 V to VDDQ + 0.3 V
DC input voltage [21] ...........................–0.5 V to VDD + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
197
216 FIT/
Mb
Logical
multi-bit
upsets
0
0.01 FIT/
Mb
Static discharge voltage
(MIL-STD-883, M. 3015) ........................................> 2,001 V
Latch-up current ....................................................> 200 mA
Single event
latch-up
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [23]
VDD
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
Typ
1.8
1.5
–
Max
Unit
V
1.7
1.9
VDD
VDDQ
VOH
1.4
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
V
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
Note 24
Note 25
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
VOL
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, nominal impedance
–
V
IOL = 0.1 mA, nominal impedance
–
0.2
V
VREF + 0.1
–0.15
–
VDDQ + 0.15
VREF – 0.1
2
V
VIL
–
V
IX
GND VI VDDQ
–2
–
A
A
V
IOZ
GND VI VDDQ, output disabled
–2
–
2
VREF
Input reference voltage [26] Typical value = 0.75 V
0.68
0.75
–
0.95
[27]
IDD
VDD operating supply
VDD = Max, IOUT = 0 mA, 450 MHz (× 36)
f = fMAX = 1/tCYC
–
1020
mA
ISB1
Automatic power-down
current
Max VDD
both ports deselected,
,
450 MHz (× 36)
–
–
330
mA
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
inputs static
,
Notes
21. Overshoot: V
22. Power-up: Assumes a linear ramp from 0 V to V
< V
+ 0.35 V (Pulse width less than t
/2), Undershoot: V
> -0.3 V (Pulse width less than t
/2).
CYC
IH(AC)
DDQ
CYC
IL(AC)
within 200 ms. During this time V < V and V
< V
.
DD
DD(min)
IH
DD
DDQ
23. All voltage referenced to ground.
24. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 RQ 350 .
DDQ
DDQ
OH
25. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 RQ 350 .
OL
26. V
= 0.68 V or 0.46 V
, whichever is larger, V
= 0.95 V or 0.54 V
, whichever is smaller.
REF(min)
DDQ
REF(max)
DDQ
27. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-87885 Rev. *A
Page 20 of 28
CY7C2245KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [28]
Description
Input HIGH voltage
Input LOW voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Parameter [29]
Description
Input capacitance
Output capacitance
Test Conditions
Max
4
Unit
pF
CIN
CO
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [29]
Description
Test Conditions
Unit
JA (0 m/s)
JA (1 m/s)
JA (3 m/s)
Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit
board
16.72
15.67
14.92
13.67
°C/W
°C/W
°C/W
°C/W
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
4.54
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[30]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
R = 50
L
0.75 V
Under
Device
Under
0.25 V
Test
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Notes
28. Overshoot: V
< V
+ 0.35 V (Pulse width less than t
/2), Undershoot: V
> -0.3 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
29. Tested initially and after any design or process change that may affect these parameters.
30. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-87885 Rev. *A
Page 21 of 28
CY7C2245KV18
Switching Characteristics
Over the Operating Range
Parameters [31, 32]
450 MHz
Unit
Consor-
tium Pa-
rameter
Cypress
Parame-
ter
Description
VDD(typical) to the first access [33]
Min
Max
tPOWER
tCYC
tKH
1
–
8.4
–
ms
ns
ns
ns
ns
tKHKH
K clock cycle time
2.2
0.4
0.4
0.94
tKHKL
tKLKH
tKHKH
Input clock (K/K) HIGH
tKL
–
Input clock (K/K) LOW
tKHKH
–
K clock rise to K clock rise (rising edge to rising edge)
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address set-up to K clock rise
0.275
0.275
0.22
–
–
–
ns
ns
ns
tSC
Control set-up to K clock rise (RPS, WPS)
tSCDDR
Double data rate control set-up to clock (K/K) rise (BWS0, BWS1, BWS2,
BWS3)
tSD
tDVKH
0.22
–
ns
D[X:0] set-up to clock (K/K) rise
Hold Times
tHA
tKHAX
tKHIX
tKHIX
0.275
0.275
0.22
–
–
–
ns
ns
ns
Address hold after K clock rise
tHC
Control hold after K clock rise (RPS, WPS)
tHCDDR
Double data rate control hold after clock (K/K) rise (BWS0, BWS1, BWS2,
BWS3)
tHD
tKHDX
0.22
–
ns
D[X:0] hold after clock (K/K) rise
Output Times
tCO
tCHQV
–
0.45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K/K clock rise to data valid
tDOH
tCHQX
–0.45
–
Data output hold after output K/K clock rise (active to active)
K/K clock rise to echo clock valid
Echo clock hold after K/K clock rise
Echo clock high to data valid
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
0.45
–
–0.45
–
0.15
–
tCQDOH
tCQH
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH [34]
–0.15
0.85
0.85
–
–
[34]
tCQHCQH tCQHCQH
CQ clock rise to CQ clock rise
Clock (K/K) rise to high Z (active to high Z) [35, 36]
Clock (K/K) rise to low Z [35, 36]
Echo clock high to QVLD valid [37]
–
(rising edge to rising edge)
tCHZ
tCLZ
tCHQZ
0.45
–
tCHQX1
tCQHQVLD
–0.45
–0.15
tQVLD
0.15
PLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock phase jitter
–
0.15
–
ns
s
ns
PLL lock time (K)
K static to PLL reset [38]
20
30
tKC Reset tKC Reset
–
Notes
31. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
= 1.5 V, input
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 21.
OL OH
32. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
33. This part has a voltage regulator internally; t
initiated.
is the time that the power must be supplied above V minimum initially before a read or write operation can be
DD
POWER
34. These parameters are extrapolated from the input timing parameters (t
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
35. t
, t
, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 21. Transition is measured ±100 mV from steady-state voltage.
CHZ CLZ
36. At any given voltage and temperature t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
37. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
Document Number: 001-87885 Rev. *A
Page 22 of 28
CY7C2245KV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.0 Cycle Read Latency [39, 40, 41]
Notes
38. Hold to > V or < V
.
IL
IH
39. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
40. Outputs are disabled (high Z) one clock cycle after a NOP.
41. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-87885 Rev. *A
Page 23 of 28
CY7C2245KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
450 CY7C2245KV18-450BZXI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Industrial
Ordering Code Definitions
CY
7
C
2245 K V18 - 450 BZ
X
I
Temperature Range:
I = Industrial = –40 C to +85 C
X = Pb-free
Package Type:
BZ = 165-ball FBGA
Speed Grade: 450 MHz
V18 = 1.8 V VDD
Process Technology: K = 65 nm
Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-87885 Rev. *A
Page 24 of 28
CY7C2245KV18
Package Diagram
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *F
Document Number: 001-87885 Rev. *A
Page 25 of 28
CY7C2245KV18
Acronyms
Document Conventions
Units of Measure
Acronym
Description
DDR
EIA
Double Data Rate
Symbol
°C
Unit of Measure
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
High-Speed Transceiver Logic
Input/Output
degree Celsius
kilohm
FBGA
HSTL
I/O
k
MHz
µA
µs
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
millivolt
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multiple Bit Upset
Least Significant Bit
Logical Single Bit Upset
Most Significant Bit
mA
mm
ms
mV
ns
LSBU
MSB
ODT
PLL
nanosecond
ohm
On-Die Termination
Phase Locked Loop
Quad Data Rate
pF
%
picofarad
percent
QDR
SEL
Single Event Latch-up
Static Random Access Memory
Test Access Port
V
volt
SRAM
TAP
W
watt
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
Test Data-Out
Test Mode Select
Document Number: 001-87885 Rev. *A
Page 26 of 28
CY7C2245KV18
Document History Page
Document Title: CY7C2245KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
Document Number: 001-87885
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
4024163
4373800
PRIT
PRIT
09/03/2013 New data sheet.
*A
05/08/2014 Updated Application Example:
Updated Figure 2.
Updated Thermal Resistance:
Updated values of JA parameter.
Included JB parameter and its details.
Document Number: 001-87885 Rev. *A
Page 27 of 28
CY7C2245KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2013-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-87885 Rev. *A
Revised May 8, 2014
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
相关型号：
CY7C225-25DI
OTP ROM, 512X8, 12ns, CMOS, CDIP24, 0.300 INCH, SLIM, HERMETIC SEALED, CERDIP-24
CYPRESS
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