CY7C2263KV18_技术文档

CY7C2263KV18/CY7C2265KV18

36-Mbit QDR^®II+ SRAM Four-Word

Burst Architecture (2.5 Cycle Read Latency) with ODT

36-Mbit QDR^®II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 Cycles:

CY7C2263KV18 – 2 M × 18

■ 550 MHz clock for high bandwidth

CY7C2265KV18 – 1 M × 36

■ Four-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 1100 MHz) at 550 MHz

The CY7C2263KV18, and CY7C2265KV18 are 1.8

V

synchronous pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn-around” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 18-bit words

(CY7C2263KV18), or 36-bit words (CY7C2265KV18) that burst

sequentially into or out of the device. Because data is transferred

into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turn-arounds”.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

These devices have an on-die termination feature supported for

D_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate external

termination resistors, reduce cost, reduce board area, and

simplify board routing.

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

❐ Supports both 1.5 V and 1.8 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)

For a complete list of related documentation, click here.

■ CY7C2263KV18 offered in both Pb-free packages and

CY7C2265KV18 offered in both Pb-free and non Pb-free

packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

550 MHz

550

450 MHz

450

400 MHz

Unit

MHz

400

Maximum operating current

× 18

× 36

850

1210

720

1020

Not Offered mA

920

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

.

DD

DDQ

Cypress Semiconductor Corporation

Document Number: 001-57843 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 4, 2016

CY7C2263KV18/CY7C2265KV18

Logic Block Diagram – CY7C2263KV18

18

D

[17:0]

Write Write Write Write

19

Address

Register

A

Reg

(18:0)

19

Address

Register

A

(18:0)

RPS

K

Control

Logic

CLK

Gen.

K

DOFF

Read Data Reg.

CQ

72

36

V

REF

18

Reg.

Control

Logic

WPS

BWS

18

36

Q

[17:0]

[1:0]

QVLD

Logic Block Diagram – CY7C2265KV18

36

D

[35:0]

Write Write Write Write

18

Address

Register

A

Reg

(17:0)

18

Address

Register

A

(17:0)

RPS

K

Control

Logic

CLK

Gen.

K

DOFF

Read Data Reg.

CQ

144

72

V

REF

36

Reg.

Control

Logic

WPS

BWS

36

72

Q

[35:0]

[3:0]

QVLD

Document Number: 001-57843 Rev. *L

Page 2 of 32

CY7C2263KV18/CY7C2265KV18

Contents

Pin Configurations ...........................................................4

Pin Definitions ..................................................................5

Functional Overview ........................................................6

Read Operations .........................................................6

Write Operations .........................................................6

Byte Write Operations .................................................7

Concurrent Transactions .............................................7

Depth Expansion .........................................................7

Programmable Impedance ..........................................7

Echo Clocks ................................................................7

Valid Data Indicator (QVLD) ........................................7

On-Die Termination (ODT) ..........................................7

PLL ..............................................................................7

Application Example ........................................................8

Truth Table ........................................................................9

Write Cycle Descriptions ...............................................10

Write Cycle Descriptions ...............................................11

IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12

Disabling the JTAG Feature ......................................12

Test Access Port .......................................................12

Performing a TAP Reset ...........................................12

TAP Registers ...........................................................12

TAP Instruction Set ...................................................12

TAP Controller State Diagram .......................................14

TAP Controller Block Diagram ......................................15

TAP Electrical Characteristics ......................................15

TAP AC Switching Characteristics ...............................16

TAP Timing and Test Conditions ..................................17

Identification Register Definitions ................................18

Scan Register Sizes .......................................................18

Instruction Codes ...........................................................18

Boundary Scan Order ....................................................19

Power Up Sequence in QDR II+ SRAM .........................20

Power Up Sequence .................................................20

PLL Constraints .........................................................20

Maximum Ratings ...........................................................21

Operating Range .............................................................21

Neutron Soft Error Immunity .........................................21

Electrical Characteristics ...............................................21

DC Electrical Characteristics .....................................21

AC Electrical Characteristics .....................................23

Capacitance ....................................................................23

Thermal Resistance ........................................................23

AC Test Loads and Waveforms .....................................23

Switching Characteristics ..............................................24

Switching Waveforms ....................................................26

Read/Write/Deselect Sequence ................................26

Ordering Information ......................................................27

Ordering Code Definitions .........................................27

Package Diagram ............................................................28

Acronyms ........................................................................29

Document Conventions .................................................29

Units of Measure .......................................................29

Document History Page .................................................30

Sales, Solutions, and Legal Information ......................32

Worldwide Sales and Design Support .......................32

Products ....................................................................32

PSoC® Solutions ......................................................32

Cypress Developer Community .................................32

Technical Support .....................................................32

Document Number: 001-57843 Rev. *L

Page 3 of 32

CY7C2263KV18/CY7C2265KV18

Pin Configurations

The pin configuration for CY7C2263KV18, and CY7C2265KV18 follow. ^[2]

Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout

CY7C2263KV18 (2 M × 18)

1

CQ

NC

DOFF

NC

TDO

2

NC/144M

Q9

3

4

5

BWS₁

NC

A

6

K

7

NC/288M

BWS₀

A

8

9

A

10

NC/72M

NC

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

A

WPS

A

RPS

A

D9

K

NC

V_DDQ

NC

A

NC

D10

Q10

Q11

D12

Q13

V_DDQ

D14

Q14

D15

D16

Q16

Q17

A

V_SS

V_DDQ

V_SS

A

NC

V_SS

V_DDQ

V_SS

A

Q7

D11

NC

V_SS

V_DD

V_SS

A

V_SS

A

V_SS

V_DD

V_SS

A

NC

D6

Q12

D13

V_REF

NC

G

H

J

NC

V_REF

Q4

K

L

NC

D3

Q15

NC

M

N

P

R

Q1

D17

NC

A

QVLD

ODT

A

D0

TCK

A

TMS

CY7C2265KV18 (1 M × 36)

1

2

3

4

5

BWS₂

BWS₃

A

6

K

7

BWS₁

BWS₀

A

8

9

10

NC/144M

Q17

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

CQ

NC/288M NC/72M

WPS

A

RPS

A

Q27

D27

D28

Q29

Q30

D30

DOFF

D31

Q32

Q33

D33

D34

Q35

TDO

Q18

Q28

D20

D29

Q21

D22

V_REF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

V_DDQ

D23

Q23

D24

D25

Q25

Q26

A

K

D17

D16

Q16

Q15

D14

Q13

V_DDQ

D12

Q12

D11

D10

Q10

Q9

V_SS

V_DDQ

V_SS

A

NC

V_SS

V_DDQ

V_SS

A

V_SS

V_DD

V_SS

A

V_SS

A

V_SS

V_DD

V_SS

A

D15

D6

Q14

D13

V_REF

Q4

G

H

J

K

L

D3

Q11

Q1

M

N

P

R

D9

A

QVLD

ODT

A

D0

A

TMS

Note

2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-57843 Rev. *L

Page 4 of 32

CY7C2263KV18/CY7C2265KV18

Pin Definitions

Pin Name

I/O

Pin Description

Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

D_[x:0]

Input-

synchronous CY7C2263KV18  D_[17:0]

CY7C2265KV18  D_[35:0]

WPS

Input-

Write port select  active LOW. Sampled on the rising edge of the K clock. When asserted active, a

synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D_[x:0]

.

BWS₀,

BWS₁,

BWS₂,

BWS₃

Input-

Byte write select 0, 1, 2 and 3  active LOW. Sampled on the rising edge of the K and K clocks when

synchronous write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C2263KV18  BWS₀controls D_[8:0]and BWS₁controls D_[17:9].

CY7C2265KV18  BWS₀controls D_[8:0], BWS₁controls D_[17:9]

,

BWS₂controls D_[26:18]and BWS₃controls D_[35:27].

All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select

ignores the corresponding byte of data and it is not written into the device

.

A

Input-

Address inputs. Sampled on the rising edge of the K clock during active read and write operations.

synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2 M × 18 (4 arrays each of 512 K × 18) for CY7C2263KV18 and 1 M × 36 (4 arrays each

of 256 K × 36) for CY7C2265KV18. Therefore, only 19 address inputs for CY7C2263KV18 and 18

address inputs for CY7C2265KV18. These inputs are ignored when the appropriate port is deselected.

Q_[x:0]

Outputs-

Data output signals. These pins drive out the requested data when the read operation is active. Valid

synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the

read port, Q_[x:0]are automatically tri-stated.

CY7C2263KV18  Q_[17:0]

CY7C2265KV18  Q_[35:0]

RPS

Input-

Read port select  active LOW. Sampled on the rising edge of positive input clock (K). When active, a

synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access

is allowed to complete and the output drivers are automatically tristated following the next rising edge of

the K clock. Each read access consists of a burst of four sequential transfers.

QVLD

Valid output Valid output indicator. The Q valid indicates valid output data. QVLD is edge aligned with CQ and CQ.

indicator

ODT ^[3]

On-die

On-die termination input. This pin is used for on-die termination of the input signals. ODT range

termination selection is made during power up initialization. A LOW on this pin selects a low range that follows

input pin

RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a

high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When

left floating, a high range termination value is selected by default.

K

Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q_[x:0]. All accesses are initiated on the rising edge of K.

K

Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q_[x:0]

.

CQ

ZQ

Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.

Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.

Input

Output impedance matching input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ, and Q_[x:0]output impedance are set to 0.2 × RQ, where RQ is a resistor

connected between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

Note

3. On-die termination (ODT) feature is supported for D

, BWS

, and K/K inputs.

[x:0]

Document Number: 001-57843 Rev. *L

Page 5 of 32

CY7C2263KV18/CY7C2265KV18

Pin Definitions (continued)

Pin Name

I/O

Pin Description

DOFF

Input

PLL turn off  active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with QDR I timing.

TDO

Output

Input

N/A

TDO pin for JTAG.

TCK

TCK pin for JTAG.

TDI

TDI pin for JTAG.

TMS

TMS pin for JTAG.

NC

Not connected to the die. Can be tied to any voltage level.

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

NC/72M

NC/144M

NC/288M

V_REF

N/A

Input-

reference measurement points.

V_DD

V_SS

Power supply Power supply inputs to the core of the device.

Ground

Ground for the device.

V_DDQ

Power supply Power supply inputs for the outputs of the device.

Read Operations

Functional Overview

The CY7C2263KV18 is organized internally as four arrays of

512 K × 18. Accesses are completed in a burst of four sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K). The

address presented to the address inputs is stored in the read

address register. Following the next two K clock rise, the

corresponding lowest order 18-bit word of data is driven onto the

Q_[17:0]using K as the output timing reference. On the

subsequent rising edge of K, the next 18-bit data word is driven

onto the Q_[17:0]. This process continues until all four 18-bit data

words have been driven out onto Q_[17:0]. The requested data is

valid 0.45 ns from the rising edge of the input clock (K or K). To

maintain the internal logic, each read access must be allowed to

complete. Each read access consists of four 18-bit data words

and takes two clock cycles to complete. Therefore, read

accesses to the device can not be initiated on two consecutive

K clock rises. The internal logic of the device ignores the second

read request. Read accesses can be initiated on every other K

clock rise. Doing so pipelines the data flow such that data is

transferred out of the device on every rising edge of the input

clocks (K and K).

The CY7C2263KV18 and CY7C2265KV18 are synchronous

pipelined burst SRAMs equipped with a read port and a write

port. The read port is dedicated to read operations and the write

port is dedicated to write operations. Data flows into the SRAM

through the write port and flows out through the read port. These

devices multiplex the address inputs to minimize the number of

address pins required. By having separate read and write ports,

the QDR II+ completely eliminates the need to “turn-around” the

data bus and avoids any possible data contention, thereby

simplifying system design. Each access consists of four 18-bit

data transfers in the case of CY7C2263KV18, and four 36-bit

data transfers in the case of CY7C2265KV18, in two clock

cycles.

These devices operate with a read latency of two and half cycles

when DOFF pin is tied HIGH. When DOFF pin is set LOW or

connected to V_SSthen device behaves in QDR I mode with a

read latency of one clock cycle.

Accesses for both ports are initiated on the positive input clock

(K). All synchronous input and output timing are referenced from

the rising edge of the input clocks (K and K).

When the read port is deselected, the CY7C2263KV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tri-states the outputs following the next

rising edge of the negative input clock (K). This enables for a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

All synchronous data inputs (D_[x:0]) pass through input registers

controlled by the input clocks (K and K). All synchronous data

outputs (Q_[x:0]) outputs pass through output registers controlled

by the rising edge of the input clocks (K and K) as well.

All synchronous control (RPS, WPS, BWS_[x:0]) inputs pass

through input registers controlled by the rising edge of the input

clocks (K and K).

Write Operations

CY7C2263KV18 is described in the following sections. The

same basic descriptions apply to CY7C2265KV18.

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the following K

clock rise the data presented to D_[17:0]is latched and stored into

Document Number: 001-57843 Rev. *L

Page 6 of 32

CY7C2263KV18/CY7C2265KV18

the lower 18-bit write data register, provided BWS_[1:0]are both

asserted active. On the subsequent rising edge of the negative

input clock (K) the information presented to D_[17:0]is also stored

into the write data register, provided BWS_[1:0]are both asserted

active. This process continues for one more cycle until four 18-bit

words (a total of 72 bits) of data are stored in the SRAM. The

72 bits of data are then written into the memory array at the

specified location. Therefore, write accesses to the device can

not be initiated on two consecutive K clock rises. The internal

logic of the device ignores the second write request. Write

accesses can be initiated on every other rising edge of the

positive input clock (K). Doing so pipelines the data flow such

that 18 bits of data can be transferred into the device on every

rising edge of the input clocks (K and K).

does not affect the other port. All pending transactions (read and

write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and V_SSto allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5 × the value of the

intended line impedance driven by the SRAM, the allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175  and 350 , with V_DDQ= 1.5 V. The

output impedance is adjusted every 1024 cycles upon power-up

to account for drifts in supply voltage and temperature.

Echo Clocks

When deselected, the write port ignores all inputs after the

pending write operations are completed.

Echo clocks are provided on the QDR II+ to simplify data capture

on high speed systems. Two echo clocks are generated by the

QDR II+. CQ is referenced with respect to K and CQ is

referenced with respect to K. These are free-running clocks and

are synchronized to the input clock of the QDR II+. The timing

for the echo clocks is shown in the Switching Characteristics on

page 24.

Byte Write Operations

Byte write operations are supported by the CY7C2263KV18. A

write operation is initiated as described in the section Write

Operations on page 6. The bytes that are written are determined

by BWS₀and BWS₁, which are sampled with each set of 18-bit

data words. Asserting the appropriate byte write select input

during the data portion of a write latches the data being

presented and writes it into the device. Deasserting the byte

write select input during the data portion of a write enables the

data stored in the device for that byte to remain unaltered. This

feature can be used to simplify read, modify, or write operations

to a byte write operation.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR II+ to simplify data capture on high

speed systems. The QVLD is generated by the QDR II+ device

along with data output. This signal is also edge-aligned with the

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

On-Die Termination (ODT)

Concurrent Transactions

These devices have an on-die termination feature for data inputs

(D_[x:0]), byte write selects (BWS_[x:0]), and input clocks (K and K).

The termination resistors are integrated within the chip. The ODT

range selection is enabled through ball R6 (ODT pin). The ODT

termination tracks value of RQ where RQ is the resistor tied to

the ZQ pin. ODT range selection is made during power-up

initialization. A LOW on this pin selects a low range that follows

RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied

to ZQ pin)A HIGH on this pin selects a high range that follows

RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied

to ZQ pin). When left floating, a high range termination value is

selected by default. For a detailed description on the ODT

implementation, refer to the application note, On-Die Termination

for QDRII+/DDRII+ SRAMs.

The read and write ports on the CY7C2263KV18 operates

completely independently of one another. As each port latches

the address inputs on different clock edges, the user can read or

write to any location, regardless of the transaction on the other

port. If the ports access the same location when a read follows a

write in successive clock cycles, the SRAM delivers the most

recent information associated with the specified address

location. This includes forwarding data from a write cycle that

was initiated on the previous K clock rise.

Read access and write access must be scheduled such that one

transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on the

previous state of the SRAM. If both ports are deselected, the

read port takes priority. If a read was initiated on the previous

cycle, the write port takes priority (as read operations can not be

initiated on consecutive cycles). If a write was initiated on the

previous cycle, the read port takes priority (as write operations

can not be initiated on consecutive cycles). Therefore, asserting

both port selects active from a deselected state results in

alternating read or write operations being initiated, with the first

access being a read.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power-up, when the DOFF is tied HIGH, the PLL is locked after

20 s of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20 s after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR I mode (with one cycle latency and a longer

access time). For information, refer to the application note, PLL

Considerations in QDRII/DDRII/QDRII+/DDRII+.

Depth Expansion

The CY7C2263KV18 has a port select input for each port. This

enables for easy depth expansion. Both port selects are sampled

on the rising edge of the positive input clock only (K). Each port

select input can deselect the specified port. Deselecting a port

Document Number: 001-57843 Rev. *L

Page 7 of 32

CY7C2263KV18/CY7C2265KV18

Application Example

Figure 2 shows two QDR II+ used in an application.

Figure 2. Application Example (Width Expansion)

ZQ

CQ/CQ

Q[x:0]

ZQ

CQ/CQ

Q[x:0]

SRAM#1

D[x:0]

SRAM#2

RQ

D[x:0]

A

RPS WPS BWS

K

A

RPS WPS BWS

K

DATA IN[2x:0]

DATA OUT [2x:0]

ADDRESS

RPS

WPS

BWS

CLKIN1/CLKIN1

CLKIN2/CLKIN2

SOURCE K

FPGA / ASIC

Document Number: 001-57843 Rev. *L

Page 8 of 32

CY7C2263KV18/CY7C2265KV18

Truth Table

The truth table for CY7C2263KV18, and CY7C2265KV18 follows. ^{[4, 5, 6, 7, 8, 9]}

Operation

Write cycle:

K

RPS WPS

DQ

L–H

H ^[10]L ^[11]D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

Read cycle:

(2.5 cycle latency)

L–H

L ^[11]

X

Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)

Load address on the rising

edge of K; wait two and

half cycles; read data on

two consecutive K and K

rising edges.

NOP: No Operation

L–H

H

X

H

X

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

Standby: Clock stopped

Stopped

Previous state

Notes

^{4. X = “Don't Care”, H = Logic HIGH, L = Logic LOW,}represents rising edge.

5. Device powers up deselected with the outputs in a tri-state condition.

6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and thirdclock cycles respectively succeeding the “t” clock cycle.

8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.

9. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

10. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

11. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.

Document Number: 001-57843 Rev. *L

Page 9 of 32

CY7C2263KV18/CY7C2265KV18

Write Cycle Descriptions

The write cycle description table for CY7C2263KV18 follows. ^{[12, 13]}

BWS₀BWS₁

K

Comments

K

L

L–H

–

During the data portion of a write sequence

CY7C2263KV18 both bytes (D_[17:0]) are written into the device.

L

–

L–H

–

L–H During the data portion of a write sequence:

CY7C2263KV18 both bytes (D_[17:0]) are written into the device.

L

H

L

–

During the data portion of a write sequence:

CY7C2263KV18 only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

L

L–H During the data portion of a write sequence

CY7C2263KV18 only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

H

L–H

–

During the data portion of a write sequence

CY7C2263KV18 only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

L

L–H During the data portion of a write sequence

CY7C2263KV18 only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

H

L–H

–

No data is written into the devices during this portion of a write operation.

L–H No data is written into the devices during this portion of a write operation.

Note

^{12. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,}represents rising edge.

13. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a

0

1

2

3

write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-57843 Rev. *L

Page 10 of 32

CY7C2263KV18/CY7C2265KV18

Write Cycle Descriptions

The write cycle description table for CY7C2265KV18 follows. ^{[14, 15]}

BWS₀BWS₁BWS₂BWS₃

K

Comments

L

L–H

–

During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

L

–

L–H

–

L–H During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

L

H

L

H

L

H

L

–

During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

L

L–H During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[17:9]) is written into the

device. D_[8:0]and D_[35:18]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[17:9]) is written into the

device. D_[8:0]and D_[35:18]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

H

L–H

–

No data is written into the device during this portion of a write operation.

L–H No data is written into the device during this portion of a write operation.

Notes

^{14. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,}represents rising edge.

15. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a

0

1

2

3

write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-57843 Rev. *L

Page 11 of 32

CY7C2263KV18/CY7C2265KV18

Instruction Register

IEEE 1149.1 Serial Boundary Scan (JTAG)

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO pins, as shown in TAP Controller Block Diagram on

page 15. Upon power-up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state, as described

in the previous section.

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant with

IEEE Standard #1149.1-2001. The TAP operates using JEDEC

standard 1.8 V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternatively be connected to V_DDthrough a pull-up resistor. TDO

must be left unconnected. Upon power-up, the device comes up

in a reset state, which does not interfere with the operation of the

device.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This enables shifting of data through the SRAM

with minimal delay. The bypass register is set LOW (V_SS) when

the BYPASS instruction is executed.

Test Access Port

Test Clock

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Boundary Scan Register

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several No Connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The pin is pulled up

internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. For information about

loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order on page 19 shows the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 18.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from the

registers. The output is active, depending upon the current state

of the TAP state machine (see Instruction Codes on page 18).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 18. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in this section in detail.

A reset is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This reset does not affect the operation of the

SRAM and can be performed while the SRAM is operating. At

power-up, the TAP is reset internally to ensure that TDO comes

up in a high Z state.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction after it is shifted in, the TAP controller must be

moved into the Update-IR state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction registers. Data

is serially loaded into the TDI pin on the rising edge of TCK. Data

is output on the TDO pin on the falling edge of TCK.

Document Number: 001-57843 Rev. *L

Page 12 of 32

CY7C2263KV18/CY7C2265KV18

IDCODE

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells before the selection

of another boundary scan test operation.

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO pins and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state. The

IDCODE instruction is loaded into the instruction register at

power up or whenever the TAP controller is supplied a

Test-Logic-Reset state.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required, that is, while the data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a high Z state until the next command is supplied during the

Update IR state.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the Shift-DR controller state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output undergoes a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This does not harm the device, but

there is no guarantee as to the value that is captured.

Repeatable results may not be possible.

The boundary scan register has a special bit located at bit #108.

When this scan cell, called the “extest output bus tri-state,” is

latched into the preload register during the Update-DR state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

high Z condition.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

times (t_CSand t_CH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK captured in the boundary scan register.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the Shift-DR state. During Update-DR, the value loaded

into that shift-register cell latches into the preload register. When

the EXTEST instruction is entered, this bit directly controls the

output Q-bus pins. Note that this bit is preset HIGH to enable the

output when the device is powered up, and also when the TAP

controller is in the Test-Logic-Reset state.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document Number: 001-57843 Rev. *L

Page 13 of 32

CY7C2263KV18/CY7C2265KV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. ^[16]

TEST-LOGIC

1

RESET

0

1

SELECT

TEST-LOGIC/

SELECT

0

IR-SCAN

IDLE

DR-SCAN

0

1

CAPTURE-DR

0

CAPTURE-IR

0

1

0

1

SHIFT-DR

1

SHIFT-IR

1

EXIT1-DR

0

EXIT1-IR

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-IR

0

UPDATE-DR

1

0

Note

16. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-57843 Rev. *L

Page 14 of 32

CY7C2263KV18/CY7C2265KV18

TAP Controller Block Diagram

0

Bypass Register

2

1

0

Selection

TDI

Selection

Circuitry

TDO

Instruction Register

Circuitry

31 30

29

.

2

Identification Register

.

108

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics

Over the Operating Range

Parameter ^{[17, 18, 19]}

Description

Output HIGH voltage

Output LOW voltage

Input HIGH voltage

Input LOW voltage

Test Conditions

I_OH=2.0 mA

Min

1.4

1.6

–

Max

–

Unit

V

V_OH1

V_OH2

V_OL1

V_OL2

V_IH

I_OH=100 A

I_OL= 2.0 mA

I_OL= 100 A

–

V

0.4

0.2

V

–

V

0.65 × V_DDV_DD+ 0.3

V

V_IL

–0.3

–5

0.35 × V_DD

5

V

I_X

Input and output load current

GND  V_I V_DD

A

Notes

17. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 21.

18. Overshoot: V < V + 0.35 V (Pulse width less than t /2), Undershoot: V /2).

> -0.3 V (Pulse width less than t

CYC

IH(AC)

DDQ

CYC

IL(AC)

19. All voltage referenced to ground.

Document Number: 001-57843 Rev. *L

Page 15 of 32

CY7C2263KV18/CY7C2265KV18

TAP AC Switching Characteristics

Over the Operating Range

Parameter ^{[20, 21]}

Description

Min

50

–

Max

–

Unit

ns

t_TCYC

TCK clock cycle time

TCK clock frequency

TCK clock HIGH

t_TF

20

–

MHz

ns

t_TH

20

t_TL

TCK clock LOW

–

ns

Setup Times

t_TMSS

t_TDIS

TMS set-up to TCK clock rise

TDI set-up to TCK clock rise

Capture set-up to TCK rise

5

–

ns

t_CS

Hold Times

t_TMSH

t_TDIH

TMS hold after TCK clock rise

TDI hold after clock rise

5

–

ns

t_CH

Capture hold after clock rise

Output Times

t_TDOV

t_TDOX

TCK clock LOW to TDO valid

TCK clock LOW to TDO invalid

–

0

10

–

ns

Notes

20. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

CS

CH

21. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

R

F

Document Number: 001-57843 Rev. *L

Page 16 of 32

CY7C2263KV18/CY7C2265KV18

TAP Timing and Test Conditions

Figure 3 shows the TAP timing and test conditions. ^[22]

Figure 3. TAP Timing and Test Conditions

0.9V

ALL INPUT PULSES

1.8V

0.9V

50

TDO

0V

Z = 50



0

C = 20 pF

L

t_TL

t_TH

GND

(a)

Test Clock

TCK

t_TCYC

t_TMSH

t_TMSS

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data In

TDI

Test Data Out

TDO

t_TDOV

t_TDOX

Note

22. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

R

F

Document Number: 001-57843 Rev. *L

Page 17 of 32

CY7C2263KV18/CY7C2265KV18

Identification Register Definitions

Value

Instruction Field

Description

CY7C2263KV18

000

CY7C2265KV18

000

11010010001100111 Defines the type of SRAM.

Revision number (31:29)

Cypress device ID (28:12)

Cypress JEDEC ID (11:1)

Version number.

11010010001010111

00000110100

Allows unique identification of SRAM

vendor.

ID register presence (0)

1

Indicates the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

3

1

ID

32

109

Boundary scan

Instruction Codes

Instruction

EXTEST

Code

000

Description

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a high Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document Number: 001-57843 Rev. *L

Page 18 of 32

CY7C2263KV18/CY7C2265KV18

Boundary Scan Order

Bit #

0

Bump ID

6R

Bit #

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Bump ID

10G

9G

Bit #

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

Bump ID

6A

Bit #

84

Bump ID

1J

1

6P

5B

5A

85

2J

2

6N

11F

11G

9F

86

3K

3

7P

4A

87

3J

4

7N

5C

4B

88

2K

5

7R

10F

11E

10E

10D

9E

89

1K

6

8R

3A

90

2L

7

8P

2A

91

3L

8

9R

1A

92

1M

1L

9

11P

10P

10N

9P

2B

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

10C

11D

9C

3B

94

3N

1C

1B

95

3M

1N

96

10M

11N

9M

9D

3D

3C

1D

2C

3E

97

2M

3P

11B

11C

9B

98

99

2N

9N

100

101

102

103

104

105

106

107

108

2P

11L

11M

9L

10B

11A

10A

9A

1P

2D

2E

3R

4R

10L

11K

10K

9J

1E

4P

8B

2F

5P

7C

3F

5N

6C

1G

1F

5R

9K

8A

Internal

10J

11J

11H

7A

3G

2G

1H

7B

6B

Document Number: 001-57843 Rev. *L

Page 19 of 32

CY7C2263KV18/CY7C2265KV18

PLL Constraints

Power Up Sequence in QDR II+ SRAM

■ PLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t_{KC Var}

QDR II+ SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

.

■ The PLL functions at frequencies down to 120 MHz.

Power Up Sequence

■ If the input clock is unstable and the PLL is enabled, then the

PLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide 20 s of stable clock to

relock to the desired clock frequency.

■ Apply power and drive DOFF either HIGH or LOW (all other

inputs can be HIGH or LOW).

❐ Apply V_DDbefore V_DDQ

.

❐ Apply V_DDQbefore V_REFor at the same time as V_REF

.

❐ Drive DOFF HIGH.

■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s

to lock the PLL.

Figure 4. Power Up Waveforms

K

Unstable Clock

> 20μs Stable clock

Stable)

DDQ

Start Normal

Operation

/

V

Clock Start (Clock Starts after V

DD

Stable (< +/- 0.1V DC per 50ns )

/

V

V_DDQ

V

V_DD

DD

DDQ

Fix HIGH (or tie to V

)

DDQ

DOFF

Document Number: 001-57843 Rev. *L

Page 20 of 32

CY7C2263KV18/CY7C2265KV18

Maximum Ratings

Operating Range

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Ambient

[24]

Range

Commercial

Industrial

Temperature (T_A)

V_DD

V_DDQ

Storage temperature ................................ –65 °C to +150 °C

0 °C to +70 °C

1.8 ± 0.1 V 1.4 V to

V_DD

Ambient temperature

with power applied ................................... –55 °C to +125 °C

–40 °C to +85 °C

Supply voltage on V_DDrelative to GND .......–0.5 V to +2.9 V

Supply voltage on V_DDQrelative to GND ...... –0.5 V to +V_DD

DC applied to outputs in high Z ........–0.5 V to V_DDQ+ 0.3 V

DC input voltage ^[23]...........................–0.5 V to V_DD+ 0.3 V

Current into outputs (LOW) ........................................ 20 mA

Neutron Soft Error Immunity

Test

Parameter Description

Conditions

Typ Max* Unit

LSBU

LMBU

SEL

Logical

single-bit

upsets

25 °C

85 °C

197

216 FIT/

Mb

Static discharge voltage

(MIL-STD-883, M. 3015) ........................................> 2,001 V

Latch-up current ....................................................> 200 mA

Logical

multi-bit

upsets

0

0.01 FIT/

Mb

Single event

latch-up

0

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

2

statistical  , 95% confidence limit calculation. For more details refer to Application

Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial

Failure Rates”

Electrical Characteristics

Over the Operating Range

DC Electrical Characteristics

Over the Operating Range

Parameter ^[25]

V_DD

Description

Power supply voltage

I/O supply voltage

Test Conditions

Min

1.7

Typ

1.8

1.5

–

Max

Unit

V

1.9

V_DD

V_DDQ

V_OH

1.4

V

Output HIGH voltage

Output LOW voltage

Output HIGH voltage

Output LOW voltage

Input HIGH voltage

Input LOW voltage

Input leakage current

Output leakage current

Note 26

Note 27

V_DDQ/2 – 0.12

V_DDQ– 0.2

V_SS

V_DDQ/2 + 0.12

V_DDQ

V

V_OL

–

V

V_OH(LOW)

V_OL(LOW)

V_IH

I_OH=0.1 mA, nominal impedance

–

V

I_OL= 0.1 mA, nominal impedance

–

0.2

V

V_REF+ 0.1

–0.15

–

V_DDQ+ 0.15

V_REF– 0.1

2

V

V_IL

–

V

I_X

GND  V_I V_DDQ

–2

–

A

V

I_OZ

GND  V_I V_DDQ,output disabled

–2

–

2

V_REF

Input reference voltage ^[28]Typical value = 0.75 V

0.68

0.75

0.95

Notes

23. Overshoot: V

24. Power-up: Assumes a linear ramp from 0 V to V

< V

+ 0.35 V (Pulse width less than t

/2), Undershoot: V

> -0.3 V (Pulse width less than t

/2).

CYC

IH(AC)

DDQ

CYC

IL(AC)

within 200 ms. During this time V < V and V

< V

.

DD

DD(min)

IH

DD

DDQ

25. All voltage referenced to ground.

26. Output are impedance controlled. I = (V

/2)/(RQ/5) for values of 175   RQ  350 .

DDQ

OH

27. Output are impedance controlled. I = (V

/2)/(RQ/5) for values of 175   RQ  350 .

OL

28. V

= 0.68 V or 0.46 V

, whichever is larger, V

= 0.95 V or 0.54 V

, whichever is smaller.

REF(min)

DDQ

REF(max)

DDQ

Document Number: 001-57843 Rev. *L

Page 21 of 32

CY7C2263KV18/CY7C2265KV18

Electrical Characteristics (continued)

Over the Operating Range

DC Electrical Characteristics (continued)

Over the Operating Range

Parameter ^[25]

Description

Test Conditions

Min

–

Typ

–

Max

850

1210

720

1020

920

360

330

310

Unit

[29]

I_DD

V_DDoperating supply

V_DD= Max, I_OUT= 0 mA, 550 MHz (× 18)

f = f_MAX= 1/t_CYC

mA

(× 36)

–

450 MHz (× 18)

(× 36)

–

mA

–

400 MHz (× 36)

–

I_SB1

Automatic power-down

current

Max V_DD

,

550 MHz (× 18)

(× 36)

–

mA

both ports deselected,

–

V_IN V_IHor V_IN V_IL,

f = f_MAX= 1/t_CYC

inputs static

,

450 MHz (× 18)

(× 36)

–

400 MHz (× 36)

–

Note

29. The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-57843 Rev. *L

Page 22 of 32

CY7C2263KV18/CY7C2265KV18

AC Electrical Characteristics

Over the Operating Range

Parameter ^[30]

Description

Input HIGH voltage

Input LOW voltage

Test Conditions

Min

V_REF+ 0.2

–0.24

Typ

–

Max

Unit

V

V_IH

V_IL

V_DDQ+ 0.24

V_REF– 0.2

–

V

Capacitance

Parameter ^[31]

Description

Input capacitance

Output capacitance

Test Conditions

Max

4

Unit

pF

C_IN

C_O

T_A= 25 C, f = 1 MHz, V_DD= 1.8 V, V_DDQ= 1.5 V

4

pF

Thermal Resistance

165-ballFBGA

Package

Parameter ^[31]

Description

Test Conditions

Unit



_JA(0 m/s)

_JA(1 m/s)

_JA(3 m/s)

Thermal resistance

(junction to ambient)

Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit

board

16.72

15.67

14.92

13.67

°C/W

_JB

Thermal resistance

(junction to board)

_JC

Thermal resistance

(junction to case)

4.54

°C/W

AC Test Loads and Waveforms

Figure 5. AC Test Loads and Waveforms

V_REF= 0.75 V

0.75 V

V_REF

0.75 V

R = 50 

OUTPUT

[32]

ALL INPUT PULSES

1.25 V

Z = 50 

0

OUTPUT

Device

R = 50 

L

0.75 V

Under

Device

Under

0.25 V

Test

5 pF

V_REF= 0.75 V

Slew Rate = 2 V/ns

ZQ

Test

ZQ

RQ =

250

(b)



250



INCLUDING

JIG AND

SCOPE

(a)

Notes

30. Overshoot: V

< V

+ 0.35 V (Pulse width less than t

/2), Undershoot: V

> -0.3 V (Pulse width less than t

/2).

IH(AC)

DDQ

CYC

IL(AC)

CYC

31. Tested initially and after any design or process change that may affect these parameters.

32. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V

= 1.5 V, input

DDQ

pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.

OL OH

Document Number: 001-57843 Rev. *L

Page 23 of 32

CY7C2263KV18/CY7C2265KV18

Switching Characteristics

Over the Operating Range

Parameters ^{[33, 34]}

550 MHz

450 MHz

400 MHz

Description

Unit

Consortium

Parameter

Cypress

Parameter

Min Max Min Max Min Max

t_POWER

t_CYC

t_KH

V_DD(typical) to the first access ^[35]

K clock cycle time

1

–

1

–

8.4

–

1

–

8.4

–

ms

ns

t_KHKH

t_KHKL

t_KLKH

t_KHKH

1.81 8.4

2.2

0.4

0.94

2.5

0.4

1.06

0.4

–

Input clock (K/K) HIGH

t_KL

–

Input clock (K/K) LOW

t_KHKH

0.77

–

K clock rise to K clock rise (rising edge to rising edge)

Setup Times

t_SA

t_AVKH

t_IVKH

Address set-up to K clock rise

0.23

–

0.275

0.22

–

0.4

–

ns

t_SC

Control set-up to K clock rise (RPS, WPS)

t_SCDDR

Double datarate controlset-upto clock (K/K) rise (BWS₀, 0.18

BWS₁, BWS₂, BWS₃)

0.28

t_SD

t_DVKH

0.18

–

0.22

–

0.28

–

ns

D_[X:0]set-up to clock (K/K) rise

Hold Times

t_HA

t_KHAX

t_KHIX

0.23

0.18

–

0.275

0.22

–

0.4

–

ns

Address hold after K clock rise

t_HC

Control hold after K clock rise (RPS, WPS)

t_HCDDR

Double data rate control hold after clock (K/K) rise

(BWS₀, BWS₁, BWS₂, BWS₃)

0.28

t_HD

t_KHDX

0.18

–

0.22

–

0.28

–

ns

D_[X:0]hold after clock (K/K) rise

Notes

33. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V

= 1.5 V, input

DDQ

pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 23.

OL OH

34. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

35. This part has a voltage regulator internally; t

initiated.

is the time that the power must be supplied above V minimum initially before a read or write operation can be

DD

POWER

Document Number: 001-57843 Rev. *L

Page 24 of 32

CY7C2263KV18/CY7C2265KV18

Switching Characteristics (continued)

Over the Operating Range

Parameters ^{[33, 34]}

550 MHz

450 MHz

400 MHz

Description

Unit

Consortium

Parameter

Cypress

Parameter

Min Max Min Max Min Max

Output Times

t_CO

t_CHQV

–

0.45

–

0.45

–

0.45

–

ns

K/K clock rise to data valid

t_DOH

t_CHQX

–0.45

Data output hold after output K/K clock rise (active to

active)

t_CCQO

t_CQOH

t_CQD

t_CHCQV

t_CHCQX

t_CQHQV

t_CQHQX

t_CQHCQL

t_CQHCQH

–

0.45

–

0.45

–

–0.45

–

0.45

–

ns

K/K clock rise to echo clock valid

Echo clock hold after K/K clock rise

Echo clock high to data valid

–0.45

–

–0.45

–

0.15

–

0.15

–

0.20

–

t_CQDOH

t_CQH

Echo clock high to data invalid

Output clock (CQ/CQ) HIGH ^[36]

–0.15

0.655

–0.15

0.85

–0.20

1.0

–

t_CQHCQH

CQ clock rise to CQ clock rise

(rising edge to rising edge) ^[36]

–

1.0

–

Clock (K/K) rise to high Z (active to high Z) ^{[37, 38]}

Clock (K/K) rise to low Z ^{[37, 38]}

Echo clock high to QVLD valid ^[39]

t_CHZ

t_CHQZ

–

0.45

–

0.45

–

0.45

–

ns

t_CLZ

t_CHQX1

t_CQHQVLD

–0.45

t_QVLD

–0.15 0.15 –0.15 0.15 –0.20 0.20

PLL Timing

t_{KC Var}

t_{KC lock}

t_{KC Reset}

t_{KC Var}

Clock phase jitter

–

0.15

–

0.15

–

0.20

–

ns

s

ns

t_{KC lock}

t_{KC Reset}

PLL lock time (K)

K static to PLL reset ^[40]

20

30

20

30

20

30

–

Notes

36. These parameters are extrapolated from the input timing parameters (t

/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by

CYC

design and are not tested in production.

37. t

, t

, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured ±100 mV from steady-state voltage.

CHZ CLZ

38. At any given voltage and temperature t

is less than t

and t

less than t

.

CHZ

CLZ

CHZ

CO

39. t

spec is applicable for both rising and falling edges of QVLD signal.

QVLD

40. Hold to > V or < V .

IH

IL

Document Number: 001-57843 Rev. *L

Page 25 of 32

CY7C2263KV18/CY7C2265KV18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 6. Waveform for 2.5 Cycle Read Latency ^{[41, 42, 43]}

WRITE

3

READ

4

NOP

1

READ

2

WRITE

5

NOP

6

7

8

K

t

KL

t

KH

CYC

KHKH

K

RPS

t

SC HC

t

SC

HC

WPS

A

A0

A1

A2

A3

t

HD

t

HD

SA

HA

t

SD

t

SD

D11

D12

D10

QVLD

D30

D32

D33

t

D13

D31

D

QVLD

t

QVLD

t

DOH

t

CQDOH

CO

t

CHZ

t

CLZ

t

CQD

Q

Q00 Q01 Q02

CCQO

Q20 Q21 Q22

Q23

Q03

(Read Latency = 2.5 Cycles)

CQOH

CQ

CCQO

t

CQHCQH

CQH

CQOH

DON’T CARE

UNDEFINED

Notes

41. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

42. Outputs are disabled (high Z) one clock cycle after a NOP.

43. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note

applies to the whole diagram.

Document Number: 001-57843 Rev. *L

Page 26 of 32

CY7C2263KV18/CY7C2265KV18

Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local

sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at

http://www.cypress.com/products

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office

closest to you, visit us at http://www.cypress.com/go/datasheet/offices.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

550 CY7C2265KV18-550BZXC

CY7C2265KV18-550BZXI

51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free

165-ball FBGA (13 × 15 × 1.4 mm) Pb-free

51-85180 165-ball FBGA (13 × 15 × 1.4 mm)

165-ball FBGA (13 × 15 × 1.4 mm) Pb-free

51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free

Commercial

Industrial

CY7C2263KV18-550BZXI

CY7C2263KV18-550BZXC

450 CY7C2265KV18-450BZC

CY7C2263KV18-450BZXI

Commercial

Industrial

400 CY7C2265KV18-400BZXI

Industrial

Ordering Code Definitions

CY

7

C 22XX K V18 - XXX BZ

X

Temperature Range: X = C or I

C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C

X = Pb-free; X Absent = Leaded

Package Type:

BZ = 165-ball FBGA

Speed Grade: XXX = 550 MHz or 450 MHz or 400 MHz

V18 = 1.8 V V_DD

Process Technology: K = 65 nm

Part Identifier: 22XX = 2263 or 2265

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

Document Number: 001-57843 Rev. *L

Page 27 of 32

CY7C2263KV18/CY7C2265KV18

Package Diagram

Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180

51-85180 *G

Document Number: 001-57843 Rev. *L

Page 28 of 32

CY7C2263KV18/CY7C2265KV18

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

Description

DDR

EIA

Double Data Rate

Unit of Measure

Electronic Industries Alliance

Fine-Pitch Ball Grid Array

High-Speed Transceiver Logic

Input/Output

°C

k

MHz

µA

µs

degree Celsius

kilohm

FBGA

HSTL

I/O

megahertz

microampere

microsecond

milliampere

millimeter

millisecond

millivolt

JEDEC

JTAG

LMBU

LSB

Joint Electron Devices Engineering Council

Joint Test Action Group

Logical Multiple Bit Upset

Least Significant Bit

Logical Single Bit Upset

Most Significant Bit

mA

mm

ms

mV

ns

LSBU

MSB

ODT

PLL

nanosecond

ohm



On-Die Termination

pF

%

picofarad

percent

Phase Locked Loop

Quad Data Rate

QDR

SEL

V

volt

Single Event Latch-Up

Static Random Access Memory

Test Access Port

W

watt

SRAM

TAP

TCK

TDI

Test Clock

Test Data-In

TDO

TMS

Test Data-Out

Test Mode Select

Document Number: 001-57843 Rev. *L

Page 29 of 32

CY7C2263KV18/CY7C2265KV18

Document History Page

Document Title: CY7C2263KV18/CY7C2265KV18, 36-Mbit QDR^®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read

Latency) with ODT

Document Number: 001-57843

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

2816636

VKN /

AESA

11/30/09

New data sheet.

*A

*B

2886418

3068547

NJY

03/02/2010 Updated Switching Characteristics (Changed minimum value of t_HCDDRand

_HCparameters from 0.28 ns to 0.22 ns at 450 MHz).

t

Updated Package Diagram.

Updated links in Sales, Solutions, and Legal Information.

NJY

10/22/2010 Changed status from Preliminary to Final.

Added Ordering Code Definitions.

Minor edits.

Updated to new template.

*C

*D

3420727

3598211

PRIT

10/24/2011 Updated Ordering Information (Updated part numbers).

Added Acronyms and Units of Measure.

04/24/2012 Updated Features (Removed CY7C2261KV18, CY7C2276KV18 related

information).

Updated Configurations (Removed CY7C2261KV18, CY7C2276KV18 related

information).

Updated Functional Description (Removed CY7C2261KV18, CY7C2276KV18

related information).

Updated Selection Guide (Removed 400 MHz and 500 MHz frequencies

related information, removed CY7C2261KV18, CY7C2276KV18 related

information).

Removed Logic Block Diagram – CY7C2261KV18.

Removed Logic Block Diagram – CY7C2276KV18.

Updated Pin Configurations (Removed CY7C2261KV18, CY7C2276KV18

related information).

Updated Pin Definitions (Removed CY7C2261KV18, CY7C2276KV18 related

information).

Updated Functional Overview (Removed CY7C2261KV18, CY7C2276KV18

related information).

Updated Truth Table (Removed CY7C2261KV18, CY7C2276KV18 related

information).

Updated Write Cycle Descriptions (Removed CY7C2261KV18 related

information).

Removed Write Cycle Descriptions (Corresponding to CY7C2276KV18).

Updated Identification Register Definitions (Removed CY7C2261KV18,

CY7C2276KV18 related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics

(Removed 400 MHz and 500 MHz frequencies related information, removed

CY7C2261KV18, CY7C2276KV18 related information)).

Updated Switching Characteristics (Removed 400 MHz and 500 MHz

frequencies related information).

Updated Package Diagram (spec 51-85180 (Changed revision from *C to *E)).

*E

*F

3793924

4055612

PRIT

10/25/2012 Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).

07/10/2013 Updated Selection Guide (Included 400 MHz frequency related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics

(Included 400 MHz frequency related information).

Updated Switching Characteristics (Included 400 MHz frequency related

information).

Updated Ordering Information (Updated part numbers).

Updated to new template.

Document Number: 001-57843 Rev. *L

Page 30 of 32

CY7C2263KV18/CY7C2265KV18

Document History Page (continued)

Document Title: CY7C2263KV18/CY7C2265KV18, 36-Mbit QDR^®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read

Latency) with ODT

Document Number: 001-57843

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*G

4119342

PRIT

09/10/2013 Updated Selection Guide (Included 500 MHz frequency related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics

(Included 500 MHz frequency related information)).

Updated Switching Characteristics (Included 500 MHz frequency related

information).

Updated Ordering Information (Updated part numbers).

*H

4172707

4374046

10/24/2013 Updated Selection Guide (Removed 500 MHz frequency related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics

(Removed 500 MHz frequency related information)).

Updated Switching Characteristics (Removed 500 MHz frequency related

information).

Updated Ordering Information (Updated part numbers).

Completing Sunset Review.

*I

PRIT

05/08/2014 Updated Application Example:

Updated Figure 2.

Updated Thermal Resistance:

Updated values of _JAand _JCparameters.

Included _JBparameter and its details.

*J

4411924

4567876

PRIT

06/18/2014 Updated Ordering Information (Updated part numbers).

*K

11/12/2014 Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Ordering Information:

Updated part numbers.

*L

5070907

PRIT

01/04/2016 Updated Package Diagram:

spec 51-85180 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

Document Number: 001-57843 Rev. *L

Page 31 of 32

CY7C2263KV18/CY7C2265KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/memory

cypress.com/go/psoc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Memory

Community | Forums | Blogs | Video | Training

Technical Support

PSoC

cypress.com/go/support

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-57843 Rev. *L

Revised January 4, 2016

Page 32 of 32

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document

may be the trademarks of their respective holders.


型号：	CY7C2263KV18
厂家：	CYPRESS
描述：	36-Mbit QDRÂ® II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 静态存储器
文件：	总32页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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