CY7C2270XV18
更新时间:2024-09-18 12:53:14
品牌:CYPRESS
描述:36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
CY7C2270XV18 概述
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36兆位的DDR II的Xtreme SRAM双字突发架构( 2.5周期读延迟)与ODT
CY7C2270XV18 数据手册
通过下载CY7C2270XV18数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CY7C2268XV18, CY7C2270XV18
36-Mbit DDR II+ Xtreme SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
Configurations
■ 36-Mbit density (2 M × 18, 1 M × 36)
With Read Cycle Latency of 2.5 cycles:
CY7C2268XV18 – 2 M × 18
■ 633 MHz clock for high bandwidth
CY7C2270XV18 – 1 M × 36
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
1266 MHz) at 633 MHz
Functional Description
The CY7C2268XV18, and CY7C2270XV18 are 1.8 V
Synchronous Pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two 18-bit words
(CY7C2268XV18), or 36-bit words (CY7C2270XV18) that burst
sequentially into or out of the device.
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-die termination (ODT) feature
❐ Supported for DQ[x:0], BWS[x:0], and K/K inputs
These devices have an On-Die Termination feature supported
for DQ[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
■ Synchronous internally self-timed writes
■ DDR II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
■ Operates similar to DDR I Device with 1 cycle read latency
when DOFF is asserted LOW
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
633 MHz
633
600 MHz Unit
600
910
MHz
mA
Maximum Operating Current
× 18
× 36
965
1230
1165
Cypress Semiconductor Corporation
Document Number: 001-70332 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 25, 2012
CY7C2268XV18, CY7C2270XV18
Logic Block Diagram – CY7C2268XV18
Write
Reg
Write
Reg
20
A
(19:0)
Address
Register
18
LD
K
K
Output
R/W
CLK
Logic
Gen.
Control
DOFF
Read Data Reg.
36
18
CQ
V
REF
18
Reg.
Reg.
Reg.
CQ
Control
Logic
R/W
18
18
BWS
[1:0]
DQ
18
[17:0]
QVLD
Logic Block Diagram – CY7C2270XV18
Write
Reg
Write
Reg
19
A
(18:0)
Address
Register
36
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
36
36
BWS
[3:0]
DQ
[35:0]
QVLD
Document Number: 001-70332 Rev. *B
Page 2 of 29
CY7C2268XV18, CY7C2270XV18
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................7
DDR Operation ............................................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
Valid Data Indicator (QVLD) ........................................7
On-Die Termination (ODT) ..........................................7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................9
Write Cycle Descriptions .................................................9
Write Cycle Descriptions ...............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port .......................................................11
Performing a TAP Reset ...........................................11
TAP Registers ...........................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Electrical Characteristics ......................................14
TAP AC Switching Characteristics ...............................15
TAP Timing and Test Conditions ..................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Power Up Sequence in DDR II+ Xtreme SRAM ............19
Power Up Sequence .................................................19
PLL Constraints .........................................................19
Maximum Ratings ...........................................................20
Neutron Soft Error Immunity .........................................20
Operating Range .............................................................20
Electrical Characteristics ...............................................20
DC Electrical Characteristics .....................................20
AC Electrical Characteristics .....................................21
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Read/Write/Deselect Sequence ................................24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Diagram ............................................................26
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measure .......................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC Solutions .........................................................29
Document Number: 001-70332 Rev. *B
Page 3 of 29
CY7C2268XV18, CY7C2270XV18
Pin Configurations
The pin configuration for CY7C2268XV18, and CY7C2270XV18 follows. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C2268XV18 (2 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
3
4
5
BWS1
NC/288M
A
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
A
B
C
D
E
F
A
R/W
A
LD
NC
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
QVLD
ODT
A
NC
DQ0
TDI
TCK
A
A
A
A
TMS
CY7C2270XV18 (1 M × 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
A
10
NC/72M
NC
11
A
B
C
D
E
F
A
R/W
A
LD
CQ
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
QVLD
ODT
A
DQ9
TMS
TCK
A
A
A
A
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-70332 Rev. *B
Page 4 of 29
CY7C2268XV18, CY7C2270XV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q[x:0] are automatically tri-stated.
CY7C2268XV18 DQ[17:0]
CY7C2270XV18 DQ[35:0]
LD
Input-
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C2268XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2270XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2 M × 18 (2 arrays each of 1 M × 18) for CY7C2268XV18, and 1 M × 36 (2 arrays each of
512 K × 36) for CY7C2270XV18. The address pins (A) can be assigned any bit order.
R/W
Input-
Synchronous Read or Write input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
ODT [2]
On-Die
On-Die Termination Input. This pin is used for On-Die termination of the input signals. ODT range
Termination selection is made during power up initialization. A LOW on this pin selects a low range that follows
input pin
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
K
to drive out data through Q[x:0]
.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on
page 23.
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+ Xtreme. The timing for the echo clocks is shown in the Switching Characteristics on
page 23.
CQ
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Note
2. On-Die Termination (ODT) feature is supported for DQ
, BWS
, and K/K inputs. ODT is enabled only during write operation and disabled during read operation.
[x:0]
[x:0]
Document Number: 001-70332 Rev. *B
Page 5 of 29
CY7C2268XV18, CY7C2270XV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
DOFF
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10 k or less pull up resistor. The device behaves in
DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with DDR I timing.
TDO
Output
Input
Input
Input
N/A
TDO Pin for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/72M
NC/144M
NC/288M
VREF
Input
Input
Input
Input-
Reference measurement points.
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
is driven onto the Q[17:0] using K as the output timing reference.
On the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
Functional Overview
The CY7C2268XV18, and CY7C2270XV18 are synchronous
pipelined Burst SRAMs equipped with a DDR interface, which
operates with a read latency of two and half cycles when DOFF
pin is tied HIGH. When DOFF pin is set LOW or connected to
VSS the device behaves in DDR I mode with a read latency of
one clock cycle.
When read access is deselected, the CY7C2268XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the negative input clock (K). This enables for a
transition between devices without the insertion of wait states in
a depth expanded memory.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the negative input clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS[X:0]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C2268XV18 is described in the following sections. The
same basic descriptions apply to CY7C2270XV18.
Read Operations
The CY7C2268XV18 is organized internally as two arrays of
1 M × 18. Accesses are completed in a burst of 2 sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 18-bit word of data from this address location
Document Number: 001-70332 Rev. *B
Page 6 of 29
CY7C2268XV18, CY7C2270XV18
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Echo Clocks
Echo clocks are provided on the DDR II+ Xtreme to simplify data
capture on high-speed systems. Two echo clocks are generated
by the DDR II+ Xtreme. CQ is referenced with respect to K and
CQ is referenced with respect to K. These are free-running
clocks and are synchronized to the input clock of the DDR II+
Xtreme. The timing for the echo clocks is shown in the Switching
Characteristics on page 23.
Byte Write Operations
Byte write operations are supported by the CY7C2268XV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR II+ Xtreme to simplify data capture
on high speed systems. The QVLD is generated by the DDR II+
Xtreme device along with data output. This signal is also edge
aligned with the echo clock and follows the timing of any data pin.
This signal is asserted half a cycle before valid data arrives.
DDR Operation
On-Die Termination (ODT)
The CY7C2268XV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C2268XV18 requires two No
Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications require third
NOP cycle to avoid contention.
These devices have an On-Die Termination feature for Data
input output signals (DQ[x:0]), Byte Write Selects (BWS[x:0]), and
Input Clocks (K and K). ODT is enabled only during write
operation and disabled during read operation. The termination
resistors are integrated within the chip. The ODT range selection
is enabled through ball R6 (ODT pin). The ODT termination
tracks value of RQ where RQ is the resistor tied to the ZQ pin.
ODT range selection is made during power up initialization. A
LOW on this pin selects a low range that follows RQ/3.33 for 175
< RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH
on this pin selects a high range that follows RQ/1.66 for 175 <
RQ < 250 (where RQ is the resistor tied to ZQ pin). When left
floating, a high range termination value is selected by default.
For a detailed description on the ODT implementation, refer to
the application note, On-Die Termination for QDRII+/DDRII+
SRAMs.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
100 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 100 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Document Number: 001-70332 Rev. *B
Page 7 of 29
CY7C2268XV18, CY7C2270XV18
Application Example
Figure 2 shows two DDR II+ Xtreme used in an application.
Figure 2. Application Example
Document Number: 001-70332 Rev. *B
Page 8 of 29
CY7C2268XV18, CY7C2270XV18
Truth Table
The truth table for the CY7C2268XV18, and CY7C2270XV18 follow. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
L–H
L
L
D(A) at K(t + 1) D(A+1) at K(t + 1)
input write data on consecutive K and K rising edges.
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
L–H
L
H
Q(A) at K(t + 2) Q(A+1) at K(t + 3)
NOP: No Operation
L–H
H
X
X
X
High Z
High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C2268XV18 follows. [3, 9]
BWS0 BWS1
K
Comments
K
L
L
L–H
–
During the data portion of a write sequence
CY7C2268XV18 both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L–H During the data portion of a write sequence:
CY7C2268XV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C2268XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C2268XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C2268XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C2268XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. Is based on a write cycle that was initiated in accordance with Truth Table. BWS , BWS , BWS , and BWS can be altered on different portions of a write cycle, as
0
1
2
3
long as the setup and hold requirements are achieved.
Document Number: 001-70332 Rev. *B
Page 9 of 29
CY7C2268XV18, CY7C2270XV18
Write Cycle Descriptions
The write cycle description table for CY7C2270XV18 follows. [10, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a write
0
1
2
3
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-70332 Rev. *B
Page 10 of 29
CY7C2268XV18, CY7C2270XV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Boundary Scan Order on page 18 shows the order in which the
bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-70332 Rev. *B
Page 11 of 29
CY7C2268XV18, CY7C2270XV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-70332 Rev. *B
Page 12 of 29
CY7C2268XV18, CY7C2270XV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
1
0
1
SHIFT-DR
1
SHIFT-IR
1
EXIT1-DR
0
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-70332 Rev. *B
Page 13 of 29
CY7C2268XV18, CY7C2270XV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
Circuitry
TDO
Instruction Register
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [13, 14, 15]
Description
Output HIGH Voltage
Test Conditions
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =2.0 mA
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
–
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
Input LOW Voltage
–
–0.3
–5
0.35 × VDD
5
V
IX
Input and Output Load Current
GND VI VDD
A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20.
14. Overshoot: V < V + 0.3 V (Pulse width less than t /2), Undershoot: V /2).
> 0.3 V (Pulse width less than t
IH(AC)
DD
TCYC
IL(AC)
TCYC
15. All Voltage referenced to Ground.
Document Number: 001-70332 Rev. *B
Page 14 of 29
CY7C2268XV18, CY7C2270XV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 V/ns.
R
F
Document Number: 001-70332 Rev. *B
Page 15 of 29
CY7C2268XV18, CY7C2270XV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [18]
Figure 3. TAP Timing and Test Conditions
0.9 V
50
ALL INPUT PULSES
1.8 V
0.9 V
TDO
0 V
Slew Rate = 1 V/ns
Z = 50
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
18. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 V/ns.
R
F
Document Number: 001-70332 Rev. *B
Page 16 of 29
CY7C2268XV18, CY7C2270XV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C2268XV18
CY7C2270XV18
000
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
000
Version number.
11010111000010100
00000110100
11010111000100100
00000110100
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-70332 Rev. *B
Page 17 of 29
CY7C2268XV18, CY7C2270XV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
Bit #
84
Bump ID
1J
1
6P
5B
5A
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
4A
87
3J
4
7N
5C
4B
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
3A
90
2L
7
8P
2A
91
3L
8
9R
1A
92
1M
1L
9
11P
10P
10N
9P
2B
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
3B
94
3N
1C
1B
95
3M
1N
96
10M
11N
9M
9D
3D
3C
1D
2C
3E
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
2D
2E
3R
4R
10L
11K
10K
9J
1E
4P
8B
2F
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-70332 Rev. *B
Page 18 of 29
CY7C2268XV18, CY7C2270XV18
PLL Constraints
Power Up Sequence in DDR II+ Xtreme SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR II+ Xtreme SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 100 s of stable clock
to relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 100 s
to lock the PLL
Figure 4. Power Up Waveforms
Document Number: 001-70332 Rev. *B
Page 19 of 29
CY7C2268XV18, CY7C2270XV18
Maximum Ratings
Neutron Soft Error Immunity
Test
Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Parameter Description
Typ Max* Unit
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25 °C
260 271
FIT/
Mb
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ......–0.5 V to VDDQ + 0.3 V
DC Input Voltage [19] ...........................–0.5 V to VDD + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Logical
Multi-Bit
Upsets
25 °C
85 °C
0
0
0.01 FIT/
Mb
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
Static Discharge Voltage
(MIL-STD-883, M 3015) ..........................................> 2,001V
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Latch up Current ....................................................> 200 mA
Maximum Junction Temperature ............................... 125 °C
Operating Range
Ambient
Temperature (TA)
[20]
[20]
Range
VDD
VDDQ
Commercial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to 1.6 V
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21]
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
1.9
VDDQ
VOH
1.4
1.6
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 22
Note 23
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
V
VOL
–
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, Nominal Impedance
–
VDDQ
0.2
V
IOL = 0.1 mA, Nominal Impedance
–
V
VREF + 0.1
–0.15
–
VDDQ + 0.15
VREF – 0.1
2
V
VIL
–
V
IX
Input Leakage Current
Output Leakage Current
Input Reference Voltage
VDD operating supply
GND VI VDDQ
2
–
A
A
V
IOZ
GND VI VDDQ, Output Disabled
Typical Value = 0.75 V
2
–
2
VREF
0.68
0.75
–
0.86
[24]
VDD = Max, IOUT = 0 mA, 633 MHz (× 18)
f = fMAX = 1/tCYC
–
–
–
–
965
mA
IDD
(× 36)
–
1230
910
600 MHz (× 18)
(× 36)
–
mA
–
1165
Notes
19. Overshoot: V
20. Power up: assumes a linear ramp from 0 V to V
21. All Voltage referenced to Ground.
< V
+ 0.3 V (Pulse width less than t
/2), Undershoot: V
> 0.3 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
within 200 ms. During this time V < V and V
V
.
DD
DD(min)
IH
DD
DDQ
22. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 RQ 350 .
DDQ
OH
23. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 RQ 350 .
OL
DDQ
24. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-70332 Rev. *B
Page 20 of 29
CY7C2268XV18, CY7C2270XV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
–
Typ
–
Max
965
Unit
ISB1
Automatic power down
current
Max VDD
,
633 MHz (× 18)
(× 36)
mA
Both ports deselected,
–
–
1230
910
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
Inputs Static
,
600 MHz (× 18)
(× 36)
–
–
mA
–
–
1165
AC Electrical Characteristics
Over the Operating Range
Parameter [25]
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
-0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Parameter [26]
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
4
Unit
pF
CIN
CO
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [26]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test With Still Air (0 m/s)
14.84
13.68
5.1
°C/W
methods and procedures for measuring
With Air flow (1 m/s)
thermal impedance, in accordance with
EIA/JESD51.
JC
Thermal resistance
(junction to case)
°C/W
Notes
25. Overshoot: V
< V
+ 0.3 V (Pulse width less than t
/2), Undershoot: V
> 0.3 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
26. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-70332 Rev. *B
Page 21 of 29
CY7C2268XV18, CY7C2270XV18
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[27]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
R = 50
L
0.75 V
Under
Device
Under
0.25 V
Test
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Note
27. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input
REF
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-70332 Rev. *B
Page 22 of 29
CY7C2268XV18, CY7C2270XV18
Switching Characteristics
Over the Operating Range
Parameters [28, 29]
633 MHz
Max
600 MHz
Max
Description
Unit
Cypress Consortium
Parameter Parameter
Min
Min
tPOWER
tCYC
tKH
VDD(typical) to the first access [30]
K clock cycle time
1
–
8.4
–
1
–
8.4
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
1.58
0.4
1.66
0.4
Input clock (K/K) HIGH
Input clock (K/K) LOW
tKL
0.4
–
0.4
–
tKHKH
K clock rise to K clock rise (rising edge to rising
edge)
0.71
–
0.75
–
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address setup to K clock rise
0.23
0.23
0.18
–
–
–
0.23
0.23
0.18
–
–
–
ns
ns
ns
tSC
Control setup to K clock rise (LD, R/W)
tSCDDR
Double data rate control setup to clock (K/K) rise
(BWS0, BWS1, BWS2, BWS3)
tSD
tDVKH
D[X:0] setup to clock (K/K) rise
0.18
–
0.18
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address hold after K clock rise
0.23
0.23
0.18
–
–
–
0.23
0.23
0.18
–
–
–
ns
ns
ns
tHC
Control hold after K clock rise (LD, R/W)
tHCDDR
Double data rate control hold after clock (K/K)
rise (BWS0, BWS1, BWS2, BWS3)
tHD
tKHDX
D[X:0] hold after clock (K/K) rise
0.18
–
0.18
–
ns
Output Times
tCCQO
tCQOH
tCQD
tCHCQV
K/K clock rise to echo clock valid
Echo clock hold after K/K clock rise
Echo clock high to data valid
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
–0.45
–
–0.45
–
0.09
–
0.09
–
tCQDOH
tCQH
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH [31]
–0.09
0.71
0.71
–0.09
0.75
0.75
–
–
tCQHCQH
CQ clock rise to CQ clock rise
–
–
(rising edge to
rising edge) [31]
tCHZ
tCHQZ
Clock (K/K) rise to high Z (active to high Z) [32, 33]
Clock (K/K) rise to low Z [32, 33]
Echo clock high to QVLD valid [34]
–
0.45
–
–
0.45
–
ns
ns
ns
tCLZ
tCHQX1
tCQHQVLD
–0.45
–0.15
–0.45
–0.15
tQVLD
0.15
0.15
PLL Timing
tKC Var
tKC lock
tKC Reset
tKC Var
Clock phase jitter
–
0.15
–
–
0.15
–
ns
s
ns
tKC lock
tKC Reset
PLL lock time (K)
K static to PLL reset [35]
100
30
100
30
–
–
Notes
28. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input
REF
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 22.
OL OH
29. When a part with a maximum frequency above 600 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
30. This part has an internal voltage regulator; t
is the time that the power is supplied above V min initially before a read or write operation can be initiated.
DD
POWER
31. These parameters are extrapolated from the input timing parameters (t
/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
32. t
, t
are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 22. Transition is measured 100 mV from steady-state voltage.
CHZ CLZ
33. At any voltage and temperature t
is less than t
.
CLZ
CHZ
34. t
specification is applicable for both rising and falling edges of QVLD signal.
QVLD
35. Hold to >V or <V .
IH
IL
Document Number: 001-70332 Rev. *B
Page 23 of 29
CY7C2268XV18, CY7C2270XV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency [36, 37, 38]
NOP
1
READ
2
READ
3
NOP
5
NOP
6
WRITE
7
WRITE
8
NOP
11
NOP
4
READ
9
NOP
10
12
K
t
t
t
t
KH
KL
KHKH
CYC
K
LD
t
t
HC
SC
R/W
A
A2
A3
A0
A4
A1
t
QVLD
t
t
t
t
SA HA
QVLD
QVLD
QVLD
t
t
HD
HD
SD
t
t
SD
D21 D30 D31
Q00 Q01 Q10 Q11
D20
Q40
DQ
t
t
CHZ
CLZ
t
t
CQ D
(Read Latency = 2.5 Cycles)
t
CQDOH
CCQO
t
CQOH
CQ
CQ
t
CQH
t
CQHCQH
t
CCQO
t
CQOH
DO N’T CA RE
UNDEFINED
Notes
36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
37. Outputs are disabled (High Z) one clock cycle after a NOP.
38. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-70332 Rev. *B
Page 24 of 29
CY7C2268XV18, CY7C2270XV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page
at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
633 CY7C2268XV18-633BZXC
CY7C2270XV18-633BZXC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Commercial
600 CY7C2268XV18-600BZXC
CY7C2270XV18-600BZXC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY
7
C 22XX X V18 - XXX BZ
X
X
Temperature Range: X = C
C = Commercial;
Pb-free
Package Type:
BZ = 165-ball FBGA
Frequency Range: 633 MHz or 600 MHz
V18 = 1.8 V
Die Revision X = Xtreme
Part Identifier
22XX = 2268 (2 M × 18) or 2270 (1 M × 36)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-70332 Rev. *B
Page 25 of 29
CY7C2268XV18, CY7C2270XV18
Package Diagram
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *F
Document Number: 001-70332 Rev. *B
Page 26 of 29
CY7C2268XV18, CY7C2270XV18
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
DDR
EIA
double data rate
Unit of Measure
electronic industries alliance
fine-pitch ball grid array
high-speed transceiver logic
input/output
°C
k
MHz
µA
µs
degree Celsius
FBGA
HSTL
I/O
kilohm
megahertz
microampere
microsecond
millivolt
JEDEC
JTAG
LMBU
LSB
joint electron devices engineering council
joint test action group
logical multi-bit upsets
least significant bit
logical single-bit upsets
most significant bit
on-die termination
mV
mA
ms
mm
ns
milliampere
millisecond
millimeter
nanosecond
ohm
LSBU
MSB
ODT
PLL
phase-locked loop
%
percent
QDR
SEL
quad data rate
pF
ps
picofarad
picosecond
volt
single event latch-up
static random access memory
test access port
SRAM
TAP
V
W
watt
TCK
TDI
test clock
test data-in
TDO
TMS
test data-out
test mode select
Document Number: 001-70332 Rev. *B
Page 27 of 29
CY7C2268XV18, CY7C2270XV18
Document History Page
Document Title: CY7C2268XV18/CY7C2270XV18, 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle
Read Latency) with ODT
Document Number: 001-70332
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
3377111
3532265
VIDB
09/20/2011 New data sheet.
*A
PRIT /
GOPA
02/22/2012 Changed status from Preliminary to Final.
*B
3783098
PRIT
10/25/2012 Updated Features (Replaced D[x:0] with DQ[x:0]).
Updated Functional Description (Replaced D[x:0] with DQ[x:0]).
Updated Pin Definitions (Updated Note 2 (Replaced D[x:0] with DQ[x:0])).
Updated Functional Overview (Updated On-Die Termination (ODT) (Replaced
D[x:0] with DQ[x:0])).
Updated Application Example (Updated Figure 2).
Updated TAP Electrical Characteristics (Updated Note 14).
Updated TAP AC Switching Characteristics (Updated Note 17).
Updated TAP Timing and Test Conditions (Updated Note 18 and updated
Figure 3).
Updated Thermal Resistance (Changed value of Theta JA parameter from
26.65 °C/W to 14.84 °C/W (for Test Condition "With Still Air (0 m/s)") for
165-ball FBGA Package, changed value of Theta JA parameter from
22.76 °C/W to 13.68 °C/W (for Test Condition "With Air flow (1 m/s)") for
165-ball FBGA Package, changed value of Theta JC parameter from
4.31 °C/W to 5.1 °C/W for 165-ball FBGA Package).
Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).
Document Number: 001-70332 Rev. *B
Page 28 of 29
CY7C2268XV18, CY7C2270XV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-70332 Rev. *B
Revised October 25, 2012
Page 29 of 29
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C2270XV18 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
CY7C2270XV18-633BZXC | INFINEON | DDR-II+ CIO | 获取价格 | |
CY7C235-25DC | ETC | x8 EPROM | 获取价格 | |
CY7C235-25JC | ETC | x8 EPROM | 获取价格 | |
CY7C235-25JCR | CYPRESS | OTP ROM, 1KX8, CMOS, PQCC28, PLASTIC, LCC-28 | 获取价格 | |
CY7C235-25JCT | CYPRESS | OTP ROM, 1KX8, CMOS, PQCC28, PLASTIC, LCC-28 | 获取价格 | |
CY7C235-25JI | CYPRESS | OTP ROM, 1KX8, 12ns, CMOS, PQCC28, PLASTIC, LCC-28 | 获取价格 | |
CY7C235-25JIT | CYPRESS | OTP ROM, 1KX8, 12ns, CMOS, PQCC28, PLASTIC, LCC-28 | 获取价格 | |
CY7C235-25PC | ETC | x8 EPROM | 获取价格 | |
CY7C235-30DC | ETC | x8 EPROM | 获取价格 | |
CY7C235-30DI | CYPRESS | OTP ROM, 1KX8, CMOS, CDIP24, 0.300 INCH, SLIM, HERMETIC SEALED, CERDIP-24 | 获取价格 |
CY7C2270XV18 相关文章
- 2024-09-20
- 5
- 2024-09-20
- 8
- 2024-09-20
- 8
- 2024-09-20
- 6