CY7C245A-18WMB [CYPRESS]
2K x 8 Reprogrammable Registered PROM; 2K ×8的可重复编程的PROM注册
| 型号： | CY7C245A-18WMB |
| 厂家： | 
CYPRESS |
| 描述： | 2K x 8 Reprogrammable Registered PROM |
| 文件： | 总12页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
— 330 mW (commercial) for -25 ns
— 660 mW (military)
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V 10% VCC, commercial and military
• TTL-compatible I/O
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Logic Block Diagram
Pin Configurations
DIP Top View
INIT
1
24
23
22
21
20
19
18
17
16
A
A
6
V
CC
O
7
A
0
2
3
4
A
8
7
O
A
1
A
A
5
9
A
2
A
4
A
10
PROGRAMMABLE
ARRAY
ROW
6
O
MULTIPLEXER
5
A
A
3
ADDRESS
3
INIT
E/E
S
A
6
2
A
4
8-BIT
A
1
5
O
7
8
9
CP
EDGE-
A
5
TRIGGERED
REGISTER
A
0
O
7
ADDRESS
DECODER
A
6
4
O
0
O
6
O
O
10
11
12
O
5
A
1
15
14
13
7
O
O
4
2
3
O
A
8
GND
O
3
A
9
COLUMN
LCC/PLCC (Opaque only) Top View
2
O
ADDRESS
A
10
1
O
3 2 1 2827
26
4
CP
A
25 10
A
5
4
3
PROGRAMMABLE
MULTIPLEXER
A
24
23
22
21
20
19
INIT
6
0
A
E/E
D
C
Q
2
E/E
S
S
7
A
1
CP
NC
8
A
0
9
CP
NC
O
7
10
11
O
0
O
6
131415161718
12
Selection Guide
7C245A-15
7C245A-18
7C245A-25
7C245A-35
Unit
ns
Minimum Address Set-up Time
Maximum Clock to Output
15
10
18
12
25
12
35
15
ns
Maximum Operating Current Standard Commercial
Military
120
120
120
90
90
mA
mA
120
120
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
RevisedNovember4, 2003
CY7C245A
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
provided with
a
programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initial-
ization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous enable (ES) has been programmed, the register
will be in the set condition causing the outputs (O0–O7) to be
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the memory location
to the address inputs (A0–A10) and a logic LOW to the enable
input. The stored data is accessed and loaded into the master
flip-flops of the data register during the address set-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O0–O7).
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C245A needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
Bit Map Data
Programmer Address
RAM Data
Contents
Data
Decimal
Hex
0
0
.
.
.
.
.
.
.
.
.
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
2047
2048
7FF
800
801
Data
Init Byte
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated, the initialize control input causes the contents of a
user-programmed 2049th 8-bit word to be loaded into the
2049
Control Byte
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
Document #: 38-04007 Rev. *D
Page 2 of 12
CY7C245A
Table 1. Mode Selection
Pin Function[1]
Read or Output Disable
Other
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A10–A4
A3
A3
A3
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A2–A1
A0
A0
A0
CP
PGM
VIL/VIH
X
E, ES
VFY
VIL
INIT
O7–O0
D7–D0
O7–O0
High Z
Init. Byte
D7–D0
O7–O0
High Z
D7–D0
High Z
D7–D0
Zeros
Mode
Read
VPP
VIH
Output Disable
Initialize
A3
A0
VIH
VIH
A3
A0
X
VIL
VIL
Program
A3
A0
VILP
VIHP
VIHP
VILP
VILP
VILP
VIHP
VIHP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VPP
VPP
VPP
VPP
VPP
VPP
VPP
Program Verify
Program Inhibit
Intelligent Program
A3
A0
A3
A0
A3
A0
Program Synchronous Enable
Program Initialization Byte
Blank Check Zeros
VIHP
VILP
A3
VPP
VPP
A0
DIP Top View
LCC/PLCC (Opaque Only) Top View
24
1
A
7
V
CC
3
2 1 2827
A
4
26
25
24
23 VFY
22
21
23
6
A
8
A
9
2
A
V
A
10
PP
5
6
7
8
9
10
11
22
3
4
A
5
A
3
A
2
21
A
4
A
10
4
A
20
5
V
PP
3
A
PGM
NC
D
7
D
1
A
2
19
A
VFY
6
0
NC
D
20
19
A
1
18
7
PGM
0
6
A
0
17
D
7
8
1314151617 18
12
D
0
D
1
D
2
16
9
15
10
D
6
D
5
D
4
D
3
14
13
11
12
GND
Figure 1. Programming Pinouts
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tHA
tCO
DC Characteristics
Parameter
VOH
VOL
VIH
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
SMD Cross Reference
SMD Number
5962-88735
Suffix
033X
04LX
Cypress Number
CY7C245A-25LMB
CY7C245A-25DMB
5962-88735
Note:
1. X = “don’t care” but not to exceed VCC + 5%.
Document #: 38-04007 Rev. *D
Page 3 of 12
CY7C245A
Maximum Ratings[2]
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm2
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-up Current.....................................................> 200 mA
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Range
Commercial
Military[3]
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
5V 10%
5V 10%
5V ±10%
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage .................................................−3.0V to +7.0V
Electrical Characteristics Over the Operating Range[4,5]
−55°C to +125°C
–40°C to +85°C
Industrial
7C245A-25
7C245A-35
7C245A-15 7C245A-18 7C245A-45
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL
2.4
2.4
2.4
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Level
Input LOW Level
VCC = Min., IOL = 16 mA
VIN = VIH or VIL
0.4
VCC 2.0 VCC 2.0
0.8 0.8
0.4
0.4
VCC
0.8
V
Guaranteed Input Logical
HIGH Voltage for All Inputs
2.0
V
Guaranteed Input Logical
LOW Voltage for All Inputs
V
IIX
Input Leakage Current
Input Clamp Diode Voltage
Output Leakage Current
GND < VIN < VCC
−10 +10 −10 +10 −10
Note 5
+10
µA
VCD
IOZ
GND < VO < VCC Output
Disabled[6]
−10 +10 −10 +10 −10
+10
µA
IOS
ICC
Output Short Circuit Current
Power Supply Current
VCC = Max., VOUT = 0.0V[7]
−20 −90 −20 −90 −20
−90 mA
VCC = Max.,
IOUT = 0 mA
Com’l
Mil
120
120
120
13
90
120
13
mA
VPP
IPP
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming Voltage
Input LOW Programming Voltage
12
13
50
12
12
V
mA
V
50
50
VIHP
VILP
3.0
3.0
3.0
0.4
0.4
0.4
V
Capacitance[5]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
10
10
COUT
pF
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. TA is the “instant on” case temperature.
4. See page 3 of this data sheet for Group A subgroup testing information.
5. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
6. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
7. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04007 Rev. *D
Page 4 of 12
CY7C245A
AC Test Loads and Waveforms[4, 5]
R1 250Ω
R1 250Ω
5V
5V
ALL INPUT PULSES
3.0V
GND
OUTPUT
OUTPUT
90%
10%
90%
10%
R2
167Ω
R2
167Ω
50 pF
5 pF
≤
5 ns
5 ns
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) Normal Load
(b) HighZ Load
Equivalent to: TH ÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
Switching Characteristics Over Operating Range[4, 5]
7C245A-15 7C245A-18 7C245A-35
7C245A-25
7C245A-35
Parameter
tSA
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
15
0
18
0
25
0
35
0
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHA
tCO
10
15
12
20
12
20
15
20
25
35
tPWC
tSES
tHES
tDI
10
10
5
12
10
5
15
12
5
20
15
5
20
15
5
ES Set-Up to Clock HIGH
ES Hold from Clock HIGH
Delay from INIT to Valid Output
INIT Recovery to Clock HIGH
INIT Pulse Width
tRI
10
10
12
12
15
15
20
20
20
25
tPWI
tCOS
tHZC
Valid Output from Clock HIGH[8]
15
15
15
15
15
15
20
20
30
30
Inactive Output from Clock
HIGH[8]
tDOE
Valid Output from E LOW[9]
Inactive Output from E HIGH[9]
12
15
15
15
15
15
20
20
30
30
ns
ns
tHZE
Notes:
8. Applies only when the synchronous (ES) function is used.
9. Applies only when the asynchronous (E) function is used.
Document #: 38-04007 Rev. *D
Page 5 of 12
CY7C245A
Switching Waveforms[5]
t
t
SA
t
HA
HA
A − A
0
10
t
t
t
t
HES
SES
HES
SES
E
S
t
t
HES
SES
t
t
t
PWC
PWC
PWC
CP
t
t
t
PWC
PWC
PWC
O
− O
0
7
t
t
t
CO
HZC
COS
t
CO
t
t
HZE
DOE
E
t
RI
t
DI
INIT
t
PWI
Document #: 38-04007 Rev. *D
Page 6 of 12
CY7C245A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
CLOCK TO OUTPUT TIME
vs. V
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CC
1.6
1.4
1.2
1.0
1.6
1.2
1.4
1.2
1.0
1.1
1.0
0.9
0.8
T =25°C
A
0.8
0.6
0.8
f = f
MAX
T =25°C
A
0.6
−55
25
125
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.6
1.2
1.0
1.6
1.4
1.2
1.0
0.8
1.4
1.2
1.0
0.8
0.8
0.6
0.4
T =25°C
A
0.6
−55
0.6
−55
25
125
4.0
4.5
5.0
5.5
6.0
25
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
1.02
1.00
0.98
30.0
25.0
20.0
15.0
V
CC
=5.5V
T =25°C
A
125
100
75
0.96
0.94
0.92
V
=5.0V
CC
10.0
5.0
50
T =25°C
A
T =25°C
CC
A
V
25
0
0.90
0.88
=4.5V
0.0
0.0
1.0
2.0
3.0
4.0
0
25
50
75
100
0
200 400
600 800 1000
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
Ordering Information
Speed (ns)
ICC
Ordering
Code
Package
Type
Operating
Range
tSA
15
15
18
tCO
10
10
12
(mA)
120
120
120
Package Type
CY7C245A-15JC
CY7C245A-15JI
CY7C245A-18JC
CY7C245A-18PC
CY7C245A-18WC
J64
J64
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
Commercial
Industrial
J64
Commercial
P13
W14
24-Lead (300-Mil) Windowed CerDIP
Document #: 38-04007 Rev. *D
Page 7 of 12
CY7C245A
Ordering Information (continued)
Speed (ns)
ICC
(mA)
Ordering
Code
Package
Type
Operating
Range
tSA
tCO
Package Type
18
12
120
CY7C245A-18DMB
CY7C245A-18QMB
CY7C245A-18WMB
CY7C245A-25PC
CY7C245A-25WC
CY7C245A-25JC
CY7C245A-25SC
CY7C245A-35WC
CY7C245A-35JC
CY7C245A-35DMB
CY7C245A-35QMB
D14
Q64
W14
P13
W14
J64
24-Lead (300-Mil) CerDIP
Military
28-Pin Windowed Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead Molded SOIC
25
35
15
20
60
90
Commercial
S13
W14
J64
60
90
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
Commercial
Military
120
D14
Q64
28-Pin Windowed Leadless Chip Carrier
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
Document #: 38-04007 Rev. *D
Page 8 of 12
CY7C245A
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
24-Lead (300-Mil) PDIP P13
51-85013-*B
Document #: 38-04007 Rev. *D
Page 9 of 12
CY7C245A
Package Diagrams (continued)
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102-**
24-Lead(300-Mil)SOIC S13
PIN 1 ID
12
1
MIN.
DIMENSIONS IN INCHES[MM]
MAX.
*
0.394[10.007]
0.419[10.642]
REFERENCE JEDEC MO-119
PACKAGE WEIGHT 0.65gms
0.291[7.391]
0.300[7.620]
PART #
13
24
0.026[0.660]
0.032[0.812]
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
SEATING PLANE
0.597[15.163]
0.615[15.621]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
0.0091[0.231]
0.0125[0.317]
*
0.050[1.270]
TYP.
0.015[0.381]
0.050[1.270]
0.004[0.101]
0.0118[0.299]
51-85025-*B
0.013[0.330]
0.019[0.482]
Document #: 38-04007 Rev. *D
Page 10 of 12
CY7C245A
Package Diagrams (continued)
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
51-80086-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04007 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C245A
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Changed from Spec number: 38-00074 to 38-04007
Updated ordering information
113863
118894
122248
130688
130942
3/6/02
DSG
GBI
RBI
*A
10/09/02
12/27/02
10/30/03
11/10/03
*B
Added power-up requirements to Operating Conditions information
Added CY7C245A-15JI part number
*C
LSY
KKV
*D
Minor change: soft copy became corrupted after signoff and before Tech
Pubs. Replaced with correct copy.
Document #: 38-04007 Rev. *D
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