CY7C266-20WC [CYPRESS]
8Kx8 Power-Switched and Reprogrammable PROM; 8Kx8电源开关和可重复编程的PROM
| 型号： | CY7C266-20WC |
| 厂家： | 
CYPRESS |
| 描述： | 8Kx8 Power-Switched and Reprogrammable PROM |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C266
CY7C266
8Kx8 Power-Switched and
Reprogrammable PROM
powers down into a low-power standby mode. It is packaged
in a 600-mil-wide package. The reprogrammable packages
are equipped with an erasure window; when exposed to UV
light, these PROMs are erased and can then be repro-
grammed. The memory cells utilize proven EPROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
floating-gate
technology
and
byte-wide
intelligent
— 20 ns (Commercial)
programming algorithms.
• Low power
The CY7C266 is a plug-in replacement for EPROM devices.
The EPROM cell requires only 12.5V for the super voltage and
low-current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming, the product will meet DC and AC specification
limits.
— 660 mW (Commercial)
• Super low standby power
— Less than 85 mW when deselected
• EPROM technology 100% programmable
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for 27C64 EPROMs
Reading is accomplished by placing an active LOW signal on
OE and CE. The contents of the memory location addressed
by the address lines (A0 through A12) will become available on
the output lines (O0 through O7).
Functional Description
The CY7C266 is a high-performance 8192-word by 8-bit
CMOS PROM. When deselected, the CY7C266 automatically
Logic Block Diagram
Pin Configurations
CerDIP
O
O
7
Top View
A
0
1
28
27
26
V
V
CC
CC
A
1
2
A
V
CC
12
A
2
3
A
7
6
NC
ROW
PROGRAMMABLE
ARRAY
A
6
4
MULTIPLEXER
25
24
23
22
21
A
8
ADDRESS
A
3
A
5
5
A
9
A
4
6
A
4
A
11
A
3
A
2
7
8
OE
O
O
5
A
5
A
10
A
1
9
20
19
18
17
16
7C266
CE
A
6
A
0
10
11
12
13
O
7
O
6
ADDRESS
DECODER
A
7
O
0
4
O
1
O
5
A
8
O
2
O
4
A
9
GND
O
3
14
15
O
COLUMN
ADDRESS
3
A
10
11
LCC
Top View
A
A
12
O
O
2
4
3
2
323130
1
A
8
A
29
6
POWER DOWN
5
6
7
8
9
10
11
12
13
A
A
5
4
28
27
9
A
A
11
1
A
3
26 NC
A
2
OE
10
25
24
A
A
1
A
0
23 CE
7C266
NC
O
0
O
7
O
6
22
21
O
0
14151617 181920
CE
OE
Cypress Semiconductor Corporation
Document #: 38-04005 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 27, 2002
CY7C266
Selection Guide
7C266-20
7C266-25
7C266-45
Unit
ns
Maximum Access Time
20
120
15
25
120
15
45
100
15
Maximum Operating Current
Maximum Standby Current
Commercial
Commercial
mA
mA
Maximum Ratings[1]
DC Program Voltage .................................................... 13.0V
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... > 200 mA
UV Exposure ................................................ 7258 Wsec/cm2
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
Ambient
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Range
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage............................................ –3.0V to +7.0V
Electrical Characteristics Over the Operating Range[2]
7C266-20
7C266-25
Parameter
Description
Test Conditions
VCC = Min.,
OH = –2.0 mA
Min.
Max.
Min.
2.4
Max.
Unit
VOH
Output HIGH Voltage
Com’l
Com’l
2.4
V
I
2.4
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
VCC = Min., IOL = 8.0 mA
0.4
0.4
V
V
2.0
2.0
0.8
0.8
V
IIX
GND < VIN < VCC
–10
+10
–10
+10
µA
VCD
Input Diode
Clamp Voltage
Note 3
IOZ
IOS
ICC
Output Leakage Current
VOL < VOUT < VOH
Output Disabled
,
–40
–20
+40
–90
120
15
–40
–20
+40
–90
120
15
µA
mA
mA
mA
Output Short
VCC = Max., VOUT = GND
Circuit Current[3]
Power Supply Current
VCC = Max., VIN = 2.0V,
IOUT = 0 mA
Com’l
Com’l
ISB
Standby Supply Current
Chip Enable Inactive,
CE > VIH, IOUT = 0 mA
Notes:
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04005 Rev. *B
Page 2 of 11
CY7C266
Electrical Characteristics Over the Operating Range[2] (continued)
7C266-45
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 16.0 mA
Min.
Max.
Unit
V
2.4
0.4
V
VIH
2.0
V
VIL
0.8
V
IIX
GND < VIN < VCC
–10
+10
mA
VCD
Input Diode Clamp
Voltage
Note 3
IOZ
IOS
ICC
ISB
Output Leakage Current
VOL < VOUT < VOH
Output Disabled
,
–10
–20
+10
–90
100
15
mA
mA
mA
mA
Output Short
VCC = Max., VOUT = GND
Circuit Current[3]
Power Supply Current
Standby Supply Current
VCC = Max., VIN = 2.0V,
IOUT = 0 mA
Com’l
Com’l
Chip Enable Inactive,
CE > VIH, IOUT = 0 mA
Capacitance[2]
Parameter
Description
Test Conditions
Max.
10
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
COUT
10
pF
Document #: 38-04005 Rev. *B
Page 3 of 11
CY7C266
AC Test Loads and Waveforms
Test Load for -20 through -25 speeds
R1 500
R1 500Ω
(658Ω MIL)
(658Ω MIL)
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
90%
10%
R2 333Ω
(403Ω MIL)
R2 333Ω
(403Ω MIL)
30 pF
5 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) NormalLoad
(b) HighZ Load
Equivalent to: THÉVENIN EQUIVALENT
200
R
TH
OUTPUT
250 MIL
Test Load for -35 through -45 speeds
R1250Ω
R1 250Ω
5V
5V
OUTPUT
OUTPUT
30pF
5 pF
R2167Ω
R2167 Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(c) NormalLoad
(d) HighZ Load
Equivalent to: THÉVENIN EQUIVALENT
100Ω
R
TH
OUTPUT
2.0V
Switching Characteristics Over the Operating Range[2]
7C266-20
7C266-25
7C266-45
Min. Max.
45
Parameter
tAA
Description
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Address to Output Valid
20
25
12
12
25
25
30
12
12
30
tHZCE
tHZOE
tAOE
tACE
tOHA
tPU
Chip Enable Inactive to High Z
Output Enable Inactive to High Z
Output Enable Active to Output Valid
Chip Enable Active to Output Valid
Data Hold from Address Change
Chip Enable Active to Power-up
Chip Enable Inactive to Power-down
45
20
20
45
3
3
3
25
25
30
30
45
45
tPD
Document #: 38-04005 Rev. *B
Page 4 of 11
CY7C266
result if the EPROM is exposed to high-intensity UV light for an
extended period of time.
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase
the devices in the windowed package. For this reason, an
opaque label should be placed over the window if the EPROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as
from a number of third party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time
would be approximately 35 minutes. The CY7C266 needs to be
within 1 inch of the lamp during erasure. Permanent damage may
Table 1. Mode Selection
Pin Function[4, 5]
Normal Operation
Program
A8
VFY
A8
A9
PGM
A9
A10
LAT
A10
X
A11
NA
A11
X
A12
NA
A12
X
CE
CE
OE
VPP
VIL
D7–D0
D7–D0
Mode
Read
VIL
O7–O0
Standby
X
X
VIH
VIL
X
Three-Stated
Three-Stated
D7–D0
Output Disable
Program
A8
A9
A10
VILP
VILP
VILP
VILP
A11
VILP
VILP
VILP
VILP
A12
VILP
VILP
VILP
VILP
VIH
VPP
VPP
VPP
VPP
VIHP
VILP
VIHP
VILP
VILP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
Program Verify
Program Inhibit
O7–O0
Three-Stated
O7–O0
Blank Check
Notes:
4. X = “don’t care” but must not exceed VCC + 5%.
5. Address A8–A12 must be latched through lines A0–A4 in Programming modes.
CerDIP
Top View
LCC/PLCC
Top View
1
28
27
26
NC
NA
V
PP
2
3
NC
4
A
7
3
2
323130
1
NC
VFY
PGM
NA
A
A
12
29
6
A
6
4
25
24
23
22
21
5
6
7
8
VFY
PGM
NA
5
28
27
26
25
24
23
22
21
A
5
5
7C266
A /A
3
4
6
A /A
7C266
A /A
4
12
11
10
11
NC
A /A
A /A
A /A
A /A
3
A /A
2
7
8
V
2
1
0
1
90
8
V
PP
PP
9
LAT
CE
D
7
LAT
CE
10
11
12
13
A /A
1
9
20
19
18
17
16
9
8
0
1
2
NC
A /A
0
10
11
12
13
D
7
D
6
D
6
D
0
D
D
14151617 181920
D
5
D
D
4
V
SS
D
3
14
15
Figure 1. Programming Pinout
Document #: 38-04005 Rev. *B
Page 5 of 11
CY7C266
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.6
1.4
1.2
1.1
1.0
0.9
0.8
1.0
0.8
1.2
1.0
0.6
0.4
T = 25°C
A
0.8
0.6
f = f
MAX
T = 25°C
A
−55
25
125
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
SUPPLY VOLTAGE(V)
SUPPLY VOLTAGE(V)
OUTPUT SOURCE CURRENT
vs. VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ACCESS TIME
vs. TEMPERATURE
60
50
40
30
35
30
1.6
1.4
1.2
1.0
25
20
15
20
10
10
5
V
CC
= 4.5V
0.8
0.6
T = 25°C
A
0
0
0
1.0
2.0
3.0
4.0
0
200 400
600 800 1000
–55
25
125
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
AMBIENT TEMPERATURE (°C)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
175
150
1.05
1.00
V
= 5.5V
CC
125
100
75
0.95
0.90
0.85
T = 25°C
A
V
= 5.0V
CC
50
T = 25°C
A
0.80
25
0
0.75
0.70
0.0
1.0
2.0
3.0
4.0
0
25
50
75
100
OUTPUT VOLTAGE (V)
CYCLE PERIOD (ns)
Document #: 38-04005 Rev. *B
Page 6 of 11
CY7C266
Ordering Information]
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
28-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
20
CY7C266-20JC
CY7C266-20WC
CY7C266-25JC
CY7C266-45PC
J64
W16
J64
Commercial
25
45
Commercial
Commercial
P15
Package Diagrams
28-Lead (600-Mil) CerDIP D16
MIL-STD-1835 D-10 Config. A
51-80019-**
Document #: 38-04005 Rev. *B
Page 7 of 11
CY7C266
Package Diagrams (continued)
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068-**
28-Lead (600-Mil) Molded DIP P15
51-85017-*A
Document #: 38-04005 Rev. *B
Page 8 of 11
CY7C266
Package Diagrams (continued)
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
51-80103-*A
Document #: 38-04005 Rev. *B
Page 9 of 11
CY7C266
Package Diagrams (continued)
28-Lead (600-Mil) Windowed CerDIP W16
MIL-STD-1835 D-10 Config. A
51-80020-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04005 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C266
Document History Page
Document Title: CY7C266 8K x 8 Power Switched and Reprogrammable PROM
Document Number: 38-04005
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113861
118897
122246
Description of Change
Change from Spec number: 38-00086 to 38-04005
Update ordering information
03/08/02
10/09/02
12/27/02
DSG
GBI
RBI
*A
*B
Add power up requirements to Operating Conditions information
Document #: 38-04005 Rev. *B
Page 11 of 11
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