CY7C277-50JCT [CYPRESS]
OTP ROM, 32KX8, 25ns, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | CY7C277-50JCT |
| 厂家： | 
CYPRESS |
| 描述： | OTP ROM, 32KX8, 25ns, CMOS, PQCC32, PLASTIC, LCC-32 OTP只读存储器 输出元件 内存集成电路 |
| 文件： | 总8页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C277
CY7C277
32K x 8 Reprogrammable Registered PROM
• Programmable address latch enable input
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered output registers
• EPROM technology, 100% programmable
• Slim 300-mil, 28-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 30-ns address set-up
— 15-ns clock to output
• Low power
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
— 60 mW (commercial)
— 715 mW (military)
Logic Block Diagram
A
14
O
O
7
X
Pin Configurations
A
13
ADDRESS
A
12
ROW
DECODER
1 OF 256
256 x 1024
PROGRAMMABLE
ARRAY
6
8-BIT
1 OF 128
MUX
A
11
A
10
DIP/Flatpack
Top View
O
5
O
4
O
3
A
9
A
8
8-BIT
EDGE-
TRIGGERED
REGISTER
15-BIT
ADDRESS
TRANSPARENT/
LATCH
1
28
27
26
A
V
CC
9
A
7
2
3
A
A
10
A
11
A
12
A
13
A
14
8
A
6
A
7
A
5
A
4
25
24
23
22
21
6
A
4
O
2
O
1
A
5
5
Y
A
3
A
4
6
ADDRESS
A
2
A
7
8
ALE
CP
3
COLUMN
DECODER
1 OF 32
A
1
A
2
A
0
ALE
O
0
A
9
1
20
19
18
17
16
E/E
S
CP
A
0
10
11
12
13
O
7
O
6
PROGRAMMABLE
CP/ALE OPTIONS
O
O
0
O
5
1
ALE
O
2
O
4
GND
O
3
14
15
PROGRAMMABLE
MULTIPLEXER
D
C
Q
E/E
S
CP
Selection Guide
7C277-30
7C277-40
Unit
ns
Minimum Address Set-Up Time
Maximum Clock to Output
30
15
40
20
ns
Maximum Operating
Current
Com’l
Mil
120
mA
mA
130
Cypress Semiconductor Corporation
Document #: 38-04006 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 27, 2002
CY7C277
enters the PROM while the ALE pin is active, and is captured
when ALE is deasserted. The user may define the polarity of
the ALE signal, with the default being active HIGH.
Functional Description
The CY7C277 is a high-performance 32K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package.
The ceramic package may be equipped with an erasure
window; when exposed to UV light, the PROM is erased and
can then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide algorithms.
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................−65°C to +150°C
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that the product will meet DC and AC
specification limits after customer programming.
Ambient Temperature with
Power Applied.................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm2
On the CY7C277, the outputs are pipelined through a
master-slave register. On the rising edge of CP, data is loaded
into the 8-bit edge triggered output register. The E/ES input
provides a programmable bit to select between asynchronous
and synchronous operation. The default condition is
asynchronous. When the asynchronous mode is selected, the
E/ES pin operates as an asynchronous output enable. If the
synchronous mode is selected, the E/ES pin is sampled on the
rising edge of CP to enable and disable the outputs. The
7C277 also provides a programmable bit to enable the
Address Latch input. If this bit is not programmed, the device
will ignore the ALE pin and the address will enter the device
asynchronously. If the ALE function is selected, the address
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Military[2]
Ambient Temperature
VCC
0°C to +70°C
5V ±10%
5V ±10%
−55°C to +125°C
Electrical Characteristics Over the Operating Range[3, 4]
7C277-30
7C277-40
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Test Conditions
VCC = Min., IOH = − 2.0 mA
VCC = Min., IOL = 8.0 mA
Min. Max. Min.
Max.
Unit
2.4
2.0
2.4
2.0
V
V
V
VOL
0.4
0.4
VIH
Guaranteed Input Logical HIGH
Voltage for All Inputs
VCC
VCC
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
0.8
0.8
V
IIX
Input Leakage Current
GND < VIN < VCC
−10
+10
−10
+10
µA
VCD
IOZ
IOS
ICC
Input Clamp Diode Voltage
Output Leakage Current
Output Short Circuit Current
Power Supply Current
Note 4
0 < VOUT < VCC, Output Disabled[5]
VCC = Max., VOUT = 0.0V[6]
−40
−20
+40
−90
120
−40
−20
+40
µA
mA
mA
−90
VCC = Max., CS > VIH Commercial
IOUT = 0 mA
Military
130
13
VPP
IPP
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming Voltage
Input LOW Programming Voltage
12
13
50
12
V
mA
V
50
VIHP
3.0
3.0
VILP
0.4
0.4
V
Notes:
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04006 Rev. *B
Page 2 of 8
CY7C277
Capacitance[4]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
10
Unit
pF
COUT
10
pF
AC Test Loads and Waveforms[4]
R1 500Ω
(658Ω MIL)
R1 500Ω
(658Ω MIL)
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
333Ω
(403Ω MIL)
R2
333Ω
30 pF
5 pF
INCLUDING
< 5 ns
< 5 ns
(403Ω MIL)
INCLUDING
JIG AND
SCOPE
JIG AND
SCOPE
(a) NormalLoad
(b) HighZ Load
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
250Ω
OUTPUT
2.0V
OUTPUT
1.9V
Military
Commercial
CY7C277 Switching Characteristics Over the Operating Range[3, 4]
7C277-30
7C277-40
Parameter
tAL
Description
Address Set-Up to ALE Inactive
Address Hold from ALE Inactive
ALE Pulse Width
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
10
10
30
0
10
10
10
40
0
tLA
tLL
tSA
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
ES Set-Up to Clock HIGH
ES Hold from Clock HIGH
Clock HIGH to Output Valid
Clock Pulse Width
tHA
tSES
tHES
tCO
tPWC
12
5
15
10
15
20
15
20
[7]
tLZC
Output Valid from Clock HIGH
Output High Z from Clock HIGH
Output Valid from E LOW
Output High Z from E HIGH
15
15
15
15
20
20
20
20
tHZC
[8]
tLZE
[8]
tHZE
Notes:
7. Applies only when the synchronous (ES) function is used.
8. Applies only when the asynchronous (E) function is used.
Document #: 38-04006 Rev. *B
Page 3 of 8
CY7C277
Architecture Configuration Bits
Architecture Bit
ALE
Architecture Verify D7–D0
Function
D1
D2
D0
0 = DEFAULT
1 = PGMED
0 = DEFAULT
1 = PGMED
0 = DEFAULT
1 = PGMED
Input Transparent
Input Latched
ALEP
E/ES
ALE = Active HIGH
ALE = Active LOW
Asynchronous Output Enable (E)
Synchronous Output Enable (ES)
Architecture Byte (8000)
Bit Map
D7
D0
Programmer Address
C
C
C
C
C
C
C C
7
6
5
4
3
2 1 0
(Hex.)
RAM Data
0000
.
Data
.
.
.
.
.
7FFF
8000
Data
Control Byte
Timing Diagram (Input Latched)[9]
A –A
0
14
t
AL
t
LA
t
SA
t
HA
ALE
t
LL
E
S
(SYNCH)
t
t
t
SES
t
SES
HES
HES
t
PWC
CP
t
t
CO
HZC
t
LZC
t
PWC
HIGHZ
HIGH Z
O –O
0
7
t
t
LZE
HZE
E
S
(ASYNCH)
Timing Diagram (Input Transparent)
A –A
0
14
t
SA
t
HA
E
S
(SYNCH)
t
t
t
t
SES
HES
SES
HES
t
PWC
CP
t
t
CO
HZC
t
LZC
t
PWC
HIGH Z
HIGHZ
O –O
0
7
t
t
LZE
HZE
E
S
(ASYNCH)
Note:
9. ALE is shown with positive polarity.
Document #: 38-04006 Rev. *B
Page 4 of 8
CY7C277
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Table 1. Mode Selection
Pin Function[10]
Read or Output Disable
Other
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
E, ES
VFY
VIL
CP
PGM
VIH
ALE
VPP
VIL
O7–O0
D7–D0
O7–O0
High Z
D7–D0
O7–O0
High Z
O7–O0
Mode
Read
Output Disable
Program
VIH
X
X
VIHP
VILP
VIHP
VILP
VILP
VPP
VPP
VPP
VPP
Program Verify
Program Inhibit
Blank Check
VIHP/VILP
VIHP
VIHP/VILP
Note:
10. X = “don’t care” but not to exceed VCC ±5%.
DIP
Top View
1
28
27
26
A
V
CC
9
2
3
A
A
10
A
11
8
A
7
4
A
25
24
23
22
21
6
A
A
12
5
A
5
13
6
A
4
A
V
14
A
7
3
PP
A
2
8
PGM
A
9
20
19
18
17
16
1
VFY
D
7
A
0
10
11
12
13
D
D
D
6
D
5
0
1
D
2
D
4
GND
14
D
3
15
Figure 1. Programming Pinouts
Document #: 38-04006 Rev. *B
Page 5 of 8
CY7C277
Typical DC and AC Characteristics
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.0
1.6
1.4
1.2
1.1
1.0
0.9
0.8
1.2
1.0
0.8
0.6
0.4
T =25°C
A
0.8
0.6
f = f
T =25°C
MAX
A
4.0
4.5
5.0
5.5
6.0
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED SET-UP TIME
vs. TEMPERATURE
60
50
40
30
30.0
25.0
20.0
15.0
1.6
1.4
1.2
1.0
0.8
20
10
10.0
5.0
T =25°C
A
V
CC
=4.5V
0.6
−55
0
0.0
0
1.0
2.0
3.0
4.0
0
200 400
600 800 1000
25
125
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
AMBIENT TEMPERATURE (°C)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
125
100
75
V
=5.0V
CC
50
T =25°C
A
25
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
C277-12
Document #: 38-04006 Rev. *B
Page 6 of 8
CY7C277
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Windowed CerDIP
30
CY7C277-30WC
W22
W22
Commercial
Military
40
CY7C277-40WMB
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
VOH
VOL
Subgroups
1, 2, 3
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tHA
tCO
1, 2, 3
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Package Diagrams
(300-Mil)
28-Lead
Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04006 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C277
Document History Page
Document Title: CY7C277 32K x 8 Programmable Registered PROM
Document Number: 38-04006
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113862
118901
122247
Description of Change
Change from Spec number: 38-00085 to 38-04006
Update ordering information
3/8/02
DSG
GBI
RBI
*A
10/09/02
12/27/02
*B
Add power up requirements to Operating Conditions information
Document #: 38-04006 Rev. *B
Page 8 of 8
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