CY7C342B [CYPRESS]
128-Macrocell MAX EPLDs; 128宏单元MAX EPLD中
| 型号： | CY7C342B |
| 厂家： | 
CYPRESS |
| 描述： | 128-Macrocell MAX EPLDs |
| 文件： | 总14页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
128-Macrocell MAX® EPLD
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Features
• 128 macrocells in eight logic array blocks (LABs)
• Eight dedicated inputs, 52 bidirectional I/O pins
• Programmable interconnect array
The 128 macrocells in the CY7C342B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
• Advanced 0.65-micron CMOS technology to increase
performance
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
• Available in 68-pin HLCC, PLCC, and PGA packages
The speed and density of the CY7C342B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 25 times the functionality of 20-pin PLDs,
the CY7C342B allows the replacement of over 50 TTL devices.
By replacing large amounts of logic, the CY7C342B reduces board
space, part count, and increases system reliability.
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
LogicBlock Diagram
1 (B6) INPUT/CLK
INPUT
INPUT
INPUT
INPUT
(A7) 68
(A8) 66
(L6) 36
(K6) 35
2 (A6)
32 (L4)
34 (L5)
INPUT
INPUT
INPUT
SYSTEM CLOCK
LABA
LABH
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
4 (A5)
5 (B4)
6 (A4)
7 (B3)
8 (A3)
9 (A2)
10 (B2)
11 (B1)
MACROCELL 9–16
MACROCELL 121–128
LAB B
LABG
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17 (E1)
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22–32
MACROCELL 102–112
P
I
A
LABC
LAB F
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 38–48
MACROCELL 86–96
LAB D
LABE
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)
MACROCELL 73–80
MACROCELL 57–64
() –PERTAIN TO 68-PIN PGA PACKAGE
3, 20, 37, 54 (B5, G2, K7, E10)
16, 33, 50, 67 (E2, K5, G10, B7)
V
CC
GND
Cypress Semiconductor Corporation
Document #: 38-03014 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Selection Guide
7C342B-15 7C342B-20
7C342B-25
7C342B-30
7C342B-35
35
Unit
Maximum Access Time
15
20
25
30
ns
Pin Configurations
HLCC, PLCC
Top View
PGA
Bottom View
L
I/O
I/O
INPUT INPUT INPUT I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND INPUT
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K
J
7
6
5
4
3
2
1 66 65 64 63 62 61
68 67
9
8
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
60
I/O
59
I/O
I/O
I/O
I/O
I/O
I/O
58
57
56
55
54
53
H
I/O
I/O
GND
I/O
I/O
V
V
CC
GND
I/O
G
F
CC
I/O
17
18
19
I/O
I/O
I/O
I/O
I/O
52
7C342B
51
50
V
CC
GND
20
21
7C342B
GND
I/O
V
CC
E
I/O
I/O
I/O
I/O
I/O
I/O
49
48
47
46
45
44
22
23
I/O
I/O
I/O
D
C
I/O
I/O
I/O
I/O
I/O
I/O
24
25
26
I/O
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
INPUT/
CLK
I/O
I/O
I/O
V
CC
GND
I/O
I/O
B
A
I/O
2
I/O
3
I/O
4
I/O INPUT INPUT INPUT I/O
I/O
10
1
5
6
7
8
9
11
Document #: 38-03014 Rev. *B
Page 2 of 14
USE ULTRA37000TM FOR
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CY7C342B
placement and routing iterations required for a programmable
gate array to achieve design timing objectives.
Logic Array Blocks
There are eight logic array blocks in the CY7C342B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Timing Delays
Timing delays within the CY7C342B may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
software by the model shown in Figure 1. The CY7C342B has
fixed internal delays, allowing the user to determine the
worst-case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C342B contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
Externally, the CY7C342B provides eight dedicated inputs,
one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level
(either VCC or GND). Each set of VCC and GND pins must
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals that may
cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or
races are avoided. The result is ease of design implemen-
tation, often in a signal pass, without the multiple internal logic
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROLDELAY
CLR
INPUT
t
LAC
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
IC
t
PIA
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
Figure 1. CY7C342B Internal Timing Model
Document #: 38-03014 Rev. *B
Page 3 of 14
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Design Security
Output Drive Current
The CY7C342B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
250
I
OL
200
150
V
= 5.0V
CC
Room Temp.
The CY7C342B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
100
50
I
OH
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
Typical ICC vs. fMAX
Timing Considerations
400
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
300
V
CC
= 5.0V
Room Temp.
When calculating synchronous frequencies, use tSU if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
200
100
0
delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1
,
or 1/(tEXP + tS1) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
MAXIMUM FREQUENCY
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
Document #: 38-03014 Rev. *B
Page 4 of 14
USE ULTRA37000TM FOR
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CY7C342B
DC Output Current per Pin[1]................... –25 mA to +25 mA
DC Input Voltage[1] .........................................–2.0V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature ................................ –65°C to +135°C
Ambient Temperature with
Power Applied............................................ –65°C to +135°C
Maximum Junction Temperature
Range
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
–40°C to +85°C
5V ± 5%
5V ± 10%
(under bias)..................................................................150°C
Supply Voltage to Ground Potential............–2.0V to +7.0V[1]
Electrical Characteristics Over the Operating Range
Parameter
Description
Supply Voltage
Test Conditions
Maximum VCC rise time is 10 ms
IOH = –4 mA DC[2]
Min.
Max.
Unit
V
VCC
VOH
VOL
VIH
VIL
IIX
4.75(4.5) 5.25(5.5)
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
2.4
V
IOL = 8 mA DC[2]
0.45
V
2.0
–0.3
–10
–40
VCC + 0.3
V
V
Input LOW Voltage
0.8
+10
+40
100
100
Input Current
VI = VCC or ground
VO = VCC or ground
µA
µA
ns
ns
IOZ
tR
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
tF
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
Unit
pF
CIN
10
20
COUT
pF
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.0V
90%
10%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
GND
≤ 6 ns
≤ 6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The I parameter refers to high-level TTL output current; the I parameter refers to low-level TTL output current.
OH
OL
Document #: 38-03014 Rev. *B
Page 5 of 14
USE ULTRA37000TM FOR
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CY7C342B
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-15
7C342B-20
Parameter
tPD1
tPD2
tSU
Description
Dedicated Input to Combinatorial Output Delay[3]
I/O Input to Combinatorial Output Delay[3]
Global Clock Set-Up Time
Min.
Max.
15
Min.
Max.
20
Unit
ns
25
33
ns
10
13
ns
tCO1
tH
Synchronous Clock Input to Output Delay[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[4]
Minimum Global Clock Period
8
9
ns
0
5
0
7
ns
tWH
ns
tWL
5
7
ns
fMAX
tCNT
fCNT
100
71.4
MHz
ns
12
15
Maximum Internal Global Clock Frequency[5]
83.3
66.7
MHZ
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-25
7C342B-30 7C342B-35
Parameter
tPD1
tPD2
tSU
Description
Dedicated Input to Combinatorial Output Delay[3]
I/O Input to Combinatorial Output Delay[3]
Global Clock Set-Up Time
Min. Max. Min. Max. Min. Max. Unit
25
40
30
45
35
55
ns
ns
15
20
25
ns
tCO1
tH
Synchronous Clock Input to Output Delay[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[4]
Minimum Global Clock Period
14
16
20
ns
0
8
0
0
ns
tWH
10
10
50
12.5
12.5
40
ns
tWL
8
ns
fMAX
tCNT
tODH
fCNT
62.5
MHz
ns
20
25
30
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency[5]
2
2
2
ns
50
40
33.3
MHz
Commercial and Industrial External Asynchronous Switching CharacteristicsOver Operating Range
7C342B-15
7C342B–20
Parameter
tACO1
tAS1
Description
Min.
Max.
Min.
Max.
Unit
ns
Asynchronous Clock Input to Output Delay[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[6]
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time[6]
15
20
5
5
5
5
6
6
7
7
ns
tAH
ns
tAWH
tAWL
ns
Asynchronous Clock Input LOW Time[6]
ns
tACNT
fACNT
tACO1
tAS1
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency[5]
Asynchronous Clock Input to Output Delay[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[5]
Input Hold Time from Asynchronous Clock Input
12
25
15
30
ns
83.3
66.7
MHz
5
6
6
8
10
10
tAH
Notes:
3. C1 = 35 pF.
4. The f
values represent the highest frequency for pipeline data.
MAX
5. This parameter is measured with a 16-bit counter programmed into each LAB
6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
and t
parameters must be swapped.
AWH
AWL
Document #: 38-03014 Rev. *B
Page 6 of 14
USE ULTRA37000TM FOR
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CY7C342B
CommercialandIndustrialExternalAsynchronousSwitchingCharacteristicsOverOperatingRange(continued)
7C342B-15
7C342B–20
Parameter
tAWH
Description
Asynchronous Clock Input HIGH Time[5]
Asynchronous Clock Input LOW Time[5]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency[5]
Min.
11
Max.
Min.
14
Max.
Unit
16
tAWL
9
11
14
tACNT
20
25
fACNT
50
40
33.3
Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range
7C342B-15
7C342B-20
Parameter
tIN
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Min.
Max.
Min.
Max.
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
8
8
5
3
5
5
tIO
4
tEXP
tLAD
tLAC
tOD
10
12
5
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[3]
Output Buffer Enable Delay[3]
Output Buffer Disable Delay[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
3
[8]
tZX
5
tXZ
5
tRSU
tRH
tLATCH
tRD
tCOMB
tIC
tICS
tFD
2
7
1
10
1
1
1
1
Register Delay
[9]
Transparent Mode Delay
1
1
Asynchronous Clock Logic Delay
Synchronous Clock Delay
6
8
0
0
Feedback Delay
1
1
tPRE
tCLR
tPIA
tIN
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
3
3
3
3
10
5
13
7
tIO
6
6
tEXP
tLAD
tLAC
tOD
12
12
10
5
14
14
12
5
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[3]
Output Buffer Enable Delay[3]
Output Buffer Disable Delay[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
[8]
tZX
10
10
11
11
tXZ
tRSU
tRH
tLATCH
tRD
6
4
8
6
10
8
3
1
4
2
Register Delay
Notes:
7. C1 = 5 pF.
8. Sample tested only for an output change of 500 mV.
9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03014 Rev. *B
Page 7 of 14
USE ULTRA37000TM FOR
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CY7C342B
Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range (continued)
7C342B-25
7C342B-30
7C342B-35
Parameter
Description
Transparent Mode Delay
Min. Max. Min. Max. Min. Max. Unit
[9]
tCOMB
3
14
3
4
16
2
4
16
1
ns
ns
ns
ns
ns
ns
ns
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
tICS
tFD
Feedback Delay
1
1
2
tPRE
tCLR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
5
6
7
5
6
7
14
16
20
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
tWH
External Synchronous
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
Document #: 38-03014 Rev. *B
Page 8 of 14
USE ULTRA37000TM FOR
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CY7C342B
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
t
IO
I/O PIN
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
t
OD
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
Document #: 38-03014 Rev. *B
Page 9 of 14
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CLOCK PIN
t
t
ICS
IN
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Ordering Information
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
15
CY7C342B-15JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
20
25
CY7C342B-20JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
CY7C342B-25HC/HI
CY7C342B-25JC/JI
CY7C342B-25RC/RI
CY7C342B-30JC/JI
H81
J81
R68
J81
68-pin Windowed Leaded Chip Carrier
68-lead Plastic Leaded Chip Carrier
68-pin Windowed Ceramic Pin Grid Array
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
30
35
Commercial/
Industrial
CY7C342B-35JC/JI
CY7C342B-35RJ/RI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
R68
68-pin Windowed Ceramic Pin Grid Array
Document #: 38-03014 Rev. *B
Page 10 of 14
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Package Diagrams
68-pin Windowed Leaded Chip Carrier H81
51-80080-**
Document #: 38-03014 Rev. *B
Page 11 of 14
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Package Diagrams (continued)
68-lead Plastic Leaded Chip Carrier J81
51-85005-*A
Document #: 38-03014 Rev. *B
Page 12 of 14
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Package Diagrams (continued)
68-Pin Windowed PGA Ceramic R68
51-80099-*A
MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress
Semiconductor Corporation. All product and company ames mentioned in this document are the trademarks of their respective
holders.
Document #: 38-03014 Rev. *B
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Document History Page
Document Title: CY7C342B 128-Macrocell MAX® EPLD
Document Number: 38-03014
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-00119 to 38-03014
PGA package diagram dimensions were updated
106314
113612
213375
04/25/01
04/11/02
See ECN
SZV
OOR
FSG
*A
*B
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03014 Rev. *B
Page 14 of 14
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