CY7C344B-15JIT [CYPRESS]
OT PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | CY7C344B-15JIT |
| 厂家： | 
CYPRESS |
| 描述： | OT PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28 时钟 输入元件 可编程逻辑 |
| 文件： | 总12页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USE ULTRA37000™
FOR ALL NEW DESIGNS
CY7C344B
32-Macrocell MAX® EPLD
densest EPLD of this size. Eight dedicated inputs and 16
bidirectional I/O pins communicate to one logic array block. In
the CY7C344B LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• Advanced 0.65-micron CMOS EPROM technology to
increase performance
The speed and density of the CY7C344B makes it a natural
for all types of applications. With just this one device, the
designer can implement complex state machines, registered
logic, and combinatorial “glue” logic, without using multiple
chips. This architectural flexibility allows the CY7C344B to
replace multichip TTL solutions, whether they are
synchronous, asynchronous, combinatorial, or all three.
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded
ceramic chip carrier (HLCC), the CY7C344B represents the
Logic Block Diagram[1]
Pin Configurations
HLCC
Top View
15(22) INPUT
15(23) INPUT
INPUT
1(8)
INPUT/CLK 2(9)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
13(20)
14(21)
4
3
2
1
28 27 26
25
5
6
7
8
9
10
11
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
MACROCELL 2
MACROCELL 1
I/O 3(10)
I/O 4(11)
I/O 5(12)
I/O 6(13)
I/O 9(16)
I/O 10(17)
I/O 11(18)
I/O 12(19)
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
I/O 23(2)
I/O 24(3)
I/O 25(4)
I/O 26(5)
24
23
22
21
20
19
INPUT
INPUT
INPUT
INPUT
I/O
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
G
L
I
O
O
B
A
L
I/O
12 13 14 1516 1718
C
O
N
T
B
U
S
R
O
L
CerDIP
Top View
INPUT
INPUT
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT/CLK
I/O
INPUT
I/O
2
3
4
I/O
I/O
I/O
I/O
5
6
7
I/O
I/O
V
CC
32
V
CC
64 EXPANDER PRODUCT TERM ARRAY
GND
I/O
GND
I/O
8
9
I/O
I/O
10
11
12
13
14
I/O
I/O
INPUT
I/O
I/O
INPUT
INPUT
INPUT
Selection Guide
7C344B-15
7C344B-20
7C344B-25
Unit
Maximum Access Time
15
20
25
ns
Note:
1. Number in () refers to J-leaded packages.
Cypress Semiconductor Corporation
Document #: 38-03036 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 6, 2005
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
DC Output Current, per Pin[2]...................–25 mA to +25 mA
DC Input Voltage[2] .........................................–2.0V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range[3]
Storage Temperature .................................–65°C to +135°C
Ambient
Ambient Temperature with
Power Applied..............................................-65°C to +135°C
Range
Commercial
Industrial
Temperature
–0°C to +70°C
–40°C to +85°C
VCC
5V ±5%
5V ±10%
Maximum Junction Temperature (Under Bias).............150°C
Supply Voltage to Ground Potential[2]............ –2.0V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Maximum VCC rise time is 10 ms
IOH = –4.0 mA DC[4]
Min.
4.75(4.5)
2.4
Max.
Unit
V
VCC
Supply Voltage
5.25(5.5)
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
V
IOL = 8 mA DC[4]
0.45
VCC+0.3
0.8
V
2.0
–0.3
–10
–40
V
Input LOW Level
V
Input Current
GND ≤ VIN ≤ VCC
+10
µA
µA
ns
ns
IOZ
tR
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
VO = VCC or GND
+40
100
tF
100
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
10
Unit
pF
CIN
COUT
12
pF
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
t
f
≤ 6 ns
≤ 6 ns
INCLUDING
JIGAND
tR
tF
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial)
163Ω
OUTPUT
1.75V
Notes:
2. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods
shorter than 20 ns.
3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. The I parameter refers to high-level TTL output current; the I parameter refers to low-level TTL output current.
OH
OL
Document #: 38-03036 Rev. *D
Page 2 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
are guaranteed to function properly with
synchronous clock under worst-case environmental and
supply voltage conditions.
a common
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
Typical ICC vs. fMAX
240
180
V
CC
=5.0V
Room Temp.
For proper operation, input and output pins must be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled.
120
60
0
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
Timing Considerations
MAXIMUM FREQUENCY
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay.
Output Drive Current
When calculating synchronous frequencies, use tSU if all
inputs are on the input pins. When expander logic is used in
the data path, add the appropriate maximum expander delay,
t
EXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP
250
200
150
+ tSU) is the lowest frequency. The lowest of these frequencies
is the maximum data-path frequency for the synchronous
configuration.
I
OL
When calculating external asynchronous frequencies, use
t
V
CC
=5.0V
AS1 if all inputs are on dedicated input pins.
Room Temp.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data-path frequency for the asynchronous configu-
ration.
100
50
I
OH
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
Document #: 38-03036 Rev. *D
Page 3 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
CONTROLDELAY
CLR
INPUT
t
LAC
t
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
IN
t
LOGIC ARRAY
DELAY
t
RSU
RD
t
t
t
COMB
LATCH
t
t
t
RH
t
LAD
SYSTEM CLOCK DELAYt
ICS
CLOCK
DELAY
I/O
I/O DELAY
I/O
t
IC
t
IO
FEEDBACK
DELAY
t
FD
Figure 1. CY7C344B Timing Model
External Synchronous Switching CharacteristicsOver Operating Range
7C344B-15
7C344B-20
7C344B-25
Parameter
tPD1
tPD2
tSU
Description
Min. Max. Min. Max. Min. Max. Unit
Dedicated Input to Combinatorial Output Delay[5] Com’l/Ind
I/O Input to Combinatorial Output Delay[5]
15
15
20
20
25
25
ns
ns
ns
ns
ns
ns
ns
Com’l/Ind
Com’l/Ind
Com’l/Ind
Global Clock Set-up Time
Synchronous Clock Input to Output Delay[5]
9
12
15
tCO1
tH
10
13
12
15
Input Hold Time from Synchronous Clock Input Com’l/Ind
0
6
6
0
7
7
0
8
8
tWH
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[6]
Minimum Global Clock Period
Com’l/Ind
Com’l/Ind
tWL
fMAX
tCNT
tODH
fCNT
Com’l/Ind 83.3
Com’l/Ind
71.4
16
62.5 MHz
20
ns
ns
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency[7]
Com’l/Ind
1
1
1
Com’l/Ind 76.9
62.5
50
MHz
Notes:
5. C1 = 35 pF
6. The f
values represent the highest frequency for pipeline data.
MAX
7. This parameter is measured with a 32-bit counter programmed into each LAB.
Document #: 38-03036 Rev. *D
Page 4 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
External Asynchronous Switching Characteristics Over Operating Range
7C344B-15 7C344B-20 7C344B-25
Min. Max. Min. Max. Min. Max. Unit
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[5]
Com’l/Ind
Com’l/Ind
15
18
22
ns
ns
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
5
6
8
tAH
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time[8]
Asynchronous Clock Input LOW Time[8]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency[7]
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
5
6
7
6
7
9
8
9
ns
ns
tAWH
tAWL
tACNT
fACNT
11
ns
13
16
20
ns
Com’l/Ind 76.9
62.5
50
MHz
Typical Internal Switching Characteristics Over Operating Range
7C344B-15
7C344B-20
7C344B-25
Parameter
tIN
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Min. Max. Min. Max. Min. Max. Unit
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l /Ind
Com’l/Ind
3
3
8
7
4
4
7
7
5
5
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tEXP
tLAD
tLAC
tOD
10
10
4
15
13
4
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[5]
Output Buffer Enable Delay[5]
Output Buffer Disable Delay[5]
4
4
tZX
7
7
tXZ
7
7
tRSU
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
4
5
4
8
5
tRH
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
10
ns
tLATCH
tRD
tCOMB
tIC
Flow-Through Latch Delay
Register Delay
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
1
1
1
7
2
1
5
5
1
1
1
8
2
1
6
6
1
1
ns
ns
ns
ns
ns
ns
ns
ns
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
1
10
3
tICS
tFD
1
tPRE
Asynchronous Register Preset Time
Asynchronous Register Clear Time
9
tCLR
9
Note:
8. This parameter is measured with a positive-edge-triggered clock at the register. For the negative-edge clocking, the t
and t
parameter must be swapped.
ACH
ACL
Document #: 38-03036 Rev. *D
Page 5 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
OD
t
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Document #: 38-03036 Rev. *D
Page 6 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
I/O PIN
t
IO
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
Document #: 38-03036 Rev. *D
Page 7 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CLOCK PIN
t
t
ICS
IN
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C344B-15HC/HI
CY7C344B-15JC/JI
CY7C344B-15PC/PI
CY7C344B-15WC/WI
CY7C344B-20HC/HI
CY7C344B-20JC/JI
CY7C344B-20PC/PI
CY7C344B-20WC/WI
CY7C344B-25HC/HI
CY7C344B-25JC/JI
CY7C344B-25PC/PI
Package Type
15
H64
J64
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial/Industrial
Commercial/Industrial
Commercial/Industrial
P21
W22
H64
J64
28-Lead Windowed CerDIP
20
25
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
Document #: 38-03036 Rev. *D
Page 8 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
51-80077-**
Document #: 38-03036 Rev. *D
Page 9 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
28-Lead (300-Mil) PDIP P21
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
Document #: 38-03036 Rev. *D
Page 10 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Package Diagrams (continued)
(300-Mil)
28-Lead
Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087-**
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03036 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C344B
Document History Page
Document Title: CY7C344 32-Macrocell MAX® EPLD
Document Number: 38-03036
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106381
122235
213375
238565
373715
06/15/01
12/28/02
See ECN
See ECN
See ECN
SZV
RBI
Change from Spec #: 38-00860 to 38-03036
*A
Power-up requirements added to Operating Range Information
Added note to title page: “Use Ultra37000 For All New Designs”
Minor change: fixed error in part number in header
Corrected header information
*B
FSG
KKV
PCX
*C
*D
Document #: 38-03036 Rev. *D
Page 12 of 12
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