CY7C346-25HI [CYPRESS]
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD); 使用ULTRA37000TM所有新设计（ 128个宏单元的MAX EPLD ）
| 型号： | CY7C346-25HI |
| 厂家： | 
CYPRESS |
| 描述： | USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) |
| 文件： | 总21页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
128-Macrocell MAX® EPLD
The 128 macrocells in the CY7C346 are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Features
• 128 macrocells in eight logic array blocks (LABs)
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
• 0.8-micron double-metal CMOS EPROM technology
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
The speed and density of the CY7C346 allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346 allows the replacement of over
50 TTL devices. By replacing large amounts of logic, the
CY7C346 reduces board space, part count, and increases
system reliability.
Functional Description
The CY7C346 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Logic Block Diagram
INPUT [59] (N4) . 36
INPUT [60] (M5) . 37
INPUT [61] (N5) . 38
INPUT [64] (N6) . 41
INPUT [65] (M7) . 42
INPUT [66] (L7) . 43
INPUT [67] (N7) . 44
INPUT [70] (L8) . 47
INPUT [71] (N9) . 48
INPUT [72] (M9) . 49
.
1 (C7) [16] INPUT/CLK
..
. 78 (A10) [9] .....
. 79 (B9) [10] .....
80 (A9) [11] .....
. 83 (A8) [14] .....
. 84 (B7) [15] .....
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
..
..
..
..
2
5
6
7
(A7) [17] .....
(C6) [20] .....
(A5) [21] .....
(B5) [22] .....
SYSTEM CLOCK
LAB A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
MACROCELL 121–128
MACROCELL 9–16
LAB B
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
MACROCELL 105–112
MACROCELL 25–32
P
I
LAB C
A
LAB F
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2)[40]
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 41–48
MACROCELL 86–96
LAB D
LAB E
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL 73–80
MACROCELL 57– 64
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] –PERTAIN TO 100-PIN PQFP PACKAGE
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]
V
CC
GND
Cypress Semiconductor Corporation
Document #: 38-03005 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 19, 2004
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Selection Guide
7C346-25
25
7C346-30
7C346-35
35
Unit
ns
Maximum Access Time
30
Maximum Operating Current
Commercial
Military
250
250
320
320
225
275
275
250
mA
325
320
Industrial
Commercial
Military
320
320
Maximum Standby Current
225
225
mA
275
275
Industrial
275
275
Pin Configurations
PLCC/CLCC
Top View
PGA
Bottom View
79 78 77 76
5 4 3 2 1 84 83 82 81 80
7
8
6
10
75
74
9
11
I/O I/O I/O INP INP INP INP
I/O I/O I/O I/O INP GND INP
V
INP I/O I/O I/O
I/O
I/O
N
CC
I/O
I/O
12
13
14
15
I/O
I/O
V
CC
INP I/O I/O I/O
M
73
72
71
70
69
68
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
GND INP INP
I/O
I/O
I/O
I/O
I/O
I/O
L
K
J
16
I/O
I/O
17
18
19
20
21
I/O
I/O
GND
GND
I/O
67
I/O
V
V
V
CC
I/O
GND GND I/O
I/O I/O I/O
I/O
H
G
F
E
CC
66
65
CC
V
CY7C346
CC
I/O I/O I/O
I/O GND GND
I/O
22
23
I/O
64
63
62
61
60
59
V
CC
I/O
V
CC
V
CC
CY7C346
V
24
25
26
CC
GND
GND
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
D
I/O
I/O
I/O
27
28
29
30
31
32
I/O
58
57
56
55
54
I/O
I/O
I/O
INP
/CLK
I/O I/O
INP
GND
I/O
I/O
I/O
C
B
I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
INP GND INP I/O I/O I/O
INP INP INP INP I/O I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
I/O
13
A
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
2
3
4
5
6
7
9
10 11
12
8
Document #: 38-03005 Rev. *B
Page 2 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Pin Configurations (continued)
PQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
1
2
I/O
80
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
3
4
77
76
I/O
5
6
7
8
9
I/O
75
74
73
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
72
71
70
10
11
12
13
V
CC
GND
GND
69
68
V
CC
INPUT
INPUT
INPUT
67
66
65
14
15
16
17
18
19
20
21
INPUT
INPUT/CLK
INPUT
INPUT
INPUT
CY7C346
64
63
62
V
CC
GND
V
CC
GND
INPUT
INPUT
INPUT
61
60
INPUT
INPUT
INPUT
59
58
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
57
56
55
54
I/O
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
53
52
29
30
I/O
I/O
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-03005 Rev. *B
Page 3 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
that may be individually configured for input, output, or bidirec-
tional data flow.
Logic Array Blocks
There are eight logic array blocks in the CY7C346. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Timing Delays
Timing delays within the CY7C346 may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
software. The CY7C346 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Externally, the CY7C346 provides 20 dedicated inputs, one of
which may be used as a system clock. There are 64 I/O pins
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
CONTROL DELAY
CLR
INPUT
t
LAC
t
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
IN
t
LOGIC ARRAY
DELAY
t
RSU
RD
t
t
t
COMB
LATCH
t
t
t
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
IC
t
PIA
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
Figure 1. CY7C346 Internal Timing Model
(either VCC or GND). Each set of VCC and GND pins must
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C346 contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
Design Security
The CY7C346 contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
For proper operation, input and output pins must be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level
Document #: 38-03005 Rev. *B
Page 4 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
obtained since programmed data within EPROM cells is
Timing Considerations
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
The CY7C346 is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
When calculating synchronous frequencies, use tS1 if all
inputs are on dedicated input pins. The parameter tS2 should
be used if data is applied at an I/O pin. If tS2 is greater than
tCO1, 1/tS2 becomes the limiting frequency in the data path
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
mode unless 1/(tWH + tWL) is less than 1/tS2
.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tS1. Determine which
of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
Typical ICC vs. fMAX
400
When calculating external asynchronous frequencies, use
t
AS1 if all inputs are on the dedicated input pins. If any data
is applied to an I/O pin, tAS2 must be used as the required
set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH
300
)
V
= 5.0V
CC
becomes the limiting frequency in the data path mode unless
1/(tAWH + tAWL) is less than 1/(tAS2 + tAH).
Room Temp.
200
100
0
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
Output Drive Current
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same asynchronous clock
as the CY7C346.
100
80
I
OL
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous) then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same.
This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This
is due to the expander logic in the second device’s clock
signal path adding an additional delay (tEXP) causing the
output data from the preceding device to change prior to the
arrival of the clock signal at the following device’s register.
V
= 5.0V
CC
60
Room Temp.
40
20
I
OH
0.45
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
Document #: 38-03005 Rev. *B
Page 5 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
DC Output Current per Pin ...................... –25 mA to +25 mA
DC Input Voltage[1] .........................................–3.0V to +7.0V
DC Program Voltage..................................................... 13.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 1100V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to+150°C
Ambient Temperature with
Power Applied............................................. –55°C to+125°C
Operating Range
Maximum Junction Temperature
(under bias)..................................................................150°C
Supply Voltage to Ground Potential...............–2.0V to +7.0V
Maximum Power Dissipation...................................2500 mW
DC VCC or GND Current............................................500 mA
Range
Commercial
Industrial
Military
Ambient Temperature
0°C to +70°C
VCC
5V ± 5%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C (Case)
Electrical Characteristics Over the Operating Range[2]
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
Max.
0.45
Unit
V
VCC = Min., IOH = –4.0 mA
2.4
VCC = Min., IOL = 8.0 mA
V
2.2
–0.3
–10
–40
–30
VCC + 0.3
0.8
V
VIL
V
IIX
Input Current
GND < VIN < VCC
+10
µA
µA
mA
mA
IOZ
Output Leakage Current
Output Short Circuit Current
VO = VCC or GND
VCC = Max., VOUT = 0.5V[3, 4]
+40
IOS
–90
ICC1
Power Supply Current (Standby) VI = GND (No Load)
Commercial
225
Military/Industrial
275
ICC2
Power Supply Current[5]
VI = VCC or GND (No Load) Commercial
250
mA
f = 1.0 MHz[4]
Military/Industrial
320
tR
tF
Recommended Input Rise Time
Recommended Input Fall Time
100
ns
ns
100
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 2V, f = 1.0 MHz
VOUT = 2V, f = 1.0 MHz
10
20
pF
pF
COUT
AC Test Loads and Waveforms[6]
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
≤ 6 ns
≤ 6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (Commercial/Military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns.
2. Typical values are for T = 25°C and V = 5V.
A
CC
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
test problems caused by tester ground degradation.
= 0.5V has been chosen to avoid
OUT
4. Guaranteed by design but not 100% tested.
5. This parameter is measured with device programmed as a 16-bit counter in each LAB.
6. Part (a) in AC Test Load and Waveforms is used for all parameters except t and t , which is used for part (b) in AC Test Load and Waveforms. All external
ER
XZ
timing parameters are measured referenced to external pins of the device.
Document #: 38-03005 Rev. *B
Page 6 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
7C346-25
7C346-30
7C346-35
Parameter
tPD1
Description
Min. Max. Min. Max. Min. Max. Unit
Dedicated Input to Combinatorial Output Delay[7]
I/O Input to Combinatorial Output Delay[10]
25
40
37
30
45
44
35
55
55
ns
ns
ns
tPD2
tPD3
Dedicated Input to Combinatorial Output Delay with Expander
Delay[11]
tPD4
I/O Input to Combinatorial Output Delay with Expander
52
59
75
ns
Delay[4, 12]
tEA
Input to Output Enable Delay[4, 7]
Input to Output Disable Delay[4, 7]
Synchronous Clock Input to Output Delay
25
25
14
30
30
30
16
35
35
35
20
42
ns
ns
ns
ns
tER
tCO1
tCO2
Synchronous Clock to Local Feedback to Combinatorial
Output[4, 13]
tS1
Dedicated Input or Feedback Set-Up Time to Synchronous
15
20
25
ns
Clock Input[7, 14]
tS2
I/O Input Set-Up Time to Synchronous Clock Input[7]
Input Hold Time from Synchronous Clock Input[7]
Synchronous Clock Input HIGH Time
30
0
36
0
45
0
ns
ns
tH
tWH
tWL
tRW
tRR
tRO
tPW
tPR
tPO
tCF
8
10
10
30
30
12.5
12.5
35
ns
Synchronous Clock Input LOW Time
Asynchronous Clear Width[4, 7]
Asynchronous Clear Recovery Time[4, 7]
Asynchronous Clear to Registered Output Delay[7]
Asynchronous Preset Width[4, 7]
Asynchronous Preset Recovery Time[4, 7]
Asynchronous Preset to Registered Output Delay[7]
Synchronous Clock to Local Feedback Input[4, 15]
8
ns
25
25
ns
35
ns
25
30
35
ns
25
25
30
30
35
35
ns
ns
25
3
30
3
35
6
ns
ns
[4]
tP
External Synchronous Clock Period (1/(fMAX3
)
16
20
25
ns
fMAX1
fMAX2
External Feedback Maximum Frequency (1/(tCO1 + tS1))[4, 16] 34.5
27.7
43.4
22.2
32.2
MHz
MHz
Internal Local Feedback Maximum Frequency, lesser of
55.5
[4, 17]
(1/(tS1 + tCF)) or (1/tCO1
)
fMAX3
fMAX4
Data Path Maximum Frequency, lesser of (1/(tWL + tWH)),
62.5
50
40
MHz
[4, 18]
(1/(tS1 + tH)) or (1/tCO1
Maximum Register Toggle Frequency (1/(tWL + tWH
Output Data Stable Time from Synchronous Clock Input[4, 20]
)
[4, 19]
)
62.5
3
50
3
40
3
MHz
ns
tOH
Notes:
7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial
output on any output pin. This delay assumes no expander terms are used to form the logic function.
8. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset)
is applied to a dedicated input only and no signal path (either clock or data) employs expander logic.
9. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used,
add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders.
10. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
11. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial
output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic.
12. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
13. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array
and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This
parameter is tested periodically by sampling production material.
14. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for
synchronous operation and tAS2 for asynchronous operation.
15. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array
input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for
feedback within the same LAB. This parameter is tested periodically by sampling production material.
16. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can
operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs.
17. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must
also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local originating
within the same LAB.
18. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data
input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation.
19. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock
signal applied to the dedicated clock input pin.
20. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.This
specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic
array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The
clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
Document #: 38-03005 Rev. *B
Page 7 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-25
7C346-30
7C346-35
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[7]
Min. Max. Min. Max. Min. Max. Unit
25
39
30
46
35
55
ns
ns
tACO2
Asynchronous Clock Input to Local Feedback to Combinatorial
Output[20]
tAS1
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[7]
5
6
8
ns
tAS2
tAH
I/O Input Set-Up Time to Asynchronous Clock Input[7]
Input Hold Time from Asynchronous Clock Input[7]
Asynchronous Clock Input HIGH Time[7]
Asynchronous Clock Input LOW Time[7, 21]
Asynchronous Clock to Local Feedback Input[4, 22]
External Asynchronous Clock Period (1/(fMAXA4))[4]
19
6
22
8
28
10
16
14
ns
ns
tAWH
tAWL
tACF
tAP
11
9
14
11
ns
ns
15
18
22
ns
20
25
30
ns
fMAXA1
External Feedback Maximum Frequency in Asynchronous
Mode (1/(tACO1 + tAS1))[4, 23]
33.3
27.7
23.2
MHz
fMAXA2
fMAXA3
fMAXA4
Maximum Internal Asynchronous Frequency[4, 24]
Data Path Maximum Frequency in Asynchronous Mode[4, 25]
50
40
50
40
33.3
40
33.3
28.5
33.3
MHz
MHz
MHz
Maximum Asynchronous Register Toggle Frequency 1/(tAWH
[4, 26]
+ tAWL
)
tAOH
Output Data Stable Time from Asynchronous Clock Input[4, 27] 15
15
15
ns
Notes:
21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay
is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin.
This parameter is tested periodically by sampling production material.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the clock
signal path or data path.
24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
This parameter is determined by the lesser of (1/(t
+ t
)) or (1/(t
ACO1
+ t
)). If register output states must also control external points, this frequency can
ACF
AS1
AWH
AWL
still be observed as long as this frequency is less than 1/t
.
This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single
LAB. This parameter is tested periodically by sampling production material.
25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by
the lesser of 1/(t
+ t
), 1/(t
+ t ) or 1/t
. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
AWH
AWL
AS1
AH
ACO1
26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
by a clock signal applied to an external dedicated input pin.
27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied
to an external dedicated input pin.
Document #: 38-03005 Rev. *B
Page 8 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346-25
7C346-30
7C346-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIN
tIO
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
5
7
9
6
6
9
tEXP
tLAD
tLAC
tOD
12
12
10
5
14
14
12
5
20
16
13
6
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
tZX
10
10
11
11
13
13
tXZ
tRSU
Register Set-Up Time Relative to
Clock Signal at Register
6
6
8
8
10
10
tRH
Register Hold Time Relative to Clock
Signal at Register
ns
tLATCH
tRD
tCOMB
tCH
Flow Through Latch Delay
3
1
3
4
2
4
4
2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Delay
Transparent Mode Delay[29]
Clock HIGH Time
8
8
10
10
12.5
12.5
tCL
Clock LOW Time
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
14
1
16
1
18
1
tICS
tFD
1
1
2
tPRE
tCLR
tPCW
Asynchronous Register Preset Time
Asynchronous Register Clear Time
5
6
7
5
6
7
Asynchronous Preset and Clear Pulse
Width
5
5
6
6
7
7
tPCR
Asynchronous Preset and Clear
Recovery Time
ns
ns
tPIA
Programmable Interconnect Array
Delay Time
14
16
20
Notes:
28. Sample tested only for an output change of 500 mV.
29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03005 Rev. *B
Page 9 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Military External Synchronous Switching Characteristics[6] Over Operating Range
7C346-30
7C346-35
Parameter
tPD1
tPD2
tPD3
Description
Min.
Max.
Min.
Max.
Unit
ns
Dedicated Input to Combinatorial Output Delay[7]
I/O Input to Combinatorial Output Delay[10]
30
45
44
35
55
55
ns
Dedicated Input to Combinatorial Output Delay with
Expander Delay[11]
ns
tPD4
I/O Input to Combinatorial Output Delay with
Expander Delay[4, 12]
59
75
ns
tEA
Input to Output Enable Delay[4, 7]
Input to Output Disable Delay[4, 7]
Synchronous Clock Input to Output Delay
30
30
16
35
35
35
20
42
ns
ns
ns
ns
tER
tCO1
tCO2
Synchronous Clock to Local Feedback to
Combinatorial Output[4, 13]
tS1
tS2
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input[7, 14]
20
36
25
45
ns
ns
I/O Input Set-Up Time to Synchronous Clock
Input[7]
tH
Input Hold Time from Synchronous Clock Input[7]
0
0
ns
ns
tWH
tWL
tRW
tRR
tRO
tPW
tPR
tPO
tCF
tP
Synchronous Clock Input HIGH Time
10
10
30
30
12.5
12.5
35
Synchronous Clock Input LOW Time
Asynchronous Clear Width[4, 7]
ns
ns
Asynchronous Clear Recovery Time[4, 7]
Asynchronous Clear to Registered Output Delay[7]
Asynchronous Preset Width[4, 7]
Asynchronous Preset Recovery Time[4, 7]
Asynchronous Preset to Registered Output Delay[7]
Synchronous Clock to Local Feedback Input[4, 15]
External Synchronous Clock Period (1/(fMAX3))[4]
35
ns
30
35
ns
30
30
35
35
ns
ns
30
3
35
6
ns
ns
20
25
ns
fMAX1
External Feedback Maximum Frequency
(1/(tCO1 + tS1))[4, 16]
27.7
22.2
MHz
fMAX2
fMAX3
fMAX4
tOH
Internal Local Feedback Maximum Frequency,
43.4
50
50
3
32.2
40
40
3
MHz
MHz
MHz
ns
[4, 17]
lesser of (1/(tS1 + tCF)) or (1/tCO1
)
Data Path Maximum Frequency, lesser of (1/(tWL
+
[4, 18]
t
WH)), (1/(tS1 + tH)) or (1/tCO1)
Maximum Register Toggle Frequency
(1/(tWL + tWH))[4, 19]
Output Data Stable Time from Synchronous Clock
Input[4, 20]
Document #: 38-03005 Rev. *B
Page 10 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Military External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-30
7C346-35
Parameter
tACO1
tACO2
Description
Asynchronous Clock Input to Output Delay[7]
Min.
Max.
Min.
Max.
Unit
ns
30
46
35
55
Asynchronous Clock Input to Local Feedback to
Combinatorial Output[20]
ns
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input[7]
6
8
ns
ns
tAS2
I/O Input Set-Up Time to Asynchronous Clock
Input[7]
22
28
tAH
Input Hold Time from Asynchronous Clock Input[7]
Asynchronous Clock Input HIGH Time[7]
Asynchronous Clock Input LOW Time[7, 21]
Asynchronous Clock to Local Feedback Input[4, 22]
External Asynchronous Clock Period (1/(fMAXA4))[4]
8
10
16
14
ns
ns
tAWH
tAWL
tACF
tAP
14
11
ns
18
22
ns
25
30
ns
fMAXA1
External Feedback Maximum Frequency in
Asynchronous Mode (1/(tACO1 + tAS1))[4, 23]
27.7
23.2
MHz
fMAXA2
fMAXA3
Maximum Internal Asynchronous Frequency[4, 24]
40
33.3
28.5
MHz
MHz
Data Path Maximum Frequency in Asynchronous
Mode[4, 25]
33.3
fMAXA4
tAOH
Maximum Asynchronous Register Toggle
40
15
33.3
15
MHz
ns
[4, 26]
Frequency 1/(tAWH + tAWL
)
Output Data Stable Time from Asynchronous Clock
Input[4, 27]
Document #: 38-03005 Rev. *B
Page 11 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Military Typical Internal Switching Characteristics Over Operating Range
7C346-30
7C346-35
Parameter
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Min.
Max.
7
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIN
tIO
9
6
9
tEXP
tLAD
tLAC
tOD
14
14
12
5
20
16
13
6
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
tZX
11
11
13
13
tXZ
tRSU
Register Set-Up Time Relative to Clock Signal at
Register
8
8
10
10
tRH
Register Hold Time Relative to Clock Signal at
Register
ns
tLATCH
tRD
tCOMB
tCH
Flow Through Latch Delay
4
2
4
4
2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Delay
Transparent Mode Delay[29]
Clock HIGH Time
10
10
12.5
12.5
tCL
Clock LOW Time
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
16
2
18
3
tICS
tFD
Feedback Delay
1
2
tPRE
tCLR
tPCW
tPCR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and Clear Pulse Width
Asynchronous Preset and Clear Recovery Time
Programmable Interconnect Array Delay Time
6
7
6
7
6
6
7
7
16
20
Document #: 38-03005 Rev. *B
Page 12 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
[7]
PD1
[10]
t
/t
PD2
COMBINATORIAL
OUTPUT
[7]
ER
t
t
HIGH-IMPEDANCE
THREE-STATE
COMBINATORIAL OR
REGISTERED OUTPUT
[7]
EA
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
External Synchronous
DEDICATED INPUTS OR
REGISTERED
[7]
FEEDBACK
t
t
t
t
WL
S1
H
WH
SYNCHRONOUS
CLOCK
t
t
/t
t
/t
CO1
RW PW
RR PR
ASYNCHRONOUS
CLEAR/PRESET
t
OH
[7]
t
/t
RO PO
REGISTERED
OUTPUTS
t
CO2
COMBINATORIAL OUTPUT FROM
[7]
REGISTERED FEEDBACK
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
t
AH
AWH
AWL
AS1
ASYNCHRONOUS
CLOCK INPUT
t
ACO1
t
/t
t
/t
RW PW
RR PR
ASYNCHRONOUS
CLEAR/PRESET
t
AOH
t
/t
RO PO
ASYNCHRONOUS REGISTERED
OUTPUTS
t
ACO2
COMBINATORIAL OUTPUT FROM
ASYNCHRONOUS REGISTERED
FEEDBACK
Document #: 38-03005 Rev. *B
Page 13 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
I/O PIN
t
PIA
t
IO
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
Internal Synchronous
t
t
CL
CH
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Document #: 38-03005 Rev. *B
Page 14 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
t
OD
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Document #: 38-03005 Rev. *B
Page 15 of 21
USE ULTRA37000TM FOR
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CY7C346
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
IIX
IOZ
ICC1
Switching Characteristics
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tPD1
tPD2
tPD3
tCO1
tS1
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tS2
tH
tWH
tWL
tRO
tPO
tACO1
tACO2
tAS1
tAH
tAWH
tAWL
Ordering Information
Speed
Package
(ns)
Ordering Code
CY7C346-25HC/HI
CY7C346-25JC/JI
CY7C346-25NC/NI
CY7C346-25RC/RI
CY7C346-30HC/HI
CY7C346-30JC/JI
CY7C346-30NC/NI
CY7C346-30HMB
CY7C346-30RMB
Name
Package Type
Operating Range
25
H84
84-pin Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
100-lead Plastic Quad Flatpack
Commercial/Industrial
J83
N100
R100
H84
100-pin Windowed Ceramic Pin Grid Array
84-pin Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
100-lead Plastic Quad Flatpack
30
Commercial/Industrial
Military
J83
N100
H84
84-pin Windowed Leaded Chip Carrier
100-pin Windowed Ceramic Pin Grid Array
R100
Document #: 38-03005 Rev. *B
Page 16 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Ordering Information (continued)
Speed
(ns)
Package
Name
Ordering Code
CY7C346-35JC/JI
CY7C346-35NC/NI
CY7C346-35RC/RI
CY7C346-35HMB
CY7C346-35RMB
Package Type
Operating Range
35
J83
N100
R100
H84
84-lead Plastic Leaded Chip Carrier
100-lead Plastic Quad Flatpack
Commercial/Industrial
100-pin Windowed Ceramic Pin Grid Array
84-pin Windowed Leaded Chip Carrier
100-pin Windowed Ceramic Pin Grid Array
Military
R100
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081-**
Document #: 38-03005 Rev. *B
Page 17 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-03005 Rev. *B
Page 18 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
51-85052-*A
Document #: 38-03005 Rev. *B
Page 19 of 21
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Package Diagrams (continued)
100-Pin Windowed Ceramic Pin Grid Array R100
51-80010-*C
MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress
Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective
holders.
Document #: 38-03005 Rev. *B
Page 20 of 21
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Document History Page
Document Title: CY7C346 128-Macrocell MAX® EPLD
Document Number: 38-03005
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number 38-00244 to 38-03005
PGA package diagram dimensions updated
106270
113614
213375
04/23/01
04/11/02
See ECN
SZV
OOR
FSG
*A
*B
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03005 Rev. *B
Page 21 of 21
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