CY7C346B-25JC/JI [CYPRESS]
128-Macrocell MAX㈢ EPLD; 128宏单元MAX® EPLD
| 型号： | CY7C346B-25JC/JI |
| 厂家： | 
CYPRESS |
| 描述： | 128-Macrocell MAX㈢ EPLD |
| 文件： | 总15页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USEULTRA37000™FOR
ALL NEW DESIGNS
CY7C346B
128-Macrocell MAX® EPLD
The 128 macrocells in the CY7C346B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Features
• 128 macrocells in eight logic array blocks (LABs)
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
• Advanced 0.65-micron CMOS technology to increase
performance
The speed and density of the CY7C346B allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346B allows the replacement of over
50 TTL CY7C346B. By replacing large amounts of logic, the
CY7C346B reduces board space, part count, and increases
system reliability.
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
Functional Description
The CY7C346B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Logic Block Diagram
INPUT [59] (N4) . 36
INPUT [60] (M5) . 37
INPUT [61] (N5) . 38
INPUT [64] (N6) . 41
INPUT [65] (M7) . 42
INPUT [66] (L7) . 43
INPUT [67] (N7) . 44
INPUT [70] (L8) . 47
INPUT [71] (N9) . 48
INPUT [72] (M9) . 49
.
1 (C7) [16] INPUT/CLK
.
. 78 (A10) [9] .....
. 79 (B9) [10] .....
80 (A9) [11] .....
. 83 (A8) [14] .....
. 84 (B7) [15] .....
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
.
.
.
.
2
5
6
7
(A7) [17] .....
(C6) [20] .....
(A5) [21] .....
(B5) [22] .....
SYSTEM CLOCK
LAB A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
MACROCELL 121–128
MACROCELL 9–16
LAB B
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
MACROCELL 105–112
MACROCELL 25–32
P
I
LAB C
A
LAB F
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2)[40]
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 41–48
MACROCELL 86–96
LAB D
LAB E
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL 73–80
MACROCELL 57– 64
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] –PERTAIN TO 100-PIN PQFP PACKAGE
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]
V
CC
GND
Cypress Semiconductor Corporation
Document #: 38-03037 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Selection Guide
Maximum Access Time
Pin Configurations
7C346B-25
7C346B-35
35
Unit
25
ns
PLCC/CLCC
Top View
PGA
Bottom View
79 78 77 76
5 4 3 2 1 84 83 82 81 80
7
8
6
10
75
9
11
I/O I/O I/O INP INP INP INP
I/O I/O I/O I/O INP GND INP
V
INP I/O I/O I/O
INP I/O I/O I/O
I/O
I/O
N
CC
I/O
I/O
12
13
14
15
I/O
I/O
74
73
72
71
70
69
68
V
CC
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
GND INP INP
I/O
I/O
I/O
I/O
I/O
I/O
L
K
J
16
I/O
I/O
17
18
19
20
21
I/O
I/O
GND
GND
I/O
67
I/O
V
V
V
CC
I/O
GND GND I/O
I/O I/O I/O
I/O
H
G
F
E
CC
66
65
CC
V
CC
I/O I/O I/O
I/O GND GND
I/O
22
23
7C346B
I/O
64
63
62
61
60
59
V
CC
I/O
V
CC
V
CC
V
24
25
26
CC
GND
GND
I/O
7C346B
I/O
I/O
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
D
I/O
I/O
I/O
27
28
29
30
31
32
I/O
58
57
56
55
54
I/O
I/O
I/O
INP
/CLK
I/O I/O
INP
GND
I/O
I/O
I/O
C
B
I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
INP GND INP I/O I/O I/O
INP INP INP INP I/O I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
I/O
13
A
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
2
3
4
5
6
7
9
10 11
12
8
Document #: 38-03037 Rev. *C
Page 2 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Pin Configurations (continued)
PQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
1
2
I/O
80
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
3
4
77
76
I/O
5
6
7
8
9
I/O
75
74
73
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
72
71
70
10
11
12
13
V
CC
GND
GND
69
68
V
CC
CY7C346B
INPUT
INPUT
INPUT
67
66
65
14
15
16
17
18
19
20
21
INPUT
INPUT/CLK
INPUT
INPUT
INPUT
64
63
62
V
CC
GND
V
CC
GND
INPUT
INPUT
INPUT
61
60
INPUT
INPUT
INPUT
59
58
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
57
56
55
54
I/O
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
53
52
29
30
I/O
I/O
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-03037 Rev. *C
Page 3 of 15
USE ULTRA37000™ FOR
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CY7C346B
Externally, the CY7C346B provides 20 dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Logic Array Blocks
There are eight logic array blocks in the CY7C346B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROL DELAY
CLR
INPUT
t
LAC
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
IC
t
PIA
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
C346B–9
Figure 1. CY7C346B Internal Timing Model
be connected directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Recommendations
Operation of the devices described herein with conditions
above those listed in the “Maximum Ratings” section of this
datasheet may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure
to absolute maximum ratings conditions for extended periods
of time may affect device reliability. The CY7C346B contains
circuitry to protect device pins from high static voltages or
electric fields, but normal precautions should be taken to avoid
application of any voltage higher than the maximum rated
voltages.
Design Security
The CY7C346B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
For proper operation, input and output pins must be
constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level
(either VCC or GND). Each set of VCC and GND pins must
Document #: 38-03037 Rev. *C
Page 4 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
program data, may be reset simply by erasing the entire
device.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
The CY7C346B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
When calculating synchronous frequencies, use tSU if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1
,
or 1/(tEXP + tSU) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
Typical ICC vs. fMAX
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins.
400
When expander logic is used in the data path, add the
appropriate maximum expander delay, tEXP to tAS1
Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP
tAS1 is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
asynchronous configuration.
.
+
300
V
= 5.0V
CC
)
Room Temp.
200
100
0
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
Output Drive Current
250
200
150
I
OL
V
= 5.0V
CC
Room Temp.
100
50
I
OH
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
Document #: 38-03037 Rev. *C
Page 5 of 15
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CY7C346B
DC Output Current per Pin[1].................... –25 mA to+25 mA
DC Input Voltage[1] ........................................–2.0V to + 7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range[2]
Storage Temperature ................................. –65°C to+135°C
Ambient Temperature with
Power Applied............................................. –65°C to+135°C
Maximum Junction Temperature
(under bias)..................................................................150°C
Supply Voltage to Ground Potential[1].............–2.0V to+7.0V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
5V ± 5%
5V ± 10%
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Supply Voltage
Test Conditions
Maximum VCC rise time is 10 ms
IOH = –4 mA DC[3]
Min.
Max.
Unit
VCC
VOH
VOL
VIH
VIL
IIX
4.75(4.5) 5.25(5.5)
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
2.4
IOL = 8 mA DC[3]
0.45
V
2.0
–0.3
–10
–40
VCC +0.3
0.8
V
Input LOW Voltage
V
Input Current
VI = VCC or ground
VO = VCC or ground
+10
µA
µA
ns
ns
IOZ
tR
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
+40
100
tF
100
Capacitance
Parameter
Description
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
10
20
COUT
pF
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
≤ 6 ns
≤ 6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. The I parameter refers to high-level TTL output current; the I parameter refers to low-level TTL output current.
OH
OL
Document #: 38-03037 Rev. *C
Page 6 of 15
USE ULTRA37000™ FOR
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CY7C346B
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C346B-25
7C346B-35
Parameter
Description
Min.
Max.
Min.
Max.
Unit
ns
tPD1
tPD2
tSU
Dedicated Input to Combinatorial Output Delay[4]
I/O Input to Combinatorial Output Delay[4]
Global Clock Set-Up Time
25
40
35
55
ns
15
25
ns
tCO1
tH
tWH
tWL
Synchronous Clock Input to Output Delay[4]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[5]
Minimum Global Clock Period
14
20
20
30
ns
0
8
0
ns
12.5
12.5
40
ns
8
ns
fMAX
tCNT
tODH
fCNT
62.5
MHz
ns
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency[6]
2
2
ns
50
33.3
MHz
Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range
7C346B-25
7C346B-35
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[4]
Min.
Max.
Min.
Max.
Unit
ns
25
35
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
5
10
ns
tAH
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time[7]
Asynchronous Clock Input LOW Time[7]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency[6]
6
11
9
10
16
14
ns
ns
tAWH
tAWL
tACNT
fACNT
ns
20
30
ns
50
33.3
MHz
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346B-25
7C346B-35
Parameter
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Min.
Max.
Min.
Max.
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIN
5
tIO
6
11
tEXP
tLAD
tLAC
tOD
tZX
12
12
10
5
20
14
13
6
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[4]
Output Buffer Enable Delay[4]
Output Buffer Disable Delay[8]
10
10
13
13
tXZ
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
6
4
12
8
tRH
Register Hold Time Relative to Clock Signal at
Register
ns
tLATCH
tRD
Flow Through Latch Delay
Register Delay
3
1
4
2
ns
ns
Notes:
4. C1 = 35 pF.
5. The f
values represent the highest frequency for pipeline data.
MAX
6. This parameter is measured with a 16-bit counter programmed into each LAB.
7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t
8. C1 = 5 pF.
and t
parameter must be swapped.
ACH
ACL
Document #: 38-03037 Rev. *C
Page 7 of 15
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CY7C346B
Commercial and Industrial Internal Switching Characteristics Over Operating Range (continued)
7C346B-25
Min. Max.
7C346B-35
Min. Max.
Parameter
tCOMB
Description
Transparent Mode Delay
Unit
ns
3
14
3
4
16
1
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
ns
tICS
tFD
ns
Feedback Delay
1
2
ns
tPRE
tCLR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
5
7
ns
5
7
ns
14
20
ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
tWH
External Synchronous
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
Document #: 38-03037 Rev. *C
Page 8 of 15
USE ULTRA37000™ FOR
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CY7C346B
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
I/O PIN
t
IO
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
Document #: 38-03037 Rev. *C
Page 9 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Switching Waveforms (continued)
Internal Synchronous
SYSTEM CLOCK PIN
t
t
ICS
IN
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
OD
t
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Ordering Information
Speed (ns)
Ordering Code
CY7C346B-25HC/HI
CY7C346B-25JC/JI
CY7C346B-25NC/NI
CY7C346B-25RC/RI
CY7C346B-35HC/HI
CY7C346B-35JC/JI
CY7C346B-35NC/NI
CY7C346B-35RC/RI
Package Name
H84
Package Type
Operating Range
25
84-pin Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
100-lead Plastic Quad Flatpack
Commercial/Industrial
J83
N100
R100
H84
100-pin Windowed Ceramic Pin Grid Array
84-pin Windowed Leaded Chip Carrier
84-lead Plastic Leaded Chip Carrier
100-lead Plastic Quad Flatpack
35
Commercial/Industrial
J83
N100
R100
100-pin Windowed Ceramic Pin Grid Array
Document #: 38-03037 Rev. *C
Page 10 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams
84-leaded Windowed Leaded Chip Carrier H84
51-80081-**
Document #: 38-03037 Rev. *C
Page 11 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
84-lead Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-03037 Rev. *C
Page 12 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
51-85052-*A
Document #: 38-03037 Rev. *C
Page 13 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Package Diagrams (continued)
110000--ppiinn Windowed Ceramic Pin Grid Array R100
51-80010-*C
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-03037 Rev. *C
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C346B
Document History Page
Document Title: CY7C346B 128-Macrocell Max® EPLD
Document Number: 38-03037
Orig. of
REV.
**
ECN NO. Issue Date Change Description of Change
106460
113615
122236
213375
07/11/01
04/11/02
12/28/02
See ECN
SZV
OOR
RBI
Change from Spec Number: 38-00861 to 38-03037
PGA diagram dimensions were updated
*A
*B
Power up requirements added to Operating Range Information
Added note to title page: “Use Ultra37000 For All New Designs”
*C
FSG
Document #: 38-03037 Rev. *C
Page 15 of 15
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