CY7C371IL-83AC [CYPRESS]
Flash PLD, 12ns, 32-Cell, CMOS, PQFP44, PLASTIC, TQFP-44;
| 型号： | CY7C371IL-83AC |
| 厂家： | 
CYPRESS |
| 描述： | Flash PLD, 12ns, 32-Cell, CMOS, PQFP44, PLASTIC, TQFP-44 |
| 文件： | 总12页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Features
• 32 macrocells in two logic blocks
• 32 I/O pins
Like all of the UltraLogic™ FLASH370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— fMAX = 143 MHz
— tPD= 8.5 n3s
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
— tS = 5 ns
— tCO = 6 ns
• Fully PCI-compliant
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i
Functional Description
Like all members of the FLASH370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C371i is
Clock
Inputs Inputs
Logic Block Diagram
3
2
INPUT
MACROCELLS
INPUT/CLOCK
MACROCELLS
2
2
16 I/Os
16 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
B
36
16
36
16
PIM
I/O0–I/O15
I/O16–I/O31
16
16
Selection Guide
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66
Unit
ns
Maximum Propagation Delay[1], tPD
Minimum Set-up, tS
Maximum Clock to Output[1], tCO
8.5
5
10
6
12
8
12
8
15
10
10
75
15
10
10
45
ns
6
6.5
75
8
8
ns
Typical Supply Current, ICC Comm./Ind.
75
75
45
mA
Note:
1. The 3.3V I/O mode timing adder, t
, must be added to this specification when V
= 3.3V.
3.3IO
CCIO
Cypress Semiconductor Corporation
Document #: 38-03032 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 19, 2004
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Pin Configurations
TQFP
Top View
PLCC
Top View
44 43 42 41 40 39 38 37 36 35 34
6
5
4
3
2
1
44 43 42 41 40
I/O /SDI
27
1
I/O /SCLK
5
33
I/O /SDI
27
I/O
26
39
38
37
36
35
34
33
32
31
30
29
I/O /SCLK
5
7
I/O
6
I/O
26
32
31
2
3
4
5
6
I/O
6
8
I/O
7
I/O
25
I/O
25
I/O
24
I/O
7
9
I/O
24
I
0
30
29
28
27
I
10
11
12
0
CLK /I
ISR
EN
4
1
CLK /I
1
4
ISR
EN
GND
I
3
GND
I
3
GND
GND
CLK /I
7
1
8
0
CLK /I
13
14
15
16
17
1
8
0
I
2
I/O
I
2
26
25
24
23
8
9
I/O
I/O
23
I/O
I/O
I/O
9
23
I/O
9
I/O
22
I/O
10
I/O
11
10
11
22
I/O
10
11
I/O
21
I/O
21
I/O
18 19 20 21 22 23 24 25 26 27 28
1213 14 15 16 17 18 19 20 21 22
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The macrocell also features a
separate feedback path to the PIM so that the register can be
buried if the I/O pin is used as an input.
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C371i remain the same.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C371i includes two logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Programming
Product Term Array
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate
associated I/O pin. The input to the macrocell is the sum of
Document #: 38-03032 Rev. *A
Page 2 of 12
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CY7C371i
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability
is available in commercial and industrial temperature ranges.
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Design Tools
Bus Hold Capabilities on all I/Os and Dedicated Inputs
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
Document #: 38-03032 Rev. *A
Page 3 of 12
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CY7C371i
Output Current into Outputs (LOW)............................. 16 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Ambient
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
Temperature VCCVCCINT
VCCIO
DC Voltage Applied to Outputs
in High-Z State.....................................................−0.5V to +7.0V
Commercial 0°C to +70°C 5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
DC Input Voltage .................................................−0.5V to +7.0V
Industrial
−40°C to +85°C 5V ± 0.5V
5V ± 0.5V or
3.3V ± 0.3V
DC Program Voltage.....................................................12.5V
Electrical Characteristics Over the Operating Range[2,3]
Parameter
Description
Test Conditions
IOH = −3.2 mA (Com’l/Ind)[4]
Min. Typ. Max. Unit
VOH
Output HIGH Voltage with VCC = Min.
Output Enabled
2.4
V
VOHZ
Output HIGH Voltage with VCC = Max.
Output Disabled[8]
IOH = 0 µA (Com’l/Ind)[4,5]
OH = −50 µA (Com’l/Ind)[4,5]
IOL = 16 mA (Com’l/Ind)[4]
4.0
3.6
0.5
7.0
0.8
+10
+50
V
V
I
VOL
VIH
VIL
IIX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
VCC = Min.
V
Guaranteed Input Logical HIGH Voltage for all inputs[6]
Guaranteed Input Logical LOW Voltage for all inputs[6]
VI = Internal GND, VI = VCC
2.0
−0.5
−10
−50
0
V
V
µA
µA
IOZ
Output Leakage Current VCC = Max., VO = GND or VO =VCC, Output Disabled
CC = Max., VO = 3.3V, Output Disabled[5]
V
–70 –125 µA
−160 mA
IOS
ICC
Output Short Circuit
Current[7,8]
VCC = Max., VOUT = 0.5V
−30
Power Supply Current
VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC
Com’l/Ind.
75
45
125 mA
[9]
Com’l “L” −66, −83
75
mA
IBHL
Input Bus Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
VCC = Min., VIH = 2.0V
VCC = Max.
+75
µA
IBHH
Input Bus Hold HIGH
Sustaining Current
−75
µA
IBHLO
IBHHO
Input Bus Hold LOW
Overdrive Current
+500 µA
−500 µA
Input Bus Hold HIGH
Overdrive Current
VCC = Max.
Capacitance[8]
Parameter
Description
Input Capacitance
Test Conditions
VIN = 5.0V at f=1 MHz
VIN = 5.0V at f = 1 MHz
Min.
Max.
Unit
pF
[10]
CI/O
8
CCLK
Clock Signal Capacitance
5
12
pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. If V is not specified, the device can be operating in either 3.3V or 5V I/O mode; V =V .
CCINT
CCIO
CC
4. I = −2 mA, I = 2 mA for SDO.
OH
OL
5. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
6. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
= 0.5V has been chosen to avoid test
OUT
8. Tested initially and after any design or process changes that may affect these parameters.
9. Measured with 16-bit counter programmed into each logic block.
10. CI/O for ISR is 15 pF Max.
EN
Document #: 38-03032 Rev. *A
Page 4 of 12
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CY7C371i
Inductance[8]
Parameter
Description
Test Conditions
44-Lead TQFP
44-Lead PLCC
Unit
L
Maximum Pin Inductance VIN = 5.0V at f= 1 MHz
2
5
nH
Endurance Characteristics[8]
Parameter
Description
Maximum Reprogramming Cycles
Test Conditions
Max.
Unit
Cycles
N
Normal Programming Conditions
100
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM'L)
319Ω (MIL)
5V
5V
OUTPUT
OUTPUT
170Ω (COM'L)
236Ω (MIL)
170Ω (COM'L)
35 pF
236Ω (MIL)
5 pF
INCLUDING
INCLUDING
JIG AND
SCOPE
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
90%
3.0V
90%
10%
Equivalent to:
THÉVENIN EQUIVALENT
10%
99Ω (COM'L)
GND
136Ω (MIL)
2.08V(COM'L)
2.13V(MIL)
< 2 ns
OUTPUT
< 2 ns
(c)
Parameter[11]
Vx
Output Waveform Measurement Level
tER(–)
1.5V
VOH
0.5V
VX
VX
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthe
0.5V
VOL
VOH
0.5V
VX
VX
0.5V
VOL
Note:
11. t measured with 5-pF AC Test Load and t measured with 35-pF AC Test Load.
ER
EA
Document #: 38-03032 Rev. *A
Page 5 of 12
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CY7C371i
Switching Characteristics Over the Operating Range [12]
7C371i−83
7C371i−66
7C371i−143 7C371i−110 7C371iL−83 7C371iL−66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
8.5
10
13
12
18
15
22
ns
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
11.5
tPDLL
Input to Output Through Transparent Input
and Output Latches[1]
13.5
15
20
24
ns
tEA
tER
Input to Output Enable[1]
13
13
14
14
19
19
24
24
ns
ns
Input to Output Disable
Input Registered/Latched Mode Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[8]
Clock or Latch Enable Input HIGH Time[8]
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
2.5
2.5
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
tIH
2
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
12
14
14
16
19
21
24
26
tICOL
InputRegisterClockorLatchEnabletoOutput
Through Transparent Output Latch[1]
ns
Output Registered/Latched Mode Parameters
tCO
tS
Clock or Latch Enable to Output[1]
6
6.5
14
8
10
24
ns
ns
Set-up Time from Input to Clock or Latch
Enable
5
0
6
0
8
0
10
0
tH
Register or Latch Data Hold Time
ns
ns
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
12
19
tSCS
tSL
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
7
9
0
9
10
12
12
15
15
ns
ns
Set-up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
0
0
0
ns
fMAX1
fMAX2
Maximum Frequency with Internal Feedback 143
111
153.8
83.3
100
66.6
83.3
MHz
MHz
[8]
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO
)
Maximum Frequency Data Path in Output
166.7
Registered/Latched Mode (Lesser of 1/(tWL
[8]
+ tWH), 1/(tS + tH), or 1/tCO
)
fMAX3
Maximum Frequency with external feedback
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[8]
91
0
80
0
50
0
41.6
0
MHz
ns
tOH-tIH
37x
Output Data Stable from Output clock minus
Input Register Hold Time for 7C37x[8,13]
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register Clock
7
9
12
15
ns
fMAX4
Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH),
125
111
76.9
62.5
MHz
1/(tIS + tIH), or 1/tSCS
)
Notes:
12. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03032 Rev. *A
Page 6 of 12
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CY7C371i
Switching Characteristics Over the Operating Range (continued)[12]
7C371i−83
7C371i−66
7C371i−143 7C371i−110 7C371iL−83 7C371iL−66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Reset/Preset Parameters
tRW
tRR
tRO
tPW
tPR
tPO
Asynchronous Reset Width[8]
8
10
12
15
17
20
22
ns
ns
ns
ns
ns
ns
Asynchronous Reset Recovery Time[8]
Asynchronous Reset to Output[1]
Asynchronous Preset Width[8]
Asynchronous Preset Recovery Time[8]
Asynchronous Preset to Output[1]
10
14
14
16
16
21
21
26
26
8
10
12
15
17
20
22
10
Tap Controller Parameters
fTAP
Tap Controller Frequency
500
500
500
500
kHz
ns
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Latched Output
INPUT
tS
tH
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
Registered Input
REGISTERED
INPUT
tIS
tIH
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
Document #: 38-03032 Rev. *A
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CY7C371i
Switching Waveforms (continued)
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICS
tSCS
OUTPUT
REGISTER CLOCK
Latched Input
LATCHED INPUT
tIS
tIH
LATCH ENABLE
tPDL
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
LATCH ENABLE
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
tHL
INPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
Document #: 38-03032 Rev. *A
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CY7C371i
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
Asynchronous Preset
tPW
INPUT
t
PO
REGISTERED
OUTPUT
t
PR
CLOCK
Output Enable/Disable
INPUT
tER
tEA
OUTPUTS
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C371i−143AC
Name
A44
J67
Package Type
143
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
CY7C371i−143JC
CY7C371i−110AC
CY7C371i−110JC
CY7C371i–110AI
CY7C371i–110JI
110
A44
J67
A44
J67
Document #: 38-03032 Rev. *A
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CY7C371i
Ordering Information (continued)
Speed
Package
Operating
Range
(MHz)
Ordering Code
CY7C371i−83AC
Name
A44
J67
A44
J67
A44
J67
A44
J67
A44
J67
A44
J67
A44
J67
A44
J67
Package Type
83
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
44-Lead Thin Plastic Quad Flat Pack
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7C371i−83JC
CY7C371i−83AI
CY7C371i−83JI
CY7C371iL−83AC
CY7C371iL−83JC
CY7C371iL−83AI
CY7C371iL−83JI
CY7C371i−66AC
CY7C371i−66JC
CY7C371i−66AI
CY7C371i−66JI
CY7C371iL−66AC
CY7C371iL−66JC
CY7C371iL−66AI
CY7C371iL−66JI
Industrial
Commercial
Industrial
66
Commercial
Industrial
Commercial
Industrial
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
Document #: 38-03032 Rev. *A
Page 10 of 12
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
FLASH370, FLASH370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03032 Rev. *A
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© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Document History Page
Document Title: CY7C371i UltraLogic™ 32-Macrocell Flash CPLD
Document Number: 38-03032
Orig. of
REV.
**
ECN NO.
106377
213375
Issue Date
06/18/01
Change
Description of Change
SZV
Changed from Spec #: 38-00497 to 38-03032
*A
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03032 Rev. *A
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