CY7C373I [CYPRESS]
UltraLogic⑩ 64-Macrocell Flash CPLD; UltraLogic ™ 64宏单元CPLD的Flash
| 型号： | CY7C373I |
| 厂家： | 
CYPRESS |
| 描述： | UltraLogic⑩ 64-Macrocell Flash CPLD |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY7C373i
UltraLogic™ 64-Macrocell Flash CPLD
• Available in 84-pin PLCC and 100-pin TQFP packages
• Pin compatible with the CY7C374i
Features
• 64 macrocells in four logic blocks
• 64 I/O pins
Functional Description
• 5 dedicated inputs including 4 clock pins
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C373i is
designed to bring the ease of use and high performance of the
• In-System Reprogrammable™ (ISR™) Flash
technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C373i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
• High speed
— fMAX = 125 MHz
— tPD = 10 ns
— tS = 5.5 ns
— tCO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
Logic Block Diagram
CLOCK
INPUTS
INPUT
1
4
INPUT/CLOCK
MACROCELLS
INPUT
MACROCELL
2
2
16 I/Os
16 I/Os
16 I/Os
LOGIC
LOGIC
BLOCK
36
16
36
I/O0-I/O15
BLOCK
I/O48−I/O63
PIM
A
D
16
16 I/Os
LOGIC
BLOCK
C
LOGIC
BLOCK
36
16
36
16
I/O16-I/O31
I/O32−I/O47
B
32
32
Selection Guide
7C373i–125 7C373i–100 7C373i–83 7C373iL-83 7C373i–66 7C373iL–66
Maximum Propagation Delay[1], tPD (ns)
Minimum Set-up, tS (ns)
Maximum Clock to Output[1], tCO (ns)
10
5.5
6.5
75
12
6.0
6.5
75
15
8
15
8
20
10
10
75
20
10
10
45
8
8
Typical Supply Current, ICC (mA)
75
45
Note:
1. The 3.3V I/O mode timing adder, t
, must be added to this specification when V
= 3.3V.
3.3IO
CCIO
Cypress Semiconductor Corporation
Document #: 38-03030 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 8, 2004
USE ULTRA37000TM FOR
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CY7C373i
Pin Configurations
PLCC
Top View
11 10
3
1
84 83
76
9
8
6
4
2
82 81 79 78 77
80
75
74
7
5
GND
I/O
55
I/O
I/O
I/O /SCLK
12
13
14
15
16
17
18
19
20
21
22
23
24
8
73
9
I/O /SDI
54
72
71
70
69
68
67
66
10
I/O
53
I/O
52
I/O
11
I/O
12
I/O
I/O
I/O
I/O
51
50
49
48
I/O
13
I/O
14
I/O
15
CLK /I
0
0
CLK /I
4
3
3
65
64
V
CCIO
GND
GND
7C373
V
CCIO
63
62
61
60
59
58
57
56
55
54
CLK /I
1
16
17
1
I/O
I/O
CLK /I
2
I/O
47
I/O
46
25
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
26
27
28
29
30
31
32
I/O
45
I/O
44
I/O
43
I/O
42
I/O
41
I/O
40
GND
39
45
46 47 48 49 50
38
43 44
51
52 53
33 34 35 36 37
40 41 42
TQFP
Top View
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
SDI
1
SCLK
GND
V
CCIO
2
3
4
I/O
55
I/O
54
I/O
8
I/O
9
72
71
70
69
I/O
I/O
I/O
I/O
I/O
I/O
53
52
51
50
49
I/O
I/O
10
11
12
5
6
7
8
I/O
I/O
68
13
67
66
I/O
I/O
9
14
15
48
10
11
12
13
CLK /I
3
GND
NC
4
3
65
64
63
62
CLK /I
0
0
V
CCIO
N/C
V
CCIO
14
GND
CLK /I
2
I/O
47
61
60
59
58
CLK /I
1
I/O
I/O
I/O
1
15
17
15
16
17
I/O
46
I/O
45
18
18
19
20
21
I/O
44
57
56
55
54
53
I/O
19
I/O
20
I/O
21
I/O
43
I/O
42
I/O
41
I/O
22
I/O
23
22
23
I/O
40
GND
52
51
V
CCIO
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
48 49 50
47
Document #: 38-03030 Rev. *A
Page 2 of 12
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CY7C373i
Programmable Interconnect Matrix
Functional Description
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C373i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
The 64 macrocells in the CY7C373i are divided between four
logic blocks. Each logic block includes 16 macrocells, a 72 x
86 product term array, and an intelligent product term allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
Like all members of the FLASH370i family, the CY7C373i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 64 I/O pins on the CY7C373i.
In addition, there is one dedicated input and four input/clock
pins.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
Finally, the CY7C373i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C373i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C373i includes four logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Product Term Array
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product term resources to macrocells that require
them. Any number of product terms between 0 and 16
inclusive can be assigned to any of the logic block macrocells
(this is called product term steering). Furthermore, product
terms can be shared among multiple macrocells. This means
that product terms that are common to more than one output
can be implemented in a single product term. Product term
steering and product term sharing help to increase the
effective density of the FLASH370i CPLDs. Note that the
product term allocator is handled by software and is invisible
to the user.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
I/O Macrocell
Each of the macrocells on the CY7C373i has a separate I/O
pin associated with it. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and two global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Design Tools
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
Document #: 38-03030 Rev. *A
Page 3 of 12
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CY7C373i
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Operating Range
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Temperature
VCC
VCCINT
Range
VCCIO
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 0.25V 5V ± 0.25V
OR
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
3.3V ± 0.3V
Industrial
−40°C to +85°C
5V ± 0.5V
5V ± 0.5V
OR
3.3V ± 0.3V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage.....................................................12.5V
Output Current into Outputs.........................................16 mA
Electrical Characteristics Over the Operating Range[2]
Parameter
VOH
Description
Test Conditions
IOH = –3.2 mA (Com’l/Ind)[3]
VCC = Max. IOH = 0 µA (Com’l/Ind)[3, 4]
Min. Typ. Max. Unit
Output HIGH Voltage
VCC = Min.
2.4
V
V
VOHZ
Output HIGH Voltage
with Output Disabled[7]
4.0
3.6
IOH = –50 µA (Com’l/Ind)[3, 4]
V
VOL
VIH
VIL
IIX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
VCC = Min.
IOL = 16 mA (Com’l/Ind)[3]
0.5
V
Guaranteed Input Logical HIGH Voltage for all Inputs[5]
Guaranteed Input Logical LOW Voltage for all Inputs[5]
VI = Internal GND, VI = VCC
2.0
–0.5
–10
–50
0
7.0
V
0.8
V
+10
µA
µA
µA
mA
IOZ
Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled
VCC = Max., VO = 3.3V, Output Disabled[4]
+50
–70 –125
–160
IOS
ICC
Output Short
VCC = Max., VOUT = 0.5V
–30
Circuit Current[6, 7]
Power Supply Current[8] VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC
Com’l/Ind.
75
45
125
75
mA
mA
µA
Com’l “L”, –66
IBHL
Input Bus Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
VCC = Min., VIH = 2.0V
VCC = Max.
+75
–75
IBHH
IBHLO
Input Bus Hold HIGH
Sustaining Current
µA
µA
µA
Input Bus Hold LOW
Overdrive Current
+500
–500
IBHHO
Input Bus Hold HIGH
Overdrive Current
VCC = Max.
Notes:
2. If V
is not specified, the device can be operating in either 3.3V or 5V I/O mode; V =V
.
CCINT
CCIO
CC
3. I = –2 mA, I = 2 mA for SDO.
OH
OL
4. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
caused by tester ground degradation.
= 0.5V has been chosen to avoid test problems
OUT
Document #: 38-03030 Rev. *A
Page 4 of 12
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CY7C373i
Capacitance[7]
Parameter
[9]
Description
Test Conditions
VIN = 5.0V at f = 1 MHz
VIN = 5.0V at f = 1 MHz
Min.
Max.
8
Unit
pF
CIN
Input Capacitance
CCLK
Clock Signal Capacitance
5
12
pF
Inductance[7]
Parameter
Description
Test Conditions
100-Pin TQFP
84-Lead PLCC
Unit
L
Maximum Pin Inductance VIN = 5.0V at f = 1 MHz
8
8
nH
Endurance Characteristics[7]
Parameter
Description
Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Max.
Unit
N
100
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM'L)
ALL INPUT PULSES
90%
5V
5V
3.0V
GND
90%
OUTPUT
OUTPUT
170Ω (COM'L)
236Ω (MIL)
10%
10%
< 2 ns
35 pF
5 pF
< 2 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
170Ω (COM'L)
(c)
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
99Ω (COM'L)
2.08V(COM'L)
OUTPUT
Parameter[10]
Vx
Output Waveform–Measurement Level
tER(–)
1.5V
VOH
VX
0.5V
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthe
0.5V
VX
VOL
0.5V
VOH
VX
VX
VOL
0.5V
(d) Test Waveforms
Notes:
7. Tested initially and after any design or process changes that may affect these parameters.
8. Measured with 16-bit counter programmed into each logic block.
9. C for dedicated Inputs, and I/Os with JTAG functionality is 12 pF Max., and for ISR is 15 pF Max.
I/O
EN
10. t measured with 5-pF AC Test Load and t measured with 35-pF AC Test Load.
ER
EA
Document #: 38-03030 Rev. *A
Page 5 of 12
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CY7C373i
Switching Characteristics Over the Operating Range[11]
7C373i–83
7C373i–66
7C373i–125 7C373i–100 7C373iL-83 7C373iL–66
Parameter
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
10
13
12
15
15
18
20
22
ns
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
tPDLL
Input to Output Through Transparent Input and
Output Latches[1]
15
16
19
24
ns
tEA
tER
Input to Output Enable[1]
14
14
16
16
19
19
24
24
ns
ns
Input to Output Disable
Input Registered/Latched Mode Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[7]
Clock or Latch Enable Input HIGH Time[7]
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
tIH
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
16
18
19
21
24
26
tICOL
Input Register Clock or Latch Enable to
ns
Output Through Transparent Output Latch[1]
Output Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
6.5
14
6.5
16
8
10
24
ns
ns
tS
Set-Up Time from Input to Clock or Latch
Enable
5.5
0
6
0
8
0
10
0
tH
Register or Latch Data Hold Time
ns
ns
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
19
tSCS
tSL
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
12
12
15
15
20
ns
ns
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch
Enable
10
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
0
0
0
0
ns
fMAX1
fMAX2
Maximum Frequency with Internal Feedback
125
100
83
66
MHz
MHz
[7]
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO
)
Maximum Frequency Data Path in Output
153.8
153.8
125
100
Registered/Latched Mode (Lesser of 1/(tWL
+
[7]
tWH), 1/(tS + tH), or 1/tCO)
fMAX3
Maximum Frequency of (2) CY7C373is with
83.3
0
80
0
62.5
0
50
0
MHz
ns
External Feedback (Lesser of 1/(tCO + tS) and
[7]
1/(tWL + tWH
)
tOH–tIH
37x
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[7, 12]
Notes:
11. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03030 Rev. *A
Page 6 of 12
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CY7C373i
Switching Characteristics Over the Operating Range[11] (continued)
7C373i–83
7C373i–66
7C373i–125 7C373i–100 7C373iL-83 7C373iL–66
Parameter
Pipelined Mode Parameters
tICS Input Register Clock to Output Register Clock
fMAX4 Maximum Frequency in Pipelined Mode (Least 125
of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
8
10
12
15
ns
83.3
66.6
50.0
MHz
[7]
1/tSCS
)
Reset/Preset Parameters
tRW
Asynchronous Reset Width[7]
10
12
12
14
15
17
20
22
ns
ns
ns
ns
ns
ns
tRR
tRO
tPW
tPR
tPO
Asynchronous Reset Recovery Time[7]
Asynchronous Reset to Output[1]
Asynchronous Preset Width[7]
Asynchronous Preset Recovery Time[7]
Asynchronous Preset to Output[1]
16
16
18
18
21
21
26
26
10
12
12
14
15
17
20
22
Tap Controller Parameter
fTAP
Tap Controller Frequency
500
500
500
500
kHz
ns
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
Switching Waveforms
Combinatorial Output
INPUT
t
PD
COMBINATORIAL
OUTPUT
Registered Output
INPUT
t
S
t
H
CLOCK
t
CO
REGISTERED
OUTPUT
t
t
WL
WH
CLOCK
Document #: 38-03030 Rev. *A
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CY7C373i
Switching Waveforms (continued)
Latched Output
INPUT
t
S
t
H
ENABLE
LATCH
t
t
CO
PDL
LATCHED
OUTPUT
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK
t
t
ICS
SCS
OUTPUT
REGISTER CLOCK
Latched Input
LATCHED INPUT
t
IS
t
IH
LATCHENABLE
t
t
ICO
PDL
COMBINATORIAL
OUTPUT
t
t
WL
WH
LATCHENABLE
Document #: 38-03030 Rev. *A
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CY7C373i
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
t
PDLL
LATCHED
OUTPUT
t
t
SL
ICOL
t
HL
INPUT LATCH
ENABLE
t
ICS
OUTPUT LATCH
ENABLE
t
t
WL
WH
LATCH ENABLE
Asynchronous Reset
t
RW
INPUT
t
RO
REGISTERED
OUTPUT
t
RR
CLOCK
Asynchronous Preset
t
PW
INPUT
t
PO
REGISTERED
OUTPUT
t
PR
CLOCK
Document #: 38-03030 Rev. *A
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CY7C373i
Switching Waveforms (continued)
Output Enable/Disable
INPUT
t
t
EA
ER
OUTPUTS
Ordering Information
Speed
Package
Type
Package
Type
Operating
Range
(MHz)
Ordering Code
CY7C373i–125AC
125
A100
J83
100-Pin Thin Quad Flatpack
Commercial
Commercial
Industrial
CY7C373i–125JC
CY7C373i–100AC
CY7C373i–100JC
CY7C373i–100AI
CY7C373i–100JI
CY7C373i–83AC
CY7C373i–83JC
CY7C373i–83AI
CY7C373i–83JI
CY7C373iL–83JC
CY7C373i–66AC
CY7C373i–66JC
CY7C373i–66AI
CY7C373i–66JI
CY7C373iL–66JC
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
100
83
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
Commercial
Industrial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
84-Lead Plastic Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
J83
Commercial
Commercial
66
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
Industrial
84-Lead Plastic Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
J83
Commercial
Document #: 38-03030 Rev. *A
Page 10 of 12
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C373i
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Warp is a registered trademark and Ultra37000, FLASH370, FLASH370i, ISR, UltraLogic, Warp Professional, and Warp Enterprise
are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be
the trademarks of their respective holders.
Document #: 38-03030 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C373i
Document History Page
Document Title: CY7C373i UltraLogic™ 64-Macrocell Flash CPLD
Document Number: 38-03030
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106375
213375
09/17/01
See ECN
SZV
FSG
Change from Spec number: 38-00495 to 38-03030
*A
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03030 Rev. *A
Page 12 of 12
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