CY7C374I-66JCT [CYPRESS]
Flash PLD, 20ns, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | CY7C374I-66JCT |
| 厂家： | 
CYPRESS |
| 描述： | Flash PLD, 20ns, CMOS, PQCC84, PLASTIC, LCC-84 时钟 输入元件 可编程逻辑 |
| 文件： | 总15页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 64 I/O pins
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is
designed to bring the ease of use as well as PCI Local Bus
Specification support and high performance of the 22V10 to
high-density CPLDs.
• Five dedicated inputs including four clock pins
• In-System Reprogrammable™ (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
• High speed
— fMAX = 125 MHz
— tPD = 10 ns
— tS = 5.5 ns
— tCO = 6.5 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin-compatible with the CY7C373i
Clock
Inputs
Inputs
Logic Block Diagram
1
4
INPUT/CLOCK
MACROCELLS
INPUT
MACROCELL
4
4
8 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
H
8 I/Os
I/O –I/O
36
16
36
16
0
7
I/O –I/O
56
63
PIM
LOGIC
BLOCK
B
LOGIC
BLOCK
G
8 I/Os
8 I/Os
8 I/Os
8 I/Os
36
16
36
16
I/O –I/O
I/O –I/O
48
8
15
55
LOGIC
BLOCK
C
LOGIC
BLOCK
F
36
16
36
16
I/O –I/O
I/O –I/O
40
16
23
47
8 I/Os
LOGIC
BLOCK
D
LOGIC
BLOCK
E
8 I/Os
36
16
36
16
I/O –I/O
I/O –I/O
32 39
24
31
32
32
Selection Guide
7C374i–125 7C374i–100 7C374i–83 7C7374iL–83 7C374i–66 7C374iL–66 Unit
Maximum Propagation Delay[1], tPD
Minimum Set-up, tS
Maximum Clock to Output[1], tCO
10
5.5
6.5
125
12
6
15
8
15
8
20
10
20
10
10
75
ns
ns
7
8
8
10
ns
Typical Supply Current, ICC
125
125
75
125
mA
Note:
1. The 3.3V I/O mode timing adder, t
, must be added to this specification when V
= 3.3V.
3.3IO
CCIO
Cypress Semiconductor Corporation
Document #: 38-03031 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 19, 2004
CY7C374i
Pin Configurations
PLCC
Top View
11 10 9
8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
GND
I/O
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
I/O
I/O
I/O /SCLK
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
8
55
9
I/O /SDI
54
10
I/O
I/O
I/O
I/O
I/O
I/O
53
52
I/O
11
I/O
12
51
50
49
48
I/O
13
I/O
14
I/O
15
CLK /I
0
0
CLK /I
3
4
3
V
CCIO
GND
GND
V
CCIO
CLK /I
1
16
17
1
I/O
CLK /I
2
I/O
47
I/O
46
I/O
I/O
I/O
I/O
I/O
I/O
I/O
18
19
20
21
I/O
45
I/O
44
I/O
43
I/O
42
I/O
41
I/O
40
57
56
55
54
22
23
GND
32 33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
34 35
38 39
PGA
Bottom View
L
I/O
I/O
25
I/O
SMODE
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
I/O
23
26
28
31
33
CC
34
36
37
39
41
42
44
I/O
24
I/O
27
I/O
30
I
2
I/O
32
GND
I/O
I/O
I/O
I/O
I/O
GND
K
J
35
38
21
SDO
I/O
22
I/O
29
V
CC
GND
I/O
40
20
18
H
I/O
43
I/O
I/O
19
CLK1 I/O
GND
16
CLK2 I/O
I/O
47
G
F
46
45
/
I1
/I
3
I/O
17
I/O
15
I/O
12
I/O
10
CLK0
V
CC
V
CC
I/O
GND
/I
0
I/O
14
I/O
11
I/O
13
I/O
49
I/O
CLK3
E
48
/I
4
I/O
51
I/O
50
D
C
I/O
I/O
V
I/O
54
SDI
I/O
I/O
1
CC ISR
52
53
55
8
EN
SCLK
I/O
9
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND I/O
B
A
GND
3
0
61
62
59
56
I/O
I/O
7
I/O
5
I/O
4
I/O
4
I/O
57
2
63
60
58
V
CC
GND
6
1
2
3
5
7
8
9
10
11
Document #: 38-03031 Rev. *A
Page 2 of 15
CY7C374i
Pin Configurations (continued)
TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
SDI
SCLK
GND
2
3
4
V
CCIO
I/O
8
I/O
9
I/O
55
I/O
54
72
71
70
69
I/O
10
I/O
11
5
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
53
52
51
50
49
I/O
I/O
12
68
13
I/O
I/O
14
15
9
67
66
10
11
12
13
14
15
16
17
48
CLK /I
0
CLK /I
3
GND
NC
0
65
64
63
62
4
3
V
CCIO
N/C
V
CCIO
GND
CLK /I
CLK /I
2
1
I/O
I/O
I/O
1
16
17
61
60
59
I O
/
47
I/O
I/O
I/O
46
45
18
18
19
20
21
58
I/O
19
I/O
20
I/O
21
57
56
55
54
53
44
43
I/O
I/O
I/O
42
41
I/O
22
23
22
23
I/O
40
I/O
V
GND
NC
24
25
52
51
CCIO
NC
26 27 28 29 30 31 32 33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
CLCC
Top View
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
GND
I/O
55
I/O
I/O
I/O /SCLK
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
8
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
9
I/O /SDI
54
10
I/O
53
I/O
52
I/O
11
I/O
12
I/O
I/O
I/O
I/O
51
50
49
48
I/O
13
I/O
14
I/O
15
CLK /I
0
0
CLK /I
4
3
3
V
CC
GND
GND
V
CC
CLK /I
1
16
17
1
I/O
CLK /I
2
I/O
47
I/O
46
I/O
I/O
I/O
I/O
I/O
I/O
I/O
18
19
20
21
I/O
45
I/O
44
I/O
43
I/O
42
I/O
41
I/O
40
57
56
55
54
22
23
GND
32 33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
34 35
38 39
Document #: 38-03031 Rev. *A
Page 3 of 15
CY7C374i
whose input comes from the I/O pin associated with the neigh-
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Functional Description
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C374i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Like all members of the FLASH370i family, the CY7C374i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O pins on the
CY7C374i. In addition, there is one dedicated input and four
input/clock pins.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
Finally, the CY7C374i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C374i remain the same.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C374i includes eight logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
I/O Macrocell
Half of the macrocells on the CY7C374i have I/O pins
associated with them. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The I/O macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and two global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Buried Macrocell
Design Tools
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the
addition of input register capability. The user can program the
buried macrocell to act as an input register (D-type or latch)
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
Document #: 38-03031 Rev. *A
Page 4 of 15
CY7C374i
Output Current into Outputs ........................................ 16 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Temperature VCC VCCINT
VCCIO
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C 5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage.....................................................12.5V
Industrial
Military[2]
−40°C to +85°C 5V ± 0.5V
5V ± 0.5V or
3.3V ± 0.3V
–55°C to +125°C 5V ± 0.5V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
Description
Test Conditions
Min. Typ. Max. Unit
VOH
Output HIGH Voltage
VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5]
2.4
V
V
IOH = –2.0 mA (Mil)
VOHZ
VOL
Output HIGH Voltage with VCC = Max. IOH = 0 µA (Com’l/Ind)[5, 6]
4.0
3.6
0.5
V
Output Disabled[9]
I
OH = –50 µA (Com’l/Ind)[5, 6]
V
Output LOW Voltage
VCC = Min. IOL = 16 mA (Com’l/Ind)[5]
V
IOL = 12 mA (Mil)
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Guaranteed Input Logical HIGH voltage for all inputs[7] 2.0
Guaranteed Input Logical LOW voltage for all inputs[7] –0.5
7.0
0.8
V
V
VI = Internal GND, VI = VCC
–10
+10
+50
–125
–160
µA
µA
µA
mA
IOZ
Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled –50
V
CC = Max., VO = 3.3V, Output Disabled[6]
0
–70
IOS
ICC
Output Short
VCC = Max., VOUT = 0.5V
–30
Circuit Current[8, 9]
Power Supply Current
VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC
Com’l/Ind.
Com’l “L” –66
Military
125
75
200
125
250
mA
mA
mA
µA
[10]
125
IBHL
Input Bus Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
VCC = Min., VIH = 2.0V
VCC = Max.
+75
–75
IBHH
IBHLO
Input Bus Hold HIGH
Sustaining Current
µA
µA
µA
Input Bus Hold LOW
Overdrive Current
+500
–500
IBHHO
Input Bus Hold HIGH
Overdrive Current
VCC = Max.
Notes:
2. T is the “instant on” case temperature.
A
3. See the last page of this specification for Group A subgroup testing information.
4. If V is not specified, the device can be operating in either 3.3V or 5V I/O mode; V =V
.
CCIO
CC
CCINT
5. I = –2 mA, I = 2 mA for SDO.
OH
OL
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
problems caused by tester ground degradation.
= 0.5V has been chosen to avoid test
OUT
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
Document #: 38-03031 Rev. *A
Page 5 of 15
CY7C374i
Capacitance[9]
Parameter
[11, 12]
Description
Input Capacitance
Test Conditions
VIN = 5.0V at f = 1 MHz
VIN = 5.0V at f = 1 MHz
Min.
Max.
Unit
pF
CI/O
8
CCLK
Clock Signal Capacitance
5
12
pF
Inductance[9]
Parameter
Description
Test Conditions
IN = 5.0V at f = 1 MHz
100-PinTQFP 84-Lead PLCC 84-Lead CLCC Unit
nH
L
Maximum Pin Inductance
V
8
8
5
Endurance Characteristics[9]
Parameter
Description
Test Conditions
Max.
Unit
N
Maximum Reprogramming Cycles
Normal Programming Conditions
100
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM'L)
ALL INPUT PULSES
90%
90%
10%
319Ω (MIL)
3.0V
5V
5V
10%
<2ns
170Ω (COM'L)
236Ω (MIL)
OUTPUT
OUTPUT
GND
<2ns
170Ω (COM'L)
236Ω (MIL)
35 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Equivalent to:
THÉVENIN EQUIVALENT
99Ω (COM'L)
136Ω (MIL)
2.08V (COM'L)
2.13V (MIL)
OUTPUT
Parameter[13]
VX
Output Waveform Measurement Level
tER(–)
1.5V
VOH
–0.5V
VX
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthc
VX
–0.5V
–0.5V
VOH
VOH
VX
VX
–0.5V
VOH
Notes:
11. C for the CLCC package are 12 pF Max
I/O
12. C for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISR is 15 pF Max.
I/O
EN
13. t measured with 5-pF AC Test Load and t measured with 35-pF AC Test Load.
ER
EA
Document #: 38-03031 Rev. *A
Page 6 of 15
CY7C374i
Switching Characteristics Over the Operating Range [14]
7C374i–83
7C374i–66
7C374i–125 7C374i–100 7C374iL–83 7C374iL–66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
10
13
12
15
15
18
20
22
ns
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
tPDLL
Input to OutputThrough Transparent Input and
Output Latches[1]
15
16
19
24
ns
tEA
tER
Input to Output Enable[1]
14
14
16
16
19
19
24
24
ns
ns
Input to Output Disable
Input Registered/Latched Mode Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[9]
Clock or Latch Enable Input HIGH Time[9]
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
tIH
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
16
18
19
21
24
26
tICOL
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1]
ns
Output Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
tS Set-Up Time from Input to Clock or Latch Enable 5.5
6.5
14
7
8
10
24
ns
ns
ns
ns
6
0
8
0
10
0
tH
Register or Latch Data Hold Time
0
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
16
19
tSCS
tSL
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
10
12
12
15
0
15
20
0
ns
ns
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
0
0
ns
fMAX1
fMAX2
Maximum Frequency with Internal Feedback
125
158.3
100
143
83
125
66
100
MHz
MHz
[9]
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO
)
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL
+
tWH), 1/(tS + tH), or 1/tCO)
fMAX3
Maximum Frequency with External Feedback 83.3
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))
76.9
0
67.5
0
50
0
MHz
ns
tOH–tIH
37x
Output Data Stable from Output Clock Minus
Input Register Hold Time for 7C37x[9, 15]
0
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register Clock
8
10
12
15
ns
fMAX4
MaximumFrequencyinPipelinedMode(Least 125
of1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),
100
83.3
66.6
MHz
or 1/tSCS
)
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03031 Rev. *A
Page 7 of 15
CY7C374i
Switching Characteristics Over the Operating Range (continued)[14]
7C374i–83
7C374i–66
7C374i–125 7C374i–100 7C374iL–83 7C374iL–66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Reset/Preset Parameters
tRW
tRR
tRO
tPW
tPR
tPO
Asynchronous Reset Width[9]
10
12
12
14
15
17
20
22
ns
ns
ns
ns
ns
ns
Asynchronous Reset Recovery Time[9]
Asynchronous Reset to Output[1]
Asynchronous Preset Width[9]
Asynchronous Preset Recovery Time[9]
Asynchronous Preset to Output[1]
16
16
18
18
21
21
26
26
10
12
12
14
15
17
20
22
Tap Controller Parameter
fTAP
Tap Controller Frequency
500
500
500
500
kHz
ns
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Registered Output
INPUT
tS
tH
CLOCK
tCO
REGISTERED
OUTPUT
tWH
tWL
CLOCK
Latched Output
INPUT
tS
tH
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
Document #: 38-03031 Rev. *A
Page 8 of 15
CY7C374i
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
t
IS
t
IH
INPUT REGISTER
CLOCK
t
ICO
COMBINATORIAL
OUTPUT
t
t
WL
WH
CLOCK
Latched Input
LATCHED INPUT
t
IS
t
IH
LATCH ENABLE
t
t
ICO
PDL
COMBINATORIAL
OUTPUT
t
t
WL
WH
LATCH ENABLE
Latched Input and Output
LATCHED INPUT
t
PDLL
LATCHED
OUTPUT
t
t
SL
ICOL
t
HL
INPUT LATCH
ENABLE
t
ICS
OUTPUT LATCH
ENABLE
t
t
WL
WH
LATCH ENABLE
Document #: 38-03031 Rev. *A
Page 9 of 15
CY7C374i
Switching Waveforms (continued)
Asynchronous Reset
t
RW
INPUT
t
RO
REGISTERED
OUTPUT
t
RR
CLOCK
Asynchronous Preset
t
PW
INPUT
t
PO
REGISTERED
OUTPUT
t
PR
CLOCK
Output Enable/Disable
INPUT
t
t
EA
ER
OUTPUTS
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C374i–125AC
Package Type
125
A100
J83
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Industrial
CY7C374i–125JC
CY7C374i–100AC
CY7C374i–100JC
CY7C374i–100AI
CY7C374i–100JI
CY7C374i–83AC
CY7C374i–83JC
CY7C374i–83AI
CY7C374i–83JI
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
100
83
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
Commercial
Industrial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
84-Lead Plastic Leaded Chip Carrier
84-Pin Ceramic Pin Grid Array
84-Pin Ceramic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
CY7C374i–83GMB
CY7C374i–83YMB
CY7C374iL–83AC
CY7C374iL–83JC
G84
Y84
A100
J83
Military
Commercial
84-Lead Plastic Leaded Chip Carrier
Document #: 38-03031 Rev. *A
Page 10 of 15
CY7C374i
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
66
CY7C374i–66AC
CY7C374i–66JC
CY7C374i–66AI
CY7C374i–66JI
A100
J83
Commercial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
Industrial
84-Lead Plastic Leaded Chip Carrier
84-Pin Ceramic Pin Grid Array
84-Pin Ceramic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
CY7C374i–66GMB
CY7C374i–66YMB
CY7C374iL–66AC
CY7C374iL–66JC
G84
Y84
A100
J83
Military
Commercial
84-Lead Plastic Leaded Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
tPD
tPDL
tPDLL
tCO
tICO
tICOL
tS
9, 10, 11
DC Characteristics
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
Parameter
VOH
VOL
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIH
VIL
IIX
tSL
IOZ
tH
ICC1
tHL
tIS
tIH
tICS
tEA
tER
Document #: 38-03031 Rev. *A
Page 11 of 15
CY7C374i
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
Document #: 38-03031 Rev. *A
Page 12 of 15
CY7C374i
Package Diagrams (continued)
84-Pin Grid Array (Cavity Up) G84
51-80015-*A
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-03031 Rev. *A
Page 13 of 15
CY7C374i
Package Diagrams (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
51-80095-*A
ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03031 Rev. *A
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C374i
Document History Page
Document Title: CY7C374i UltraLogic™ 128-Macrocell Flash CPLD
Document Number: 38-03031
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106376
213375
07/11/01
See ECN
SZV
FSG
Changed from Spec number: 38-00496 to 38-03031
*A
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03031 Rev. *A
Page 15 of 15
相关型号：
©2020 ICPDF网 联系我们和版权申明