CY7C4022KV13-933FCXC

CY7C4022KV13/CY7C4042KV13

72-Mbit QDR™-IV XP SRAM

Features

Configurations

■ 72-Mbit density (4M × 18, 2M × 36)

■ Total Random Transaction Rate^[1]of 2132 MT/s

CY7C4022KV13 – 4M × 18

CY7C4042KV13 – 2M × 36

■ Maximum operating frequency of 1066 MHz

Functional Description

■ Read latency of 8.0 clock cycles and Write Latency of 5.0 clock

The QDR™-IV XP (Xtreme Performance) SRAM is

high-performance memory device that has been optimized to

maximize the number of random transactions per second by the

use of two independent bi-directional data ports.

a

cycles

■ 8 bank architecture enables one access per bank per cycle

■ Two-word burst on all accesses

These ports are equipped with DDR interfaces and designated

as port A and port B respectively. Accesses to these two data

ports are concurrent and independent of each other. Access to

each port is through a common address bus running at DDR. The

control signals are running at SDR and determine if a read or

write should be performed.

■ Dual independent bi-directional data ports

❐ Double data rate (DDR) data ports

❐ Supports concurrent read/write transactions on both ports

■ Single address port used to control both data ports

❐ DDR address signaling

There are three types of differential clocks:

■ Single data rate (SDR) control signaling

■ (CK, CK#) for address and command clocking

■ (DKA, DKA#, DKB, DKB#) for data input clocking

■ (QKA, QKA#, QKB, QKB#) for data output clocking

■ High-speed transceiver logic (HSTL) and stub series

terminated logic (SSTL) compatible signaling (JESD8-16A

compliant)

❐ I/O V_DDQ= 1.2 V ± 50 mV or 1.25 V ± 50 mV

Addresses for port A are latched on the rising edge of the input

clock (CK), and addresses for port B are latched on the falling

edge of the input clock (CK).

■ Pseudo open drain (POD) signaling (JESD8-24 compliant)

❐ I/O V_DDQ= 1.1 V ± 50 mV or 1.2 V ± 50 mV

■ Core voltage

❐ V_DD= 1.3 V ± 40 mV

This QDR-IV XP SRAM is internally partitioned into eight internal

banks. Each bank can be accessed once for every clock cycle

enabling the SRAM to operate at high frequencies.

■ On-die termination (ODT)

❐ Programmable for clock, address/command and data inputs

The QDR-IV XP SRAM device is offered in a two-word burst

option and is available in × 18 and × 36 bus width configurations.

■ Internal self calibration of output impedance through ZQ pin

For an × 18 bus width configuration, there are 22 address bits,

and for an × 36 bus width configuration, there are 21 address bits

respectively.

■ Bus inversion to reduce switching noise and power

❐ Programmable on/off for address and data

An on-chip ECC circuitry detects and corrects all single-bit

memory errors, including those induced by soft error events such

as cosmic rays, alpha particles, etc. The resulting SER of these

devices is expected to be less than 0.01 FITs/Mb, a

four-order-of-magnitude improvement over previous generation

SRAMs.

■ Address bus parity error protection

■ Training sequence for per-bit deskew

■ On-chip error correction code (ECC) to reduce soft error rate

(SER)

■ JTAG 1149.1 test access port (JESD8-26 compliant)

❐ 1.3-V LVCMOS signaling

For a complete list of related resources, click here.

■ Available in 361-ball FCBGA Pb-free package (21 × 21 mm)

Selection Guide

QDR-IV

2132 (MT/s)

QDR-IV

1866 (MT/s)

Description

Unit

Maximum Operating Frequency

Maximum Operating Current

1066

4100

4500

933

3400

4000

MHz

mA

× 18

× 36

Note

1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured

in million transactions per second.

Cypress Semiconductor Corporation

Document Number: 001-79552 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 3, 2017

CY7C4022KV13/CY7C4042KV13

Logic Block Diagram – CY7C4022KV13

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CY7C4022KV13/CY7C4042KV13

Logic Block Diagram – CY7C4042KV13

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CY7C4022KV13/CY7C4042KV13

Contents

Pin Configurations ...........................................................5

Pin Definitions ..................................................................7

Functional Overview ........................................................9

Clocking .......................................................................9

Command Cycles ........................................................9

Read and Write Data Cycles .......................................9

Banking Operation .......................................................9

Address and Data Bus Inversion .................................9

Address Parity ...........................................................10

Port Enable ................................................................10

On-Die Termination (ODT) Operation .......................10

JTAG Operation ........................................................10

Power Up and Reset .................................................10

Operation Modes .......................................................11

Deskew Training Sequence ......................................12

I/O Signaling Standards ............................................12

Initialization ................................................................13

Configuration Registers .............................................14

Configuration Registers Description ..........................15

Configuration Register Definitions .............................15

I/O Type and Port Enable Bit Definitions ...................17

ODT Termination Bit Definitions ................................18

Drive Strength Bit Definitions ....................................19

IEEE 1149.1 Serial Boundary Scan (JTAG) ..................20

Test Access Port .......................................................20

TAP Registers ...........................................................20

TAP Instruction Set ...................................................20

TAP Controller State Diagram .......................................22

TAP Controller Block Diagram ......................................23

TAP Electrical Characteristics ......................................24

TAP AC Switching Characteristics ...............................24

TAP Timing Diagram ......................................................25

Identification Register Definitions ................................26

Scan Register Sizes .......................................................26

Instruction Codes ...........................................................26

Boundary Scan Order ....................................................27

Maximum Ratings ...........................................................30

Operating Range .............................................................30

Neutron Soft Error Immunity .........................................30

Electrical Characteristics ...............................................30

Capacitance ....................................................................32

Thermal Resistance ........................................................32

AC Test Load and Waveform .........................................32

Switching Characteristics ..............................................33

Switching Waveforms ....................................................35

Ordering Information ......................................................42

Ordering Code Definitions .........................................42

Package Diagram ............................................................43

Acronyms ........................................................................44

Document Conventions .................................................44

Units of Measure .......................................................44

Document History Page .................................................45

Sales, Solutions, and Legal Information ......................46

Worldwide Sales and Design Support .......................46

Products ....................................................................46

PSoC® Solutions ......................................................46

Cypress Developer Community .................................46

Technical Support .....................................................46

Document Number: 001-79552 Rev. *O

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CY7C4022KV13/CY7C4042KV13

Pin Configurations

Figure 1. 361-ball FCBGA Pinout

CY7C4022KV13 (4M × 18)

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CY7C4022KV13/CY7C4042KV13

Pin Configurations (continued)

Figure 2. 361-ball FCBGA Pinout

CY7C4042KV13 (2M × 36)

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CY7C4022KV13/CY7C4042KV13

Pin Definitions

Pin Name

I/Os

Pin Description

CK, CK#

Input Clock Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address

input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples

the control and address inputs for port A, while the falling edge of CK samples the control and address

inputs for port B. CK# is 180 degrees out of phase with CK.

A[x:0]

Input

Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write

operations. These address inputs are used for read and write operations on both ports. The lower

three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are

also known as bank address pins.

For (× 36) data width - Address inputs A[19:0] are used and A[24:20] are reserved.

For (× 18) data width - Address inputs A[20:0] are used and A[24:21] are reserved.

The reserved address inputs are No Connects and may be tied high, tied low, or left floating.

AP

Input

Address Parity Input. Used to provide even parity across the address pins.

For (× 36) data width - AP covers address inputs A[20:0]

For (× 18) data width - AP covers address inputs A[21:0]

PE#

Output

Input

Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,

PE# will remain LOW until cleared by a Configuration Register command.

AINV

Address Inversion Pin for Address and Address Parity Inputs.

For (× 36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).

For (× 18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).

DKA[1:0],

DKA#[1:0],

DKB[1:0],

DKB#[1:0]

Input

Data Input Clock.

DKA[0]/DKA#[0] controls the DQA[17:0] inputs for × 36 configuration and DQA[8:0] inputs for × 18

configuration respectively

DKA[1]/DKA#[1] controls the DQA[35:18] inputs for × 36 configuration and DQA[17:9] inputs for × 18

configuration respectively

DKB[0]/DKB#[0] controls the DQB[17:0] inputs for × 36 configuration and DQB[8:0] inputs for × 18

configuration respectively

DKB[1]/DKB#[1] controls the DQB[35:18] inputs for × 36 configuration and DQB[17:9] inputs for × 18

configuration respectively

QKA[1:0],

QKA#[1:0],

QKB[1:0],

QKB#[1:0]

Output

Data Output Clock.

QKA[0]/QKA#[0] controls the DQA[17:0] outputs for ×36 configuration and DQA[8:0] outputs for × 18

configuration respectively

QKA[1]/QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for

× 18 configuration respectively

QKB[0]/QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for × 18

configuration respectively

QKB[1]/QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for

× 18 configuration respectively

Input/Output Data Input/Output.Bidirectional data bus.

For (× 36) data width  DQA_[35:0]; DQB_[35:0]

DQA[x:0],

DQB[x:0]

For (× 18) data width  DQA_[17:0]; DQB_[17:0]

Input/Output Data Inversion Pin for DQ Data Bus.

DINVA[1:0],

DINVB[1:0]

DINVA[0] covers DQA[17:0] for × 36 configuration and DQA[8:0] for × 18 configuration respectively

DINVA[1] covers DQA[35:18] for × 36 configuration and DQA[17:9] for × 18 configuration respectively

DINVB[0] covers DQB[17:0] for × 36 configuration and DQB[8:0] for × 18 configuration respectively

DINVB[1] covers DQB[35:18] for × 36 configuration and DQB[17:9] for × 18 configuration respectively

LDA#, LDB#

Input

Synchronous Load Input.LDA# is sampled on the rising edge of the CK clock, while LDB# is sampled

on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables

commands for data port B. LDx# enables the commands when LDx# is LOW and disables the

commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but

internal operations continue.

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CY7C4022KV13/CY7C4042KV13

Pin Definitions (continued)

Pin Name

I/Os

Pin Description

RWA#,

RWB#

Input

Synchronous Read/Write Input. RWA# input is sampled on the rising edge of the CK clock, while

RWB# is sampled on the falling edge of the CK clock. The RWA# input is used in conjunction with the

LDA# input to select a Read or Write Operation. Similarly, the RWB# input is used in conjunction with

the LDB# input to select a read or write operation.

QVLDA

QVLDB

Output

Input

Output Data Valid Indicator. The QVLD pin indicates valid output data. QVLD is edge aligned with

QKx and QKx#.

[1:0],

[1:0]

ZQ/ZT

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance.

CFG#

RST#

Input

Configuration bit. This pin is used to configure different mode registers.

Active Low Asynchronous RST. This pin is active when RST# is LOW and inactive when RST# is

HIGH. The RST# pin has an internal pull down resistor.

LBK0#,

LBK1#

Input

Output

Input

Loopback mode for control and address/command/clock deskewing.

TMS

Test Mode Select Input pin for JTAG. This pin may be left unconnected if the JTAG function is not

used in the circuit.

TDI

Test Data Input pin for JTAG. This pin may be left unconnected if the JTAG function is not used in

the circuit.

TCK

Test Clock Input pin for JTAG. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

TRST#

Test Data Output pin for JTAG. This pin may be left unconnected if the JTAG function is not used in

the circuit.

Test Reset Input pin for JTAG. This pin must be tied to VDD if the JTAG function is not used in the

system. TRST# input is applicable only in JTAG mode.

DNU

N/A

Do Not Use. Do Not Use pins.

VREF

Reference

Reference Voltage Input. Static input used to set the reference level for inputs, outputs, and AC

measurement points.

VDD

Power

Ground

Power Supply Inputs to the Core of the Device.

Power Supply Inputs for the Outputs of the Device.

Ground for the Device.

VDDQ

VSS

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CY7C4022KV13/CY7C4042KV13

Write data is supplied to the DQA pins exactly five clock cycles

from the rising edge of the CK signal corresponding to the cycle

that the write command was initiated.

Functional Overview

The QDR-IV XP SRAM is a two-word burst synchronous SRAM

equipped with dual independent bidirectional data ports. The

following sections describe the operation of QDR-IV XP SRAM.

Write data is supplied to the DQB pins exactly five clock cycles

from the falling edge of the CK signal corresponding to the cycle

that the write command was initiated.

Clocking

Banking Operation

There are three groups of clock signals: CK/CK#, DKx/DKx#,

and QKx/QKx#, where x can be A or B, referring to the respective

ports.

The QDR-IV XP SRAM is designed with 8 internal banks. The

lower three address pins (A0, A1, and A2) select the bank that

will be accessed. These address inputs are also known as bank

address pins.

The CK/CK# clock is associated with the address and control

pins: A[24:0], LDA#, LDB#, RWA#, RWB#. The CK/CK#

transitions are centered with respect to the address and control

signal transitions.

Bank Access Rules

1. On the rising edge of the input clock, any bank address may

be accessed. This is the address associated with port A.

The DKx/DKx# clocks are associated with write data. The

DKx/DKx# clocks are used as source-centered clocks for the

DDR DQx and DINVx pins, when acting as inputs for the write

data.

2. On the falling edge of the input clock, any other bank

address may be accessed. This is the address associated

with port B.

The QKx/QKx# clocks are associated with read data. The

QKx/QKx# clocks are used as source-synchronous clocks for

the double data rate DQx and DINVx pins, when acting as

outputs for the read data.

3. If port A did not issue a command on the rising edge of the

input clock, then port B may access any bank address on the

falling edge of the input clock.

4. From the rising edge of the input clock cycle to the next

rising edge of the input clock, there is no address

restriction. Port A may access any bank at any time.

Command Cycles

The QDR-IV XP SRAM read and write commands are driven by

the control inputs (LDA#, LDB#, RWA#, and RWB#) and the

Address Bus.

To clarify, the banking restriction only applies in a single clock

cycle. Since the port A address is sampled on the rising edge of

the input clock, there are no restrictions with port A access.

Because the port B address is sampled on the falling edge of the

input clock, port B has the restriction that it must use a different

bank than port A.

The port A control inputs (LDA# and RWA#) are sampled at the

rising edge of the input clock. The port B control inputs (LDB#

and RWB#) are sampled at the falling edge of the input clock.

For port A:

Banking Violations

When LDA# = 0 and RWA# = 1, a read operation is initiated.

When LDA# = 0 and RWA# = 0, a write operation is initiated.

The address is sampled on the rising edge of the input clock.

1. Accesses for port A cannot cause a banking violation, only

accesses to port B can.

2. If port B tries to access the same bank as port A, then the port

B access to the memory array is ignored. The port A access

will still occur normally.

For port B:

When LDB# = 0 and RWB# = 1, a read operation is initiated.

When LDB# = 0 and RWB# = 0, a write operation is initiated.

The address is sampled on the falling edge of the input clock.

3. If the requested cycle on port B was a write, then there will be

no external indication that a banking violation occurred.

4. If the requested cycle on port B was a read, then there will be

no QVLDB signal generated. Outputs will remain tristated.

Read and Write Data Cycles

Address and Data Bus Inversion

Read data is supplied to the DQA pins exactly eight clock cycles

from the rising edge of the CK signal corresponding to the cycle

where the read command was initiated. QVLDA is asserted

one-half clock cycle prior to the first data word driven on the bus.

It is de asserted one-half cycle prior to the last data word driven

on the bus. Data outputs are tri stated in the clock following the

last data word.

To reduce simultaneous switching noise and I/O current, QDR-IV

XP SRAM provides the ability to invert all address and data pins.

The AINV pin indicates whether the address bus- A[24:0], and

the address parity bit, AP, is inverted. The address bus and parity

bit are considered one group. The function of the AINV is

controlled by the memory controller. However, the following rules

should be used in the system design.

Read data is supplied to the DQB pins exactly eight clock cycles

from the falling edge of the CK signal corresponding to the cycle

that the read command was initiated. QVLDB is asserted

one-half clock cycle prior to the first data word driven on the bus.

It is de-asserted one-half cycle prior to the last data word driven

on the bus. Data outputs are tristated in the clock following the

last data word.

■ For a × 36 configuration part, 20 address pins plus 1 parity bit

are used for 21 signals in the address group.If the number of

0’s in theaddressgroup is>11, AINVissetto1bythecontroller.

As a result, no more than 11 pins may switch in the same

direction during each bit time.

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CY7C4022KV13/CY7C4042KV13

■ For a × 18 data width part, 21 address pins plus 1 parity bit are

used for 22 signals in the address group. If the number of 0’s

in the address group is > 12, AINV is set to 1 by the controller.

As a result, no more than 12 pins may switch in the same

direction during each bit time.

Note The memory controller should generate address parity

based on the address bus first. Address inversion is done later

on the address bus and address parity bit.

Port Enable

The QDR-IV XP SRAM has two independent bidirectional data

ports. However, some system designers may either choose to

use only one port, or use one port as read-only and one port as

write-only.

The DINVA and DINVB pins indicate whether the corresponding

DQA and DQB pins are inverted.

■ For a × 36 data width part, the data bus for each port is split

into groups of 18 pins. Each 18-pin data group is guaranteed

to be driving less than or equal to 10 pins low on any given

cycle. If the number of 0’s in the data group is >10, DINV is set

to 1.As a result, no more than 10 pins may switch in the same

direction during each bit time.

If a port is used in a uni-directional mode, disable the data clocks

(DKx/DKx# or QKx/QKx#) to reduce EMI effects in the system.

In addition, disable the corresponding control input (RWx#).

Port B may be programmed to be entirely disabled. If port B is

not used, then the following must happen:

■ For a × 18 data width part, the data bus for each port is split

into groups of 9 pins. Each 9 pin data group is guaranteed to

be driving less than or equal to five pins low on any given cycle.

If the number of 0’s in the data group is >5, DINV is set to 1 As

a result, no more than five pins may switch in the same direction

during each bit time.

■ The data clocks (DKB/DKB# and QKB/QKB#) and the control

inputs (LDB# and RWB#) must be disabled.

■ All data bus signals must be tristated. This includes DQB,

DINVB and QVLDB.

■ All input signals related to port B can be left floating or tied to

either 1 or 0 without any adverse effects on the port A operation.

AINV, DINVA[1:0], DINVB[1:0] are all active high. When set to 1,

the corresponding bus is inverted. If the data inversion feature is

programmed to be OFF, then the DINVA/DINVB output bits will

always be driven to 0.

■ When port B is not used. All output signals related to port B are

inactive.

These functions are programmable through the configuration

registers and can be enabled or disabled for the address bus and

the data bus independently.

A configuration register option is provided to specify if one of the

ports is not used or is operating in a unidirectional mode.

On-Die Termination (ODT) Operation

During configuration register read and write cycles, the address

inversion input is ignored and the data inversion output is always

driven to 0 when the register read data is driven on the data bus.

Specifically, the register read data is driven on DQA[7:0] and the

DINVA[0] bit is driven to 0. All other DQA/DQB data bits and

DINVA/DINVB bits are tristated. In addition, the address parity

input (AP) is ignored.

When enabled, the ODT circuits for the chip will be enabled

during all NOP and write cycles. The ODT is temporary disabled

only during read cycles because the read data is driven out.

Specifically, ODT is disabled one-half clock cycle before the first

beat of the read data is driven on the data bus and remains

disabled during the entire read operation. ODT is enabled again

one-half clock cycle after the last beat of read data is driven on

the data bus.

Address Parity

The QDR-IV XP SRAM provides an address parity feature to

provide integrity on the address bus. Two pins are provided to

support this function: AP and PE#.

JTAG Operation

The JTAG interface uses five signals: TRST#, TCK, TMS, TDI,

and TDO. For normal JTAG operation, the use of TRST# is not

optional for this device.

The AP pin is used to provide an even parity across the address

pins. The value of AP is set so that the total number of 1’s

(including the AP bit) is even. The AP pin is a DDR input.

While in the JTAG mode, the following conditions are true:

Internally, when an address parity error is detected, the access

to the memory array is ignored if it was a write cycle. A read

access continues normally even if an address parity error is

detected.

■ ODT for all pins is disabled.

If the JTAG function is not used in the system, then the TRST#

pin must be tied to VDD and the TCK input must be driven low

or tied to VSS. TMS, TDI, and TDO may be left floating.

Externally, the PE# pin is used to indicate that an address parity

error has occurred. This pin is Active Low and is set to 0 within

RL cycles after the address parity error is detected. It remains

asserted until the error is cleared through the configuration

registers.

Power Up and Reset

The QDR-IV XP SRAM has specific power up and reset

requirements to guarantee reliable operation.

The address parity function is optional and can be enabled or

disabled in the configuration registers.

Power-Up Sequence

■ Apply V_DDbefore V_DDQ

.

During configuration register read and write cycles, the address

parity input is ignored. Parity is not checked during these cycles.

■ Apply V_DDQbefore V_REFor at the same time as V_REF

.

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CY7C4022KV13/CY7C4042KV13

Reset Sequence

Operation Modes

The QDR-IV XP has three unique modes of operation:

Refer to the Reset timing diagram (Figure 16 on page 41).

1. Configuration

2. Loopback

1. As the power comes up, all inputs may be in an undefined

state except RST# and TRST#, which must be LOW during

t_PWR

.

3. Memory Access

2. The first signal that should be driven to the device is the input

clock (CK/CK#), which may be unstable for the duration of

These modes are defined by the level of the control signals

CFG#, LBK0#, LBK1#, LDA#, LDB#.

t_PWR

.

It is intended that these operations are mutually exclusive. In

other words, one operation mode cannot be performed

simultaneously with another operation mode.

3. After the input clock has stabilized, all the control inputs

should be driven to a valid value as follows:

a. RST# = 0

b. CFG# = 1

c. LBK0# = 1

d. LBK1# = 1

e. LDA# = 1

f. LDB# = 1

There is no priority given for inadvertently asserting the control

signals at the wrong time. The internal chip behavior is not

defined for improper control signal assertion. The system

must strictly adhere to proper mode transitions as defined in the

following section for proper, device operation.

Configuration

4. Reset should remain asserted, while all other control inputs

de-asserted, for a minimum time of 200 µs (t_RSS).

A Configuration operation mode is entered when the CFG#

signal is asserted. Memory Access or Loopback operations

should not be performed for a minimum of 32 clocks prior to

entering this mode.

5. At the rising edge of reset, the address bits A[13:0] are

sampled to load in the ODT values and Port Enable values.

After reset, internal operations in the device may start. This

may include operations such as PLL initialization, resetting

and internal registers.

While in this mode, the control signals LDB#, LBK0# and LBK1#

must not be asserted. However, LDA# is used to perform the

actual Register Read and Write operations.

6. However, all external control signals must remain de-asserted

for a minimum time of 400000 clocks (t_RSH). During this time

all other signals (data and address busses) should be driven

to a valid level. All inputs to the device should be driven to a

valid level.

Memory Access or Loopback operations should not be

performed for a minimum of 32 clocks after exiting this mode.

Loopback

A Loopback operation mode is entered when the LBK0# and/or

LBK1# signals are asserted. Memory Access or Configuration

operations should NOT be performed for a minimum of 32 clocks

prior to entering this mode.

7. After this, the device is in normal operating mode and ready

to respond to control inputs.

Typically, after a reset sequence, the system starts to perform a

training sequence, involving the steps outlined in the following

section.

Just after entering this mode, an additional 32 clocks are

required before the part is ready to accept toggling valid inputs

for training.

However, RST# may be asserted at anytime by the system, and

the system may wish to initiate normal read/write operations after

a reset sequence without going through another training

sequence. The chip should be able to accept normal read/write

operations immediately following t_RSHafter the de-assertion of

RST#.

While in this mode, LDA# and LDB# may be toggled for training.

Memory Access or Configuration operations should NOT be

performed for a minimum of 32 clocks after exiting this mode.

Data inversion is not used during the Loopback mode. Even if

the configuration register has this feature enabled, it is

temporarily ignored during the Loopback mode.

PLL Reset Operation

The configuration registers contain a bit to reset the PLL.

Operating the QDR-IV XP device without the PLL enabled is not

supported–timing characteristics are not guaranteed when the

PLL is disabled. However, this bit is intended to allow the system

to reset the PLL locking circuitry.

Memory Access

If the control signals CFG#, LBK0#, and LBK1# are not asserted,

then the device is in the memory access mode. This mode is the

normal operating mode of the device.

Resetting the PLL is accomplished by first programming the PLL

Reset bit to 1 to disable the PLL, and then programming the bit

to 0 to enable the PLL. After these steps, the PLL will re-lock to

the input clock. A wait time of t_PLLis required.

While in this mode, a memory access cycle is performed when

the LDA# and/or LDB# signals are asserted. The control signals

CFG#, LBK0# and LBK1# must NOT be asserted when

performing a memory access cycle.

A memory access should not be performed for a minimum of 32

clocks prior to leaving this mode.

Document Number: 001-79552 Rev. *O

Page 11 of 46

CY7C4022KV13/CY7C4042KV13

The Write Training Enable bit has no effect on the read data

cycles.

Deskew Training Sequence

The QDR-IV XP SRAM provides support that allows a memory

controller to deskew signals for a high speed operation. The

memory controller provides the deskew function, if deskew is

desired. During the deskew operation the QDR-IV XP SRAM

operates in the Loopback mode.

After the data pattern is written into the memory, standard read

commands permit the system to deskew with respect to the

QK/QK# data output clocks the following signals:

DQA, DINVA, QVLDA, DQB, DINVB, QVLDB

Refer to Loopback Timing Diagram (Figure 15 on page 40)

Deskew is achieved in three steps

1. Control/address deskew

Write Data Deskew

Write data deskew is performed using write commands to the

memory followed by read commands.

2. Read data deskew

The deskewed read data path is used to determine whether or

not the write data was received correctly by the device.

3. Write data deskew

This permits the system to deskew with respect to the DK/DK#

input data clocks the following signals:

Control/Address Deskew

Assert LBK0# to 0 and/or LBK1# to 0

The following 39 signals are looped back:

DQA, DINVA, DQB, DINVB

I/O Signaling Standards

■ DKA0, DKA0#, DKA1, DKA1#

■ DKB0, DKB0#, DKB1, DKB1#

■ LDA#, RWA#, LDB#, RWB#

■ A[24:0], AINV, AP

Several I/O signaling standards are supported by the QDR-IV XP

SRAM, which are programmable by the user. They are:

■ 1.2 V and 1.25 V HSTL/SSTL

■ 1.1 V and 1.2 V POD

The clock inputs DKA0, DKA0#, DKA1#, DKB0, DKB0#, DKB1,

and DKB1# are free running clock inputs and should be

continuously running during the training sequence. In addition, a

wait time of tPLL is needed.

The I/O Signaling Standard is programmed on the rising edge of

reset by sampling the address bus inputs. Once programmed,

the value cannot be changed. Only the rising edge of another

reset can change the value.

Refer to Table 1 on page 14 for the loopback signal mapping.

All Address, Control, and Data I/O signals – with the exception

of six pins (listed as LVCMOS in the LVCMOS Signaling section)

– will program to comply with HSTL/SSTL, or POD compliant.

For each pin that is looped back, the input pin is sampled on both

the rising and falling edges using the input clock (CK/CK#).

The value output on the rising edge of the output clock

(QKA/QKA#) will be the value that was sampled on the rising

edge of the input clock.

HSTL/SSTL Signaling

HSTL/SSTL is supported at the V_DDQvoltages of 1.2 V and

1.25 V nominal.

The value output on the falling edge of the output clock

(QKA/QKA#) will be the inverted value that was sampled on the

falling edge of the input clock.

The ODT termination values can be set to:

■ 40, 60, or, 120 ohms with a 220-ohm reference resistor

The delay from the input pins to the DQA outputs is t_LBL, which

is 16 clocks.

■ 50 or 100 ohms with a 180-ohm reference resistor.

The drive strength can be programmed to:

Read Data Deskew

■ 40 or 60 ohms with a 220-ohm reference resistor

■ 50 ohms with a 180-ohm reference resistor

At this time, the address, control, and data input clocks are

already deskewed.

Read data deskew requires a training pattern to be written into

the memory using data held at constant values.

A reference resistor of 180 ohms or 220 ohms is supported with

HSTL/SSTL signaling.

Complex data patterns such as the following may be written into

the memory using the non-deskewed DQA and/or DQB signals

and the write training enable bit.

POD Signaling

POD is supported at V_DDQvoltages of 1.1 V and 1.2 V nominal.

The ODT termination values can be set to:

Write training enable set to 1:

During Write Data Cycles:

The First Data Beat (First Data Burst) is sampled from the data

bus.

The Second Data Beat (Second Data Burst) is the inverted

sample from the data bus.

■ 50 or 100 ohms with a 180-ohm reference resistor

■ 60 or 120 ohms with a 220-ohm reference resistor

The drive strength can be programmed to:

■ 50 ohms with a 180-ohm reference resistor

Write training enable set to 0:

During Write Data Cycles:

Both First and Second Data Beats are sampled from the data

bus, which is the normal operation.

■ 40 or 60 ohms with a 220-ohm reference resistor

A reference resistor of 180 ohms or 220 ohms is supported with

POD signaling.

Document Number: 001-79552 Rev. *O

Page 12 of 46

CY7C4022KV13/CY7C4042KV13

LVCMOS Signaling

The following flowchart illustrates the initialization procedure:

Six I/O signals are permanently set to use LVCMOS signaling at

a voltage of 1.3 V nominal. These signals are referenced to the

core voltage supply, V_DD. They are:

Figure 3. Flowchart illustrating initialization procedure

RST#, TRST#, TCK, TMS, TDI, and TDO

All the five JTAG signals as well as the main reset input are 1.3 V

LVCMOS.

In addition, ODT is disabled at all times on these LVCMOS

signals.

Initialization

The QDR-IV XP SRAM must be initialized before it can operate

in normal functional mode. Initialization uses four special pins:

- RST# pin to reset the device

- CFG# pin to program the Configuration Registers

- LBK0# and LBK1# pins for the Loopback function

Power on

Apply power to the chip as described in Power-Up Sequence.

Reset Chip

Apply reset to the QDR-IV XP SRAM as described in Reset

Sequence.

Configure the Impedance

Assert Config (CFG# = 0) and program the impedance control

register.

Wait for the PLL to Lock

Since the input impedance is updated, allow the PLL time (t_PLL

to lock to the input clock.

)

Document Number: 001-79552 Rev. *O

Page 13 of 46

CY7C4022KV13/CY7C4042KV13

Configure Training Options

At this time, the address and data inversion options need to be

programmed. In addition, the write training function needs to be

enabled.

Table 1. Loopback Signal Mapping

Input Pin

Output Pin

Assert Config (CFG# = 0) and program:

■ Write Training (Turn On)

LBK0# = 0

LBK1# = 0

LBK0# = 0

LBK1# = 1

LBK0# = 1

LBK1# = 0

A0

A1

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

AINV

DKA0

DKA0#

DKA1

DKA1#

LDA#

RWA#

DKB0

DKB0#

DKB1

DKB1#

LDB#

RWB#

AP

DQA0

DQA1

DQA2

DQA3

DQA4

DQA5

DQA6

DQA7

DQA8

DQA9

DQA10

DQA11

DQA12

■ Address Inversion Enable

■ Data Inversion Enable

A2

Control/Address Deskew

A3

Control and address deskew can now be performed by the

memory controller.

A4

A5

Read Data Deskew

A6

After control and address deskew, the read data path is

deskewed as described in Deskew Training Sequence.

A7

A8

Write Data Deskew

A9

Write data path is deskewed following the read data path

deskew.

A10

A11

A12

Configure Runtime Options

After the training is complete, disable the write training function.

Finally, enable the address parity option at this time.

Configuration Registers

Assert Config (CFG# = 0) and program:

■ Write Training (Turn off)

■ Parity Enable

The QDR-IV XP SRAM contains internal registers that are

programmed by the system using a special configuration cycle.

These registers are used to enable and control several options

as described in this section. All registers are 8-bits wide. The

write operation is performed using only the address pins to

define the register address and register write data. For a read

operation, the register read data is provided on the data port A

output pins. Refer to Figure 14 on page 39 for programming

details.

Normal Operation

If the system detects a need to deskew again, the process must

start again from the Configure Training Options step.The

following table defines the loopback mapping:

During the rising edge of RST#, the address pins A[13:0] are

sampled. The value sampled becomes the reset value of certain

bits in the registers defined below. This is used to set termination,

impedance, and port configuration values immediately upon

reset. These values can be overwritten later through a register

write operation.

When a parity error occurs, the complete address of the first

error is recorded in registers 4, 5, 6, and 7 along with the port A/B

error bit. The port A/B error bit will indicate from which port the

address parity error came – 0 for port A and 1 for port B. This

information will remain latched until cleared by writing a 1 to the

address parity error clear bit in register 3.

Two counters are used to indicate if multiple address parity errors

occurred. The port A error count is a running count of the number

of parity errors on port A addresses, and similarly the port B error

count is a running count of the number of parity errors on port B

addresses. They will each independently count to a maximum

value of 3 and then stop counting. These counters are free

running, and they are both reset by writing a 1 to the address

parity error clear bit in register 3.

Document Number: 001-79552 Rev. *O

Page 14 of 46

CY7C4022KV13/CY7C4042KV13

Configuration Registers Description

Table 2. Configuration Register Table

Register Address

Description

0

1

2

3

4

5

6

7

Termination Control Register

Impedance Control Register

Option Control Register

Function Control Register

Address Parity Status Register 0

Address Parity Status Register 1

Address Parity Status Register 2

Address Parity Status Register 3

Configuration Register Definitions

Table 3. Address 0: Termination Control Register (Read/Write)

ODT Global

Enable

ODT/ZQ

Auto Update Command

Address /

Command

Address /

Clock Input Clock Input Clock Input

Command Group KU[2] Group KU[1] Group KU[0]

Function

Input Group Input Group Input Group

IU[2]

IU[1]

IU[0]

Bit Location

Reset Value

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Note: ODT/ZQ Auto Update needs to be turned on if ODT/ZQ configuration is changed

Table 4. Address 1: Impedance Control Register (Read/Write)

Pull Down

Pull Up

Unused

Data Input

Function

Group PD[1] Group PD[0] Group PU[1] Group PU[0]

Group QU[2] Group QU[1] Group QU[0]

Bit Location

Reset Value

7

1

6

0

5

1

4

0

3

0

2

1

0

A10

A9

A8

Table 5. Address 2: Option Control Register (Read/Write Bits 7-3) (Read-Only Bits 2-0) ^[2]

Write Train

Enable

Data Inv

Enable

Address Inv

Enable

Address

Parity Enable

PLL Reset

I/O Type

Port

Enable[1]

Port Enable[0]

Function

Bit Location

Reset Value

7

0

6

0

5

0

4

0

3

0

2

1

0

A13

A12

A11

Table 6. Address 3: Function Control Register (Write Only)

Unused

Address Parity

Error Clear

Function

Bit Location

Reset Value

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Note

2. The Bits 2–0 are read only and can be changed only on the rising edge of reset

Document Number: 001-79552 Rev. *O

Page 15 of 46

CY7C4022KV13/CY7C4042KV13

Table 7. Address 4: Address Parity Status Register 0 (Read Only)

Port B Error Count

(1:0)

Port A Error Count

(1:0)

Port A/B Error

AINV Bit

Unused

Function

Bit Location

Reset Value

7:6

00

5:4

00

3

0

2

0

1

0

Table 8. Address 5: Address Parity Status Register 1 (Read Only)

Function

Address (23:16)

Bit Location

7:0

Reset Value

00000000

Note: Unused address locations will be read as 0

Table 9. Address 6: Address Parity Status Register 2 (Read Only)

Function

Bit Location

Reset Value

Address (15:8)

7:0

00000000

Table 10. Address 7: Address Parity Status Register 3 (Read Only)

Function

Bit Location

Reset Value

Address (7:0)

7:0

00000000

Document Number: 001-79552 Rev. *O

Page 16 of 46

CY7C4022KV13/CY7C4042KV13

I/O Type and Port Enable Bit Definitions

Table 11. I/O Type Bit Definition specified in Address 2: Option Control Register

I/O Type

Function

HSTL/SSTL

POD

0

1

Table 12. Port Enable Bit Definition specified in Address 2: Option Control Register

Port B

Clocks and

Controls

Port A

Clocks and

Controls

Port Enable

[1:0]

Port B

Mode

Port A

Mode

Function

0

1

0

1

0

1

Fixed Port Mode

Write Only

Disabled

Enabled

Read Only

Enabled

Disabled

Enabled

DKB - On

QKB - Off

LDB# - On

RWB# - Off

DKA - Off

QKA - On

LDA# - On

RWA# - Off

Only Port A

Enable

DKB - Off

QKB - Off

LDB# - Off

RWB# - Off

DKA - On

QKA - On

LDA# - On

RWA# - On

Not supported

DKB - Off

QKB - Off

LDB# - Off

RWB# - Off

DKA - Off

QKA - Off

LDA# - Off

RWA# - Off

Both Ports

Enabled

DKB - On

QKB - On

LDB# - On

RWB# - On

DKA - On

QKA - On

LDA# - On

RWA# - On

Document Number: 001-79552 Rev. *O

Page 17 of 46

CY7C4022KV13/CY7C4042KV13

ODT Termination Bit Definitions

Table 13. Clock Input Group Bit Definition specified in Address 0: Termination Control Register

ODT

Global

Enable

Termination Value HSTL/SSTL Mode

Termination Value POD Mode

Divisor

Value

KU[2:0]

ZT 180 ohm

ZT 220 ohm

ZT 180 ohm

ZT 220 ohm

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

–

OFF

8.33%

12.50%

16.67%

25%

50%

-

Not supported

50 ohm

Not supported

40 ohm

Not supported

50 ohm

Not supported

60 ohm

100 ohm

120 ohm

100 ohm

120 ohm

Not supported

-

Note: Termination values are accurate to ±15%

ZQ tolerance is 1%

Table 14. Address/Command Input Group Bit Definition specified in Address 0: Termination Control Register

ODT

Global

Enable

Termination Value HSTL/SSTL Mode

Termination Value POD Mode

Divisor

Value

IU[2:0]

ZT 180 ohm

ZT 220 ohm

ZT 180 ohm

ZT 220 ohm

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

–

OFF

8.33%

12.50%

16.67%

25%

50%

–

Not supported

50 ohm

Not supported

40 ohm

Not supported

50 ohm

Not supported

60 ohm

100 ohm

120 ohm

100 ohm

120 ohm

Not supported

–

Note: Termination values are accurate to ±15%

ZQ tolerance is 1%

Table 15. Data Input Group Bit Definition specified in Address 1: Impedance Control Register

ODT

Global

Enable

Termination Value HSTL/SSTL Mode

Termination Value POD Mode

Divisor

Value

QU[2:0]

ZT 180 ohm

ZT 220 ohm

ZT 180 ohm

ZT 220 ohm

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

–

OFF

8.33%

12.50%

16.67%

25%

50%

–

Not supported

50 ohm

Not supported

40 ohm

Not supported

50 ohm

Not supported

60 ohm

100 ohm

120 ohm

100 ohm

120 ohm

Not supported

–

Note: Termination values are accurate to ±15%

ZQ tolerance is 1%

Document Number: 001-79552 Rev. *O

Page 18 of 46

CY7C4022KV13/CY7C4042KV13

Drive Strength Bit Definitions

Table 16. Pull-Up Driver Bit Definition specified in Address 1: Impedance Control Register

Impedance Value HSTL/SSTL Mode

Impedance Value POD Mode

Divisor

Value

PU[1:0]

ZT 180 ohm

Not supported

50 ohm

ZT 220 ohm

Not supported

40 ohm

ZT 180 ohm

Not supported

50 ohm

ZT 220 ohm

Not supported

40 ohm

0

1

0

1

0

1

14.17%

16.67%

25%

60 ohm

–

Not supported

Note: Termination values are accurate to ±15%

ZQ tolerance is 1%

Table 17. Pull-Down Driver Bit Definition

Impedance Value HSTL/SSTL Mode

Impedance Value POD Mode

Divisor

Value

PD[1:0]

ZT 180 ohm

Not supported

50 ohm

ZT 220 ohm

Not supported

40 ohm

ZT 180 ohm

Not supported

50 ohm

ZT 220 ohm

Not supported

40 ohm

0

1

0

1

0

1

14.17%

16.67%

25%

60 ohm

–

Not supported

Note: Termination values are accurate to ±15%

ZQ tolerance is 1%

Document Number: 001-79552 Rev. *O

Page 19 of 46

CY7C4022KV13/CY7C4042KV13

Instruction Register

IEEE 1149.1 Serial Boundary Scan (JTAG)

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO pins, as shown in Figure 5 on page 23. Upon power up,

the instruction register is loaded with the IDCODE instruction. It

is also loaded with the IDCODE instruction if the controller is

placed in a RST state, as described in the previous section.

QDR-IV XP SRAMs incorporate a serial boundary scan test

access port (TAP) in the FCBGA package. This part is fully

compliant with IEEE Standard #1149.1-2001. In the JTAG mode

the ODT feature for all pins is disabled.

If the JTAG function is not used in the circuit, then TCK inputs

must be driven low or tied to VSS. TRST#, TMS, TDI, and TDO

may be left floating. An internal Pull-Up resistor is implemented

on the TRST#, TMS, and TDI inputs to ensure that these inputs

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

are HIGH during t_PWR

Test Access Port

Test Clock (TCK)

.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between TDI

and TDO pins. This enables shifting of data through the SRAM

with minimal delay. The bypass register is set LOW (VSS) when

the BYPASS instruction is executed.

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

Boundary Scan Register

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The pin is pulled up

internally, resulting in a logic HIGH level.

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several No Connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

Test Data-In (TDI)

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. For information on

loading the instruction register, see Figure 4 on page 22. TDI is

internally pulled up and can be unconnected if the TAP is unused

in an application. TDI is connected to the most significant bit

(MSB) on any register.

The Boundary Scan Order on page 27 shows the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Test Data-Out (TDO)

Identification (ID) Register

The TDO output pin is used to serially clock data out from the

registers. The output is active, depending upon the current state

of the TAP state machine (see Instruction Codes on page 26).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 26.

Test Reset (TRST#)

The TRST# input pin is used to reset the TAP controller.

Alternatively, a reset may be performed by forcing TMS HIGH

(V_DD) for five rising edges of TCK.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 26. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in this section in detail.

This reset does not affect the operation of the SRAM and can be

performed while the SRAM is operating. At power up, the TAP is

reset internally to ensure that TDO comes up in a high Z state.

TAP Registers

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction after it is shifted in, the TAP controller must be

moved into the Update-IR state.

Registers are connected between the TDI and TDO pins to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction registers. Data

is serially loaded into the TDI pin on the rising edge of TCK. Data

is output on the TDO pin on the falling edge of TCK.

Document Number: 001-79552 Rev. *O

Page 20 of 46

CY7C4022KV13/CY7C4042KV13

IDCODE

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required, that is, while the data

captured is shifted out, the preloaded data can be shifted in.

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO pins and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state. The

IDCODE instruction is loaded into the instruction register at

power up or whenever the TAP controller is supplied a

Test-Logic-RST state.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a High Z state until the next command is supplied during the

Update IR state. Both Port A and Port B are enabled once this

command has been executed.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the Shift-DR controller state. Both Port A and Port B are

enabled after this command is executed.

SAMPLE/PRELOAD

EXTEST OUTPUT BUS TRISTATE

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tristate mode.

The boundary scan register has output enable control bits

located at Bit #49 and Bit #50. Bit# 49 enables the output pins

for DQB and Bit#50 enables DQA and PE# pins.

Remember that the TAP controller clock can only operate at a

frequency up to 20 MHz, while the SRAM clock operates more

than an order of magnitude faster. Because there is a large

difference in the clock frequencies, it is possible that during the

Capture-DR state, an input or output undergoes a transition. The

TAP may then try to capture a signal while in transition

(metastable state). This does not harm the device, but there is

no guarantee as to the value that is captured. Repeatable results

may not be possible.

When these scan cells, called the “extest output bus tristate,” are

latched into the preload register during the Update-DR state in

the TAP controller, they directly control the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

High Z condition.

These bits can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the Shift-DR state. During Update-DR, the value loaded

into that shift-register cell latches into the preload register. When

the EXTEST instruction is entered, these bits directly controls the

output Q-bus pins. Note that these bits are pre-set LOW to

disable the output when the device is powered up, and also when

the TAP controller is in the Test-Logic-RST state.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

times (t_CSand t_CH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK captured in the boundary scan register.

Reserved

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells before the selection

of another boundary scan test operation.

Document Number: 001-79552 Rev. *O

Page 21 of 46

CY7C4022KV13/CY7C4042KV13

TAP Controller State Diagram

Figure 4. TAP Controller State Diagram ^[2]

TEST-LOGIC

1

RST

0

1

SELECT

IR-SCAN

TEST-LOGIC/

SELECT

0

IDLE

DR-SCAN

0

1

CAPTURE-DR

0

CAPTURE-IR

0

1

SHIFT-DR

1

SHIFT-IR

1

0

EXIT1-DR

0

EXIT1-IR

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-IR

0

UPDATE-DR

1

0

Note

3. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-79552 Rev. *O

Page 22 of 46

CY7C4022KV13/CY7C4042KV13

TAP Controller Block Diagram

Figure 5. TAP Controller Block Diagram

0

Bypass Register

2

1

0

Selection

TDI

Selection

Circuitry

TDO

Instruction Register

Circuitry

31 30

29

.

2

Identification Register

.

135

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TRST#

Document Number: 001-79552 Rev. *O

Page 23 of 46

CY7C4022KV13/CY7C4042KV13

TAP Electrical Characteristics

Over the Operating Range

Parameter

V_OH

Description

Test Conditions

Min

Max

Unit

LVCMOS High Level Output

Voltage

I_OH= 100µA

V_DD× 0.8

–

V

V_OL

V_IH

V_IL

LVCMOS Low Level Output

Voltage

I_OL= 100 µA

–

V_DD× 0.2

V

LVCMOS High Level Input

Voltage (DC)

V_DD× 0.7 V_DD+ 0.2

LVCMOS Low Level Input

Voltage (DC)

–0.2

V_DD× 0.3

I_X

LVCMOS Input Leakage Current

–

10

A

I_OZ

LVCMOS Output Leakage

Current

TAP AC Switching Characteristics

Over the Operating Range

Parameter

Description

Min

50

–

Max

–

Unit

ns

t_TCYC

TCK clock cycle time

TCK clock frequency

TCK clock HIGH

t_TF

20

–

MHz

ns

t_TH

20

t_TL

TCK clock LOW

–

ns

Setup Times

t_TMSS

t_TDIS

TMS setup to TCK clock rise

TDI setup to TCK clock rise

Capture setup to TCK rise

5

–

ns

t_CS

Hold Times

t_TMSH

t_TDIH

TMS hold after TCK clock rise

TDI hold after clock rise

5

–

ns

t_CH

Capture hold after clock rise

Output Times

t_TDOV

t_TDOX

TCK clock LOW to TDO valid

TCK clock LOW to TDO invalid

–

0

10

–

ns

Note: t and t refer to setup and hold time requirements of latching data from the boundary scan register.

CS

CH

Document Number: 001-79552 Rev. *O

Page 24 of 46

CY7C4022KV13/CY7C4042KV13

TAP Timing Diagram

Figure 6. TAP Timing Diagram

Document Number: 001-79552 Rev. *O

Page 25 of 46

CY7C4022KV13/CY7C4042KV13

Identification Register Definitions

Value

Instruction Field

Description

CY7C4022KV13

000

CY7C4042KV13

000

11011010101100100 Defines the type of SRAM.

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

Version number.

11011010101010100

00000110100

Allows unique identification of SRAM

vendor.

ID Register Presence (0)

1

Indicates the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

3

1

ID

32

136

Boundary Scan

Instruction Codes

Instruction

EXTEST

Code

000

Description

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document Number: 001-79552 Rev. *O

Page 26 of 46

CY7C4022KV13/CY7C4042KV13

Boundary Scan Order

CY7C4042KV13

CY7C4022KV13

× 18 Device

DQA<17>

DQA<10>

DQA<16>

NC

Bit

Bump

× 36 Device

DQA<26>

DQA<19>

DQA<25>

DQA<35>

DQA<23>

DQA<31>

QVLDA<1>

QKA<1>

0

12A

13B

14A

15B

16A

18B

17C

16C

14C

12C

12D

13D

15D

17D

18E

15F

16F

17F

18G

16G

17H

15H

16J

1

2

3

4

DQA<14>

NC

5

6

QVLDA<1>

QKA<1>

DQA<11>

DQA<9>

DINVA<1>

DQA<13>

DQA<12>

QKA#<1>

NC

7

8

DQA<20>

DQA<18>

DINVA<1>

DQA<22>

DQA<21>

QKA#<1>

DQA<32>

DQA<24>

DKA<1>

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

DQA<15>

DKA<1>

DKA#<1>

NC

DKA#<1>

DQA<33>

DQA<34>

DQA<27>

DQA<28>

DQA<30>

DQA<29>

RST#

NC

18J

NC

18K

18L

16L

15M

17M

18N

16N

15P

16P

17P

18R

17T

15T

13T

12T

12U

14U

16U

17U

18V

15V

RST#

DQB<29>

DQB<30>

DQB<28>

DQB<27>

DQB<33>

DQB<34>

DQB<24>

DKB<1>

NC

DQB<15>

DKB<1>

DKB#<1>

NC

DKB#<1>

DQB<32>

QKB#<1>

DQB<21>

DQB<22>

DINVB<1>

DQB<18>

DQB<20>

QKB<1>

QKB#<1>

DQB<12>

DQB<13>

DINVB<1>

DQB<9>

DQB<11>

QKB<1>

QVLDB<1>

NC

QVLDB<1>

DQB<31>

DQB<35>

NC

Document Number: 001-79552 Rev. *O

Page 27 of 46

CY7C4022KV13/CY7C4042KV13

Boundary Scan Order (continued)

CY7C4042KV13

CY7C4022KV13

× 18 Device

DQB<10>

DQB<17>

DQB<16>

DQB<14>

Internal_DQB

Internal_DQA

PE#

Bit

Bump

× 36 Device

DQB<19>

DQB<26>

DQB<25>

DQB<23>

Internal_DQB

Internal_DQA

PE#

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

13V

12W

14W

16W

10V

8P

A<15>

7N

A<9>

9N

NC/1152M

AP

NC/576M

AP

10P

10N

11N

12P

13N

13L

12M

11L

10L

10M

9L

A<2>

NC/2304M

A<16>

NC/1152M

A<16>

A<10>

A<8>

A<12>

A<18>

RWB#

AINV

A<17>

8M

A<11>

7L

A<7>

7J

A<5>

9J

A<19>

10K

10J

11J

13J

12H

10H

8H

CK#

CK

NC/144M

A<6>

A<20>

A<6>

LDB#

RWA#

LDA#

7G

A<3>

9G

NC/288M

A<1>

NC/144M

A<1>

10G

11G

13G

12F

10F

8F

NC/576M

A<4>

NC/288M

A<4>

A<14>

A<0>

A<13>

10D

10B

10A

8A

CFG#

LBK#<1>

LBK#<0>

DQA<8>

DQA<1>

DQA<7>

DQA<17>

LBK#<1>

LBK#<0>

DQA<8>

DQA<1>

DQA<7>

NC

7B

6A

5B

Document Number: 001-79552 Rev. *O

Page 28 of 46

CY7C4022KV13/CY7C4042KV13

Boundary Scan Order (continued)

CY7C4042KV13

CY7C4022KV13

× 18 Device

DQA<5>

NC

Bit

Bump

× 36 Device

DQA<5>

DQA<13>

QVLDA<0>

QKA<0>

92

4A

2B

3C

4C

6C

8C

8D

7D

5D

3D

2E

3F

4F

5F

4G

2G

3H

5H

4J

93

94

QVLDA<0>

QKA<0>

DQA<2>

DQA<0>

DINVA<0>

DQA<4>

DQA<3>

QKA#<0>

NC

95

96

DQA<2>

DQA<0>

DINVA<0>

DQA<4>

DQA<3>

QKA#<0>

DQA<14>

DKA#<0>

DKA<0>

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

DKA#<0>

DKA<0>

DQA<6>

NC

DQA<6>

DQA<16>

DQA<15>

DQA<9>

DQA<10>

DQA<12>

DQA<11>

DQB<11>

DQB<12>

DQB<10>

DQB<9>

DQB<15>

DQB<16>

DQB<6>

DKB<0>

NC

2J

NC

2L

NC

4L

NC

5M

3M

2N

4N

5P

4P

3P

2R

3T

5T

7T

8T

8U

6U

4U

3U

2V

5V

7V

8W

6W

4W

NC

DQB<6>

DKB<0>

DKB#<0>

NC

DKB#<0>

DQB<14>

QKB#<0>

DQB<3>

DQB<4>

DINVB<0>

DQB<0>

DQB<2>

QKB<0>

QKB#<0>

DQB<3>

DQB<4>

DINVB<0>

DQB<0>

DQB<2>

QKB<0>

QVLDB<0>

NC

QVLDB<0>

DQB<13>

DQB<17>

DQB<1>

DQB<8>

DQB<7>

DQB<5>

NC

DQB<1>

DQB<8>

DQB<7>

DQB<5>

Document Number: 001-79552 Rev. *O

Page 29 of 46

CY7C4022KV13/CY7C4042KV13

Maximum Ratings

Operating Range

Ambient

Temperature (T_A)

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Range

V_DD

V_DDQ

Commercial

Industrial

0 °C to +70 °C

1.3V ±

40 mV

1.1 V ± 50 mV

1.2 V ± 50 mV

Storage temperature ................................ –65 °C to +150 °C

–40 °C to +85 °C

Ambient temperature

with Power Applied .................................. –55 °C to +125 °C

Maximum Junction Temperature ............................... 125 °C

Neutron Soft Error Immunity

Supply Voltage on

Test

Parameter Description

Conditions

V_DDRelative to GND .................................–0.3 V to +1.35 V

Typ Max* Unit

Supply Voltage on

V_DDQRelative to GND ...............................–0.3 V to +1.35 V

LSBU

LMBU

SEL

Logical

single-bit

upsets

25 °C

85 °C

0

0.01 FIT/

Mb

DC Input Voltage .......................................–0.3 V to +1.35 V

Current into Outputs (LOW) ........................................ 20 mA

Logical

multi-bit

upsets

0.01 FIT/

Mb

Static Discharge Voltage

(MIL-STD-883, M. 3015) ......................................... > 2001V

Latch up current .....................................................> 200 mA

Single event

latch-up

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

2

statistical  , 95% confidence limit calculation. For more details refer to Application

Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure

Rates – AN54908.

Electrical Characteristics

Over the Operating Range

Parameter

Description

Min

Typ

Max

Unit

POD Signaling Mode

[4]

V_DD

Core supply voltage (1.3 V ± 40 mV)

1.26

1.05

1.15

1.3

1.1

1.2

1.34

1.15

1.25

V

[4]

V_DDQ

POD I/O supply voltage (1.1 V ± 50 mV)

POD I/O supply voltage (1.2 V ± 50 mV)

POD reference voltage

V

[4, 5]

V_REF

V_DDQ× 0.69 V_DDQ× 0.7 V_DDQ× 0.71

V

[4]

V_OL(DC)

POD low level output voltage (DC)

–

V_REF+ 0.08

–0.15

–

0.5

V

[4, 6]

V_IH(DC)

POD high level input voltage (DC)

V_DDQ+ 0.15

V

[4, 6]

[4, 7]

V_IL(DC)

V_IH(AC)

V_IL(AC)

POD low level input voltage

V_REF– 0.08

V

POD high level input voltage (DC)

V_REF+ 0.15

–

V

POD low level input voltage

V_REF– 0.15

V

V_MP(DC)

V_ID(DC)

V_ID(AC)

V_IN

POD differential Input Mid-Point Voltage; Pin and Pin#

POD differential Input Differential Voltage (DC); Pin and Pin#

POD differential Input Differential Voltage (AC); Pin and Pin#

POD single-ended Input Voltage; Pin and Pin#

POD single-ended Input Voltage Slew Rate; Pin and Pin#

V_REF– 0.08

0.16

V_REF+ 0.08

V

–

V

0.30

–

V

0.27

V_DDQ+ 0.15

–

V

V_INS

3

V/ns

V

V_IX(AC)

POD differential Input Crossing Point Voltage (AC); Pin and

Pin#

V_REF– 0.08

V_REF+ 0.08

Notes

4. All voltages referenced to VSS (GND).

5. Peak to Peak AC noise on V must not exceed +/–2% V

(DC).

DDQ

REF

6.

7.

V

/V (DC) are specified with ODT disabled.

IH IL

/V (AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.

IH IL

Document Number: 001-79552 Rev. *O

Page 30 of 46

CY7C4022KV13/CY7C4042KV13

Electrical Characteristics (continued)

Over the Operating Range

Parameter

[8]

Description

Min

–

Typ

–

Max

200

Unit

µA

I_X

POD input leakage current

[8]

I_OZ

POD output leakage current

–

200

µA

[9, 10]

I_DD

V_DDoperating supply (1066 MHz, × 18)

V_DDoperating supply (1066 MHz, × 36)

V_DDoperating supply (933 MHz, × 18)

V_DDoperating supply (933 MHz, × 36)

–

2800

3920

2520

3520

4100

4500

3400

4000

mA

–

HSTL/SSTL Signaling Mode

[11]

V_DD

Core supply voltage (1.3 V ± 40 mV)

1.26

1.15

1.2

1.3

1.2

1.34

1.25

1.3

V

[11]

V_DDQ

I/O supply voltage (1.2 V ± 50 mV)

I/O supply voltage (1.25 V ± 50 mV)

HSTL/SSTL reference voltage (DC)

HSTL/SSTL reference voltage (AC)

HSTL/SSTL high level input voltage (DC)

HSTL/SSTL low level input voltage (DC)

HSTL/SSTL high level input voltage (AC)

HSTL/SSTL low level input voltage (AC)

1.25

[11, 12]

V_REF(DC)

V_REF(AC)

V_DDQ× 0.48 V_DDQ× 0.5 V_DDQ× 0.52

V_DDQ× 0.47 V_DDQ× 0.5 V_DDQ× 0.53

[11, 13]

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

V_REF+ 0.8

–0.15

–

V_DDQ+ 0.15

V_REF– 0.08

V_DDQ+ 0.24

V_REF– 0.15

–

[11, 13]

[11, 14]

[11]

V_REF+ 0.15

–0.24

V_OH(DC)

HSTL/SSTL high level output voltage (DC) –

I_OH= –0.25 × V_DDQ/R_OH

V_DDQ× 0.712 V_DDQ× 0.75

[11]

V_OL(DC)

HSTL/SSTL low level output voltage (DC) –

–

V_DDQ× 0.25 V_DDQ× 0.288

V

I

_OL= 0.25 × V_DDQ/R_OL

V_IX

HSTL/SSTL input Voltage Cross point

HSTL/SSTL AC Input Differential Voltage

HSTL/SSTL DC Input Differential Voltage

HSTL/SSTL DC Common Mode Input

HSTL/SSTL Output voltage cross point

HSTL/SSTL AC Output Voltage

–

V_DDQ× 0.5

–

V_DDQ+ 0.48

V_DDQ+ 0.30

V_DDQ× 0.6

–

V

V_DIF(AC)

V_DIF(DC)

V_DIF(CM)

V_OX

V_OUT(AC)

0.30

–

0.16

–

V

V_DDQ× 0.4

V_DDQ× 0.5

V

–

V_DDQ× 0.5

V

–0.24

–

V_DDQ+ 0.24

V_DDQ+ 0.15

200

V

V_OUT(DC)

HSTL/SSTL DC Output Voltage

–0.15

V

[8]

I_X

HSTL/SSTL input leakage current

HSTL/SSTL output leakage current

V_DDoperating supply (1066 MHz, × 18)

V_DDoperating supply (1066 MHz, × 36)

V_DDoperating supply (933 MHz, × 18)

V_DDoperating supply (933 MHz, × 36)

–

µA

mA

[8]

I_OZ

–

200

[9, 10]

I_DD

2800

3920

2520

3520

4100

4500

3400

4000

Notes

8. Output driver into High Z with ODT disabled.

9. The operation current is calculated with 50% read cycle and 50% write cycle.

10. Typical operation current specifications are tested at 1.3V VDD.

11. All voltages referenced to VSS (GND).

12. Peak to Peak AC noise on V

must not exceed +/–2% V

(DC).

REF

DDQ

13. V /V (DC) are specified with ODT disabled.

IH IL

14. V /V (AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.

IH IL

Document Number: 001-79552 Rev. *O

Page 31 of 46

CY7C4022KV13/CY7C4042KV13

Capacitance

Table 18. Capacitance

Parameter ^[15]

Description

Test Conditions

Max

4

Unit

pF

C_IN

C_O

Input capacitance

Output capacitance

T_A= 25 C, f = 1 MHz, V_DD= 1.3 V, V_DDQ= 1.25 V

4

pF

Thermal Resistance

Table 19. Thermal Resistance

361-ball FCBGA

Package

Parameter ^[15]

Description

Test Conditions

Unit

_JA

Thermal resistance

(junction to ambient)

Test conditions follow standard With Still Air (0 m/s)

12.00

10.57

9.09

°C/W

test methods and procedures for

measuring thermal impedance, in

With Air Flow (1 m/s)

accordance with EIA/JESD51.

With Air Flow (3 m/s)

_JB

_JC

Thermal resistance

(junction to board)

3.03

Thermal resistance

(junction to case)

0.029

°C/W

AC Test Load and Waveform

Figure 7. AC Test Load and Waveform

Note

15. Tested initially and after any design or process change that may affect these parameters.

Document Number: 001-79552 Rev. *O

Page 32 of 46

CY7C4022KV13/CY7C4042KV13

Switching Characteristics

Over the Operating Range ^{[16, 17, 18, 19, 20, 21, 22, 23]}

1066 MHz

933 MHz

Cypress

Description

Parameter

Unit

Min

Max

Min

Max

t_CK

CK, DKx, QKx clock Period

CK, DKx LOW time

0.938

0.45*

–0.055

–

3.333

1.071

0.45*

–0.060

–

3.333

ns

t_CK

ns

t_CKL

t_CKH

t_JIT(per)

t_JIT(cc)

t_AS

–

CK, DKx HIGH time

–

Clock Period Jitter

0.055

0.060

Cycle-to-cycle Jitter

0.110

0.120

A to CK setup

0.125

0.170

0.150

0.170

–0.15

0.125

0.150

–

0.135

0.180

–0.172

0.135

0.180

–

t_AH

CK to A hold

–

t_ASH

t_CS

CK to A setup-hold window

LDx#, RWx# to CK setup

CK to LDx#, RWx# hold

CK to LDx#, RWx# setup-hold window

CK to DKx skew

–

t_CH

–

t_CSH

t_CKDK

t_IS

–

0.15

–

0.172

DQx, DINVx to DKx setup

DKx to DQx, DINVx hold

–

t_IH

–

t_ISH0

DKx[0] to DQx[17:0], DINVx[0] (× 36) or

–

DKx[0] to DQx[8:0], DINVx[0] (× 18) setup-hold window

t_ISH1

DKx[1] to DQx[35:18], DINVx[1] (× 36) or

DKx[1] to DQx[17:9], DINVx[1] (× 18) setup-hold window

0.150

–

0.180

–

ns

t_Rise(se)

t_Fall(se)

t_Rise(diff)

t_Fall(diff)

t_QKL

Single ended Output Signal Rise Time 20%–80%

Single ended Output Signal Fall Time 20%–80%

Differential Output Signal Rise Time 20%–80%

Differential Output Signal Fall Time 20%–80%

QKx LOW time

2

6

2

6

V/ns

t_CK

2

3

2

3

10

3

10

3

10

0.45*

–0.225

–

0.45*

–0.257

–

t_QKH

QKx HIGH time

–

t_CK

t_CKQK

CK to QKx skew

0.225

0.075

0.257

0.085

ns

t_QKQ0

QKx[0] to DQx[17:0], DINVx[0] (× 36) or

QKx[0] to DQx[8:0], DINVx[0] (× 18)

ns

t_QH0

QKx[0] to DQx[17:0], DINVx[0] (× 36) or

QKx[0] to DQx[8:0], DINVx[0] (× 18)

0.40*

–

0.075

–

0.40*

–

0.085

–

t_CK

ns

t_QKQ1

t_QH1

QKx[1] to DQx[35:18], DINVx[1] (× 36) or

QKx[1] to DQx[17:9], DINVx[1] (× 18)

QKx[1] to DQx[35:18], DINVx[1] (× 36) or

QKx[1] to DQx[17:9], DINVx[1] (× 18)

0.40*

t_CK

Notes

16. x refers to Port A and Port B. For example, DQx refers to DQA and DQB.

17. Input hold timing assumes rising edge slew rate of 4 V/ns measured from V /V (DC) to V

.

REF

IL IH

18. Input setup timing assumes falling edge slew rate of 4 V/ns measured from V

to V /V (AC).

REF

IL IH

19. All output timing assumes the load shown in Figure 8.

20. Setup/hold window, t

t

are used for pin to pin timing budgeting and cannot be directly applied without performing de-skew training.

ASH, CSH, ISH

21. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

22. Frequency drift is not allowed.

23. t

, t

and t

are guaranteed by design.

QKL QKH QKQ QKQX ASH CSH

ISH

Document Number: 001-79552 Rev. *O

Page 33 of 46

CY7C4022KV13/CY7C4042KV13

Switching Characteristics (continued)

Over the Operating Range ^{[16, 17, 18, 19, 20, 21, 22, 23]}

1066 MHz

933 MHz

Max

Cypress

Description

Parameter

Unit

Min

Max

Min

–

t_QKQV0

t_QVH0

t_QKQV1

t_QVH1

t_PWR

t_RSS

QKx[0] to QVLDx

–

0.85*

–

0.112

0.128

ns

t_CK

ns

QKx[0] to QVLDx

–

0.85*

–

QKx[1] to QVLDx

0.112

0.128

QKx[1] to QVLDx

0.85*

200

400000*

500*

200

–

0.85*

200

400000*

500*

200

–

t_CK

ms

µs

V_DD(Typical) to the first access

RST# pulse width

–

t_RSH

t_RDS

t_RDH

t_TSS

RST# deasserted to first active command

A to RST# setup

–

t_CK

µs

–

A to RST# hold

–

TRST# pulse width

–

t_TSH

TRST# deasserted to first JTAG command

Time for PLL to stabilize after being reset

Loopback Latency

–

µs

t_PLL

100

16*

5

100

16*

5

µs

t_LBL

16*

t_CK

ns

t_CD

Loopback Output Delay

Active mode to Configuration mode

–

t_CFGS

t_CFGH

32*

–

32*

–

t_CK

Configuration mode to Active mode Register Access

without ODT or PLL programming updates

32*

–

32*

–

t_CFGH

Configuration mode to Active mode Register Access with

ODT programming updates

4096*

100

–

4096*

100

–

t_CK

µs

Configuration mode to Active mode Register Access with

PLL programming updates

t_CFGD

t_CLDS

t_CLDH

t_CFGA

t_CLDW

t_CRDL

t_CRDH

t_DQVLD

Configuration command to Configuration command

CFG# assertion to LDA# assertion

80*

32*

16*

–

80*

32*

16*

–

t_CK

LDA# deassertion to CFG# deassertion

CFG# assertion to Address assertion

–

LDA# pulse width for Configuration command

LDA# assertion to Read Data Latency

CFG# deassertion to Read Data Hold

DQAx to QVLDA<0> in Configuration mode

–

32*

2

32*

2

0*

-2

–2

Document Number: 001-79552 Rev. *O

Page 34 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms

Figure 8. Rise and Fall Time Definitions for Output Signals

Nominal Rise-Fall Time Definition for Single-Ended Output Signals

Nominal Rise-Fall Time Definition for Differential Output Signals

Document Number: 001-79552 Rev. *O

Page 35 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 9. Input and Output Timing Waveforms

Address and Command Input Timing

Data Input Timing

Data Output Timing

Document Number: 001-79552 Rev. *O

Page 36 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 10. Waveforms for 8.0 Cycle Read Latency (Read to Write Timing Waveform)

Figure 11. Waveforms for 8.0 Cycle Read Latency (Write to Read Timing Waveform)

Document Number: 001-79552 Rev. *O

Page 37 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 12. Configuration Write Timing Waveform

Note: It is recommended to keep CFG# asserted during the configuration write or read operation

Figure 13. Configuration Read Timing Waveform

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

Note: It is recommended to keep CFG# asserted during the configuration write or read operation

Document Number: 001-79552 Rev. *O

Page 38 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 14. Configuration Write and Read Timing Waveform

(a) Configuration Multiple Cycle - Write followed by Read Operation

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

Note: It is recommended to keep CFG# asserted during the configuration write or read operation

(b) Configuration Multiple Cycle - Back to Back Read Operation

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

Note: It is recommended to keep CFG# asserted during the configuration write or read operation

Document Number: 001-79552 Rev. *O

Page 39 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 15. Loopback TIming

Document Number: 001-79552 Rev. *O

Page 40 of 46

CY7C4022KV13/CY7C4042KV13

Switching Waveforms (continued)

Figure 16. Reset TImings

Document Number: 001-79552 Rev. *O

Page 41 of 46

CY7C4022KV13/CY7C4042KV13

Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local

sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page

at http://www.cypress.com/products

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office

closest to you, visit us at http://www.cypress.com/go/datasheet/offices.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

1066 CY7C4022KV13-106FCXC

CY7C4042KV13-106FCXC

933 CY7C4022KV13-933FCXC

CY7C4042KV13-933FCXC

CY7C4022KV13-933FCXI

001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free

Commercial

Industrial

001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free

Ordering Code Definitions

CY

7

C

40x2

K

V13 - XXX FC

X

Temperature Range: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: 361-ball Flip Chip BGA

Speed Grade: 106 = 1066 MHz or 933 = 933 MHz

VDD = 1.3 V

Die Revision: K = 65nm

Part Identifier: 4022 or 4042

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

Document Number: 001-79552 Rev. *O

Page 42 of 46

CY7C4022KV13/CY7C4042KV13

Package Diagram

Figure 17. 361-ball FCBGA (21 × 21 × 2.515 mm) FR0AA Package Outline, 001-70319

001-70319 *D

Document Number: 001-79552 Rev. *O

Page 43 of 46

CY7C4022KV13/CY7C4042KV13

Acronyms

Document Conventions

Table 20. Acronyms used in this document

Units of Measure

Table 21. Units of Measure

Symbol

Acronym

DDR

RTR

Description

Double Data Rate

Unit of Measure

Random Transaction Rate

Electronic Industries Alliance

Electromagnetic Interference

Flip-Chip Ball Grid Array

Input/Output

°C

MHz

µA

µs

degree Celsius

megahertz

microampere

microsecond

milliampere

millimeter

millisecond

millivolt

EIA

EMI

FCBGA

I/O

mA

mm

ms

mV

ns

JEDEC

JTAG

LMBU

LSB

Joint Electron Devices Engineering Council

Joint Test Action Group

Logical Multiple Bit Upset

Least Significant Bit

Logical Single Bit Upset

Most Significant Bit

nanosecond

ohm

LSBU

MSB

ODT

PLL



%

percent

On-Die Termination

Phase Locked Loop

Quad Data Rate

pF

V

picofarad

volt

QDR

SDR

SEL

W

watt

Single Data Rate

Single Event Latch-up

Soft Error Rate

SER

SRAM

TAP

Static Random Access Memory

Test Access Port

TCK

Test Clock

TDI

Test Data-In

TDO

TMS

Test Data-Out

Test Mode Select

Document Number: 001-79552 Rev. *O

Page 44 of 46

CY7C4022KV13/CY7C4042KV13

Document History Page

Document Title: CY7C4022KV13/CY7C4042KV13, 72-Mbit QDR™-IV XP SRAM

Document Number: 001-79552

Submission

Date

Orig. of

Change

Rev.

ECN

Description of Change

*G

*H

4283232

4414677

03/25/2014

06/20/2014

PRIT

Post to web.

Updated AC Test Load and Waveform:

Updated Figure 7 (Changed value of RQ resistor from 200  to 180 ).

Updated Switching Characteristics:

Added t_{ASH, CSH}, t_ISHparameters and their details.

t

Updated Note 20 and 23.

Completing Sunset Review.

*I

4504029

4575129

09/16/2014

11/20/2014

PRIT

Updated Switching Characteristics:

Updated Note 23.

Updated Package Diagram:

spec 001-70319 – Changed revision from *C to *D.

*J

Updated Functional Description:

Added “For a complete list of related resources, click here.” at the end.

Added Errata.

*K

*L

4710842

4951480

04/02/2015

10/07/2015

PRIT

Updated Operating Range:

Replaced “Case Temperature (T_C)” with “Ambient Temperature (T_A)” in column

heading.

Updated Logic Block Diagram – CY7C4042KV13.

Updated Switching Characteristics:

Changed maximum value of t_CKparameter from 1.875 ns to 3.333 ns for

1066 MHz speed bin.

Changed maximum value of t_CKparameter from 2.143 ns to 3.333 ns for

933 MHz speed bin.

Removed Errata.

Updated to new template.

*M

5157690

03/01/2016

PRIT

Added Industrial Temperature Range related information in all instances across

the document.

Updated Ordering Information:

Updated part numbers.

Updated to new template.

*N

*O

5381153

5843004

07/29/2016

08/03/2017

PRIT

AJU

Updated Switching Characteristics:

Added t_CFGAparameter and its details.

Updated Switching Waveforms:

Updated Figure 12, Figure 13, and Figure 14.

Updated to new template.

Completing Sunset Review.

Document Number: 001-79552 Rev. *O

Page 45 of 46

CY7C4022KV13/CY7C4042KV13

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-79552 Rev. *O

Revised August 3, 2017

Page 46 of 46


型号：	CY7C4022KV13-933FCXC
厂家：	CYPRESS
描述：	72-Mbit QDRâ¢-IV XP SRAM 静态存储器
文件：	总46页 (文件大小：1165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C4022KV13-933FCXC [CYPRESS]

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