CY7C404 [CYPRESS]
64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO; 64 ×4级联FIFO / 64 ×5级联FIFO
| 型号： | CY7C404 |
| 厂家： | 
CYPRESS |
| 描述： | 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO |
| 文件： | 总13页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C402
CY7C401/CY7C403
CY7C402/CY7C404
64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
Features
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
The devices accept 4- or 5-bit words at the data input (DI –
0
DI ) under the control of the shift in (SI) input. The stored
n
High-speed first-in first-out memory (FIFO)
words stack up at the output (DO – DO ) in the order they
0
n
• Processed with high-speed CMOS for optimum
speed/power
• 25-MHz data rates
• 50-ns bubble-through time—25 MHz
• Expandable in word width and/or length
• 5-volt power supply ± 10% tolerance, both commercial
and military
• Independent asynchronous inputs and outputs
• TTL-compatible interface
• Output enable function available on CY7C403 and
CY7C404
were entered. A read command on the shift out (SO) input
causes the next to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) signal acts
as a flag to indicate when the input is ready to accept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to provide a signal for cascad-
ing.
Parallel expansion for wider words is accomplished by logical-
ly ANDing the IR and OR signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The IR
pin of the receiving device is connected to the SO pin of the
sending device, and the OR pin of the sending device is con-
nected to the SI pin of the receiving device.
• Capable of withstanding greater than 2001V electro-
static discharge
• Pin compatible with MMI 67401A/67402A
Functional Description
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
Logic Block Diagram
Pin Configurations
DIP
DIP
(CY7C401) NC
(CY7C403) OE
IR
(CY7C402) NC
(CY7C404) OE
IR
SI
V
V
CC
1
2
3
4
5
6
7
8
16
15
14
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
CC
INPUT
SO
OR
DO
DO
SO
OR
DO
DO
DO
DO
DO
MR
CONTROL
WRITE POINTER
SI
SI
LOGIC
IR
CY7C402
CY7C404
CY7C401
DI
DI
13
CY7C403
12
0
0
OUTPUT
0
1
0
1
OE
DO
WRITE MULTIPLEXER
ENABLE
DI
1
DI
1
DI
DI
11 DO
2
2
2
3
2
3
4
DI
DI
DI
DI
0
1
2
3
10
9
DI
3
GND
DI
3
DI
4
GND
DO
MR
0
DATAIN
C401–2
MEMORY
ARRAY
DO
1
C401–4
DO
2
DATAIN
LCC
LCC
(DI
)
4
DO
3
(DO )
4
READ MULTIPLEXER
READ POINTER
MASTER
RESET
3 2 1 2019
18
3 2 1 2019
18
MR
OR
DO
DO
DO
NC
4
4
SI
SI
0
1
SO
OR
5
17 OR
16 DO
15 DO
5
6
7
8
17
16
15
14
0
1
2
DI
DI
DI
DI
DI
DI
DI
OUTPUT
CONTROL
LOGIC
0
1
2
CY7C401
CY7C403
CY7C402
CY7C404
6
7
8
0
1
2
2
3
NC
14
DO
DO
3
910111213
910111213
C401–1
C401–3
C401–5
Selection Guide
7C401/2–5
7C40X–10
7C40X–15
7C40X–25
Operating Frequency (MHz)
5
10
75
90
15
75
90
25
75
90
Maximum Operating
Current (mA)
Commercial
Military
75
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
March 1986 – Revised April 1995
•
408-943-2600
CY7C401/CY7C403
CY7C402/CY7C404
Output Current, into Outputs (LOW)............................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
Temperature
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ±10%
5V ±10%
[1]
Military
–55°C to +125°C
DC Input Voltage............................................ –3.0V to +7.0V
Power Dissipation..........................................................1.0W
[2]
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)
7C40X–10, 15, 25
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –4.0 mA
OH
Min.
Max.
Unit
V
V
V
V
V
V
2.4
V
V
OH
OL
IH
CC
CC
= Min., I = 8.0 mA
0.4
6.0
0.8
+10
OL
2.0
–3.0
–10
V
Input LOW Voltage
V
IL
I
Input Leakage Current
Input Diode Clamp Voltage
Output Leakage Current
GND ≤ V ≤ V
CC
µA
IX
[3]
CD
I
[3]
V
I
GND ≤ V
≤ V , V = 5.5V
–50
+50
µA
OZ
OUT
CC
CC
Output Disabled (CY7C403 and CY7C404)
[4]
I
I
Output Short Circuit Current
Power Supply Current
V
V
= Max., V = GND
OUT
–90
75
mA
mA
mA
OS
CC
CC
CC
= Max., I
= 0 mA
Commercial
Military
OUT
90
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
5
7
IN
A
V
= 4.5V
CC
pF
OUT
Notes:
1. A is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
T
3. The CMOS process does not provide a clamp diode. However, the FIFO is insensitive to –3V dc input levels and –5V undershoot pulses of less than 10 ns
(measured at 50% output).
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C401/CY7C403
CY7C402/CY7C404
AC Test Loads and Waveforms
ALL INPUT PULSES
R1 437Ω
R1 437Ω
3.0V
GND
5V
5V
OUTPUT
90%
10%
90%
10%
OUTPUT
R2
272Ω
R2
272Ω
30 pF
5 pF
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C401–6
C401–7
(a)
(b)
Equivalent to: THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
C401–8
[2, 6]
Switching Characteristics Over the Operating Range
7C401–5
7C402–5
[7]
7C40X–10
7C40X–15 7C40X–25
Test
Parameter
Description
Operating Frequency
SI HIGH Time
Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
f
Note 8
5
10
15
25
MHz
ns
O
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
20
45
0
20
30
0
20
25
0
11
20
0
PHSI
PLSI
SSI
SO LOW Time
ns
Data Set-Up to SI
Note 9
Note 9
ns
Data Hold from SI
60
40
30
20
ns
HSI
Delay, SI HIGH to IR LOW
Delay, SI LOW to IR HIGH
SO HIGH Time
75
75
40
45
35
40
21/22 ns
DLIR
DHIR
PHSO
PLSO
DLOR
DHOR
SOR
HSO
BT
28/30 ns
20
45
20
25
20
25
11
20
ns
SO LOW Time
ns
Delay, SO HIGH to OR LOW
Delay, SO LOW to OR HIGH
Data Set-Up to OR HIGH
Data Hold from SO LOW
Bubble-Through Time
Data Set-Up to IR
75
80
40
55
35
40
19/21 ns
34/37 ns
0
5
0
0
0
ns
5
5
5
ns
200
10
5
95
10
5
65
10
5
50/60 ns
Note 10
Note 10
5
ns
ns
ns
ns
ns
ns
SIR
Data Hold from IR
30
20
20
40
40
30
20
20
30
35
30
20
20
25
25
20
15
15
25
10
HIR
Input Ready Pulse HIGH
Output Ready Pulse HIGH
MR Pulse Width
PIR
POR
PMR
DSI
MR HIGH to SI HIGH
MR LOW to OR LOW
MR LOW to IR HIGH
MR LOW to Output LOW
Output Valid from OE LOW
Output High Z from OE HIGH
85
85
50
—
—
40
40
40
35
30
35
35
35
30
25
35
35
25
20
15
ns
ns
ns
ns
ns
DOR
DIR
Note 11
Note 12
LZMR
OOE
HZOE
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Loads and Waveforms.
7. Commercial/Military
8. I/fO > tPHSI + tDHIR, I/fO > tPHSO + tDHOR
9. tSSI and tHSI apply when memory is not full.
10.
tSIR and tHIR apply when memory is full, SI is high and minimum bubble-through (tBT) conditions exist.
11. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO.
12. HIGH-Z transitions are referenced to the steady-state VOH –500 mV and VOL +500 mV levels on the output. tHZOE is tested with 5-pF load capacitance as
in part (b) of AC Test Loads and Waveforms.
3
CY7C401/CY7C403
CY7C402/CY7C404
Application of the 7C403–25/7C404–25 at 25 MHz
Operational Description
Application of the CY7C403 or CY7C404 Cypress CMOS
FIFOs requires knowledge of characteristics that are not easily
specified in a datasheet, but which are necessary for reliable
operation under all conditions, so we will specify them here.
Concept
Unlike traditional FIFOs, these devices are designed using a
dual-port memory, read and write pointer, and control logic.
The read and write pointers are incremented by the SO and SI
respectively. The availability of an empty space to shift in data
is indicated by the IR signal, while the presence of data at the
output is indicated by the OR signal. The conventional concept
of bubble-through is absent. Instead, the delay for input data
to appear at the output is the time required to move a pointer
and propagate an OR signal. The output enable (OE) signal
provides the capability to OR tie multiple FIFOs together on
a common bus.
When an empty FIFO is filled with initial information at maxi-
mum “shift in” SI frequency, followed by immediate shifting out
of the data also at maximum “shift out” SO frequency, the de-
signer must be aware of a window of time which follows the
initial rising edge of the OR signal, during which time the SO
signal is not recognized. This condition exists only at
high-speed operation where more than one SO may be gen-
erated inside the prohibited window. This condition does not
inhibit the operation of the FIFO at full-frequency operation,
but rather delays the full 25-MHz operation until after the win-
dow has passed.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) signal. This causes the FIFO to enter an empty condition
signified by the OR signal being LOW at the same time the IR
There are several implementation techniques for managing
the window so that all SO signals are recognized:
signal is HIGH. In this condition, the data outputs (DO – DO )
will be in a LOW state.
1. The first involves delaying SO operation such that it does
not occur in the critical window. This can be accomplished
by causing a fixed delay of 40 ns “initiated by the SI signal
only when the FIFO is empty” to inhibit or gate the SO ac-
tivity. However, this requires that the SO operation be at
least temporarily synchronized with the input SI operation.
In synchronous applications this may well be possible and
a valid solution.
0
n
Shifting Data In
Data is shifted in on the rising edge of the SI signal. This loads
input data into the first word location of the FIFO. On the falling
edge of the SI signal, the write pointer is moved to the next
word position and the IR signal goes HIGH, indicating the
readiness to accept new data. If the FIFO is full, the IR will
remain LOW until a word of data is shifted out.
2. Another solution not uncommon in synchronous applica-
tions is to only begin shifting data out of the FIFO when it is
more than half full. This is a common method of FIFO ap-
plication, as earlier FIFOs could not be operated at maxi-
mum frequency when near full or empty. Although Cypress
FIFOs do not have this limitation, any system designed in
this manner will not encounter the window condition de-
scribed above.
Shifting Data Out
Data is shifted out of the FIFO on the falling edge of the SO
signal. This causes the internal read pointer to be advanced to
the next word location. If data is present, valid data will appear
on the outputs and the OR signal will go HIGH. If data is not
present, the OR signal will stay LOW indicating the FIFO is
empty. Upon the rising edge of SO, the OR signal goes LOW.
The data outputs of the FIFO should be sampled with
edge-sensitive type D flip-flops (or equivalent), using the SO
signal as the clock input to the flip-flop.
3. The window may also be managed by not allowing the first
SO signal to occur until the window in question has passed.
This can be accomplished by delaying the SO 40 ns from
the rising edge of the initial OR signal. This however in-
volves the requirement that this only occurs on the first oc-
currence of data being loaded into the FIFO from an empty
condition and therefore requires the knowledge of IR and
SI conditions as well as SO.
Bubble-Through
Two bubble-through conditions exist. The first is when the de-
vice is empty. After a word is shifted into an empty device, the
data propagates to the output. After a delay, the OR flag goes
HIGH, indicating valid data at the output.
4. Handshaking with the OR signal is a third method of avoid-
ing the window in question. With this technique the rising
edge of SO, or the fact that SO signal is HIGH, will cause
the OR signal to go LOW. The SO signal is not taken LOW
again, advancing the internal pointer to the next data, until
the OR signal goes LOW. This ensures that the SO pulse
that is initiated in the window will be automatically extended
long enough to be recognized.
The second bubble-through condition occurs when the device
is full. Shifting data out creates an empty location that propa-
gates to the input. After a delay, the IR flag goes HIGH. If the
SI signal is HIGH at this time, data on the input will be shifted
in.
5. There remains the decision as to what signal will be used
to latch the data from the output of the FIFO into the receiv-
ing source. The leading edge of the SO signal is most ap-
propriate because data is guaranteed to be stable prior to
and after the SO leading edge for each FIFO. This is a
solution for any number of FIFOs in parallel.
Possible Minimum Pulse Width Violation at the Boundary
Conditions
If the handshaking signals IR and OR are not properly used to
generate the SI and SO signals, it is possible to violate the
minimum (effective) SI and SO positive pulse widths at the full
and empty boundaries.
Any of the above solutions will ensure the correct operation of
a Cypress FIFO at 25 MHz. The specific implementation is left
to the designer and is dependent on the specific application
needs.
When this violation occurs, the operation of the FIFO is unpre-
dictable. It must then be reset, and all data is lost.
4
CY7C401/CY7C403
CY7C402/CY7C404
Switching Waveforms
Data In Timing Diagram
I/f
I/f
O
O
SHIFT IN
t
t
t
DHIR
PHSI
PLSI
INPUT READY
DATA IN
t
t
DLIR
HSI
t
SSI
C401–9
Data Out Timing Diagram
I/f
I/f
O
O
SHIFT OUT
t
t
t
DHOR
PHSO
PLSO
OUTPUT READY
DATA OUT
t
t
t
DLOR
HSO
SOR
C401–10
Bubble Through, Data Out To Data In Diagram
SHIFT OUT
SHIFT IN
t
BT
INPUT READY
t
PIR
DATA IN
t
t
HIR
SIR
C401–11
5
CY7C401/CY7C403
CY7C402/CY7C404
Switching Waveforms (continued)
Bubble Through, Data In To Data Out Diagram
SHIFTIN
SHIFT OUT
t
BT
t
POR
OUTPUT READY
t
SOR
DATA OUT
C401–12
Master Reset Timing Diagram
t
PMR
MASTER RESET
INPUT READY
t
DIR
t
DOR
OUTPUT READY
SHIFT IN
t
DSI
t
LZMR
DATA OUT
C401–13
Output Enable Timing Diagram
OUTPUT ENABLE
t
t
OOE
HZOE
DATA OUT
NOTE 10
C401–14
6
CY7C401/CY7C403
CY7C402/CY7C404
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
60
50
40
30
20
1.4
1.2
1.0
1.2
0.8
1.0
0.8
0.6
0.4
V
IN
=5.0V
V
V
IN
=5.5V
=5.0V
CC
V
CC
=5.0V
T =25°C
A
10
0
T =25°C
A
0.0
4.0
4.5
5.0
5.5
6.0
–55
25
125
0.0
1.0
2.0
3.0
4.0
AMBIENTTEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE
NORMALIZED FREQUENCY
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
140
120
100
80
1.2
1.1
1.2
1.0
1.0
0.9
60
40
0.8
V
=5.0V
CC
0.8
0.7
20
0
0.0
T =25°C
A
0.6
–55
4.0
4.5
5.0
5.5
6.0
25
125
1.0
2.0
3.0
4.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
TYPICAL FREQUENCY CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. FREQUENCY
CC
1.6
1.5
1.4
1.3
1.1
1.0
0.9
0.8
1.2
1.1
1.0
0.7
0.0
0
200 400
600 800 1000
0
5
10 15 20 25 30 35
FREQUENCY (MHz)
C401–15
CAPACITANCE (pF)
7
CY7C401/CY7C403
CY7C402/CY7C404
FIFO Expansion[13, 14, 15, 16, 17]
[18]
128 x 4 Application
SHIFT IN
SI
IR
OR
SO
SI
IR
OR
SO
OUTPUT READY
SHIFT OUT
INPUT READY
DI
0
DO
DI
0
DO
0
0
DI
DO
DI
DO
1
1
1
1
DATA OUT
DATA IN
DO
DO
2
DI
2
DI
2
2
DI
3
MR DO
DI
3
MR DO
3
3
MR
C401–16
[19]
192 x 12 Application
SHIFT OUT
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
DI
SO
OR
DO
DI
0
DO
DI
0
DO
0
0
0
0
DI
1
DO
DI
1
DO
DI
1
DO
1
1
1
DO
DO
DO
2
DI
2
DI
2
DI
2
2
2
DI MR DO
DI MR DO
DI MR DO
3 3
3
3
3
3
COMPOSITE
INPUT READY
COMPOSITE
OUTPUT READY
IR
SI
DI
SO
OR
IR
SI
DI
SO
OR
IR
SI
DI
SO
OR
DO
DO
DO
0
0
0
0
0
0
DI
1
DO
DI
1
DO
DI
1
DO
1
1
1
DO
DO
DO
2
DI
2
DI
2
DI
2
2
2
DI MR DO
DI MR DO
DI MR DO
3 3
3
3
3
3
SHIFT IN
IR
SI
DI
SO
OR
IR
SI
DI
SO
OR
IR
SI
DI
SO
OR
DO
DO
DO
0
0
0
0
0
0
DI
1
DO
DI
1
DO
DI
1
DO
1
1
1
DO
DO
DO
2
DI
2
DI
2
DI
2
2
2
DI MR DO
DI MR DO
DI MR DO
3 3
3
3
3
3
MR
C401–17
Notes:
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.
However, OR will remain LOW, indicating data at the output is not valid.
14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW
until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.
15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH
for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,
they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,
then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset
is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.
18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready
flags. This need is due to the variation of delays of the FIFOs.
8
CY7C401/CY7C403
CY7C402/CY7C404
Ordering Information
Speed
Package
Name
Operating
(MHz)
Ordering Code
CY7C401–5PC
Package Type
Range
5
P1
D2
P1
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
Commercial
Commercial
10
CY7C401–10DC
CY7C401–10PC
CY7C401–10DMB
CY7C401–10LMB
CY7C401–15DC
CY7C401–15PC
CY7C401–15DMB
CY7C401–15LMB
CY7C401–25DC
CY7C401–25PC
CY7C401–25DMB
CY7C401–25LMB
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
L61
D2
P1
Military
20-Pin Square Leadless Chip Carrier
16-Lead (300-Mil) CerDIP
15
25
Commercial
Military
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
L61
D2
P1
20-Pin Square Leadless Chip Carrier
16-Lead (300-Mil) CerDIP
Commercial
Military
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
L61
20-Pin Square Leadless Chip Carrier
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C402–5PC
Package Type
5
P3
D4
P3
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
Commercial
Commercial
10
CY7C402–10DC
CY7C402–10PC
CY7C402–10DMB
CY7C402–10LMB
CY7C402–15DC
CY7C402–15PC
CY7C402–15DMB
CY7C402–15LMB
CY7C402–25DC
CY7C402–25PC
CY7C402–25DMB
CY7C402–25LMB
20-Pin Square Leadless Chip Carrier
18-Lead (300-Mil) CerDIP
D4
L61
D4
P3
Military
20-Pin Square Leadless Chip Carrier
18-Lead (300-Mil) CerDIP
15
25
Commercial
Military
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
D4
L61
D4
P3
20-Pin Square Leadless Chip Carrier
18-Lead (300-Mil) CerDIP
Commercial
Military
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
D4
L61
20-Pin Square Leadless Chip Carrier
9
CY7C401/CY7C403
CY7C402/CY7C404
Ordering Information (continued)
Speed
(MHz)
Package
Operating
Ordering Code
CY7C403–10DC
CY7C403–10PC
CY7C403–10DMB
CY7C403–10LMB
CY7C403–15DC
CY7C403–15PC
CY7C403–15DMB
CY7C403–15LMB
CY7C403–25DC
CY7C403–25PC
CY7C403–25DMB
CY7C403–25LMB
Name
Package Type
16-Lead (300-Mil) CerDIP
Range
10
15
25
D2
Commercial
P1
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
Military
L61
D2
20-Pin Square Leadless Chip Carrier
16-Lead (300-Mil) CerDIP
Commercial
Military
P1
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
L61
D2
20-Pin Square Leadless Chip Carrier
16-Lead (300-Mil) CerDIP
Commercial
Military
P1
16-Lead (300-Mil) Molded DIP
16-Lead (300-Mil) CerDIP
D2
L61
20-Pin Square Leadless Chip Carrier
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C404–10DC
CY7C404–10PC
CY7C404–10DMB
CY7C404–10LMB
CY7C404–15DC
CY7C404–15PC
CY7C404–15DMB
CY7C404–15LMB
CY7C404–25DC
CY7C404–25PC
CY7C404–25DMB
CY7C404–25LMB
Package Type
18-Lead (300-Mil) CerDIP
10
15
25
D4
P3
Commercial
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
D4
L61
D4
P3
Military
20-Pin Square Leadless Chip Carrier
18-Lead (300-Mil) CerDIP
Commercial
Military
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
D4
L61
D4
P3
20-Pin Square Leadless Chip Carrier
18-Lead (300-Mil) CerDIP
Commercial
Military
18-Lead (300-Mil) Molded DIP
18-Lead (300-Mil) CerDIP
D4
L61
20-Pin Square Leadless Chip Carrier
10
CY7C401/CY7C403
CY7C402/CY7C404
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
Subgroups
1, 2, 3
Parameters
Subgroups
V
V
V
V
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
OH
O
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
OL
IH
PHSI
PLSI
SSI
Max.
IL
I
I
I
I
IX
HSI
OZ
OS
CC
DLIR
DHIR
PHSO
PLSO
DLOR
DHOR
SOR
HSO
BT
SIR
HIR
PIR
POR
PMR
DSI
DOR
DIR
LZMR
OOE
HZOE
Document #: 38–00040–H
11
CY7C401/CY7C403
CY7C402/CY7C404
Package Diagrams
16-Lead (300-Mil) CerDIP D2
MIL-STD-1835 D-2 Config.A
18-Lead (300-Mil) CerDIP D4
MIL-STD-1835 D-8 Config.A
20-Pin Square Leadless Chip Carrier L61
MIL-STD-1835 C–2A
12
CY7C401/CY7C403
CY7C402/CY7C404
Package Diagrams (continued)
16-Lead (300-Mil) Molded DIP P1
18-Lead (300-Mil) Molded DIP P3
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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