CY7C421-20VXC [CYPRESS]
256/512/1K/2K/4K x 9 Asynchronous FIFO; 五百一十二分之二百五十六/ 1K / 2K / 4K ×9异步FIFO
| 型号： | CY7C421-20VXC |
| 厂家： | 
CYPRESS |
| 描述： | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
| 文件： | 总25页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C419/21/25/29/33256/512/1K/2K/4K
x 9 Asynchronous FIFO
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
600-mil wide and 300-mil wide packages. They are, respec-
tively, 256, 512, 1,024, 2,048, and 4,096 words by 9-bits wide.
Features
• Asynchronous first-in first-out (FIFO) buffer memories
• 256 x 9 (CY7C419)
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are provided to prevent overrun and underrun. Three
additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to
another in parallel, thus eliminating the serial addition of
propagation delays, so that throughput is not reduced. Data is
steered in a similar manner.
• 512 x 9 (CY7C421)
• 1K x 9 (CY7C425)
• 2K x 9 (CY7C429)
• 4K x 9 (CY7C433)
• Dual-ported RAM cell
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W) signal is LOW. Read occurs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R is HIGH.
• High-speed 50.0-MHz read/write independent of
depth/width
• Low operating power: ICC = 35 mA
• Empty and Full flags (Half Full flag in standalone)
• TTL compatible
A Half Full (HF) output flag is provided that is valid in the
standalone and width expansion configurations. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it will be
activated.
• Retransmit in standalone
• Expandable in width
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
• Pb-Free Packages Available
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the data.
• Pin compatible and functionally equivalent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated
using an advanced 0.65-micron P-well CMOS technology.
Input ESD protection is greater than 2000V and latch-up is
prevented by careful layout and guard rings.
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
Cypress Semiconductor Corporation
Document #: 38-06001 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 30, 2005
CY7C419/21/25/29/33
DATAINPUTS
(D –D
Logic Block Diagram
Pin Configurations
)
8
0
DIP
Top View
PLCC/LCC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
V
cc
W
D
D
4
D
5
D
6
4
3
2
1
323130
29
8
3
2
1
0
D
2
D
6
5
WRITE
W
D
D
D
D
RAMARRAY
256x 9
D
D
6
7
8
9
10
11
12
13
28
27
CONTROL
7
1
25
24
23
22
21
NC
D
0
512x 9
D
7
7C419
XI
FF
FL/RT
MR
EF
WRITE
POINTER
1024x 9
2048x 9
4096x 9
READ
POINTER
26
25
24
23
22
21
7C419
7C421/5/9
7C433
FL/RT
MR
EF
7C420/1
7C424/5
7C428/9
7C432/3
XI
FF
Q
0
Q
1
Q
0
Q
1
XO/HF
20
19
18
17
16
15
XO/HF
NC
Q
2
Q
7
Q
7
Q
6
Q
6
Q
2
14 151617 181920
THREE-
Q
3
Q
8
Q
5
STATE
Q
4
BUFFERS
R
GND
TQFP
Top View
DATA OUTPUTS
(Q –Q )
0
8
MR
RESET
LOGIC
FL/RT
READ
CONTROL
R
32 3130 29 28 27 26 25
FLAG
EF
FF
D
LOGIC
7
D
D
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
1
0
FL/RT
NC
NC
7C419
7C421/5/9
7C433
NC
XI
NC
EXPANSION
LOGIC
XI
MR
EF
XO/HF
FF
Q
0
XO/HF
Q
1
Q
7
9
10 11 12 13 14 15 16
Selection Guide
256 x 9
7C419–10 7C419–15
7C419–30 7C419–40
7C420–40 7C420–65
512 x 9 (600-mil only)
512 x 9
7C420–20 7C420–25
7C421–10 7C421–15 7C421–20 7C421–25 7C421–30 7C421–40 7C421–65
7C424–20 7C424–25 7C424–30 7C424–40 7C424–65
1K x 9 (600-mil only)
1K x 9
7C425–10 7C425–15 7C425–20 7C425–25 7C425–30 7C425–40 7C425–65
2K x 9 (600-mil only)
2K x 9
7C428–20
7C429–10 7C429–15 7C429–20 7C429–25 7C429–30 7C429–40 7C429–65
7C432–25 7C432–40
7C433–10 7C433–15 7C433–20 7C433–25 7C433–30 7C433–40 7C433–65
7C428–65
4K x 9 (600-mil only)
4K x 9
Frequency (MHz)
50
10
35
40
15
35
33.3
20
28.5
25
25
30
35
20
40
35
12.5
65
Maximum Access Time (ns)
ICC1 (mA)
35
35
35
Maximum Rating[1]
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Power Dissipation.......................................................... 1.0W
Output Current, into Outputs (LOW)............................ 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Static Discharge Voltage............................................>2000V
(per MIL–STD–883, Method 3015)
Latch-Up Current.....................................................>200 mA
Note:
1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.
Document #: 38-06001 Rev. *B
Page 2 of 25
CY7C419/21/25/29/33
Operating Range
Range
Commercial
Industrial
Military
Ambient Temperature[2]
VCC
0°C to + 70°C
–40°C to +85°C
–55°C to +125°C
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
7C419–10, 15, 30, 40
7C420/1–10, 15, 20, 25, 30, 40, 65
7C424/5–10, 15, 20, 25, 30, 40, 65
7C428/9–10, 15, 20, 25, 30, 40, 65
7C432/3–10, 15, 20, 25, 30, 40, 65
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Unit
V
2.4
VOL
0.4
VCC
VCC
0.8
V
VIH
Com’l
Mil/Ind
2.0
2.2
V
VIL
IIX
Input LOW Voltage
Note 4
–10
V
Input Leakage Current
Output Leakage Current
Output Short Circuit Current[5]
GND < VI < VCC
+10
+10
–90
µA
µA
mA
IOZ
IOS
R > VIH, GND < VO < VCC
VCC = Max., VOUT = GND
–10
Electrical Characteristics Over the Operating Range[3] (continued)
7C419–10
7C419–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C420–25
7C421–25
7C424–25
7C425–25
7C421–10
7C425–10
7C429–10
7C433–10
7C421–15
7C425–15
7C429–15
7C433–15
7C429–25
7C432–25
7C433–25
7C433–20
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l
85
65
55
90
50
80
mA
Mil/Ind
100
ICC1
Operating Current
Standby Current
VCC = Max.,
Com’l
35
35
35
35
mA
I
OUT = 0 mA
F = 20 MHz
ISB1
All Inputs =
Com’l
Mil/Ind
Com’l
Mil/Ind
10
5
10
15
5
10
15
5
10
15
5
mA
mA
VIH Min.
ISB2
Power-Down Current All Inputs >
VCC –0.2V
8
8
8
Notes:
2. T is the “instant on” case temperature.
A
3. See the last page of this specification for Group A subgroup testing information.
4. V (Min.) = –2.0V for pulse durations of less than 20 ns.
IL
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-06001 Rev. *B
Page 3 of 25
CY7C419/21/25/29/33
Electrical Characteristics Over the Operating Range[3] (continued)
7C419–30
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
7C429–40
7C432–40
7C433–40
7C433–65
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max.
Unit
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l
40
75
35
70
35
65
mA
Mil/Ind
ICC1
Operating Current
VCC = Max.,
Com’l
35
35
35
mA
I
OUT = 0 mA
F = 20 MHz
ISB1
ISB2
Standby Current
All Inputs =
Com’l
Mil
10
15
5
10
15
5
10
15
5
mA
mA
VIH Min.
Power-Down Current
All Inputs >
VCC –0.2V
Com’l
Mil
8
8
8
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 4.5V
6
6
COUT
pF
AC Test Loads and Waveforms
R1 500 Ω
R1 500 Ω
5V
5V
OUTPUT
ALL INPUT PULSES
3.0V
GND
OUTPUT
90%
90%
10%
10%
R2
333Ω
R2
333Ω
30 pF
5 pF
≤ 3 ns
≤ 3 ns
INCLUDING
JIGAND
INCLUDING
JIGAND
SCOPE
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06001 Rev. *B
Page 4 of 25
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8]
7C419–10
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C420–25
7C421–25
7C424–25
7C425–25
7C421–10
7C425–10
7C429–10
7C433–10
7C429–25
7C432–25
7C433–25
7C433–20
Parameter
Description
Read Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC
tA
tRR
tPR
20
25
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time
10
15
20
15
25
Read Recovery Time
Read Pulse Width
10
10
3
10
15
3
10
20
3
10
25
3
[6,9]
tLZR
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
[9,10]
tDVR
5
5
5
5
[6,9,10]
tHZR
15
15
18
tWC
tPW
20
10
5
25
15
5
30
20
5
35
25
5
Write Pulse Width
[6,9]
tHWZ
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
tWR
10
6
10
8
10
12
0
10
15
0
tSD
tHD
Data Hold Time
0
0
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
MR Cycle Time
20
10
10
10
10
20
10
10
25
15
10
15
15
25
15
10
30
20
10
20
20
30
20
10
35
25
10
25
25
35
25
10
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
tRTR
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified I /I and 30 pF load
OL OH
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
9. t
transition is measured at +200 mV from V and –200 mV from V . t
transition is measured at the 1.5V level. t
and t transition is measured
LZR
HZR
OL
OH DVR
HWZ
at ±100 mV from the steady state.
10. t and t use capacitance loading as in part (b) of AC Test Load and Waveforms.
HZR
DVR
Document #: 38-06001 Rev. *B
Page 5 of 25
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8] (continued)
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
7C419–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C420–25
7C421–25
7C424–25
7C425–25
7C421–15
7C425–15
7C429–15
7C433–15
7C429–25
7C432–25
7C433–25
7C433–20
Parameter
tEFL
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
MR to EF LOW
MR to HF HIGH
MR to FF HIGH
20
20
20
10
10
10
10
10
10
10
25
25
25
15
15
15
15
15
15
15
30
30
30
20
20
20
20
20
20
20
35
35
35
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH
tFFH
tREF
Read LOW to EF LOW
tRFF
Read HIGH to FF HIGH
tWEF
tWFF
tWHF
tRHF
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
tRAE
Effective Read from Write HIGH
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
tRPE
10
10
15
15
20
20
25
25
tWAF
tWPF
tXOL
10
15
20
25
10
10
15
15
20
20
25
25
tXOH
Document #: 38-06001 Rev. *B
Page 6 of 25
CY7C419/21/25/29/33
Switching Characteristics Over the Operating Range[7, 8] (continued)
7C419–30
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
7C429–40
7C432–40
7C433–40
7C433–65
Parameter
tRC
Description
Read Cycle Time
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
50
80
tA
Access Time
30
40
65
20
tRR
tPR
tLZR
Read Recovery Time
10
30
3
10
40
3
15
65
3
Read Pulse Width
[6,9]
Read LOW to Low Z
[9,10]
tDVR
tHZR
tWC
tPW
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
5
5
5
[6,9,10]
20
20
40
30
5
50
40
5
80
65
5
Write Pulse Width
[6,9]
tHWZ
tWR
Write HIGH to Low Z
Write Recovery Time
10
18
0
10
20
0
15
30
0
tSD
Data Set-Up Time
tHD
Data Hold Time
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
MR Cycle Time
40
30
10
30
30
40
30
10
50
40
10
40
40
50
40
10
80
65
15
65
65
80
65
15
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
40
40
40
30
30
30
30
30
30
30
50
50
50
35
35
35
35
35
35
35
80
80
80
60
60
60
60
60
60
60
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
MR to HF HIGH
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width After FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
30
30
40
40
65
65
30
35
60
30
30
40
40
65
65
Document #: 38-06001 Rev. *B
Page 7 of 25
CY7C419/21/25/29/33
Switching Waveforms
Asynchronous Read and Write
t
t
PR
RC
t
t
RR
t
A
A
R
t
t
t
HZR
LZR
DVR
DATA VALID
DATA VALID
Q –Q
0
8
t
WC
t
t
WR
PW
W
t
t
HD
SD
DATA VALID
DATA VALID
D –D
0
8
Master Reset
[12]
t
MRSC
t
PMR
MR
[11]
R, W
t
RPW
t
WPW
t
RMR
t
EFL
EF
t
HFH
HF
FF
t
FFH
Half-full Flag
HALF FULL
HALF FULL+1
HALF FULL
W
R
t
RHF
t
WHF
HF
Notes:
11. W and R ≥ V around the rising edge of MR.
IH
12. t
= t
+ t
.
MRSC
PMR
RMR
Document #: 38-06001 Rev. *B
Page 8 of 25
CY7C419/21/25/29/33
Switching Waveforms (continued)
Last Write to First Read Full Flag
ADDITIONAL
READS
LAST WRITE
R
FIRST READ
FIRST WRITE
W
t
t
RFF
WFF
FF
Last Read to First Write Empty Flag
ADDITIONAL
WRITES
LAST READ
W
FIRST WRITE
FIRST READ
R
t
t
WEF
REF
EF
t
A
VALID
VALID
DATA OUT
Retransmit[13]
[14]
RTC
t
t
PRT
FL/RT
R,W
t
RTR
Notes:
13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
.
RTC
14. t
= t
+ t
.
RTC
PRT
RTR
Document #: 38-06001 Rev. *B
Page 9 of 25
CY7C419/21/25/29/33
Switching Waveforms (continued)
Empty Flag and Read Data Flow-through Mode
DATA IN
W
t
RAE
R
t
RPE
t
REF
EF
t
WEF
t
A
t
HWZ
DATA OUT
DATA VALID
Full Flag and Write Data Flow-through Mode
R
t
t
WAF
WPF
W
t
t
WFF
RFF
FF
t
HD
DATA IN
DATA VALID
t
A
t
SD
DATA OUT
DATA VALID
Document #: 38-06001 Rev. *B
Page 10 of 25
CY7C419/21/25/29/33
Switching Waveforms (continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
W
t
WR
t
t
XOH
XOL
[15]
XO (XI )
1
2
t
t
HD
HD
t
t
SD
SD
DATA VALID
DATA VALID
D –D
0
8
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
R
t
RR
t
t
XOH
XOL
[15]
XO (XI )
1
2
t
HZR
t
DVR
t
t
DVR
LZR
DATA
VALID
DATA
VALID
Q –Q
0
8
t
A
t
A
Note:
15. Expansion Out of device 1 (XO ) is connected to Expansion In of device 2 (XI ).
1
2
Resetting the FIFO
Architecture
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH tRPW/tWPW before and tRMR after the rising
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of
dual-port RAM cells), a read pointer, a write pointer, control
signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and
Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is
necessary to achieve truly asynchronous operation of the
inputs and outputs. A second benefit is that the time required
to increment the read and write pointers is much less than the
time that would be required for data propagation through the
memory, which would be the case if the memory were imple-
mented using the conventional register array architecture.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW tWHF after the falling edge of W following the FIFO
actually being Half Full. Therefore, the HF is active once the
Document #: 38-06001 Rev. *B
Page 11 of 25
CY7C419/21/25/29/33
FIFO is filled to half its capacity plus one word. HF will remain
LOW while less than one half of total memory is available for
writing. The LOW-to-HIGH transition of HF occurs tRHF after
the rising edge of R when the FIFO goes from half full +1 to
half full. HF is available in standalone and width expansion
modes. FF goes LOW tWFF after the falling edge of W, during
the cycle in which the last available location is filled. Internal
logic prevents overrunning a full FIFO. Writes to a full FIFO are
ignored and the write pointer is not incremented. FF goes
HIGH tRFF after a read from a full FIFO.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle,
Expansion Out (XO) of one device is connected to Expansion
In (XI) of the next device, with XO of the last device connected
to XI of the first device. In the depth expansion mode the First
Load (FL) input, when grounded, indicates that this part is the
first to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and pulsed
LOW again when the last physical location is read. Only one
FIFO is enabled for read and one for write at any given time.
All other devices are in standby.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q0–Q8) are in a high-impedance condition
between read operations (R HIGH), when the FIFO is empty,
or when the FIFO is not the active device in the depth
expansion mode.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
of word widths in increments of 9. When expanding in depth,
a composite FF must be created by ORing the FFs together.
Likewise, a composite EF is created by ORing the EFs
together. HF and RT functions are not available in depth
expansion mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high-impedance state and remain
such until a write is performed. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read tWEF after a valid write.
Use of the Empty and Full Flags
In order to achieve the maximum frequency, the flags must be
valid at the beginning of the next cycle. However, because
they can be updated by either edge of the read of write signal,
they must be valid by one-half of a cycle. Cypress FIFOs meet
this requirement; some competitors’ FIFOs do not.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on
RT resets the internal read pointer to the first physical location
of the FIFO. R and W must both be HIGH while and tRTR after
retransmit is LOW. With every read cycle after retransmit,
previously accessed data as well as not previously accessed
data is read and the read pointer is incremented until it is equal
to the write pointer. Full, Half Full, and Empty flags are
governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT are transmitted also.
The reason why the flags are required to be valid by the next
cycle is fairly complex. It has to do with the “effective pulse
width violation” phenomenon, which can occur at the full and
empty boundary conditions, if the flags are not properly used.
The empty flag must be used to prevent reading from an empty
FIFO and the full flag must be used to prevent writing into a full
FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are
ignored by the FIFO, and nothing happens. Next, a single word
is written into the FIFO, with a signal that is asynchronous to
the read signal. The (internal) state machine in the FIFO goes
from empty to empty+1. However, it does this asynchronously
with respect to the read signal, so that it cannot be determined
what the effective pulse width of the read signal is, because
the state machine does not look at the read signal until it goes
to the empty+1 state. In a similar manner, the minimum write
pulse width may be violated by attempting to write into a full
FIFO, and asynchronously performing a read. The empty and
full flags are used to avoid these effective pulse width viola-
tions, but in order to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
Up to the full depth of the FIFO can be repeatedly retrans-
mitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can
be expanded in width to provide word widths greater than nine
in increments of nine. During width expansion mode, all control
line inputs are common to all devices, and flag outputs from
any device can be monitored.
Document #: 38-06001 Rev. *B
Page 12 of 25
CY7C419/21/25/29/33
XO
R
W
D
FF
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
9
9
Q
V
CC
XI
XO
FULL
FF
EMPTY
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
XI
XO
*
FF
EF
FL
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
9
MR
XI
* FIRSTDEVICE
Figure 1. Depth Expansion
Document #: 38-06001 Rev. *B
Page 13 of 25
CY7C419/21/25/29/33
Ordering Information
Speed
(ns)
Package
Type
Operating
Range
Ordering Code
Package Type
10
CY7C419–10AC
CY7C419–10JC
CY7C419–10JXC
CY7C419–10PC
CY7C419–10VC
CY7C419–15AC
CY7C419–15JC
CY7C419–15JXC
CY7C419–15VC
CY7C419-15VXC
CY7C419–15JI
CY7C419–30JC
CY7C419–40AC
CY7C419–40JC
A32
J65
J65
P21
V21
A32
J65
J65
V21
V21
J65
J65
A32
J65
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carriers
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
15
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded SOJ
Commercial
28-Lead (300-Mil) Pb-Free Molded SOJ
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
Industrial
30
40
Commercial
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C420–25PC
Package Type
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
25
P15
P15
P15
Commercial
40
CY7C420–40PC
CY7C420–65PC
65
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C421–10AC
Package Type
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carriers
28-Lead (300-Mil) Molded DIP
10
A32
J65
J65
P21
V21
A32
A32
J65
J65
V21
D22
L55
J65
J65
P21
V21
V21
J65
Commercial
CY7C421–10JC
CY7C421–10JXC
CY7C421–10PC
CY7C421–10VC
CY7C421–15AC
CY7C421–15AXC
CY7C421–15JC
CY7C421–15JI
28-Lead (300-Mil) Molded SOJ
15
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded SOJ
Commercial
Industrial
Military
CY7C421–15VI
CY7C421–15DMB
CY7C421–15LMB
CY7C421–20JC
CY7C421–20JXC
CY7C421–20PC
CY7C421–20VC
CY7C421–20VXC
CY7C421–20JI
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carriers
28-Lead (300-Mil) Molded DIP
20
Commercial
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) Pb-Free Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
Document #: 38-06001 Rev. *B
Page 14 of 25
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C421–25JC
Package Type
25
J65
P21
V21
J65
P21
D22
J65
P21
J65
D22
L55
J65
P21
V21
J65
J65
P21
V21
J65
D22
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
Commercial
CY7C421–25PC
CY7C421–25VC
CY7C421–25JI
CY7C421–25PI
CY7C421–25DMB
CY7C421–30JC
CY7C421–30PC
CY7C421–30JI
CY7C421–30DMB
CY7C421–30LMB
CY7C421–40JC
CY7C421–40PC
CY7C421–40VC
CY7C421–40JI
CY7C421–65JC
CY7C421–65PC
CY7C421–65VC
CY7C421–65JI
CY7C421–65DMB
Industrial
Military
30
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) CerDIP
Commercial
Industrial
Military
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) CerDIP
40
65
Commercial
Industrial
Commercial
Industrial
Military
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C424–40PC
CY7C424–65PC
Package Type
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
40
P15
P15
Commercial
Commercial
65
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C425–10AC
Package Type
10
A32
A32
J65
J65
P21
V21
J65
J65
P21
D22
L55
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
CY7C425–10AXC
CY7C425–10JC
CY7C425–10JXC
CY7C425–10PC
CY7C425–10VC
CY7C425–15JC
CY7C425–15JXC
CY7C425–15PC
CY7C425–15DMB
CY7C425–15LMB
28-Lead (300-Mil) Molded SOJ
15
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Document #: 38-06001 Rev. *B
Page 15 of 25
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C425–20JC
Package Type
20
J65
J65
P21
V21
V21
J65
P21
J65
V21
D22
L55
J65
P21
V21
V21
J65
P21
V21
J65
J65
P21
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
CY7C425–20JXC
CY7C425–20PC
CY7C425–20VC
CY7C425–20VXC
CY7C425–25JC
CY7C425–25PC
CY7C425–25JI
CY7C425–25VI
CY7C425–25DMB
CY7C425–25LMB
CY7C425–30JC
CY7C425–30PC
CY7C425–30VC
CY7C425–30VI
CY7C425–40JC
CY7C425–40PC
CY7C425–40VC
CY7C425–40JI
CY7C425–65JC
CY7C425–65PC
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) Pb-Free Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
25
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
30
40
65
Commercial
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
Industrial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Industrial
Commercial
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C428–20PC
Package Type
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) CerDIP
20
P15
D16
P15
Commercial
Military
25
CY7C428–25DMB
CY7C428–65PC
65
28-Lead (600-Mil) Molded DIP
Commercial
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C429–10AC
Package Type
10
A32
A32
J65
P21
J65
J65
J65
D22
L55
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
CY7C429–10AXC
CY7C429–10JC
CY7C429–10PC
CY7C429–15JC
CY7C429–15JXC
CY7C429–15JI
15
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) CerDIP
Commercial
Industrial
Military
CY7C429–15DMB
CY7C429–15LMB
32-Pin Rectangular Leadless Chip Carrier
Document #: 38-06001 Rev. *B
Page 16 of 25
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C429–20JC
Package Type
20
J65
J65
P21
V21
D22
J65
P21
V21
J65
D22
L55
J65
P21
V21
D22
A32
J65
P21
J65
P21
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
Commercial
CY7C429–20JXC
CY7C429–20PC
CY7C429–20VC
CY7C429–20DMB
CY7C429–25JC
CY7C429–25PC
CY7C429–25VC
CY7C429–25JI
Military
25
30
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) CerDIP
Commercial
Industrial
Military
CY7C429–25DMB
CY7C429–25LMB
CY7C429–30JC
CY7C429–30PC
CY7C429–30VC
CY7C429–30DMB
CY7C429–40AC
CY7C429–40JC
CY7C429–40PC
CY7C429–65JC
CY7C429–65PC
CY7C429–65JI
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
Commercial
Military
40
65
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C432–25PC
CY7C432–40PC
Package Type
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Molded DIP
25
P15
P15
Commercial
Commercial
40
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C433–10AC
Package Type
10
A32
A32
J65
J65
P21
V21
A32
J65
J65
J65
P21
D22
L55
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
CY7C433–10AXC
CY7C433–10JC
CY7C433–10JXC
CY7C433–10PC
CY7C433–10VC
CY7C433–15AC
CY7C433–15JC
CY7C433–15JXC
CY7C433–15JI
28-Lead (300-Mil) Molded SOJ
15
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
Industrial
Military
CY7C433–15PI
CY7C433–15DMB
CY7C433–15LMB
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Document #: 38-06001 Rev. *B
Page 17 of 25
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C433–20AC
Package Type
20
A32
A32
J65
J65
P21
J65
P21
V21
J65
J65
P21
J65
P21
D22
L55
J65
P21
V21
J65
J65
P21
32-Pin Thin Plastic Quad Flatpack
32-Pin Pb-Free Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Pb-Free Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
CY7C433–20AXC
CY7C433–20JC
CY7C433–20JXC
CY7C433–20PC
CY7C433–25JC
CY7C433–25PC
CY7C433–25VC
CY7C433–25JI
CY7C433–30JC
CY7C433–30PC
CY7C433–30JI
CY7C433–30PI
CY7C433–30DMB
CY7C433–30LMB
CY7C433–40JC
CY7C433–40PC
CY7C433–40VC
CY7C433–40JI
CY7C433–65JC
CY7C433–65PC
25
30
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Industrial
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Industrial
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
40
65
Commercial
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Industrial
Commercial
Document #: 38-06001 Rev. *B
Page 18 of 25
CY7C419/21/25/29/33
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameters
VOH
Subgroups
1, 2, 3
Parameters
tRC
Subgroups
9, 10, 11
VOL
VIH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tA
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
tRR
VIL Max.
IIX
tPR
tDVR
tWC
ICC
ICC1
ISB1
ISB2
IOS
tPW
tWR
tSD
tHD
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
Document #: 38-06001 Rev. *B
Page 19 of 25
CY7C419/21/25/29/33
Package Diagrams
32-Lead Thin Plastic Quad Flat Pack A32
32-Lead Pb-Free Thin Plastic Quad Flat Pack A32
51-85063-*B
28-Lead (600-Mil) CerDIP D16
MIL-STD-1835 D-10 Config. A
51-80019-**
Document #: 38-06001 Rev. *B
Page 20 of 25
CY7C419/21/25/29/33
Package Diagrams (continued)
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032-**
Document #: 38-06001 Rev. *B
Page 21 of 25
CY7C419/21/25/29/33
Package Diagrams (continued)
32-Lead Plastic Leaded Chip Carrier J65
32-Lead Pb-Free Plastic Leaded Chip Carrier J65
51-85002-*B
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068-**
Document #: 38-06001 Rev. *B
Page 22 of 25
CY7C419/21/25/29/33
Package Diagrams (continued)
28-Lead (600-Mil) Molded DIP P15
51-85017-*A
28-Lead (300-Mil) PDIP P21
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
Document #: 38-06001 Rev. *B
Page 23 of 25
CY7C419/21/25/29/33
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
28-Lead (300-Mil) Pb-Free Molded SOJ V21
MIN.
DIMENSIONS IN INCHES
MAX.
PIN 1 ID
DETAIL
A
EXTERNAL LEAD DESIGN
14
1
0.291
0.330
0.300
0.350
0.026
0.032
0.013
15
28
0.014
0.020
0.019
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06001 Rev. *B
Page 24 of 25
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C419/21/25/29/33
Document History Page
Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433 256/512/1K/2K/4Kx9 Asynchronous FIFO
Document Number: 38-06001
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
106462
122332
383597
07/11/01
12/30/02
SZV
RBI
Change from Spec Number: 38-00079 to 38-06001
Added power up requirements to maximum ratings information.
*A
*B
See ECN PCX
Added Pb-Free Logo
Added to Part-Ordering Information:
CY7C419–10JXC, CY7C419–15JXC, CY7C419-15VXC,
CY7C421–10JXC, CY7C421–15AXC, CY7C421–20JXC,
CY7C421–20VXC, CY7C425–10AXC, CY7C425–10JXC,
CY7C425–15JXC, CY7C425–20JXC, CY7C425–20VXC,
CY7C429–10AXC, CY7C429–15JXC, CY7C429–20JXC,
CY7C433–10AXC, CY7C433–10JXC, CY7C433–15JXC,
CY7C433–20AXC, CY7C433–20JXC
Document #: 38-06001 Rev. *B
Page 25 of 25
相关型号：
©2020 ICPDF网 联系我们和版权申明