CY7C4251-10JCR [CYPRESS]
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| 型号： | CY7C4251-10JCR |
| 厂家： | 
CYPRESS |
| 描述： | 暂无描述 存储 内存集成电路 先进先出芯片 时钟 |
| 文件： | 总18页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
Functional Description
• High-speed, low-power, First-In, First-Out (FIFO)
memories
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
• Low power (ICC = 35 mA)
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
• 32-pin PLCC
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
D
0- 8
Logic Block Diagram
Pin Configuration
PLCC
Top View
INPUT
REGISTER
4
3
2
1 323130
29
28
D
RS
WEN1
1
5
6
7
8
9
D
0
WCLK WEN1 WEN2/LD
PAF
PAE
27 WCLK
26
25
24
23
22
21
WEN2/LD
FLAG
PROGRAM
REGISTER
GND
REN1
RCLK
REN2
OE
V
CC
Q
Q
Q
Q
10
11
12
13
8
7
6
5
Write
CONTROL
EF
14151617181920
PAE
PAF
FF
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
TQFP
Top View
Write
POINTER
Read
POINTER
32 31 30 29 28 27 26 25
8k x 9
1
2
3
4
5
6
7
8
24
WEN1
D
D
1
0
23
WCLK
WEN2/LD
22
21
20
19
PAF
PAE
RESET
LOGIC
RS
V
CC
Q
Q
GND
8
7
REN1
RCLK
REN2
Q
6
Q
5
THREE-STATE
OUTPUTREGISTER
18
17
Read
CONTROL
9 10 11 1213 14 15 16
OE
Q
0- 8
RCLK REN1 REN2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06016 Rev. *A
Revised March 6, 2202
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Selection Guide
-10
100
8
-15
66.7
10
15
4
-25
40
15
25
6
Unit
MHz
ns
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
10
3
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
0.5
8
1
1
ns
10
35
40
15
35
40
ns
Active Power Supply Current
Commercial
Industrial
35
40
ICC1
CY7C4421
CY7C4201
256 × 9
CY7C4211
CY7C4221
CY7C4231
2K × 9
CY7C4241
CY7C4251
Density
64 × 9
512 × 9
1K × 9
4K × 9
8K × 9
active. REN1 and REN2 must set up tENS before RCLK for it
to be a valid Read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid Write function.
Functional Description
The CY7C42X1 providesfour statuspins: Empty, Full, AlmostEmpty,
Almost Full. The Almost Empty/Almost Full flags are programmable
to single word granularity. The programmable flags default to
Empty – 7 and Full – 7.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
The flags are synchronous, i.e., they change state relative to
either the Read clock (RCLK) or the Write clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full, and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle.
after tOE.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid Read on its Q0–8 outputs
even after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only Write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every Write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going Read operation.
All configurations are fabricated using advanced 0.65µ N-Well
CMOS technology. Input ESD protection is greater than 2001V, and
latch-up is prevented by the use of guard rings.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a
Read pointer, a Write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two Write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
Write enable pin.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0–8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, a falling edge must occur on RS and the
user must not read or Write while RS is LOW. All flags are
guaranteed to be valid tRSF after RS is taken LOW.
If the FIFO is configured to have two Write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load
(WEN2/LD) is HIGH, data can be loaded into the input register
and RAM array on the LOW-to-HIGH transition of every Write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of any on-going Read operation.
Programming
FIFO Operation
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0–8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q0–8 outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are
Document #: 38-06016 Rev. *A
Page 2 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full offset
LSB register, and full offset MSB register, respectively, when
WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the registers sizes and default values for the various device
types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal
Read and Write operation. The next time WEN2/LD is brought
LOW, a Write operation stores data in the next offset register
in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK Read register
contents to the data outputs. Writes and reads should not be
preformed simultaneously on the offset registers.
64 ×9
256 ×9
512 ×9
1K ×9
0
0
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
6 5
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
0
0
1
1
(MSB)
0
(MSB)
00
6 5
7
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
1
1
(MSB)
0
(MSB)
00
2K ×9
4K ×9
8K ×9
0
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
0
0
2
3
4
(MSB)
0000
(MSB)
00000
(MSB)
000
7
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
2
3
4
(MSB)
000
(MSB)
0000
(MSB)
00000
Figure 1. Offset Register Location and Default Values
Document #: 38-06016 Rev. *A
Page 3 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Programmable Flag (PAE, PAF) Operation
(256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m),
CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251
(8K – m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the Read
and Write pointers.
Table 1. Writing the Offset Registers
LD WEN WCLK[1]
Selection
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK when
the FIFO contains (n + 1) or greater unread words.
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421. (64 – m), CY7C4201
Table 2. Status Flags
Number of Words in FIFO
CY7C4421
CY7C4201
CY7C4211
FF
H
H
H
H
H
L
PAF
H
PAE
L
EF
L
0
0
0
1 to n[2]
1 to n[2]
1 to n[2]
H
L
H
H
H
H
H
(n + 1) to 32
33 to (64 – (m + 1))
(64 – m)[3] to 63
64
(n + 1) to 128
129 to (256 – (m + 1))
(256 – m)[3] to 255
256
(n + 1) to 256
257 to (512 – (m + 1))
(512 – m)[3] to 511
512
H
H
H
H
L
H
L
H
Number of Words in FIFO
CY7C4231 CY7C4241
CY7C4221
0
1 to n[2]
CY7C4251
FF PAF PAE
EF
L
0
0
0
H
H
H
H
H
L
H
H
H
H
L
L
L
1 to n[2]
1 to n[2]
1 to n[2]
H
H
H
H
H
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
(n + 1) to 4096
H
H
H
H
513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
(1024 – m)[3] to 1023
(2048 – m)[3] to 2047
(4096 – m)[3] to 4095
(8192 – m)[3] to 8191
1024
2048
4096
8192
L
Notes:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of
RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06016 Rev. *A
Page 4 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Width Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
RESET(RS)
RESET(RS)
DATAIN (D)
18
9
9
Read CLOCK(RCLK)
Write CLOCK(WCLK)
Read ENABLE1 (REN1)
Write ENABLE 1 (WEN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
Write ENABLE2/LOAD
(WEN2/LD)
EMPTY FLAG (EF) #1
CY7C42X1
CY7C42X1
PROGRAMMABLE (PAF)
FULL FLAG (FF) # 1
EF
EMPTY FLAG (EF) #2
EF
FF
FF
DATA OUT (Q)
9
18
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
42X1–16
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory
Used in a Width Expansion Configuration
Document #: 38-06016 Rev. *A
Page 5 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................>200mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Commercial
Industrial[4]
Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State............................................... –0.5V to +7.0V
0°C to +70°C
5V ±10%
5V ±10%
–40°C to +85°C
DC Input Voltage............................................ –3.0V to +7.0V
Pin Definitions
Pin
Name
I/O
Description
D0–8
Q0–8
Data Inputs
I
O
I
Data Inputs for 9-bit Bus
Data Outputs for 9-bit Bus
Data Outputs
Write Enable 1
WEN1
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD Dual Write Enable 2
I
I
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Mode Pin
Load
REN1, REN2 Read Enable
Inputs
I
I
Enables Device for Read Operation
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1is LOW, WEN2/LD is HIGH, and the
FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
PAF
RS
Programmable
Almost Full
O
I
When PAFis LOW, the FIFO is almost full based on the almost full offset value programmed into
the FIFO.
Reset
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Note:
4. TA is the “instant on” case temperature.
Document #: 38-06016 Rev. *A
Page 6 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Electrical Characteristics Over the Operating Range[5]
-10
-15
-25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
V
IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
OL = 8.0 mA
0.4
0.4
0.4
V
I
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.2
–3.0
–10
VCC
0.8
2.2
–3.0
–10
VCC
0.8
2.2
–3.0
–10
VCC
0.8
V
V
Input Leakage
Current
VCC = Max.
+10
+10
+10
µA
[6]
IOS
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
–90
–10
–90
–10
–90
–10
mA
mA
IOZL
IOZH
Output OFF,
High-Z Current
OE > VIH,
VSS < VO < VCC
+10
+10
+10
[7]
ICC1
Active Power Supply
Current
Commercial
35
40
10
15
35
40
10
15
35
40
10
15
mA
mA
mA
mA
Industrial
[8]
ICC2
Average Standby
Current
Commercial
Industrial
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
5
7
Unit
pF
pF
CIN
COUT
AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
5V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
680Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
Equivalentto:
THÉVENIN EQUIVALENT
SCOPE
420Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
-10
-15
-25
Parameter
tS
Description
Clock Cycle Frequency
Min.
Max.
100
8
Min.
Max.
66.7
10
Min.
Max.
40
Unit
MHz
ns
tA
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
2
2
15
6
2
15
tCLK
tCLKH
tCLKL
10
4.5
4.5
3
25
10
10
6
ns
ns
6
ns
tDS
4
ns
Notes:
5. See the last page of this specification for Group A subgroup testing information.
6. Test no more than one output at a time for not more than one second.
7. Outputs open. Tested at Frequency = 20 MHz.
8. All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ
.
11. CL = 5 pF for tOHZ
.
Document #: 38-06016 Rev. *A
Page 7 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Characteristics Over the Operating Range
-10
-15
-25
Parameter
tDH
Description
Min.
0.5
3
Max.
Min.
1
Max.
Min.
1
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
tENS
tENH
tRS
Enable Set-up Time
4
6
Enable Hold Time
Reset Pulse Width[12]
0.5
10
8
1
1
15
10
10
25
15
15
tRSS
tRSR
tRSF
Reset Set-up Time
Reset Recovery Time
8
Reset to Flag and Output Time
Output Enable to Output in Low-Z[13]
Output Enable to Output Valid
Output Enable to Output in High-Z[13]
Write Clock to Full Flag
10
15
25
tOLZ
0
3
3
0
3
3
0
3
3
tOE
7
7
8
8
8
8
8
12
12
15
15
15
15
tOHZ
tWFF
tREF
8
10
10
10
10
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
tPAF
tPAE
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
18
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
ns
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
8
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
t
t
WFF
(if applicable)
WFF
FF
[14]
t
SKEW1
RCLK
REN1,REN2
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06016 Rev. *A
Page 8 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1,REN2
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q
–Q
8
0
t
OLZ
t
OHZ
t
OE
OE
[15]
t
SKEW1
WCLK
WEN1
WEN2
Reset Timing[16]
t
RS
RS
t
t
t
RSR
RSS
RSS
REN1,
REN2
t
RSR
WEN1
t
t
RSR
RSS
[17]
WEN2/LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
[18]
E
O =1
Q
Q
8
0 -
OE=0
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *A
Page 9 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D0–D8
VALIDWrite)
D
2
D
3
D
4
D0(FIRST
D
1
t
ENS
[19]
FRL
t
WEN1
WEN2
(if applicable)
t
SKEW1
RCLK
t
REF
EF
[20]
tA
t
A
REN1,
REN2
Q0–Q
D
0
D
1
8
t
OLZ
t
OE
OE
Empty Flag Timing
WCLK
t
t
DS
DS
DATAWRITE2
DATAWRITE1
D –D
0
8
t
t
ENH
ENH
t
t
ENS
t
t
ENS
WEN1
WEN2
(if applicable)
ENS
t
t
ENS
ENH
ENH
[19]
[19]
t
t
FRL
FRL
RCLK
t
t
t
REF
t
t
SKEW1
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
DATA Read
Q –Q
0
8
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or
tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *A
Page 10 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Full Flag Timing
NO Write
NO Write
NO Write
WCLK
[14]
[14]
t
t
DS
DATA Write
t
t
SKEW1
SKEW1
DATA Write
D –D
0
8
t
t
WFF
WFF
WFF
FF
WEN1
WEN2
(if applicable)
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN1,
REN2
LOW
OE
t
A
t
A
DATA Read
NEXT DATA Read
DATA IN OUTPUT REGISTER
Q –Q
0
8
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN1
t
t
ENS
ENH
WEN2
(if applicable)
t
t
ENS
[21]
ENH
Note
22
PAE
N + 1 WORDS
INFIFO
Note
23
t
PAE
t
t
PAE
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Document #: 38-06016 Rev. *A
Page 11 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Programmable Almost Full FlagTiming
Note
24
t
t
CLKL
CLKH
WCLK
t
t
t
ENS
ENH
WEN1
Note
25
WEN2
(if applicable)
t
t
PAF
ENS
ENH
FULL − M WORDS
PAF
[26]
IN FIFO
FULL − M+1 WORDS
IN FIFO
[27]
t
t
PAF
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
WEN1
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
24. If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,
4096 – m words for CY7C4241, 8192 – m words for CY7C4251.
27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *A
Page 12 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
PAF OFFSET
MSB
REN1,
REN2
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q –Q
0
8
Document #: 38-06016 Rev. *A
Page 13 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Typical AC and DC Characteristics
NORMALIZED SUPPLYCURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
1.20
1.10
1.00
0.90
0.80
1.4
1.2
1.10
V
= 3.0V
= 5.0V
IN
V
= 5.0V
CC
V
CC
T = 25°C
A
1.00
0.90
0.80
0.70
0.60
f = 100 MHz
V
IN
= 3.0V
1.0
V
= 3.0V
IN
T = 25°C
A
0.8
0.6
f = 100 MHz
4
4.5
5
5.5
6
−55
25
125
0
25
50
75
100
SUPPLY VOLTAGE(V)
AMBIENT TEMPERATURE (°C)
FREQUENCY (MHz)
NORMALIZED t vs. SUPPLY
A
VOLTAGE
NORMALIZED t vs.
A
AMBIENT TEMPERATURE
TYPICAL t CHANGEvs.
A
OUTPUT LOADING
1.50
1.25
1.00
0.75
0.50
1.2
1.1
40
V
CC
= 5.0V
25
10
0
1.0
0.9
0.8
V
= 5.0V
CC
T = 25°C
A
4
−55
25
125
4.5
5
5.5
6
0
200 400 600
800 1000
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
CAPACITANCE (pF)
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
160
55
140
120
100
80
45
60
35
25
40
20
0
0
1
2
3
4
0
1
2
3
4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Document #: 38-06016 Rev. *A
Page 14 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Ordering Information
64 x 9 Synchronous FIFO
Speed
(ns)
Package
Name
Package
Type
Operating
Range
Ordering Code
10
CY7C4421-10AC
CY7C4421-10JC
CY7C4421-15AC
CY7C4421-15JC
A32
J65
A32
J65
32-lead Thin Quad Flatpack
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
32-lead Plastic Leaded Chip Carrier
Commercial
15
Commercial
256 x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4201-10AC
CY7C4201-10JC
CY7C4201-15AC
CY7C4201-15JC
CY7C4201-25AC
CY7C4201-25JC
CY7C4201-25AI
A32
J65
A32
J65
A32
J65
A32
32-lead Thin Quad Flatpack
Commercial
Commercial
Commercial
Industrial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
15
25
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
512 x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4211-10AC
CY7C4211-10JC
CY7C4211-10AI
CY7C4211-10JI
CY7C4211-15AC
CY7C4211-15JC
CY7C4211-15AI
CY7C4211-25AC
CY7C4211-25JC
A32
J65
A32
J65
A32
J65
A32
A32
J65
32-lead Thin Quad Flatpack
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Industrial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
15
25
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Industrial
32-lead Thin Quad Flatpack
Commercial
32-lead Plastic Leaded Chip Carrier
1K x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4221-10AC
CY7C4221-10JC
CY7C4221-15AC
CY7C4221-15JC
CY7C4221-25AC
CY7C4221-25JC
A32
J65
A32
J65
A32
J65
32-lead Thin Quad Flatpack
Commercial
Commercial
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
15
25
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
32-lead Plastic Leaded Chip Carrier
2K x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4231-10AC
CY7C4231-10JC
CY7C4231-15AC
A32
J65
A32
32-lead Thin Quad Flatpack
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Commercial
15
Commercial
Document #: 38-06016 Rev. *A
Page 15 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
2K x 9 Synchronous FIFO (continued)
Speed
Package
Name
Package
Operating
Range
(ns)
Ordering Code
CY7C4231-15JC
Type
J65
A32
J65
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
25
CY7C4231-25AC
CY7C4231-25JC
Commercial
32-lead Plastic Leaded Chip Carrier
4K x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4241-10AC
CY7C4241-10JC
CY7C4241-10JI
CY7C4241-15AC
CY7C4241-15JC
CY7C4241-25AC
CY7C4241-25JC
CY7C4241-25JI
A32
J65
J65
A32
J65
A32
J65
J65
32-lead Thin Quad Flatpack
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Industrial
15
25
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Commercial
Industrial
32-lead Plastic Leaded Chip Carrier
32-lead Plastic Leaded Chip Carrier
8K x 9 Synchronous FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4251-10AC
CY7C4251-10JC
CY7C4251-10AI
CY7C4251-15AC
CY7C4251-15JC
CY7C4251-25AC
CY7C4251-25JC
CY7C4251-25AI
A32
J65
A32
A32
J65
A32
J65
A32
32-lead Thin Quad Flatpack
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Industrial
15
25
32-lead Thin Quad Flatpack
Commercial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Commercial
Industrial
32-lead Plastic Leaded Chip Carrier
32-lead Thin Quad Flatpack
Document #: 38-06016 Rev. *A
Page 16 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Package Diagrams
32-lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32
51-85063-B
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06016 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document Title: CY7C4421/4201/4211/4221, CY7C4231/4241/4251 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Document Number: 38-06016
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106477
110725
Description of Change
Change from Spec number: 38-00419 to 38-06016
Change Input Leakage current IIX unit from mA to µA (typo)
09/10/01
03/20/02
SZV
FSG
*A
Document #: 38-06016 Rev. *A
Page 18 of 18
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