CY7C4265V-15JI [CYPRESS]
FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | CY7C4265V-15JI |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总19页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 5422
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs
Features
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
the
CY7C42X5V Synchronous FIFO
family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 67-MHz operation (15 ns read/write cycle
times)
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
• Low power
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocksmay be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
I
I
= 30 mA
= 3 mA
—
—
CC
SB
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• Retransmit function
• Output Enable (OE pin
)
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 STQFP
• Pin-compatible density upgrade to
CY7C42X5V-JC/ASC families
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V and the FL pin of all the remaining devic-
SS
.
es should be tied to V
CC
D
0 – 17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
High
FF
EF
Density
Dual-Port
RAM Array
FLAG
LOGIC
PAE
PAF
8Kx9
16Kx9
32Kx9
64Kx9
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
THREE–STATE
OUTPUTREGISTER
READ
CONTROL
WXI
WXO/HF
RXI
EXPANSION
LOGIC
OE
Q
0 – 17
RXO
4275V–1
RCLK
REN
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 6, 1997 - Revised February 26, 1998
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Pin Configurations
PLCC
Top View
STQFP
Top View
9
8
7
6
5
4
3 2 1 68 67 66 65 64 63 62 61
V
/SMODE
D
D
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
CC
14
13
Q
Q
48
47
D
D
D
D
D
D
1
2
14
15
14
13
12
Q
Q
14
13
13
D
12
GND
46
45
3
4
D
D
11
10
GND
Q
12
Q
12
Q
V
44
43
42
41
11
5
6
7
8
11
10
D
9
Q
V
11
CC
V
CC
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
CC
Q
10
D
9
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
D
8
Q
10
9
Q
9
D
D
8
GND
Q
GND
40
39
7
9
10
D
D
7
6
5
GND
Q
8
D
D
D
D
D
D
6
Q
8
38
37
36
11
12
13
Q
7
5
D
21
22
23
24
25
26
Q
7
V
CC
Q
6
4
3
D
4
Q
5
D
D
D
3
35
34
Q
6
47
46
45
44
14
15
GND
2
Q
4
2
Q
5
1
D
33
V
CC
16
0
1
GND
Q
D
0
4
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
4275V–3
4275V–2
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
Functional Description (continued)
The CY7C4255/65/75/85V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty, Half
Full, Almost Full, and Full (see Table 2). The Half Full flag shares the
WXO pin. This flag is valid in the stand-alone and width-expansion
configurations. In the depth expansion, this pin provides
the expansion out (WXO) information that is used to signal
the next FIFO when it will be activated.
become synchronous if the V /SMODE is tied to V . All
CC
SS
configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
66.7
10
15
4
40
15
25
6
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0
1
10
30
35
15
30
Active Power Supply
Commercial
Industrial
Current (I
) (mA)
CC1
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
Density
8K x 18
16K x 18
32K x 18
64K x 18
Package
64-pin 10x10 TQFP 64-pin 10x10 TQFP 64-pin 10x10 TQFP 64-pin 10x10 TQFP
68-pin PLCC 68-pin PLCC 68-pin PLCC 68-pin PLCC
2
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Pin Definitions
Signal Name
Description
I/O
Function
D
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
O
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
0–17
Q
0–17
WEN
REN
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
FF
PAE
Programmable
Almost Empty
value programmed into the FIFO. PAE is asynchronous when V /SMODE is tied
CC
to V ; it is synchronized to RCLK when V /SMODE is tied to V .
CC
CC
SS
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V /SMODE is tied to
CC
V
; it is synchronized to WCLK when V /SMODE is tied to V
.
CC
CC
SS
LD
Load
I
I
When LD is LOW, D
ble-flag-offset register.
(Q
) are written (read) into (from) the programma-
0–17
0–17
FL/RT
First Load/
Retransmit
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to V ; all other
SS
devices will have FL tied to V . In standard mode or width expansion, FL is tied
CC
to V on all devices.
SS
Not Cascaded – Tied to V . Retransmit function is also available in stand-alone
SS
mode by strobing RT.
WXI
RXI
RXO
RS
Write Expansion
Input
I
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
.
SS
Read Expansion
Input
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
.
SS
Read Expansion
Output
O
I
Cascaded – Connected to RXI of next device.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
V
/SMODE Synchronous
Almost Empty/
I
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
CC
Almost Full Flags
Synchronous Almost Empty/Almost Full flags – tied to V
.
SS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
3
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................–55°C to +125°C
Operating Range
Ambient
Temperature
Supply Voltage to Ground Potential .........–0.5V to V +0.5V
CC
Range
V
CC
DC Voltage Applied to Outputs
in High Z State .........................................–0.5V to V +0.5V
Commercial
0°C to +70°C
3.3V +300mV
and −600mV
CC
DC Input Voltage ..........................................−0.5V to V +0.5V
CC
[1]
Industrial
–40°C to +85°C
3.3V +300mV
and −600mV
[2]
Electrical Characteristics Over the Operating Range
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage
V
V
= Min., I
= 3.0V. I
= –1.0 mA
= –2.0 mA
2.4
2.4
V
OH
CC
CC
OH
OH
V
Output LOW Voltage
V
V
= Min.,I = 4.0 mA
0.4
0.4
V
OL
CC
CC
OL
= 3.0V.,I = 8.0 mA
OL
[3]
V
V
Input HIGH Voltage
Input LOW Voltage
2.0
–0.5
–10
V
2.0
–0.5
–10
V
CC
V
V
IH
[3]
CC
0.8
0.8
IL
I
Input Leakage
Current
V
= Max.
+10
+10
µA
IX
CC
I
I
Output OFF,
High Z Current
OE > V ,
–10
+10
–10
+10
30
µA
OZL
OZH
IH
V
< V < V
SS O CC
[4]
I
Active Power Supply
Current
Com’l
Ind
30
35
3
mA
mA
mA
mA
CC1
[5]
SB
I
Average Standby
Current
Com’l
Ind
3
3
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
C
T = 25°C, f = 1 MHz,
5
7
IN
A
V
= 3.3V
CC
C
pF
OUT
Notes:
1. A is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
T
previous device or VSS
.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10MHz. Outputs
are unloaded.
5. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at VSS. All outputs are unloaded.
6. Tested initially and after any design changes that may affect these parameters.
4
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
AC Test Loads and Waveforms[7, 8]
R1=330
Ω
3.3V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
90%
10%
R2=510
10%
Ω
C
L
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
4285V–4
4275V–5
Equivalent to:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2.0V
Switching Characteristics Over the Operating Range
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Parameter
Description
Clock Cycle Frequency
Min.
Max.
66.7
10
Min.
Max.
40
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
2
15
6
2
25
10
10
6
15
A
CLK
CLKH
CLKL
DS
6
4
0
1
DH
Enable Set-Up Time
Enable Hold Time
4
6
ENS
ENH
RS
0
1
[9]
Reset Pulse Width
15
10
25
15
Reset Recovery Time
RSR
RSF
PRT
RTR
OLZ
OE
Reset to Flag and Output Time
Retransmit Pulse Width
15
25
60
90
0
60
90
0
Retransmit Recovery Time
Output Enable to Output in Low Z
Output Enable to Output Valid
[10]
[10]
3
10
8
3
12
12
15
15
20
Output Enable to Output in High Z
Write Clock to Full Flag
3
3
OHZ
WFF
REF
PAFasynch
10
10
16
Read Clock to Empty Flag
[11]
Clock to Programmable Almost-Full Flag
(Asynchronous mode, V /SMODE tied to V
)
CC
CC
t
t
Clock to Programmable Almost-Full Flag
10
16
15
20
ns
ns
PAFsynch
(Synchronous mode, V /SMODE tied to V
)
CC
SS
[11]
Clock to Programmable Almost-Empty Flag
(Asynchronous mode, V /SMODE tied to V
PAEasynch
)
CC
CC
Notes:
7. CL = 30 pF for all AC parameters except for tOHZ
.
8. CL = 5 pF for tOHZ
.
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
11. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E)
.
5
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
t
Clock to Programmable Almost-Full Flag
10
15
ns
PAEsynch
(Synchronous mode, V /SMODE tied to V
)
SS
CC
t
t
t
t
t
Clock to Half-Full Flag
16
10
20
15
ns
ns
ns
ns
ns
HF
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
XO
6.5
5
10
10
10
XI
XIS
Skew Time between Read Clock and Write Clock for
Full Flag
6
SKEW1
t
t
Skew Time between Read Clock and Write Clock for
Empty Flag
6
10
18
ns
ns
SKEW2
SKEW3
Skew Time between Read Clock and Write Clock for
Programmable Almost Empty and Programmable
Almost Full Flags (Synchronous Mode only)
15
6
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[12]
t
SKEW1
RCLK
REN
4275V–6
Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[13]
SKEW2
t
WCLK
WEN
4275V–7
Notes:
12. SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
t
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
13. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
7
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
[14]
Reset Timing
t
RS
RS
t
RSR
REN,WEN,
LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
[15]
OE=1
Q
Q
0 – 17
OE=0
4275V–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
0
D
0
D
1
D
2
D
3
D
4
(FIRSTVALIDWRITE)
17
t
ENS
[16]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
[17]
t
A
t
A
Q –Q
0
D
0
D
1
17
t
OLZ
t
OE
OE
4275V–9
Notes:
14. The clocks (RCLK, WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
16. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
17. The first word is available the cycle after EF goes HIGH, always.
8
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
D0
D1
D –D
0
17
t
t
t
ENH
t
ENH
ENS
ENS
WEN
[16]
FRL
t
[16]
FRL
t
RCLK
t
t
t
REF
t
REF
t
SKEW2
REF
SKEW2
EF
REN
OE
t
A
D0
Q –Q
0
17
4275V–10
Full FlagTiming
NO WRITE
NO WRITE
WCLK
[12]
[12]
t
t
DS
DATA WRITE
t
SKEW1
SKEW1
DATA WRITE
D –D
0
17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN
OE
LOW
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
17
4275V–11
9
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Half-Full Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL + 1
OR MORE
HALF
HALF FULL OR LESS
FULL OR LESS
HF
t
HF
RCLK
REN
t
ENS
4275V–12
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
PAE
[18]
N + 1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
REN
t
ENS
4275V–13
Note:
18. PAE is offset = n. Number of data words into FIFO already = n.
10
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKL
CLKH
WCLK
WEN
PAE
t
t
ENS ENH
19
Note
N + 1 WORDS
IN FIFO
Note
21
t
PAE synch
[20]
t
t
SKEW3
PAE synch
RCLK
REN
t
ENS
t
t
ENS ENH
4275V–14
Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
22
Note
WCLK
WEN
t
t
ENS ENH
t
PAF
FULL– M WORDS
[23]
[24]
IN FIFO
PAF
FULL– (M+1) WORDS
[25]
IN FIFO
t
PAF
RCLK
REN
t
ENS
4275V–15
Notes:
19. PAE offset − n.
20.
tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
21. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
22. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768− (m + 1)
for the CY7C4275V, and 65536 − (m + 1) for the CY7C4285V.
23. PAF is offset = m.
24. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V.
25. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V.
11
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
26
Note
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
PAF
t
PAF
FULL– M WORDS
IN FIFO
[24]
FULL – M + 1 WORDS
IN FIFO
t
[27]
PAF synch
t
SKEW3
RCLK
REN
t
ENS
t
t
ENH
ENS
4275V–16
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D –D
0
17
D
D –
0
PAE OFFSET
PAF OFFSET
11
4275V–17
Notes:
26. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
27. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the
rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
12
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
A
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Q –Q
0
17
4275V–18
Write Expansion Out Timing
t
CLKH
WCLK
Note 29
Note 28
t
XO
WXO
t
XO
t
ENS
WEN
4275V–19
Read Expansion Out Timing
t
CLKH
WCLK
Note 29
t
XO
RXO
REN
t
XO
t
ENS
4275V–20
Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
4275V–21
Notes:
28. Write to Last Physical Location.
29. Read from Last Physical Location.
13
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Switching Waveforms (continued)
Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
4275V–22
[30, 31, 32]
Retransmit Timing
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
4275V–23
Notes:
30. Clocks are free running in this case.
31. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR
.
32. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
14
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
operation. When the LD pin is set LOW, and WEN is LOW, the next
offset register in sequence is written.
Architecture
The CY7C4255/65/75/85V consists of an array of
8K/16K/32K/64K words of 18 bits each (implemented by a du-
al-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF,
PAE, HF, PAF, FF). The CY7C4255/65/75/85V also includes the con-
trol signals WXI, RXI, WXO, RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then, data
can be read on the LOW-to-HIGH transition of the read clock (RCLK).
Table 1. Write Offset Register
[33]
LD WEN WCLK
Selection
Resetting the FIFO
0
0
Writing to offset registers:
Empty Offset
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of RS
only if OE is asserted. In order for the FIFO to reset to its default state,
the user must not read or write while RS is LOW.
Full Offset
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
FIFO Operation
When the WEN signal is active (LOW), data present on the D
0–17
pins is written into the FIFO on each rising edge of the WCLK signal.
Similarly, when the RENsignal is active LOW, data in the FIFO mem-
ory will be presented on the Q
outputs. New data will be present-
0–17
ed on each rising edge of RCLK while REN is active LOW and OE is
LOW. REN must set up t before RCLK for it to be a valid read
Flag Operation
ENS
function. WEN must occur t
function.
before WCLK for it to be a valid write
ENS
The CY7C4255/65/75/85V devices provide five flag pins to in-
dicate the condition of the FIFO contents. Empty and Full are
An output enable (OE) pin is provided to three-state the Q
putswhen OE is deasserted. When OE isenabled(LOW), data inthe
output register will be available to the Q outputs after t . If de-
out-
0–17
synchronous. PAEand PAF are synchronous if V /SMODE is tied
CC
to V
.
SS
0–17
OE
vices are cascaded, the OE function will only output data on the FIFO
that is read enabled.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations
are inhibited whenever FF is LOW regardlessof the state of WEN. FF
is synchronized to WCLK, i.e., it is exclusively updated by each rising
edge of WCLK.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
outputs
0–17
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the state
of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by
each rising edge of RCLK.
Programming
The CY7C4255/65/75/85V devices contain two 16-bit offset
registers. Data present on D during a program write will de-
0–15
terminethe distance from Empty (Full) that theAlmost Empty(Almost
Full) flags become active. If the user elects not to program the FIFO’s
flags, thedefault offset values areused (see Table 2). When the Load
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/75/85V features programmable Almost
Empty and Almost Full Flags. Each flag can be programmed
(described in the Programming section) a specific distance
from the corresponding boundary flags (Empty or Full). When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAF or PAE will be asserted,
signifying that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
LD pin is set LOW and WEN is set LOW, data on the inputs D
is
0–15
written into the Empty offset register on the first LOW-to-HIGH transi-
tion of the write clock (WCLK). When the LD pin and WEN are held
LOW then data is written into the Full offset register on the second
LOW-to-HIGH transition of the write clock (WCLK). The third transi-
tion of thewrite clock (WCLK) again writestothe Emptyoffset register
(see Table 1). Writing all offset registers does not have to occur at
one time. One or two offset registers can be written and then, by
bringing the LD pin HIGH, the FIFO is returned to normal read/write
When the SMODE pin is tied LOW, the PAF flag signal transition is
causedbytherising edge of thewrite clockand thePAE flagtransition
is caused by the rising edge of the read clock.
Note:
33. The same selection sequence applies to reading from the registers. RENis enabled and read is performed on the LOW-to-HIGH transition of RCLK.
15
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Table 2. Flag Truth Table
Number of Words in FIFO
7C4255V – 8K x 18
7C4265V – 16K x 18 7C4275V – 32K x 18 7C4285V – 64K x 18 FF PAF HF PAE EF
0
0
0
0
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
[34]
[34]
[34]
[34]
1 to n
(n+1) to 4096
1 to n
1 to n
1 to n
(n+1) to 8192
(n+1) to 16384
(n+1) to 32768
H
H
4097 to (8192–(m+1)) 8193 to (16384
–(m+1))
16385 to
(32768–(m+1))
32769 to (65536
–(m+1))
[35]
[35]
[35]
[35]
(8192–m) to 8192
(16384–m) to
16384
(32768–m) to
32767
(65536–m) to
65535
H
L
L
L
L
L
H
H
H
H
8192
16384
32768
65536
Notes:
34. n = Empty Offset (Default Values: CY7C4255/65/75/85V n = 127).
35. m = Full Offset (Default Values: CY7C4255/65/75/85V n = 127).
retransmit cycle. Data written to the FIFO after activation of RT are
transmitted also.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the inter-
nal read pointer to the first physical location of the FIFO. WCLK and
The CY7C4255/65/75/85V can be expanded in width to pro-
vide word widths greater than 18 in increments of 18. During
width expansion mode all control line inputs are common and
all flags are available. Empty (Full) flags should be created by
ANDing the Empty (Full) flags of every FIFO; the PAE and PAF
flags can be detected from any one device. This technique will
avoid reading data from, or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure 1 demonstrates a 36-word
width by using two CY7C4255/65/75/85Vs.
RCLKmay befreerunning but must be disabledduring andt
after
RTR
the retransmit pulse. With every valid read cycle after retransmit, pre-
viously accessed data is read and the read pointer is incriminated
until it is equal to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during a
RESET(RS)
RESET(RS)
DATA IN (D)
36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
PROGRAMMABLE (PAF)
7C4255V
7C4265V
7C4275V
7C4285V
7C4255V
7C4265V
7C4275V
7C4285V
EMPTY FLAG (EF)
EF
FF
FF
EF
DATA OUT (Q)
18
36
FULL FLAG (FF)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4275V–24
Figure 1. Block Diagram of 8K/16K/32K/64K x 18 Low Voltage Synchronous FIFO Memory Used in a Width Expansion
Configuration
16
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
Depth Expansion Configuration
(with Programmable Flags)
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
The CY7C4255/65/75/85V can easily be adapted to applica-
tions requiring more than 8K/16K/32K/64K words of buffering.
5. All Load (LD) pins are tied together.
Figure
2
shows
Depth
Expansion
using
three
CY7C4255/65/75/85Vs. Maximum depth is limited only by signal
loading. Follow these steps:
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
1. The first device must be designated by grounding the First
Load (FL) control input.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
2. All other devices must have FL in the HIGH state.
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
V
CC
FL
FF
PAF
EF
PAE
WXI RXI
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
DATAIN (D)
DATA OUT (Q)
V
CC
FL
FF
PAF
EF
PAE
WXI RXI
WRITECLOCK (WCLK)
WRITEENABLE(WEN)
READCLOCK(RCLK)
READENABLE(REN)
WXO RXO
7C4255V
7C4265V
7C4275V
7C4285V
RESET(RS)
OUTPUTENABLE (OE)
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
FIRST LOAD(FL)
4275V–25
Figure 2. Block Diagram of 8K/16K/32K/64K x 18 Low Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
17
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Ordering Information
8Kx18 Low Voltage Deep Sync FIFO
Speed
(ns)
Package
Package
Type
Operating
Range
Ordering Code
CY7C4255V–15ASC
CY7C4255V–15JC
CY7C4255V–15ASI
CY7C4255V–15JI
CY7C4255V–25ASC
CY7C4255V–25JC
Name
A64
J81
15
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
A64
J81
64-Lead 10x10 Thin Quad Flatpack Industrial
68-Lead Plastic Leaded Chip Carrier
25
A64
J81
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
16Kx18 Low Voltage Deep Sync FIFO
Speed
(ns)
Package
Package
Type
Operating
Range
Ordering Code
CY7C4265V–15ASC
CY7C4265V–15JC
CY7C4265V–15ASI
CY7C4265V–15JI
CY7C4265V–25ASC
CY7C4265V–25JC
Name
A64
J81
15
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
A64
J81
64-Lead 10x10 Thin Quad Flatpack Industrial
68-Lead Plastic Leaded Chip Carrier
25
A64
J81
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
32Kx18 Low Voltage Deep Sync FIFO
Speed
(ns)
Package
Package
Type
Operating
Range
Ordering Code
CY7C4275V–15ASC
CY7C4275V–15JC
CY7C4275V–15ASI
CY7C4275V–15JI
CY7C4275V–25ASC
CY7C4275V–25JC
Name
A64
J81
15
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
A64
J81
64-Lead 10x10 Thin Quad Flatpack Industrial
68-Lead Plastic Leaded Chip Carrier
25
A64
J81
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
64Kx18 Low Voltage Deep Sync FIFO
Speed
(ns)
Package
Package
Type
Operating
Range
Ordering Code
CY7C4285V–15ASC
CY7C4285V–15JC
CY7C4285V–15ASI
CY7C4285V–15JI
CY7C4285V–25ASC
CY7C4285V–25JC
Name
A64
J81
15
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
A64
J81
64-Lead 10x10 Thin Quad Flatpack Industrial
68-Lead Plastic Leaded Chip Carrier
25
A64
J81
64-Lead 10x10 Thin Quad Flatpack Commercial
68-Lead Plastic Leaded Chip Carrier
Document #: 38-00654-A
18
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
PRELIMINARY
Package Diagrams
64-Pin Thin Quad Flat Pack A64
68-Lead Plastic Leaded Chip Carrier J81
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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