CY7C4271-35AC [CYPRESS]
16K/32K x 9 Deep Sync FIFOs; 16K / 32K ×9深度的FIFO同步
| 型号： | CY7C4271-35AC |
| 厂家： | 
CYPRESS |
| 描述： | 16K/32K x 9 Deep Sync FIFOs |
| 文件： | 总18页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 35 mA
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full,HalfFull, andprogrammableAlmostEmpty
and Almost Full status flags
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
• TTL-compatible
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
PLCC/LCC
Top View
D
0 −
Logic Block Diagram
Pin Configuration
8
INPUT
REGISTER
4
3
2
1
32 31 30
29
D
RS
1
5
6
7
8
D
28
27
26
0
WEN1
WCLK
WEN2/LD
PAF
PAE
WCLK WEN1 WEN2/LD
CY7C4261
CY7C4271
GND
FLAG
PROGRAM
REGISTER
V
9
25
24
23
22
21
CC
REN1
RCLK
REN2
OE
Q
8
10
11
12
13
Q
7
WRITE
CONTROL
Q
6
Q
5
EF
14 15 16 17 18 19 20
PAE
PAF
FF
FLAG
LOGIC
TQFP
RAM
Top View
ARRAY
16Kx 9
32Kx 9
WRITE
POINTER
READ
POINTER
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
WEN1
D
1
D
0
RESET
LOGIC
23
WCLK
RS
WEN2/LD
22
21
20
19
PAF
PAE
CY7C4261
CY7C4271
V
CC
THREE-STATE
OUTPUT REGISTER
Q
8
GND
REN1
READ
CONTROL
Q
7
Q
6
RCLK
REN2
18
17
OE
Q
5
Q
0 −
9
10 11 12 13 14 15 16
8
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06015 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 21, 2003
CY7C4261
CY7C4271
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
Functional Description (continued)
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full–7.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Pin Definitions
Signal Name
D0−8
Description
Data Inputs
I/O
Description
I
O
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
Write Enable 1
Data Outputs for 9-bit bus.
WEN1
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
REN1, REN2 Read Enable
Inputs
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LDis asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO. PAE is synchronized to RCLK.
PAF
RS
Programmable
Almost Full
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Selection Guide
7C4261/71-10
7C4261/71-15
7C4261/71-25
7C4261/71-35
Unit
MHz
ns
Maximum Frequency
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
Maximum Access Time
Minimum Cycle Time
10
3
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
0.5
8
1
1
2
ns
10
35
40
15
35
40
20
35
40
ns
Active Power Supply Commercial
35
40
mA
Current (ICC1
)
Industrial/
Military
Document #: 38-06015 Rev. *B
Page 2 of 18
CY7C4261
CY7C4271
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
CY7C4261
16K × 9
CY7C4271
Density
32K × 9
Package
32-pin PLCC,TQFP
32-pin
LCC,PLCC,TQFP
Programming
When WEN2/LDis held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, WEN2/LD
can be used to access the four 8-bit offset registers contained in the
CY7C4261/71 for writing or reading data to these registers.
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF).
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from thedata inputsto the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and full
offset MSB register, respectively, when WEN2/LD and WEN1 are
LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD
and WEN1 are LOW writes data to the empty LSB register again.
Figure 1 shows the registers sizes and default values for the various
device types.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q0−8) go LOW tRSF after the rising
edge of RS. In order for the FIFO to reset to its default state, a falling
edge must occur on RS and the user must not read or write while RS
is LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
16K ×9
32K ×9
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
FIFO Operation
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value= 007h
When the WEN1 signal is active LOW, WEN2 is active HIGH, and
FF is active HIGH, data present on the D0−8 pins is written into the
FIFO on each rising edge of the WCLK signal. Similarly, when the
REN1andREN2signalsareactive LOWandEFis activeHIGH, data
in the FIFO memory will be presented on the Q0−8 outputs. New data
will be presented on each rising edge of RCLK while REN1 and
REN2 are active. REN1 and REN2 must set up tENS before RCLK
for it to be a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
5
6
(MSB)
000000
(MSB)
0000000
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value= 007h
An output enable (OE) pin is provided to three-state the Q0−8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q0−8 outputs after tOE. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
5
6
(MSB)
000000
(MSB)
0000000
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−8 outputs even
after additional reads occur.
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) (PAF) states are deter-
mined by their corresponding offset registers and the
difference between the read and write pointers.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM
Document #: 38-06015 Rev. *B
Page 3 of 18
CY7C4261
CY7C4271
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
Table 1. Writing the Offset Registers
WCLK[1]
LD
WEN
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261 (16K-m) and CY7C4271
(32K-m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Full Offset (MSB)
0
1
1
0
No Operation
Write Into FIFO
1
1
No Operation
Table 2. Status Flags
Number of Words in FIFO
CY7C4261
CY7C4271
FF
H
H
H
H
L
PAF
H
PAE
L
EF
L
0
0
1 to n[2]
1 to n[2]
H
L
H
H
H
H
(n+1) to (16384 − (m+1))
(16384 − m)[3] to 16383
16384
(n+1) to (32768 − (m+1))
(32768 − m)[3] to 32767
32768
H
H
L
H
L
H
Width-Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAEand PAF)
can be detected from any one device. Figure 2 demonstrates
a 18-bit word width by using two CY7C4261/71s. Any word
width can be attained by adding additional CY7C4261/71s.
The CY7C4261/71 devices provide four flag pins to indicate
the condition of the FIFO contents. Empty, Full, PAE, and PAF
are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FFis LOW regardless of the
state of WEN1and WEN2/LD. FF is synchronized to WCLK, i.e.,
it is exclusively updated by each rising edge of WCLK.
When the CY7C4261/71 is in a Width-Expansion Configu-
ration, the Read Enable (REN2) control input can be grounded
(see Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06015 Rev. *B
Page 4 of 18
CY7C4261
CY7C4271
RESET(RS)
RESET(RS)
DATAIN (D)
18
9
9
READCLOCK(RCLK)
WRITECLOCK(WCLK)
READENABLE1 (REN1)
WRITE ENABLE1(WEN1)
OUTPUT ENABLE(OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
WRITE ENABLE2/LOAD
(WEN2/LD)
CY7C4261/71
CY7C4261/71
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
EMPTY FLAG (EF) #2
EF
FF
FF
EF
DATA OUT (Q)
9
18
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration
Document #: 38-06015 Rev. *B
Page 5 of 18
CY7C4261
CY7C4271
Maximum Ratings[4]
DC Input Voltage..........................................−0.5V to Vcc+0.5V
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .......................................−65°C to +150°C
Latch-up Current......................................................>200 mA
Operating Range
Ambient Temperature with
Power Applied....................................................−55°C to +125°C
Range
Commercial
Industrial[5]
Military
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential .................−0.5V to +7.0V
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High-Z State............................................−0.5V to VCC + 0.5V
−40°C to +85°C
−55°C to +125°C
Electrical Characteristics Over the Operating Range[6]
7C4261/71− 10 7C4261/71− 15 7C4261/71− 25 7C4261/71− 35
Parameter
Description
Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
OH = −2.0 mA
2.4
2.4
2.4
2.4
V
V
V
V
I
VOL
VIH
VIH
Output LOW Voltage VCC = Min.,
OL = 8.0 mA
0.4
0.4
VCC
VCC
0.4
VCC
VCC
0.4
VCC
VCC
I
Input HIGH Voltage
(comm./ind.)
2.0
2.2
VCC
VCC
2.0
2.2
2.0
2.2
2.0
2.2
Input HIGH Voltage
(military)
VIL
IIX
Input LOW Voltage
−0.5
−10
−10
0.8
+10
+10
−0.5
−10
−10
0.8
+10
+10
−0.5
−10
−10
0.8
+10
+10
−0.5
−10
−10
0.8
+10
+10
V
Input Leakage Current VCC = Max.
µA
µA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO< VCC
[7]
ICC1
Active Power Supply
Current
Com’l
Ind/Mil
Com’l
Ind/Mil
35
40
10
15
35
40
10
15
35
40
10
15
35
40
10
15
mA
mA
mA
mA
[8]
ISB
Average Standby
Current
Capacitance[9]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
5
7
pF
pF
COUT
AC Test Loads and Waveforms[10, 11]
R11.1KW
5V
OUTPUT
ALL INPUT PULSES
90%
3.0V
GND
90%
10%
10%
R2
680Ω
C
INCLUDING
JIG AND
SCOPE
L
≤3ns
≤ 3ns
Equivalent to:
THÉVENIN EQUIVALENT
420Ω
OUTPUT
1.91V
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. TA is the “instant on” case temperature.
6. See the last page of this specification for Group A subgroup testing information.
7. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 Mhz, while data inputs switch
at 10 MHz. Outputs are unloaded. ICC1(typical) = (20 mA + (freq – 20 MHz) * (0.7 mA/MHz)).
8. All inputs = VCC – 0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz). All outputs are unloaded.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ
.
11. CL = 5 pF for tOHZ
.
Document #: 38-06015 Rev. *B
Page 6 of 18
CY7C4261
CY7C4271
Switching Characteristics Over the Operating Range
7C4261/71−10 7C4261/71−15 7C4261/71−25 7C4261/71− 35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
tS
Description
Clock Cycle Frequency
100
8
66.7
10
40
15
28.6 MHz
20
tA
Data Access Time
2
10
4.5
4.5
3
2
15
6
2
25
10
10
6
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-up Time
4
tDH
Data Hold Time
0.5
3
1
1
2
tENS
tENH
tRS
Enable Set-up Time
4
6
7
Enable Hold Time
Reset Pulse Width[12]
0.5
10
8
1
1
2
15
10
10
25
15
15
35
20
20
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
8
Reset to Flag and Output Time
Output Enable to Output in Low Z[13]
Output Enable to Output Valid
Output Enable to Output in High Z[13]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
10
15
25
35
0
3
3
0
3
3
0
3
3
0
3
3
7
7
8
8
8
8
8
12
12
15
15
15
15
15
15
20
20
20
20
tOHZ
tWFF
tREF
tPAF
8
10
10
10
10
tPAE
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
18
12
20
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
ns
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06015 Rev. *B
Page 7 of 18
CY7C4261
CY7C4271
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
t
t
WFF
WFF
FF
[14]
t
SKEW1
RCLK
REN1, REN2
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1, REN2
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[15]
SKEW1
t
WCLK
WEN1
WEN2
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06015 Rev. *B
Page 8 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Reset Timing[16]
t
RS
RS
t
t
t
t
RSR
RSS
REN1,
REN2
RSR
RSS
WEN1
t
t
RSR
RSS
[18]
WEN2/LD
t
RSF
RSF
RSF
EF,PAE
FF,PAF
t
t
[17]
O =1
E
Q
Q
8
0 -
OE=0
First Data Word Latency after Reset with Read and Write
WCLK
t
DS
D –D
D (FIRST VALID WRITE)
0
D
1
D
2
D
3
D
4
0
8
t
ENS
[19]
t
WEN1
FRL
WEN2
(if applicable)
t
SKEW1
RCLK
t
REF
EF
t
t
A
A
[20]
REN1,
REN2
Q –Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06015 Rev. *B
Page 9 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
DATA WRITE 2
DATA WRITE 1
D –D
0
8
t
t
ENH
ENH
ENH
t
t
t
ENS
t
t
ENS
WEN1
t
t
ENS
ENH
ENS
WEN2
(if applicable)
[19]
[19]
t
FRL
FRL
RCLK
t
t
t
t
t
SKEW1
REF
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
NO WRITE
DATA READ
Q –Q
0
8
NO WRITE
Full Flag Timing
WCLK
[14]
SKEW1
[14]
SKEW1
t
t
DS
DATA WRITE
t
DATA WRITE
D –D
0
8
t
t
t
WFF
WFF
WFF
FF
WEN1
WEN2
(if applicable)
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN1,
REN2
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
Page 10 of 18
DATA IN OUTPUT REGISTER
Q –Q
0
8
Document #: 38-06015 Rev. *B
CY7C4261
CY7C4271
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN1
t
t
ENS ENH
WEN2
(if applicable)
t
t
ENS ENH
Note
22
PAE
N + 1 WORDS
IN FIFO
Note 23
t
PAE
[21]
ESKEW2
t
t
PAE
RCLK
t
ENS
t
t
ENS ENH
REN1,
REN2
Programmable Almost Full Flag Timing
Note
24
t
t
CLKL
CLKH
WCLK
t
t
ENS ENH
WEN1
WEN2
(if applicable)
Note
25
t
t
t
PAF
ENS ENH
FULL − MWORDS
[26]
PAF
IN FIFO
FULL − (M+1)WORDS
IN FIFO
[27]
t
t
PAF
SKEW2
RCLK
t
ENS
t
t
ENS ENH
REN1,
REN2
Note:
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset= n.
23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW
24. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271.
27.
tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06015 Rev. *B
Page 11 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
WEN1
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
PAF OFFSET
MSB
REN1,
REN2
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q –Q
0
15
Document #: 38-06015 Rev. *B
Page 12 of 18
CY7C4261
CY7C4271
Typical AC and DC Characteristics
NORMALIZED t vs. AMBIENT
A
TEMPERATURE
NORMALIZED t vs. SUPPLY
VOLTAGE
A
1.20
1.60
1.40
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
T =25°C
V
CC
=5.0V
5.00
A
4.00
4.50
5.00
5.50
6.00
−55.00
65.00
125.00
AMBIENT TEMPERATURE( C)
°
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
1.20
1.75
1.50
1.25
1.00
0.75
0.50
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
V
=3.0V
V =3.0V
IN
IN
V
=5.0V
CC
T =25°C
V =5.0V
A
CC
T =25°C
A
f = 28 MHz
f = 28 MHz
5.00
V
=3.0V
IN
4.00
4.50
5.00
5.50
6.00
−55.00
65.00
125.00
20.00 30.00 40.00 50.00 60.00
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE ( C)
°
FREQUENCY (MHz)
Ordering Information
16Kx9 Deep Sync FIFO
Speed
(ns)
Package
Name
Package
Type
Operating
Range
Ordering Code
10
CY7C4261-10AC
CY7C4261-10JC
CY7C4261-10AI
CY7C4261-10JI
CY7C4261-15AC
CY7C4261-15JC
CY7C4261-15AI
CY7C4261-15JI
CY7C4261-25AC
CY7C4261-25JC
CY7C4261-25AI
CY7C4261-25JI
A32
J65
A32
J65
A32
J65
A32
J65
A32
J65
A32
J65
32-Lead Thin Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
15
25
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
Document #: 38-06015 Rev. *B
Page 13 of 18
CY7C4261
CY7C4271
Ordering Information (continued)
16Kx9 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C4261-35AC
35
A32
J65
A32
J65
32-Lead Thin Quad Flatpack
Commercial
CY7C4261-35JC
CY7C4261-35AI
CY7C4261-35JI
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Industrial
32-Lead Plastic Leaded Chip Carrier
32Kx9 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4271-10AC
CY7C4271-10JC
CY7C4271-10AI
CY7C4271-10JI
CY7C4271-15AC
CY7C4271-15JC
CY7C4271-15AI
CY7C4271-15JI
CY7C4271-15LMB
5962-9736101QYA
CY7C4271-25AC
CY7C4271-25JC
CY7C4271-25AI
CY7C4271-25JI
CY7C4271-35AC
CY7C4271-35JC
CY7C4271-35AI
CY7C4271-35JI
A32
J65
A32
J65
A32
J65
A32
J65
L55
L55
A32
J65
A32
J65
A32
J65
A32
J65
32-Lead Thin Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
15
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Ceramic Leaded Chip Carrier
32-Lead Ceramic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Military
25
35
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
Commercial
Industrial
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
VIH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIL Max.
IIX
ICC
ICC1
ISB1
ISB2
IOS
Document #: 38-06015 Rev. *B
Page 14 of 18
CY7C4261
CY7C4271
Switching Characteristics
Parameters
Subgroups
9, 10, 11
tRC
tA
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
tRR
tPR
tDVR
tWC
tPW
tWR
tSD
tHD
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
Document #: 38-06015 Rev. *B
Page 15 of 18
CY7C4261
CY7C4271
Package Diagrams
32-Lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32
51-85063-*B
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
Document #: 38-06015 Rev. *B
Page 16 of 18
CY7C4261
CY7C4271
Package Diagrams (continued)
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06015 Rev. *B
Page 17 of 18
CY7C4261
CY7C4271
Document History Page
Document Title: CY7C4261, CY7C4271 16K/32K X 9 Deep Synchronous FIFOs
Document Number: 38-06015
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106476
122267
127853
09/10/01
12/26/02
08/22/03
SZV
RBI
Changed from Spec number: 38-00658 to 38-06015
*A
Added power-up requirements Maximum Ratings Information
*B
FSG
Switching Waveforms section: fixed misplaced footnote in tA in “First Data
Word Latency after Reset with Read and Write” drawing
Switching Waveforms section: changed tSKEW2 to tSKEW1 (typo) in “Empty
Flag Timing” drawing
Document #: 38-06015 Rev. *B
Page 18 of 18
相关型号：
©2020 ICPDF网 联系我们和版权申明