CY7C4271V-25JCR [CYPRESS]
FIFO, 32KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | CY7C4271V-25JCR |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 32KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32 存储 内存集成电路 先进先出芯片 时钟 |
| 文件： | 总16页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs
Features
Functional Description
• 3.3V operation for low power consumption and easy
The CY7C4261/71/81/91V are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71/81/91V are pin-compatible to the
CY7C42x1V Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261V)
• 32K × 9 (CY7C4271V)
• 64K × 9 (CY7C4281V)
• 128K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
• Low power
— ICC = 25 mA
— ISB = 4 mA
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1 and WEN2/LD are held active, data is continually
written into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enable pins (REN1, REN2). In addition,
the CY7C4261/71/81/91V has an output enable pin (OE). The
read (RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width- Expansion capability
• 32-pin PLCC
• Pin-compatible density upgrade to CY7C42X1V family
• Pin-compatible 3.3V solutions for CY7C4261/71/81/91
D
LogicBlock Diagram
0−8
Pin Configuration
PLCC
Top View
INPUT
REGISTER
4
3
2
1
32 31 30
29
WCLK
WEN1WEN2/LD
D
D
PAF
PAE
RS
1
5
6
7
8
FLAG
28
27
26
0
WEN1
WCLK
WEN2/LD
PROGRAM
REGISTER
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
WRITE
GND
V
9
CC
25
24
23
22
21
CONTROL
REN1
RCLK
REN2
OE
Q
8
10
11
12
13
EF
Q
7
Q
6
Q
5
PAE
PAF
FF
FLAG
LOGIC
Dual Port
RAM Array
16K/32K
14 15 16 17 18 19 20
WRITE
POINTER
READ
64K/128K
x 9
POINTER
RESET
LOGIC
RS
THREE-STATE
READ
CONTROL
REGISTER
OUTPUT
OE
Q
0−8
RCLK
REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06013 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 25, 2003
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Selection Guide
7C4261/71/81/91V-10
7C4261/71/81/91V-15
7C4261/71/81/91V-25
Unit
MHz
ns
Maximum Frequency
100
8
66.7
10
15
4
40
15
25
6
Maximum Access Time
Minimum Cycle Time
10
3.5
0
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
0
1
ns
8
10
25
30
15
25
ns
Active Power Supply
Commercial
25
mA
Current (ICC1
)
Industrial
CY7C4261V
16K x 9
CY7C4271V
32K x 9
CY7C4281V
64K x 9
CY7C4291V
128K x 9
Density
Package
32-pin PLCC
32-pin PLCC
32-pin PLCC
32-pin PLCC
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
Q0−8
Data Outputs
Write Enable 1
WEN1
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
REN1, REN2 Read Enable
Inputs
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
PAF
RS
Programmable
Almost Full
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Document #: 38-06013 Rev. *A
Page 2 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
data in the output register will be available to the Q0-8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
Functional Description (continued)
The CY7C4261/71/81/91V provides four status pins: Empty,
Full, Programmable Almost Empty, and Programmable Almost
Full. The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty +7 and Full -7.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0-8 outputs
even after additional reads occur.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
All configurations are fabricated using an advanced 0.35m
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
Architecture
The CY7C4261/71/81/91V consists of an array of 16K, 32K,
64K, or 128K words of nine bits each (implemented by a
dual-port array of SRAM cells), a read pointer, a write pointer,
control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2,
RS), and flags (EF, PAE, PAF, FF).
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0–8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 9-bit offset registers
contained in the CY7C4261/71/81/91V for writing or reading
data to these registers.
FIFO Operation
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full offset
LSB register, and full offset MSB register, respectively, when
WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the registers sizes and default values for the various device
types.
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D0–8 pins is written
into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN1 and REN2 signals are active LOW
and EF is active HIGH, data in the FIFO memory will be
presented on the Q0-8 outputs. New data will be presented on
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up tENS before RCLK for it to be a
valid read function. WEN1 and WEN2 must occur tENS before
WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
Document #: 38-06013 Rev. *A
Page 3 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
16k x 9
32k x 9
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value= 007h
Programmable Flag (PAE, PAF) Operation
6
5
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
(MSB)
(MSB)
Default Value= 000h
Default Value = 000h
0
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value= 007h
Table 1. Writing the Offset Registers[1]
0
5
6
LD
WEN
WCLK
Selection
(MSB)
Default Value= 000h
(MSB)
Default Value= 000h
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
64k x 9
128k x 9
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
Full Offset (MSB)
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value= 007h
0
1
1
0
No Operation
7
Write Into FIFO
(MSB)
(MSB)
Default Value = 000h
Default Value = 000h
1
1
No Operation
7
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value= 007h
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
(MSB)
(MSB)
Default Value = 000h
Default Value = 000h
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as mand determines the operation of PAF. PAE is synchronized to
the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261V (16k – m), CY7C4271V
(32k – m), CY7C4281V (64k - m) and CY7C4291V (128k – m).
PAF is set HIGH by the LOW-to-HIGH transition of WCLK
when the number of available memory locations is greater
than m.
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06013 Rev. *A
Page 4 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Table 2. Status Flags
Number of Words in FIFO
CY7C4271V CY7C4281V
CY7C4261V
CY7C4291V
1 to n[2]
FF PAF PAE EF
0
0
0
0
H
H
H
H
H
H
L
L
L
H
H
1 to n[2]
1 to n[2]
1 to n[2]
(n+1) to (1638 − (m+1)) (n+1) to (32768 − (m+1)) (n+1) to (65536 − (m+1)) (n+1) to (131072−
H
(m+1))
(16384 − m)[3] to 16383 (32768 − m)[3] to 32767 (65536 − m)[3] to 65535 (131072 − m)[3] to
H
L
L
L
H
H
H
H
131071
16384
32768
65536
131072
Width-Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EFand FF). The partial status flags (PAE and PAF) can
be detected from any one device. Figure 2 demonstrates a 18-bit
word width by using two CY7C42x1Vs. Any word width can be
attained by adding additional CY7C42x1Vs.
The CY7C4261/71/81/91V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty, Full, PAE,
and PAF are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state of
WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is
exclusively updated by each rising edge of WCLK.
When the CY7C42x1V is in a Width-Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN1 and REN2. EF is synchronized to RCLK, i.e.,
it is exclusively updated by each rising edge of RCLK.
RESET(RS)
RESET(RS)
DATAIN (D)
18
9
9
READCLOCK(RCLK)
READENABLE1 (REN1)
OUTPUT ENABLE(OE)
WRITECLOCK(WCLK)
WRITE ENABLE1(WEN1)
WRITE ENABLE2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAE)
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
EMPTY FLAG (EF) #1
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
EMPTY FLAG (EF) #2
DATA OUT (Q)
EF
FF
FF
EF
9
18
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 16k/32k/64k/128k x 9 Low-Voltage Deep Sync FIFO Memory
Used in a Width-Expansion Configuration
Notes:
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06013 Rev. *A
Page 5 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
DC Input Voltage ................................... –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ...................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +3.6V
[4]
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
DC Voltage Applied to Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
3.3V ±300 mV
3.3V ±300 mV
−40°C to +85°C
Electrical Characteristics Over the Operating Range
7C4261/71/81/91V- 7C4261/71/81/91V- 7C4261/71/81/91V-
10 15 25
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH
Voltage
VCC = Min., IOH = −1.0 mA
2.4
2.4
2.4
V
V
CC = 3.0V, IOH = −2.0 mA
VCC = Min., IOL = 4.0 mA
CC = 3.0V, IOL = 8.0 mA
VOL
VIH
VIL
IIX
Output LOW
Voltage
.04
VCC
0.8
0.4
VCC
0.8
0.4
VCC
0.8
V
V
V
Input HIGH
Voltage
2.0
−0.5
−10
−10
2.0
−0.5
−10
−10
2.0
−0.5
−10
−10
Input LOW
Voltage
V
Input Leakage VCC = Max.
Current
+10
+10
25
+10
+10
+10
+10
25
µA
µA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO< VCC
[5]
ICC1
Active Power
Supply Current
Com’l
Ind
25
30
4
mA
mA
mA
mA
[6]
ISB
Average
Standby Current
Com’l
Ind
4
4
4
Capacitance[7]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
5
7
pF
pF
COUT
AC Test Loads and Waveforms (-15 and -25)[8, 9]
R1=330Ω
3.3V
All Input Pulses
OUTPUT
3.0V
GND
90%
10%
90%
10%
C
L
R2=510Ω
INCLUDING
JIG AND
≤ 3 ns
≤ 3 ns
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2.0V
Notes:
4. VCC Range for commercial -10 ns is 3.3V ±150mV.
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency of 20 MHz, while data inputs switch
at 10 MHz. Outputs are unloaded.)
6. All inputs = VCC − 0.2V, except WCLK and RCLK (which are at frequency = 0 MHz). All outputs are unloaded.
7. Tested initially and after any design or process changes that may affect these parameters.
8. CL = 30 pF for all AC parameters except for tOHZ
.
9. CL = 5 pF for tOHZ
.
Document #: 38-06013 Rev. *A
Page 6 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
AC Test Loads and Waveforms (continued) (-10)
VCC/2
All Input Pulses
50Ω
3.0V
GND
90%
10%
90%
10%
I/O
Z0=50Ω
≤
3 ns
≤ 3 ns
Switching Characteristics Over the Operating Range
7C4261/71/81/91V- 7C4261/71/81/91V- 7C4261/71/81/91V-
10 15 25
Parameter
tS
Description
Clock Cycle Frequency
Min.
Max.
100
8
Min.
Max.
66.7
10
Min.
Max.
40
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
Data Access Time
2
10
4.5
4.5
3.5
0
2
15
6
2
25
10
10
6
15
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-up Time
4
tDH
Data Hold Time
0
1
tENS
tENH
tRS
Enable Set-up Time
3.5
0
4
6
Enable Hold Time
Reset Pulse Width[10]
0
1
10
8
15
10
10
25
15
15
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
8
Reset to Flag and Output Time
Output Enable to Output in Low Z[11]
Output Enable to Output Valid
Output Enable to Output in High Z[11]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
10
15
25
0
3
3
0
3
3
0
3
3
7
7
8
8
8
8
10
8
12
12
15
15
15
15
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
10
10
10
10
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
18
tSKEW2
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and
Almost-Full Flag
10
15
ns
Notes:
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
Document #: 38-06013 Rev. *A
Page 7 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
t
t
WFF
WFF
FF
[12]
t
SKEW1
RCLK
REN1, REN2
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1, REN2
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[13]
t
SKEW1
WCLK
WEN1
WEN2
Notes:
12. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
13. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06013 Rev. *A
Page 8 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
[14]
Reset Timing
t
RS
RS
t
t
t
t
RSR
RSS
REN1,
REN2
RSR
RSS
WEN1
t
t
RSR
RSS
[16]
WEN2/LD
t
t
t
RSF
RSF
RSF
EF,PAE
PAF
FF,
[15]
O =1
E
Q
Q
8
0 −
OE=0
Notes:
14. The clocks (RCLK, WCLK) can be free-running during reset.
15. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
Document #: 38-06013 Rev. *A
Page 9 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
First Data Word Latency after Reset with Read and Write
WCLK
t
DS
D –D
D (FIRST VALID WRITE)
0
D
1
D
2
D
3
D
4
0
8
t
ENS
[17]
t
WEN1
FRL
WEN2
(if applicable)
t
SKEW1
RCLK
EF
t
REF
[18]
t
A
t
A
REN1,
REN2
Q –Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
Notes:
17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
18. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06013 Rev. *A
Page 10 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
DATA WRITE 2
DATA WRITE 1
D –D
0
8
t
t
ENH
ENH
ENH
t
t
t
ENS
t
t
ENS
WEN1
t
t
ENS
ENH
ENS
WEN2
(if applicable)
[17]
[17]
t
FRL
FRL
RCLK
t
t
t
REF
t
t
SKEW1
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
DATA READ
Q –Q
0
8
Document #: 38-06013 Rev. *A
Page 11 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
WCLK
[12]
[12]
t
t
DS
DATA WRITE
t
SKEW1
SKEW1
DATA WRITE
D –D
0
8
t
t
t
WFF
WFF
WFF
FF
WEN1
WEN2
(if applicable)
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN1,
REN2
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
8
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN1
t
t
ENS
ENH
WEN2
(if applicable)
20
Note
t
t
ENS
ENH
PAE
N + 1 WORDS
IN FIFO
Note21
t
PAE
[19]
t
t
PAE
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Notes:
19. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
20. PAE offset = n.
21. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
Document #: 38-06013 Rev. *A
Page 12 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
22
Note
t
t
CLKL
CLKH
WCLK
t
t
ENS ENH
WEN1
23
WEN2
(if applicable)
Note
t
t
t
PAF
ENS ENH
(FULL −M) WORDS
PAF
[24]
IN FIFO
FULL − (M+1)WORDS
IN FIFO
[25]
t
t
PAF
SKEW2
RCLK
t
ENS
t
t
ENS ENH
REN1,
REN2
WriteProgrammable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
WEN1
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
22. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
23. PAF offset = m.
24. 16K − m words for CY7C4261V, 32K – m words for CY7C4271V, 64K − m words for CY7C4281V, and 128K − m words for CY4291V.
25.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06013 Rev. *A
Page 13 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
PAF OFFSET
MSB
REN1,
REN2
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q –Q
0
15
Ordering Information
16Kx9 Low-voltage Deep Sync FIFO
Speed
(ns)
10
Package
Name
Operating
Ordering Code
CY7C4261V-10JC
Package Type
Range
Commercial
Commercial
Industrial
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
15
CY7C4261V-15JC
CY7C4261V-15JI
CY7C4261V-25JC
25
Commercial
32Kx9 Low-voltage Deep Sync FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
10
CY7C4271V-10JC
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
15
CY7C4271V-15JC
CY7C4271V-15JI
CY7C4271V-25JC
25
Commercial
64kx9 Low-voltage Deep Sync FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
10
CY7C4281V-10JC
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
15
CY7C4281V-15JC
CY7C4281V-15JI
CY7C4281V-25JC
25
Commercial
128kx9 Low-voltage Deep Sync FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
10
CY7C4291V-10JC
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
15
CY7C4291V-15JC
CY7C4291V-15JI
CY7C4291V-25JC
25
Commercial
Document #: 38-06013 Rev. *A
Page 14 of 16
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Package Diagram
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
Deep Sync is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-06013 Rev. *A
Page 15 of 16
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Document History Page
Document Title: CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16K/32K/64K/128K/X9 Low-Voltage Deep Sync FIFO
Document Number: 38-06013
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
106474
127858
09/15/01
09/04/03
SZV
FSG
Changed Spec number from 38-00656 to 38-06013
*A
Changed: tSKEW2 to tSKEW1 in Switching Waveforms “Empty Flag Timing” diagram
Fixed flag timing diagram in Switching Waveforms section
Document #: 38-06013 Rev. *A
Page 16 of 16
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