CY7C4291-25JC [CYPRESS]
64K/128K x 9 Deep Sync FIFOs; 64K / 128K ×9深度的FIFO同步型号: | CY7C4291-25JC |
厂家: | CYPRESS |
描述: | 64K/128K x 9 Deep Sync FIFOs |
文件: | 总16页 (文件大小:432K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C4281 CY7C429164K/128K
x 9 Deep Sync FIFOs
CY7C4281
CY7C4291
64K/128K x 9 Deep Sync FIFOs
• Pb-Free Packages Available
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
The CY7C4281/91 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
• 64K × 9 (CY7C4281)
• 128K × 9 (CY7C4291)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— ICC = 40 mA
— ISB = 2 mA
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
• Fully asynchronous and simultaneous read and write
operation
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Pin-compatible density upgrade to CY7C42X1
family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
D
0–8
Pin Configuration
Logic Block Diagram
INPUT
REGISTER
PLCC
Top View
WCLK WEN1 WEN2/LD
4
3
2
1
32 31 30
29
D
D
PAF
PAE
RS
1
5
6
FLAG
PROGRAM
REGISTER
28
27
26
0
WEN1
WCLK
WEN2/LD
7
8
9
WRITE
CONTROL
CY7C4281
CY7C4291
GND
REN1
RCLK
REN2
OE
V
CC
25
24
23
22
21
Q
8
Q
7
10
11
12
13
EF
PAE
PAF
FF
FLAG
LOGIC
Q
6
Q
5
Dual Port
14 15 16 17 18 19 20
RAMARRAY
64K x 9
128K x 9
WRITE
POINTER
READ
POINTER
RESET
LOGIC
RS
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
OE
Q
0–8
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06007 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 2, 2005
CY7C4281
CY7C4291
Pin Definitions
Signal Name
Description
I/O
Description
D0–8
Data Inputs
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
Q0−8
Data Outputs
Write Enable 1
WEN1
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
REN1, REN2 Read Enable
Inputs
I
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is
HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the
programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO. PAE is synchronized to RCLK.
PAF
RS
Programmable
Almost Full
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
CY7C4281
64k x 9
CY7C4291
128k x 9
Density
Package
32-pin PLCC
32-pin PLCC
Selection Guide
7C4281/91-10
7C4281/91-15
7C4281/91-25
Unit
MHz
ns
Maximum Frequency
100
8
66.7
10
15
4
40
15
25
6
Maximum Access Time
Minimum Cycle Time
10
3
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
0.5
8
1
1
ns
10
40
15
40
ns
Active Power Supply Current (ICC1
)
Commercial
Industrial
40
45
mA
Document #: 38-06007 Rev. *C
Page 2 of 16
CY7C4281
CY7C4291
Write Enable 1 (WEN1) — If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Functional Description (continued)
The CY7C4281/91 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost
Full. The Almost Empty/Almost Full flags are programmable to
single-word granularity. The programmable flags default to
Empty+7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
Write Enable 2/Load (WEN2/LD) — This is a dual-purpose
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Architecture
The CY7C4281/91 consists of an array of 64K to 128K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF,
PAE, PAF, FF).
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four nine-bit offset
registers contained in the CY7C4281/4291 for writing or
reading data to these registers.
Resetting the FIFO
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the registers sizes and default values for the various device
types.
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0–8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and FF is active HIGH, data present on the D0–8 pins is written
into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN1 and REN2 signals are active LOW
and EF is active HIGH, data in the FIFO memory will be
presented on the Q0–8 outputs. New data will be presented on
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up tENS before RCLK for it to be
a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
64K ×9
128K×9
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value= 007h
7
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
(MSB)
Default Value = 000h
(MSB)
Default Value= 000h
7
7
7
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value= 007h
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–8 outputs
even after additional reads occur.
(MSB)
Default Value = 000h
(MSB)
Default Value= 000h
Figure 1. Offset Register Location and Default Values
Document #: 38-06007 Rev. *C
Page 3 of 16
CY7C4281
CY7C4291
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in
sequence.
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4281 (64K-m) and CY7C4291
(128K-m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 2. Status Flags
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Number of Words in FIFO
CY7C4281
CY7C4291
FF PAF PAE EF
0
0
H
H
H
H
L
H
H
H
L
L
L
L
1 to n[2]
1 to n[2]
H
H
H
H
Programmable Flag (PAE, PAF) Operation
(n+1) to (65536 −(m+1)) (n+1) to (131072−(m+1))
(65536 − m)[3] to 65535 131072 −m)[3] to131071
H
H
H
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
65536
131072
L
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
Table 1. Writing the Offset Registers
WCLK[1]
LD
WEN
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Full Offset (MSB)
0
1
1
0
No Operation
Write Into FIFO
Flag Operation
The CY7C4281/91 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty, Full, PAE, and PAF
are synchronous.
1
1
No Operation
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK,
i.e., it is exclusively updated by each rising edge of WCLK.
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n + 1) or greater unread words.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06007 Rev. *C
Page 4 of 16
CY7C4281
CY7C4291
RESET(RS)
RESET(RS)
DATAIN (D)
18
9
9
READCLOCK(RCLK)
WRITECLOCK(WCLK)
READENABLE1 (REN1)
WRITE ENABLE1(WEN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
WRITE ENABLE2/LOAD
(WEN2/LD)
CY7C4281/91
CY7C4281/91
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
EMPTY FLAG (EF) #2
EF
FF
FF
EF
DATA OUT (Q)
9
18
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
Document #: 38-06007 Rev. *C
Page 5 of 16
CY7C4281
CY7C4291
DC Input Voltage....................................... −0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .......................................−65°C to +150°C
Ambient Temperature with
Power Applied....................................................−55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Latch-up Current.....................................................> 200 mA
Operating Range[4]
Range
Commercial
Industrial[5]
Ambient Temperature
0°C to +70°C
VCC
DC Voltage Applied to Outputs
in High-Z State............................................−0.5V to VCC + 0.5V
5V ± 10%
5V ± 10%
−40°C to +85°C
Electrical Characteristics Over the Operating Range
7C42X1−10
7C42X1−15
7C42X1−25
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
VOL
VIH
VIL
VCC = Min., IOH = −2.0 mA 2.4
2.4
2.4
V
VCC = Min., IOL = 8.0 mA
0.4
VCC
0.8
0.4
VCC
0.8
0.4
VCC
0.8
V
V
2.0
2.0
−0.5
−10
−10
2.0
−0.5
−10
−10
Input LOW Voltage
−0.5
V
IIX
Input Leakage Current
Output OFF, High Z Current
VCC = Max.
−10
+10
+10
+10
+10
+10
+10
µA
µA
IOZL
IOZH
OE > VIH, VSS < VO< VCC −10
[6]
ICC1
Active Power Supply Current
Average Standby Current
Com’l
Ind
40
45
2
40
45
2
40
45
2
mA
mA
mA
mA
[7]
ISB
Com’l
Ind
2
Capacitance[8]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
5
7
pF
pF
COUT
AC Test Loads and Waveforms[9, 10]
R11.1KΩ
5V
ALL INPUT PULSES
OUTPUT
3.0V
90%
10%
90%
10%
R2
680Ω
C
L
GND
INCLUDING
JIG AND
≤ 3 ns
≤ 3 ns
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
420Ω
OUTPUT
1.91V
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. T is the “instant on” case temperature.
A
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 MHz, while data inputs switch
at 10 MHz. Outputs are unloaded. Icc1(typical) = (20 mA + (freq – 20 MHz)*(0.7 mA/MHz)).
7. All inputs = V – 0.2V, except WCLK and RCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
8. Tested initially and after any design or process changes that may affect these parameters.
9. C = 30 pF for all AC parameters except for t
.
L
OHZ
10. C = 5 pF for t
.
L
OHZ
Document #: 38-06007 Rev. *C
Page 6 of 16
CY7C4281
CY7C4291
Switching Characteristics Over the Operating Range
7C42X1-10
7C42X1-15
7C42X1-25
Parameter
tS
Description
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Unit
100
8
66.7
10
40
15
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
Data Access Time
2
10
4.5
4.5
3
2
15
6
2
25
10
10
6
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-up Time
4
tDH
Data Hold Time
0.5
3
1
1
tENS
tENH
tRS
Enable Set-up Time
4
6
Enable Hold Time
Reset Pulse Width[11]
0.5
10
8
1
1
15
10
10
25
15
15
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
8
Reset to Flag and Output Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
Output Enable to Output in High Z[12]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
10
15
25
0
3
3
0
3
3
0
3
3
7
7
8
8
8
8
8
12
12
15
15
15
15
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
8
10
10
10
10
Skew Time between Read Clock and Write Clock for
Empty Flag and Full Flag
5
6
10
18
tSKEW2
Skew Time between Read Clock and Write Clock for
Almost-Empty Flag and Almost-Full Flag
10
15
ns
Notes:
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
Document #: 38-06007 Rev. *C
Page 7 of 16
CY7C4281
CY7C4291
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
t
t
WFF
WFF
FF
[13]
t
SKEW1
RCLK
REN1, REN2
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1, REN2
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[14]
SKEW1
t
WCLK
WEN1
WEN2
Notes:
13. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
SKEW1
between the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
14. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
SKEW1
between the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW2
Document #: 38-06007 Rev. *C
Page 8 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
Reset Timing[15]
t
RS
RS
t
t
t
t
RSR
RSS
REN1,
REN2
RSR
RSS
WEN1
t
t
RSR
RSS
WEN2/LD [17]
t
RSF
RSF
RSF
EF,PAE
FF,PAF
Q0–Q8
t
t
[16]
OE = 1
OE = 0
Notes:
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Document #: 38-06007 Rev. *C
Page 9 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
First Data Word Latency after Reset with Read and Write
WCLK
t
DS
D –D
D
0
(FIRST VALID WRITE)
D
1
D
2
D
3
D
4
0
8
t
ENS
[18]
t
WEN1
FRL
WEN2
(if applicable)
t
SKEW1
RCLK
EF
t
REF
[19]
t
A
t
A
REN1,
REN2
Q –Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
Notes:
18. When t
> minimum specification, t
(maximum) = t
+ t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
SKEW1
FRL
CLK
SKEW2
SKEW1
FRL
CLK
SKEW1 CLK
+ t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
19. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06007 Rev. *C
Page 10 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
DATA WRITE 2
DATA WRITE 1
D –D
0
8
t
t
ENH
ENH
t
ENS
WEN1
t
t
ENS
t
t
ENS
ENH
ENH
t
ENS
WEN2
(if applicable)
[18]
[18]
t
t
FRL
FRL
RCLK
t
t
t
t
t
SKEW2
REF
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
DATA READ
Q –Q
0
8
Document #: 38-06007 Rev. *C
Page 11 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
Full Flag Timing
NO WRITE
NO WRITE
WCLK
[13]
SKEW1
[13]
t
t
DS
DATA WRITE
t
SKEW1
DATA WRITE
D –D
0
8
t
t
t
WFF
WFF
WFF
FF
WEN1
WEN2
(if applicable)
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN1,
REN2
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
8
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
t
t
t
ENS
ENH
WEN1
WEN2
(if applicable)
t
ENS
[20]
ENH
Note 21
PAE
N + 1 WORDS
IN FIFO
Note 22
t
PAE
t
t
PAE
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Notes:
20. t
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
SKEW2
WCLK and the rising RCLK is less than t
, then PAE may not change state until the next RCLK.
SKEW2
21. PAE offset = n.
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n −1) words in the FIFO when PAE goes LOW.
Document #: 38-06007 Rev. *C
Page 12 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
Note 23
WCLK
t
t
ENS ENH
WEN1
WEN2
(if applicable)
Note 24
t
t
t
PAF
ENS ENH
(FULL −M) WORDS
IN FIFO[25]
PAF
FULL − (M+1)WORDS
IN FIFO
[26]
t
t
PAF
SKEW2
RCLK
t
ENS
t
t
ENS ENH
REN1,
REN2
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
WEN1
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
23. If a write is performed on this rising edge of the write clock, there will be Full − (m − 1) words of the FIFO when PAF goes LOW.
24. PAF offset = m.
25. 16,384 − m words for CY7C4281, 32,768 − m words for CY4291.
26. t
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge
SKEW2
of RCLK and the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK.
SKEW2
Document #: 38-06007 Rev. *C
Page 13 of 16
CY7C4281
CY7C4291
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
PAF OFFSET
MSB
REN1,
REN2
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q –Q
0
15
Ordering Information
64K x 9 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4281-10JC
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Industrial
CY7C4281-10JI
CY7C4281-15JC
CY7C4281-25JC
15
25
Commercial
Commercial
128K x 9 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4291-10JC
CY7C4291-10JXC
CY7C4291-10JI
CY7C4291-15JC
CY7C4291-15JXC
CY7C4291-25JC
J65
J65
J65
J65
J65
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Industrial
15
25
Commercial
32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial
32-Lead Plastic Leaded Chip Carrier
Commercial
Document #: 38-06007 Rev. *C
Page 14 of 16
CY7C4281
CY7C4291
Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65
32-Lead Pb-Free Plastic Leaded Chip Carrier J65
51-85002-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06007 Rev. *C
Page 15 of 16
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C4281
CY7C4291
Document History Page
Document Title: CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs
Document Number: 38-06007
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106468
122259
127854
07/12/01
12/26/02
08/22/03
SZV
RBI
Change from Spec number: 38-00587 to 38-06007
*A
Power up requirements added to Operating Range Information
*B
FSG
Removed Preliminary
Fixed empty flag timing diagram
Switching waveform diagram typo fixed
*C
386004
See ECN
ESH
Added Pb-Free logo to top of front page
Added CY7C4291-10JXC, CY7C4291-15JXC to ordering information
Document #: 38-06007 Rev. *C
Page 16 of 16
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