CY7C43684AV-15AI_技术文档

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

3.3V 1K/4K/16K x36 x2 Bidirectional

Synchronous FIFO w/ Bus Matching

• Fully asynchronous and simultaneous read and write

operation permitted

Features

• 3.3Vhigh-speed,low-power,bidirectional,First-InFirst-

Out (FIFO) memories w/ bus matching capabilities

• 1K x 36 x 2 (CY7C43644AV)

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and

Almost Empty flags

• 4K x 36 x 2 (CY7C43664AV)

• Retransmit function

• 16K x 36 x 2 (CY7C43684AV)

• 0.25-micron CMOS for optimum speed/power

• Standard or FWFT user selectable mode

• Partial Reset

• High-speed 133-MHz operation (7.5-ns read/write cycle

times)

• Low power

— I_CC= 60 mA

— I_SB= 10 mA

• Big or Little Endian format for word or byte bus sizes

• 128-Pin TQFP packaging

• Easily expandable in width and depth

Logic Block Diagram

MBF1

CLKA

Mail1

Register

CSA

Port A

Control

Logic

CLKB

CSB

W/RA

ENA

MBA

RT2

1K/4K/16K

x36

Dual Ported

Memory

W/RB

Port B

Control

Logic

ENB

MBB

RTI

BE

(FIFO 1)

BM

SIZE

MRS1

PRS1

FIFO1,

Mail1

Reset

Logic

Write

Pointer

Read

Pointer

FFA/IRA

AFA

Status

Flag Logic

EFB/ORB

AEB

36

SPM

FS0/SD

FS1/SEN

B_0–35

Timing

Mode

Programmable

Flag Offset

Registers

BE/FWFT

36

A_0–35

Status

Flag Logic

FFB/IRB

AFB

EFA/ORA

AEA

Read

Pointer

Write

Pointer

FIFO1,

Mail1

Reset

Logic

MRS2

PRS2

1K/4K/16K

x36

Dual Ported

Memory

(FIFO 2)

Mail2

Register

MBF2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06025 Rev. **

Revised March 27, 2001

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Pin Configuration^[1]

TQFP

Top View

W/RA

ENA

CLKA

GND

A₃₅

1

102

CLKB

PRS2

V_CC

2

3

101

100

99

4

5

6

7

B₃₅

B₃₄

B₃₃

B₃₂

GND

NC

98

97

96

95

A₃₄

A₃₃

A₃₂

8

9

V_CC

A₃₁

94

93

10

11

12

B₃₁

B₃₀

B₂₉

A₃₀

92

91

90

GND

A₂₉

A₂₈

A₂₇

A₂₆

A₂₅

A₂₄

A₂₃

13

14

B₂₈

B₂₇

B₂₆

RT1

89

88

15

16

17

CY7C43644AV

87

86

85

B₂₅

B₂₄

BM

18

19

CY7C43664AV

CY7C43684AV

84

83

BE/FWFT

GND

A₂₂

20

21

22

23

GND

B₂₃

B₂₂

B₂₁

B₂₀

B₁₉

B₁₈

GND

B₁₇

B₁₆

82

81

80

79

V_CC

A₂₁

24

25

A₂₀

78

77

A₁₉

26

27

28

29

30

31

32

A₁₈

76

75

74

GND

A₁₇

A₁₆

A₁₅

A₁₄

A₁₃

RT2

A₁₂

SIZE

V_CC

73

72

B₁₅

B₁₄

B₁₃

B₁₂

GND

B₁₁

B₁₀

71

70

69

33

34

68

67

66

65

35

36

37

38

GND

A₁₁

A₁₀

Note:

1. Pin-compatible to IDT7236x4 family.

Document #: 38-06025 Rev. **

Page 2 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

access that word (along with all other words residing in mem-

ory). In the First-Word Fall-Through mode (FWFT), the first

long-word (36-bit wide) written to an empty FIFO appears au-

tomatically on the outputs, no read operation required (never-

theless, accessing subsequent words does necessitate a for-

mal read request). The state of the BE/FWFT pin during FIFO

operation determines the mode in use.

Functional Description

The CY7C436X4AV is a monolithic, high-speed, low-power,

CMOS Bidirectional Synchronous FIFO memory which sup-

ports clock frequencies up to 133 MHz and has read access

times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-

port SRAM FIFOs on board each chip buffer data in opposite

directions. FIFO data on Port B can be input and output in

36-bit, 18-bit, or 9-bit formats with a choice of Big or Little En-

dian configurations.

Each FIFO has a combined Empty/Output Ready flag (EFA/

ORA and EFB/ORB) and a combined Full/Input Ready flag

(FFA/IRA and FFB/IRB). The EF and FF functions are selected

in the CY Standard mode. EF indicates whether the memory

is empty and FF indicates whether the FIFO memory is full.

The IR and OR functions are selected in the First-Word Fall-

Through mode. IR indicates whether or not the FIFO has avail-

able memory locations. OR shows whether the FIFO has data

available for reading or not. It marks the presence of valid data

on the outputs.

The CY7C436X4AV is a synchronous (clocked) FIFO, mean-

ing each port employs a synchronous interface. All data trans-

fers through a port are gated to the LOW-to-HIGH transition of

a port clock by enable signals. The clocks for each port are

independent of one another and can be asynchronous or co-

incident. The enables for each port are arranged to provide a

simple bidirectional interface between microprocessors and/or

buses with synchronous control.

Each FIFO has a programmable Almost Empty flag (AEA and

AEB) and a programmable Almost Full flag (AFA and AFB).

AEA and AEB are asserted when a selected number of words

written to FIFO memory achieve a predetermined “almost

empty state.” AFA and AFB are asserted when a selected

number of words written to the memory achieve a predeter-

mined “almost full state.” ^[2]

Communication between each port may bypass the FIFOs via

two mailbox registers. The mailbox registers’ width matches

the selected Port B bus width. Each mailbox register has a flag

(MBF1 and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436X4AV: Master

Reset and Partial Reset. Master Reset initializes the read and

write pointers to the first location of the memory array, config-

ures the FIFO for Big or Little Endian byte arrangement and

selects serial flag programming, parallel flag programming, or

one of the three possible default flag offset settings, 8, 16, or

64. Each FIFO has its own independent Master Reset pin,

MRS1 and MRS2.

IRA, IRB, AFA, and AFB are synchronized to the port clock that

writes data into its array. ORA, ORB, AEA, and AEB are syn-

chronized to the port clock that reads data from its array. Pro-

grammable offset for AEA, AEB, AFA, and AFB are loaded in

parallel using Port A or in serial via the SD input. Three default

offset settings are also provided. The AEA and AEB threshold

can be set at 8, 16, or 64 locations from the empty boundary

and AFA and AFB threshold can be set at 8, 16, or 64 locations

from the full boundary. All these choices are made using the

FS0 and FS1 inputs during Master Reset.

Partial Reset also sets the read and write pointers to the first

location of the memory. Unlike Master Reset, any settings ex-

isting prior to Partial Reset (i.e., programming method and par-

tial flag default offsets) are retained. Partial Reset is useful

since it permits flushing of the FIFO memory without changing

any configuration settings. Each FIFO has its own, indepen-

dent Partial Reset pin, PRS1 and PRS2.

Two or more devices may be used in parallel to create wider

data paths. A Retransmit feature is available on these devices.

The CY7C436X4AV FIFOs are characterized for operation

from 0°C to 70°C commercial, and from –40°C to 85°C indus-

trial. Input ESD protection is greater than 2001V, and latch-up

is prevented by the use of guard rings.

The CY7C436X4AV have two modes of operation: In the CY

Standard mode, the first word written to an empty FIFO is de-

posited into the memory array. A read operation is required to

Selection Guide

CY7C43644/64/84AV

−7

133

6

−10

−15

Maximum Frequency (MHz)

Maximum Access Time (ns)

Minimum Cycle Time (ns)

100

8

66.7

10

15

5

7.5

3

10

4

Minimum Data or Enable Set-Up (ns)

Minimum Data or Enable Hold (ns)

Maximum Flag Delay (ns)

0

6

8

10

60

Active Power Supply

Current (I_CC1) (mA)

Commercial

Industrial

60

Document #: 38-06025 Rev. **

Page 3 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

CY7C43644AV

1K x 36 x2

CY7C43664AV

4K x 36 x2

CY7C43684AV

16K x 36 x2

128 TQFP

Density

Package

128 TQFP

Pin Definitions

Signal Name

Description

I/O

Function

A_0–35

AEA

Port A Data

I/O 36-bit bidirectional data port for side A.

Port A Almost

Empty Flag

O

Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number

of words in FIFO2 is less than or equalto thevalue in the Almost Empty A offset register,

X2. ^[2]

AEB

AFA

AFB

Port B Almost

Empty Flag

Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number

of words in FIFO1 is less than or equalto thevalue in the Almost Empty B offset register,

X1. ^[2]

Port A Almost

Full Flag

Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset

register, Y1. ^[2]

Port B Almost

Full Flag

Programmable Almost Full flag synchronized to CLKB. It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset

register, Y2. ^[2]

B_0–35

Port B Data

I/O 36-bit bidirectional data port for side B.

I

BE/FWFT

Big Endian/

This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian

operation. In this case, depending on the bus size, the most significant byte or word on

Port A is transferred to Port B first for A-to-B data flow. For data flowing from port B to

Port A, the first word/byte written to Port B will come out as the most significant word/

byte on port A. On the other hand, a LOW on BE will select Little Endian operation. In

this case, the least significant byte or word on Port A is transferred to Port B first for A-

to-B data flow. Similarly, the first word/byte written into port B will come out as the least

significant word/byte on Port A for B-to-A data flow. After Master Reset, this pin selects

the timing mode. A HIGH on BE/FWFT selects CY Standard mode, a LOW selects

First-Word Fall-Through mode. Once the timing mode has been selected, the level on

this pin must be static throughout device operation.

First-Word Fall-

Through Select

BM

Bus Match

Select (Port A)

I

A HIGH on this pin enables either byte or word bus width on Port B, depending on the

state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to

select the bus size and endian arrangement for Port B. The level of BM must be static

throughout device operation.

CLKA

CLKB

Port A Clock

Port B Clock

I

CLKA is a continuous clock that synchronizes all data transfers through Port A and can

be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all

synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through Port B and can

be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all

synchronized to the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip

Select

I

CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A_0–35are in the high-impedance state when CSA is HIGH.

CSB

Port B Chip

Select

CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B_0–35are in the high-impedance state when CSB is HIGH.

EFA/ORA

Port A Empty/

Output Ready

Flag

O

This is a dual-function pin. In the CY Standard mode, the EFA function is selected. EFA

indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

function is selected. ORA indicates the presence of valid data on A_0–35outputs, avail-

able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.

EFB/ORB

Port B Empty/

Output Ready

Flag

O

This is a dual-function pin. In the CY Standard mode, the EFB function is selected. EFB

indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB

function is selected. ORB indicates the presence of valid data on B_0–35outputs, avail-

able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.

Note:

2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be

asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to “Designing

with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.

Document #: 38-06025 Rev. **

Page 4 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Pin Definitions (continued)

Signal Name

Description

I/O

Function

ENA

Port A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data

on Port A.

ENB

Port B Enable

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data

on Port B.

FFA/IRA

PortA Full/Input

Ready Flag

O

This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA

indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function

is selected. IRAindicateswhetherornot thereis spaceavailablefor writingtotheFIFO1

memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

FFB/IRB

PortB Full/Input

Ready Flag

O

This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB

indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function

is selected. IRBindicateswhetherornot thereis spaceavailablefor writingtotheFIFO2

memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

FS1/SEN

FS0/SD

Flag Offset

Select 1/Serial

Enable

I

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-

ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag

offset programming method. Three offset register programming methods are available:

automatically load one of three preset values (8, 16, or 64), parallel load from Port A,

and serial load. When serial load is selected for flag offset register programming, FS1/

SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When

FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X

and Y registers. The number of bit writes required to program the offset registers is 40

for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV. The

first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.

Flag Offset

Select 0/Serial

Data

MBA

MBB

Port A Mailbox

Select

I

A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.

When a read operation is performed on Port A, a HIGH level on MBA selects data from

the Mail2 register for output and a LOW level selects FIFO2 output register data for

output. When a write operation is performed on port A, a HIGH level on MBA will write

the data into Mail1 register, while a LOW level will write the data into FIFO1.

Port B Mailbox

Select

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.

When a read operation is performed on Port B, a HIGH level on MBB selects data from

the Mail1 register for output and a LOW level selects FIFO1 output register data for

output. When a write operation is performed on port B, a HIGH level on MBB will write

the data into Mail2 register, while a LOW level will write the data into FIFO2.

MBF1

MBF2

MRS1

Mail1 Register

Flag

O

I

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1

register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set

HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB

is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

Mail2 Register

Flag

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2

register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set

HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA

is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

FIFO1 Master

Reset

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects

theprogramming method(serialor parallel) and one of three programmable flag default

offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four

LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must

occur while MRS1 is LOW.

MRS2

PRS1

FIFO2 Master

Reset

I

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects

one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-

tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is

LOW.

FIFO1 Partial

Reset

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes. During Partial Reset, the

currently selected bus size, endian arrangement, programming method (serial or par-

allel), and programmable flag settings are all retained.

Document #: 38-06025 Rev. **

Page 5 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Pin Definitions (continued)

Signal Name

Description

I/O

Function

PRS2

FIFO2 Partial

Reset

I

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes. During Partial Reset, the

currently selected bus size, endian arrangement, programming method (serial or par-

allel), and programmable flag settings are all retained.

RT1

RT2

SIZE

Retransmit

FIFO1

I

A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing

the read pointer back to location zero. The user willstill need to perform read operations

to retransmit the data. Retransmit function applies to CY standard mode only.

Retransmit

FIFO2

A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by bringing

the read pointer back to location zero. The user willstill need to perform read operations

to retransmit the data. Retransmit function applies to CY standard mode only.

Bus Size Select

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW

on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and

BE to select the bus size and endian arrangement for Port B. The level of SIZE must

be static throughout device operation.

SPM

Serial

Programming

I

A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin

selects parallel programming or default offsets (8, 16, or 64).

W/RA

Port A Write/

Read Select

A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-to-HIGH transition of CLKA. The A_0–35outputs are in the high-impedance state

when W/RA is HIGH.

W/RB

Port B Write/

Read Select

I

A LOW selects a write operation and a HIGH selects a read operation on Port B for a

LOW-to-HIGH transition of CLKB. The B_0–35outputs are in the high-impedance state

when W/RB is LOW.

Maximum Ratings^[3]

Static Discharge Voltage ........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current..................................................... >200 mA

Storage Temperature ...................................... 65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied................................................... 55°C to +125°C

Ambient

[5]

Range

Commercial

Industrial

Temperature

0°C to +70°C

40°C to +85°C

V_CC

Supply Voltage to Ground Potential ................ 0.5V to +7.0V

3.3V ± 10%

DC Voltage Applied to Outputs

in High Z State^[4]......................................... 0.5V to V_CC+0.5V

DC Input Voltage^[4]...................................... 0.5V to V_CC+0.5V

Output Current into Outputs (LOW) .............................20 mA

Note:

3. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

4. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

5. Operating V_CCRange for -7 speed is 3.3V ± 5%.

Document #: 38-06025 Rev. **

Page 6 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Electrical Characteristics Over the Operating Range

CY7C43644/64/84AV

Parameter

V_OH

Description

Test Conditions

V_CC= 3.0V,

I_OH2.0 mA

Min.

Max.

Unit

Output HIGH Voltage

2.4

V

=

V_OL

Output LOW Voltage

V_CC= 3.0V,

I_OL= 8.0 mA

0.5

V

V_IH

V_IL

I_IX

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

2.0

0.5

10

V_CC

0.8

V

V_CC= Max.

+10

µA

I_OZL

I_OZH

Output OFF, High Z

Current

V_SS< V_O< V_CC

10

[6]

I_CC1

Active Power Supply

Current

Com’l

Ind

60

10

mA

[7]

I_SB

Average Standby

Current

Com’l

Ind

Capacitance^[8]

Parameter

Description

Test Conditions

Max.

Unit

C_IN

Input Capacitance

Output Capacitance

T_A= 25°C, f = 1 MHz,

V_CC= 3.3V

4

8

pF

C_OUT

AC Test Loads and Waveforms (-10 & -15)

R1=330Ω

3.3V

ALL INPUT PULSES

OUTPUT

3.0V

GND

90%

10%

90%

10%

[13]

C =30 pF

R2=680Ω

L

≤ 3 ns

INCLUDING

JIG AND

SCOPE

AC Test Loads and Waveforms (-7)

V

CC

/2

ALL INPUT PULSES

3.0V

GND

90%

10%

50Ω

90%

10%

I/O

Z0=50Ω

≤ 3 ns

Notes:

6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs

are unloaded.

7. All inputs = V_CC– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

8. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-06025 Rev. **

Page 7 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Characteristics Over the Operating Range

CY7C43644/

64/84AV

–7

CY7C43644/

64/84AV

–10

CY7C43644/

64/84AV

–15

Parameter

f_S

Description

Min.

Max.

Min.

Max.

Min. Max. Unit

Clock Frequency, CLKA or CLKB

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA or CLKB HIGH

Pulse Duration, CLKA or CLKB LOW

133

100

67

MHz

ns

t_CLK

7.5

3.5

3

10

4

15

6

t_CLKH

t_CLKL

t_DS

ns

4

6

ns

Set-Up Time, A_0–35before CLKA↑ and B_0–35before

CLKB↑

4

5

ns

t_ENS

t_RSTS

t_FSS

Set-Up Time, CSA, W/RA, ENA, and MBA before

CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑

3

2.5

5

4

7

5

ns

Set-Up Time, MRS1, MRS2, PRS1, PRS2, RT1 or

5

RT2 LOW before CLKA↑ or CLKB↑^[9]

Set-Up Time, FS0 and FS1 before MRS1 andMRS2

HIGH

7.5

t_BES

Set-Up Time, BE/FWFT before MRS1 and MRS2

HIGH

5

t_SPMS

t_SDS

t_SENS

t_FWS

t_DH

Set-Up Time, SPM before MRS1 and MRS2 HIGH

Set-Up Time, FS0/SD before CLKA↑

5

3

0

7

4

0

7.5

5

ns

Set-Up Time, FS1/SEN before CLKA↑

Set-Up Time, BE/FWFT before CLKA↑

5

0

Hold Time, A_0–35after CLKA↑ and B_0–35after

CLKB↑

0

t_ENH

t_RSTH

t_FSH

Hold Time, CSA, W/RA, ENA, and MBA after

CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑

0

1

0

2

1

0

2

ns

HoldTime,MRS1, MRS2, PRS1, PRS2, RT1or RT2

LOW after CLKA↑ or CLKB↑^[9]

Hold Time, FS0 and FS1 after MRS1 and MRS2

HIGH

t_BEH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

Hold Time, SPM after MRS1 and MRS2 HIGH

Hold Time, FS0/SD after CLKA↑

1

0

1

0

1

2

0

2

ns

t_SPMH

t_SDH

t_SENH

t_SPH

Hold Time, FS1/SEN after CLKA↑

Hold Time, FS1/SEN HIGH after MRS1 and MRS2

HIGH

[10]

t_SKEW1

Skew Time between CLKA↑ and CLKB↑ for EFA/

ORA, EFB/ORB, FFA/IRA, and FFB/IRB

5

7

5

8

7.5

12

ns

[10]

t_SKEW2

Skew Time between CLKA↑ and CLKB↑ for AEA,

AEB, AFA, AFB

t_A

Access Time, CLKA↑ to A_0–35and CLKB↑ to B_0–35

1

6

1

8

3

2

10

ns

t_WFF

Propagation Delay Time, CLKA↑ to FFA/IRA and

CLKB↑ to FFB/IRB

t_REF

Propagation Delay Time, CLKA↑ to EFA/ORA and

CLKB↑ to EFB/ORB

1

6

1

8

2

10

ns

Notes:

9. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

10. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB

cycle.

Document #: 38-06025 Rev. **

Page 8 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Characteristics Over the Operating Range (continued)

CY7C43644/

64/84AV

–7

CY7C43644/

64/84AV

–10

CY7C43644/

64/84AV

–15

Parameter

Description

Min.

Max.

Min.

Max.

Min. Max. Unit

t_PAE

Propagation Delay Time, CLKA↑ to AEA and

CLKB↑ to AEB

1

6

1

8

1

0

10

12

ns

t_PAF

PropagationDelayTime, CLKA↑ toAFA and CLKB↑

to AFB

1

0

6

1

0

8

t_PMF

Propagation Delay Time, CLKA↑ to MBF1 LOW or

MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1

HIGH

t_PMR

t_MDV

t_RSF

Propagation Delay Time, CLKA↑ to B_0–35^[11]and

CLKB↑ to A_0–35

1

7

6

2

1

11

9

3

1

12

11

15

ns

[12]

Propagation Delay Time, MBA to A_0–35Valid and

MBB to B_0–35Valid

Propagation Delay Time, MRS1 or PRS1 LOW to

AEB LOW, AFA HIGH, FFA / IRA LOW, EFB /ORB

LOW and MBF1 HIGH and MRS2 or PRS2 LOW to

AEA LOW, AFB HIGH, FFB / IRB LOW, EFA /ORA

LOW and MBF2 HIGH

10

t_EN

Enable Time, CSA or W/RA LOW to A_0–35Active

and CSB LOW and W/RB HIGH to B_0–35Active

1

6

5

2

1

8

6

2

1

10

8

ns

[13]

t_DIS

Disable Time, CSA or W/RA HIGH to A_0–35at High

Impedance and CSB HIGH or W/RB LOW to B_0–35

at High Impedance

t_RTR

Retransmit Recovery Time

90

ns

Notes:

11. Writing data to the Mail1 register when the B_0–35outputs are active and MBB is HIGH.

12. Writing data to the Mail2 register when the A_0–35outputs are active and MBA is HIGH

13.

C_L= 5 pF for t_DIS..

Document #: 38-06025 Rev. **

Page 9 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms

[14, 15]

FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKA

CLKB

t_RSTS

t_RSTH

MRS1

t_FWS

t_BES

t_BEH

BE/FWFT

BE

FWFT

t_SPMS

t_SPMH

SPM

t_FSS

t_FSH

FS1/SEN,

FS0/SD

t_RSF

t_WFF

FFA/IRA

t_RSF

EFB/ORB

t_RSF

AEB

t_RSF

AFA

t_RSF

MBF1

Notes:

14. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.

15. PRS1 must be HIGH during Master Reset.

Document #: 38-06025 Rev. **

Page 10 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

[16, 17]

FIFO1 Partial Reset (CY Standard and FWFT Modes)

CLKA

CLKB

t_RSTH

t_RSTS

PRS1

t_WFF

t_RSF

FFA/IRA

t_RSF

EFB/ORB

t_RSF

AEB

t_RSF

AFA

t_RSF

MBF1

Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

[18]

(CY Standard and FWFT Modes)

CLKA

MRS1, MRS2

t_FSS

t_FSH

SPM

t_FSH

t_FSS

FS1/SEN,

FS0/SD

t_WFF

FFA/IRA

[19]

t_ENS

t_ENH

t_SKEW1

ENA

t_DH

t_DS

A_{0 − 35}

CLKB

AFA Offset (Y1)

AEB Offset (X1)

AEA Offset (X2) First Word to FIFO1

AFB Offset (Y2)

t_WFF

FFB/IRB

Notes:

16. Partial Reset is performed in the same manner for FIFO2.

17. MRS1 must be HIGH during Partial Reset.

18. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel

when FFA/IRA is HIGH.

19. t_SKEW1is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising

edge of CLKA and rising edge of CLKB is less than t_SKEW1, then FFB/IRB may transition HIGH one cycle later than shown.

Document #: 38-06025 Rev. **

Page 11 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

Serial Programming of the Almost-Full Flag and Almost-Empty Flag

Offset Values (CY Standard and FWFT Modes)^{[20, 21]}

CLKA

MRS1, MRS2

t_FSS

t_FSH

SPM

t_WFF

t_SKEW1

t_SENSt_SENH

FFA/IRA

t_FSS

t_SPH

t_SENS

t_SENH

FS1/SEN

FS0/SD ^[21]

t_SDS

t_FSS

t_FSH

t_SDH

t_SDS

AFA Offset (Y1) MSB

AEA Offset (X2) LSB

CLKB

t_WFF

FFB/IRB

Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

t_CLK

t_CLKL

t_CLKH

CLKA

FFA/IRA

HIGH

t_ENS

t_ENH

CSA

t_ENSt_ENH

W/RA ^[22]

MBA

t_ENSt_ENH

t_ENH

t_ENS

t_ENH

t_ENS

ENA

t_DS

t_DH

[23]

A_0–35

[23]

W2

W1

Notes:

20. It is not necessary to program offset register bits on consecutive clock cycles. Attempts to write into FIFO memory are ignored until FFA/IRA is set HIGH.

21. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).

22. If W/RA switches from read to write before the assertion of CSA, t_ENS=t_DIS+t_ENS

23. Written to FIFO1.

.

Document #: 38-06025 Rev. **

Page 12 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

t_CLK

t_CLKH

t_CLKL

CLKB

FFB/IRB

CSB

HIGH

t_ENS

t_ENH

t_ENSt_ENH

[24]

W/RB

t_ENS

t_ENH

t_DH

MBB

t_ENH

t_ENS

ENB

t_DS

W1

B₀₋₃₅

[25]

W2

Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKB

FFB/IRB

HIGH

t_ENS

t_ENH

CSB

t_ENS

[24]

W/RB

t_ENSt_ENH

MBB

t_ENH

t_ENS

t_ENH

ENB

t_DH

t_DS

B_0–17

Note:

24. If W/RB switches from read to write before the assertion of CSB, t_ENS=t_DIS+t_ENS

25. Written to FIFO2.

.

Document #: 38-06025 Rev. **

Page 13 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

Port B Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKB

FFB/IRB

CSB

HIGH

t_ENS

t_ENH

t_ENS

[24]

W/RB

t_ENH

t_ENS

t_ENH

MBB

t_ENH

t_ENS

ENB

B_0–8

t_DS

t_DH

Port B Long-Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

t_CLK

t_CLKH

t_CLKL

CLKB

EFB/ORB

CSB

[24]

W/RB

MBB

ENB

t_ENS

t_ENH

t_ENS

t_EN

t_ENH

t_ENS

t_A

t_DIS

t_MDV

No Operation

t_EN

B_0–35

(Standard Mode)

[26]

W2

Previous Data

t_A

W1

t_DIS

t_A

t_MDV

OR

B_0–35

(FWFT Mode)

t_EN

[26]

W3

[26]

W1

W2

Note:

26. Read From FIFO1.

Document #: 38-06025 Rev. **

Page 14 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

[27]

Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

CLKB

EFB/ORB

CSB

[24]

W/RB

MBB

t_ENH

t_ENS

ENB

t_A

t_DIS

t_MDV

t_A

No Operation

B_0–17

t_EN

(Standard Mode)

Previous Data

OR

t_DIS

t_A

t_MDV

t_A

t_EN

B_0–17

(FWFT Mode)

Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)^[28]

CLKB

EFB/ORB

CSB

HIGH

[24]

W/RB

MBB

ENB

t

_ENSt_ENH

t_DIS

t_A

t_MDV

t_A

No Operation

t_EN

B_0–8

(Standard Mode)

OR

t_A

Previous Data

t_A

t_DIS

t_MDV

t_A

t_EN

B_0–8

(FWFT Mode)

Notes:

27. Unused word B_18–35contains all zeroes for word-size reads.

28. Unused bytes B_9–17, B_18–26, and B_27–35contain all zeroes for byte-size reads.

Document #: 38-06025 Rev. **

Page 15 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

t_CLK

t_CLKH

t_CLKL

CLKA

EFA/ORA

CSA

HIGH

[22]

W/RA

MBA

t_ENSt_ENH

t_ENS

t_ENH

ENA

t_A

t_DIS

t_MDV

No Operation

t_EN

A₀₋₃₅

[29]

W2

W1^[29]

Previous Data

t_A

(Standard Mode)

OR

A₀₋₃₅

(FWFT Mode)

t_MDV

t_DIS

t_A

t_EN

[29]

W3

W2^[29]

W1^[29]

Note:

29. Read From FIFO2.

Document #: 38-06025 Rev. **

Page 16 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)^[30]

t_CLK

t_CLKH

t_CLKL

CLKA

CSA

LOW

HIGH

W/RA

t

_ENSt_ENH

MBA

t

_ENSt_ENH

ENA

FFA/IRA

HIGH

t_DSt_DH

W1

A_0–35

CLKB

t_CLKH

t_CLKL

[31]

t_SKEW1

t_REF

t_CLK

EFB/ORB

FIFO1 Empty

CSB

LOW

HIGH

W/RB

MBB

ENB

LOW

t

_ENSt_ENH

t_A

B_0–35

W1

Old Data in FIFO1 Output Register

Notes:

30. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.

31. t_SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of ORB HIGH and

load of the first word to the output register may occur one CLKB cycle later than shown.

Document #: 38-06025 Rev. **

Page 17 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

EFB Flag Timing and First Data Read Fall Through when FIFO1 is

Empty (CY Standard Mode) ^[30]

t_CLK

t_CLKH

t_CLKL

CLKA

CSA

LOW

HIGH

W/RA

MBA

t_ENH

t_ENS

t

_ENSt_ENH

ENA

FFA/IRA

A_0–35

HIGH

t_DSt_DH

W1

[32]

t_CLKH

t_CLKL

t_SKEW1

CLKB

t_REF

t_CLK

EFB/ORB

CSB

FIFO1 Empty

LOW

HIGH

W/RB

MBB

ENB

LOW

t

_ENSt_ENH

t_A

B_0–35

W1

Note:

32. t_SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

Document #: 38-06025 Rev. **

Page 18 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty

(FWFT Mode) ^[33]

t_CLK

t_CLKH

t_CLKL

CLKB

CSB

LOW

W/RB

MBB

t

_ENSt_ENH

t_ENH

t_ENS

ENB

HIGH

FFB/IRB

B_0–35

t_DH

t_DS

W1

[34]

t_CLKH

t_CLKL

t_SKEW1

CLKA

t_REF

t_CLK

EFA/ORA

CSA

FIFO2 Empty

LOW

W/RA

MBA

ENA

LOW

t_{ENS ENH}

t

t_A

A_0–35

W1

Old Data in FIFO2 Output Register

Notes:

33. If Port B size is word or byte, t_SKEW1is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

34.

t

_SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output

register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t_SKEW1, then the transition of ORA HIGH and

load of the first word to the output register may occur one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

Page 19 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)^[33]

t_CLK

t_CLKH

t_CLKL

CLKB

CSB

LOW

W/RB

MBB

t_ENH

t_ENS

t_ENH

t_ENS

ENB

HIGH

FFB/IRB

B_0–35

t_DSt_DH

W1

[35]

t_CLKH

t_CLKL

t_SKEW1

CLKA

t_REF

t_CLK

EFA/ORA

CSA

FIFO2 Empty

LOW

W/RA

MBA

ENA

A_0–35

LOW

t_{ENS ENH}

t

t_A

W1

Note:

35. t_SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than t_SKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

Page 20 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode) ^[33]

t_CLK

t_CLKL

t_CLKH

CLKB

CSB

LOW

W/RB

MBB

HIGH

LOW

t_{ENS ENH}

t

ENB

EFB/ORB

B_0–35

HIGH

tA

Next Word From FIFO1

Previous Word in FIFO1 Output Register

[36]

t_CLKH

t_CLKL

t_SKEW1

CLKA

t_WFF

t_CLK

FFA/IRA

CSA

FIFO1 Full

LOW

HIGH

W/RA

t_{ENS ENH}

t

MBA

ENA

t_{ENS ENH}

t

t_DS

t_DH

A_0–35

To FIFO1

Note:

36. t_SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than t_SKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

Page 21 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

[33]

FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)

t_CLK

t_CLKL

t_CLKH

CLKB

CSB

LOW

W/RB

MBB

HIGH

LOW

t

_ENSt_ENH

ENB

EFB/ORB

B_0–35

HIGH

t_A

Next Word From FIFO1

Previous Word in FIFO1 Output Register

[37]

t_CLKH

t_CLKL

t_SKEW1

CLKA

t_WFF

t_CLK

FFA/IRA

CSA

FIFO1 Full

LOW

HIGH

W/RA

t_ENH

t_ENS

MBA

ENA

A₀₋₃₅

t

_ENSt_ENH

t_DSt_DH

Note:

37. t_SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than t_SKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

Page 22 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)^[38]

t_CLK

t_CLKL

t_CLKH

CLKA

LOW

CSA

LOW

W/RA

MBA

t

_ENSt_ENH

ENA

EFA/ORA

A_0–35

HIGH

tA

Next Word From FIFO2

Previous Word in FIFO2 Output Register

[39]

t_CLKH

t_CLKL

t_SKEW1

CLKB

t_WFF

t_CLK

FIFO2 Full

LOW

FFB/IRB

CSB

W/RB

LOW

t_ENH

t_ENS

MBB

ENB

t_ENH

t_ENS

t_DSt_DH

B_0–35

To FIFO2

Notes:

38. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long-word, respectively.

39. _SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.

t

Document #: 38-06025 Rev. **

Page 23 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)^[40]

t_CLK

t_CLKL

t_CLKH

CLKA

CSA

LOW

W/RA

MBA

LOW

t

_ENSt_ENH

ENA

HIGH

EFA/ORA

A_0–35

t_A

Next Word From FIFO2

Previous Word in FIFO2 Output Register

[41]

t_CLKH

t_CLKL

t_SKEW1

CLKB

FFB/IRB

CSB

t_WFF

t_CLK

FIFO2 Full

LOW

W/RB

MBB

ENB

t

_ENSt_ENH

t_ENH

t_ENS

t_DSt_DH

B_0–35

To FIFO2

Notes:

40. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long-word, respectively.

41. t_SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of FFB HIGH may occur one CLKB cycle later than shown.

Document #: 38-06025 Rev. **

Page 24 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Switching Waveforms (continued)

Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes) ^{[42, 43]}

CLKA

t_ENH

t_ENS

t_ENH

X1 Words in FIFO

ENA

[44]

t_SKEW2

CLKB

t_PAE

(X1+1) Words in FIFO1 (X1+2) Words in FIFO1

(X1+2)Words in FIFO1

t_ENS

X1 Word in FIFO1

AEB

ENB

t_ENH

t_ENS

Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes) ^{[45, 46]}

CLKB

t_ENH

t_ENS

X2 Words in FIFO

ENB

[47]

t_SKEW2

CLKA

t_PAE

(X2+2) Words in FIFO2

(X2+2)Words in FIFO2

t_ENS

X2 Word in FIFO2

(X2+1) Words in FIFO2

AEA

ENA

t_ENH

t_ENS

Notes:

42. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

read from the FIFO.

43. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.

44. t_SKEW2is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than t_SKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

45. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been

read from the FIFO.

46. If Port B size is word or byte, t_SKEW2is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.

47.

t_SKEW2is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than t_SKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

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PRELIMINARY

Switching Waveforms (continued)

Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)^{[2, 46, 48, 49]}

[50]

t_SKEW2

CLKA

t_ENS

t_ENH

ENA

AFA

t_PAF

[D–(Y1+1)] Words in FIFO1

[D–(Y1+2)] words in FIFO1

(D–Y1)Words in FIFO1

CLKB

ENB

t_ENH

t_ENS

Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)^{[2, 45, 49, 51]}

[52]

t_SKEW2

CLKB

t_ENS

t_ENH

ENB

AFB

t_PAF

[D–(Y2+1)] Words in FIFO2

[D–(Y2+2)] words in FIFO2

(D–Y2)Words in FIFO2

CLKA

ENA

t_ENH

t_ENS

Notes:

48. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been

read from the FIFO.

49. D = Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV.

50. t_SKEW2is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than t_SKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

51. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long-word, respectively.

52.

t

_SKEW2is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than t_SKEW2, then AFB may transition HIGH one CLKA cycle later than shown.

Document #: 38-06025 Rev. **

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CY7C43644AV

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PRELIMINARY

Switching Waveforms (continued)

Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)^[53]

CLKA

t_ENH

t_ENS

CSA

t_ENH

t_ENS

[22]

W/RA

MBA

t_ENH

t_ENS

t_DS

t_ENH

ENA

t_DH

A_0–35

CLKB

W1

t_PMF

MBF1

CSB

W/RB^[24]

MBB

t_ENH

t_ENS

ENB

t_MDV

FIFO1 Output Register

t_EN

t_DIS

t_PMR

B_0-35

W1 (Remains valid in Mail1 Register after read)

Note:

53. If Port B is configured for word size, data can be written to the Mail1 register using A_0–17(A_18–35are “Don’t Care” inputs). In this first case B_0–17will have

valid data (B_18–35will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A_0–8(A_9–35are “Don’t Care”

inputs). In this second case, B_0–8will have valid data (B_9–35will be indeterminate).

Document #: 38-06025 Rev. **

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PRELIMINARY

Switching Waveforms (continued)

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)^[54]

CLKB

t_ENH

t_ENS

CSB

t_ENH

[24]

W/RB

MBB

t_ENH

t_ENS

ENB

t_DH

t_DS

W1

B_0–35

CLKA

t_PMF

MBF2

CSA

[22]

W/RA

MBA

ENA

A₀₋₃₅

t_ENS

t_ENH

t_MDV

FIFO2 Output Register

t_EN

t_PMR

t_DIS

W1 (Remains valid in Mail2 Register after read)

[55, 56, 57, 58]

FIFO1 Retransmit Timing

CLKA

CLKB

RT1

t_RSTS

t_RSTH

t

RTR

ENB

EFB/FFA

Notes:

54. If Port B is configured for word size, data can be written to the Mail2 register using B_0–17(B_18–35are “Don’t Care” inputs). In this first case A_0–17will have

valid data (A_18–35will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B_0–8(B_9–35are “Don’t Care”

inputs). In this second case, A_0–8will have valid data (A_9–35will be indeterminate).

55. Retransmit is performed in the same manner for FIFO2.

56. Clocks are free running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and

during the retransmit operation, i.e, when RT1 is LOW and t_RTRafter the RT1 rising edge.

57. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but the Empty and Full flags will be

valid at t_RTR

.

58. For the AEA, AEB, AFA,and AFB flags, two clock cycle are necessary after t_RTRto update these flags.

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PRELIMINARY

dian arrangement. When data is moving in the direction from

Port A to Port B, the most significant byte (word) of the long-

word written to Port A will be transferred to Port B first; the least

significant byte (word) of the long word written to Port A will be

transferred to Port B last. When data is moving in the direction

from Port B to Port A, the byte (word) written to Port B first will

be transferred to Port A as the most significant byte (word) of

the long-word; the byte (word) written to Port B last will be

transferred to Port A as the least significant byte (word) of the

long-word.

Signal Description

Master Reset (MRS1, MRS2)

Each of the two FIFO memories of the CY7C436X4AV under-

goes a complete reset by taking its associated Master Reset

(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)

and four Port B clock (CLKB) LOW-to-HIGH transitions. The

Master Reset inputs can switch asynchronously to the clocks.

A Master Reset initializes the internal read and write pointers

and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW,

the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the

Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag

(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag

(MBF1, MBF2) of the parallel mailbox register HIGH. After a

Master Reset, the FIFO’s Full/Input Ready flag is set HIGH

after two clock cycles to begin normal operation. A Master Re-

set must be performed on the FIFO after power up, before data

is written to its memory.

A LOW on the BE/FWFT input when the Master Reset (MRS1

and MRS2) inputs go from LOW to HIGH will select a Little

Endian arrangement. When data is moving in the direction

from Port A to Port B, the least significant byte (word) of the

long word written to Port A will be transferred to Port B first; the

most significant byte (word) of the long-word written to Port A

will be transferred to Port B last. When data is moving in the

direction from Port B to Port A, the byte (word) written to Port

B first will be transferred to port A as the least significant byte

(word) of the long-word; the byte (word) written to Port B last

will be transferred to Port A as the most significant byte (word)

of the long-word.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,

MRS2) input latches the value of the Big Endian (BE) input or

determining the order by which bytes are transferred through

Port B.

After Master Reset, the FWFT select function is active, permit-

ting a choice between two possible timing modes: CY Stan-

dard mode or First-Word Fall-Through (FWFT) mode. Once

the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the

BE/FWFT input at the second LOW-to-HIGH transition of

CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-

dard mode. This mode uses the Empty Flag function (EFA,

EFB) to indicate whether or not there are any words present in

the FIFO memory. It uses the Full Flag function (FFA, FFB) to

indicate whether or not the FIFO memory has any free space

for writing. In CY Standard mode, every word read from the

FIFO, including the first, must be requested using a formal

read operation.

A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)

input latches the values of the Flag select (FS0, FS1) and Se-

rial Programming Mode (SPM) inputs for choosing the Almost

Full and Almost Empty offset programming method (see Al-

most Empty and Almost Full flag offset programming below).

Partial Reset (PRS1, PRS2)

Each of the two FIFO memories of the CY7C436X4AV under-

goes a limited reset by taking its associated Partial Reset

(PRS1, PRS2) input LOW for at least four Port A clock (CLKA)

and four Port B clock (CLKB) LOW-to-HIGH transitions. The

Partial Reset inputs can switch asynchronously to the clocks.

A Partial Reset initializes the internal read and write pointers

and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW,

the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the

Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag

(AFA, AFB) HIGH. A Partial Reset also forces the Mailbox flag

(MBF1, MBF2) of the parallel mailbox register HIGH. After a

Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH

after two clock cycles to begin normal operation.

Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW

on the BE/FWFT input at the second LOW-to-HIGH transition

of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT

mode. This mode uses the Output Ready function (ORA,

ORB) to indicate whether or not there is valid data at the data

outputs (A_0–35or B_0–35). It also uses the Input Ready function

(IRA, IRB) to indicate whether or not the FIFO memory has any

free space for writing. In the FWFT mode, the first word written

to an empty FIFO goes directly to data outputs, no read re-

quest necessary. Subsequent words must be accessed by

performing a formal read operation.

Whatever flag offsets, programming method (parallel or seri-

al), and timing mode (FWFT or CY Standard mode) are cur-

rently selected at the time a Partial Reset is initiated, those

settings will remain unchanged upon completion of the reset

operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Master Reset would be in-

convenient.

Following Master Reset, the level applied to the BE/FWFT in-

put to choose the desired timing mode must remain static

throughout the FIFO operation.

Programming the Almost Empty and Almost Full Flags

Big Endian/First Word Fall Through (BE/FWFT)

Four registers in the CY7C436X4AV are used to hold the offset

values for the Almost Empty and Almost Full flags. The Port B

Almost Empty flag (AEB) offset register is labeled X1 and the

Port A Almost Empty flag (AEA) offset register is labeled X2.

The Port A Almost Full flag (AFA) offset register is labeled Y1

and the Port B Almost Full flag (AFB) offset register is labeled

Y2. The index of each register name corresponds with preset

values during the reset of a FIFO, programmed in parallel us-

ing the FIFO’s Port A data inputs, or programmed in serial

using the Serial Data (SD) input (see Table 1). To load a FIFO’s

Almost Empty flag and Almost Full flag offset registers with

one of the three preset values listed in Table 1, the Serial

This is a dual-purpose pin. At the time of Master Reset, the BE

select function is active, permitting a choice of Big or Little

Endian byte arrangement for data written to or read from Port

B. This selection determines the order by which bytes (or

words) of data are transferred through this port. For the follow-

ing illustrations, assume that a byte (or word) bus size has

been selected for Port B. (Note that when Port B is configured

for a long word size, the Big Endian function has no application

and the BE input is a “Don’t Care.”)

A HIGH on the BE/FWFT input when the Master Reset (MRS1

and MRS2) inputs go from LOW to HIGH will select a Big En-

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Program Mode (SPM) and at least one of the flag-select inputs

must be HIGH during the LOW-to-HIGH transition of its Master

Reset input (MRS1 and MRS2). For example, to load the pre-

set value of 64 into X1 and Y1, SPM, FS0, and FS1 must be

HIGH when FIFO1 reset (MRS1) returns HIGH. Flag-offset

registers associated with FIFO2 are loaded with one of the

preset values in the same way with Master Reset (MRS2).

When using one of the preset values for the flag offsets, the

FIFOs can be reset simultaneously or at different times.

The Port B control signals are identical to those of Port A with

the exception that the Port B Write/Read select (W/RB) is the

inverse of the Port A Write/Read select (W/RA). The state of

the Port B data (B_0–35) lines is controlled by the Port B Chip

Select (CSB) and Port B Write/Read select (W/RB). The B_0–35

lines are in the high-impedance state when either CSB is

HIGH or W/RB is LOW. The B_0–35lines are active outputs

when CSB is LOW and W/RB is HIGH.

Data is loaded into FIFO2 from the B_0–35inputs on a LOW-to-

HIGH transition of CLKB when CSB is LOW, W/RB is LOW,

ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read

from FIFO1 to the B_0–35outputs by a LOW-to-HIGH transition

of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,

MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO

reads and writes on Port B are independent of any concurrent

Port A operation.

To program the X1, X2, Y1, and Y2 registers in parallel from

Port A, perform a Master Reset on both FIFOs simultaneously

with SPM HIGH and FS0 and FS1 LOW during the LOW-to-

HIGH transition of MRS1 and MRS2. After this reset is com-

plete, the first four writes to FIFO1 do not store data in RAM

but load the offset registers in the order Y1, X1, Y2, X2. The

Port A data inputs used by the offset registers are (A_0–9),

(A_0–11), or (A_0–13), for the CY7C436X4AV, respectively. The

highest numbered input is used as the most significant bit of

the binary number in each case. Valid programming values for

the registers range from 0 to 1023 for the CY7C43644AV; 0 to

The set-up and hold time constraints to the port clocks for the

port Chip Selects and Write/Read selects are only for enabling

write and read operations and are not related to high-imped-

ance control of the data outputs. If a port enable is LOW during

a clock cycle, the port’s Chip Select and Write/Read select

may change states during the set-up and hold time window of

the cycle.

4095 for the CY7C43664AV;

0

to 16383 for the

CY7C43684AV.^[2]After all the offset registers are programmed

from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH

and both FIFOs begin normal operation.

When operating the FIFO in FWFT mode and the Output

Ready flag is LOW, the next word written is automatically sent

to the FIFO’s output register by the LOW-to-HIGH transition of

the port clock that sets the Output Ready flag HIGH, data re-

siding in the FIFO’s memory array is clocked to the output reg-

ister only when a read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

To program the X1, X2, Y1, and Y2 registers serially, initiate a

Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN

HIGH during the LOW-to-HIGH transition of MRS1 and MRS2.

After this reset is complete, the X and Y register values are

loaded bit-wise through the FS0/SD input on each LOW-to-

HIGH transition of CLKA that the FS1/SEN input is LOW. Forty,

forty-eight, or fifty-six bit writes are needed to complete the

programming for the CY7C436X4AV, respectively. The four

registers are written in the order Y1, X1, Y2, and, finally, X2.

The first-bit write stores the most significant bit of the Y1 reg-

ister and the last-bit write stores the least significant bit of the

X2 register.

When operating the FIFO in CY Standard mode, data residing

in the FIFO’s memory array is clocked to the output register

only when a read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

Synchronized FIFO Flags

When the option to program the offset registers serially is cho-

sen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW

until all register bits are written. FFA/IRA is set HIGH by the

LOW-to-HIGH transition of CLKA after the last bit is loaded to

allow normal FIFO1 operation. The Port B Full/Input ready

(FFB/IRB) flag also remains LOW throughout the serial pro-

gramming process, until all register bits are written. FFB/IRB

is set HIGH by the LOW-to-HIGH transition of CLKB after the

last bit is loaded to allow normal FIFO2 operation.

Each FIFO is synchronized to its port clock through at least

two flip-flop stages. This is done to improve flag-signal reliabil-

ity by reducing the probability of the metastable events when

CLKA and CLKB operate asynchronously to one another. EFA/

ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.

EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to

CLKB. Table 4 and Table 5 show the relationship of each port

flag to FIFO1 and FIFO2.

SPM, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

Empty/Output Ready Flags (EFA/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT mode, the Output

Ready (ORA, ORB) function is selected. When the Output

Ready flag is HIGH, new data is present in the FIFO output

register. When the Output Ready flag is LOW, the previous

data word remains in the FIFO output register and any FIFO

reads are ignored.

FIFO Write/Read Operation

The state of the Port A data (A_0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A_0–35lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A_0–35lines are active outputs

when both CSA and W/RA are LOW.

In the CY Standard mode, the Empty Flag (EFA, EFB) function

is selected. When the Empty Flag is HIGH, data is available in

the FIFO’s RAM memory for reading to the output register.

When Empty Flag is LOW, the previous data word remains in

the FIFO output register and any FIFO reads are ignored.

Data is loaded into FIFO1 from the A_0–35inputs on a LOW-to-

HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,

ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read

from FIFO2 to the A_0–35outputs by a LOW-to-HIGH transition

of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA

is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and

writes on Port A are independent of any concurrent Port B

operation.

The Empty/Output Ready flag of a FIFO is synchronized to the

port clock that reads data from its array. For both the FWFT

and CY Standard modes, the FIFO read pointer is increment-

ed each time a new word is clocked to its output register. The

state machine that controls an Output Ready flag monitors a

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CY7C43644AV

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PRELIMINARY

write pointer and read pointer comparator that indicates when

the FIFO SRAM status is empty, empty+1, or empty+2.

status is almost empty, almost empty+1, or almost empty+2.

The Almost Empty state is defined by the contents of register

X1 for AEB and register X2 for AEA. These registers are load-

ed with preset values during a FIFO reset, programmed from

Port A, or programmed serially (see Almost Empty flag and

Almost Full flag offset programming above). An Almost Empty

flag is LOW when its FIFO contains X or less words and is

HIGH when its FIFO contains (X+2) or more words. ^[2]

In FWFT Mode, from the time a word is written to a FIFO, it can

be shifted to the FIFO output register in a minimum of three

cycles of the Output Ready flag synchronizing clock. There-

fore, an Output Ready flag is LOW if a word in memory is the

next data to be sent to the FIFO output register and three

cycles have not elapsed since the time the word was written.

The Output Ready flag of the FIFO remains LOW until the third

LOW-to-HIGH transition of the synchronizing clock occurs, si-

multaneously forcing the Output Ready flag HIGH and shifting

the word to the FIFO output register.

The Almost Empty flag is set HIGH by the first LOW-to-HIGH

transition of its synchronizing clock after two FIFO writes that

fills memory to the (X+2) level. A LOW-to-HIGH transition of an

Almost Empty flag synchronizing clock begins the first syn-

chronization cycle if it occurs at time t_SKEW2or greater after

the write that fills the FIFO to (X+2) words. Otherwise, the sub-

sequent synchronizing clock cycle will be the first synchroni-

zation cycle.

In the CY Standard mode, from the time a word is written to a

FIFO, the Empty Flag will indicate the presence of data avail-

able for reading in a minimum of two cycles of the Empty Flag

synchronizing clock. Therefore, an Empty Flag is LOW if a

word in memory is the next data to be sent to the FIFO output

register and two cycles have not elapsed since the time the

word was written. The Empty Flag of the FIFO remains LOW

until the second LOW-to-HIGH transition of the synchronizing

clock occurs, forcing the Empty Flag HIGH; only then will data

be read.

Almost Full Flags (AFA, AFB)

The Almost Full flag of a FIFO is synchronized to the port clock

that writes data to its array. The state machine that controls an

Almost Full flag monitors a write pointer and read pointer com-

parator that indicates when the FIFO SRAM status is almost

full, almost full–1, or almost full–2. The Almost Full state is

defined by the contents of register Y1 for AFA and register Y2

for AFB. These registers are loaded with preset values during

a FIFO reset, programmed from Port A, or programmed seri-

ally (see Almost Empty flag and Almost Full flag offset pro-

gramming above). An Almost Full flag is LOW when the num-

ber of words in its FIFO is greater than or equal to (1024–Y),

(4096–Y), or (16384–Y) for the CY7C436X4AV respectively.

An Almost Full flag is HIGH when the number of words in its

FIFO is less than or equal to [1024–(Y+2)], [4096–(Y+2)], or

[16384–(Y+2)], for the CY7C436X4AV respectively.^[2]

A LOW-to-HIGH transition on an Empty/Output Ready flag

synchronizing clock begins the first synchronization cycle of a

write if the clock transition occurs at time t_SKEW1or greater

after the write. Otherwise, the subsequent clock cycle can be

the first synchronization cycle.

Full/Input Ready Flags (FFA/IRA, FFB/IRB)

This is a dual-purpose flag. In FWFT mode, the Input Ready

(IRA and IRB) function is selected. In CY Standard mode, the

Full Flag (FFA and FFB) function is selected. For both timing

modes, when the Full/Input Ready flag is HIGH, a memory

location is free in the SRAM to receive new data. No memory

locations are free when the Full/Input Ready flag is LOW and

any writes to the FIFO are ignored.

The Almost Full flag is set HIGH by the first LOW-to-HIGH

transition of its synchronizing clock after two FIFO reads that

reduces the number of words in memory to [1024/4096/

16384–(Y+2)]. A LOW-to-HIGH transition of an Almost Full

flag synchronizing clock begins the first synchronization cycle

if it occurs at time t_SKEW2or greater after the read that reduces

the number of words in memory to [1024/4096/16384–(Y+2)].

Otherwise, the subsequent synchronizing clock cycle will be

the first synchronization cycle.

The Full/Input Ready flag of a FIFO is synchronized to the port

clock that writes data to its array. For both FWFT and CY Stan-

dard modes, each time a word is written to a FIFO, its write

pointer is incremented. The state machine that controls a Full/

Input Ready flag monitors a write pointer and read pointer

comparator that indicates when the FIFO SRAM status is full,

full–1, or full–2. From the time a word is read from a FIFO, its

previous memory location is ready to be written to in a mini-

mum of two cycles of the Full/Input Ready flag synchronizing

clock. Therefore, a Full/Input Ready flag is LOW if less than

two cycles of the Full/Input Ready flag synchronizing clock

have elapsed since the next memory write location has been

read. The second LOW-to-HIGH transition on the Full/Input

Ready flag synchronizing clock after the read sets the Full/

Input Ready flag HIGH.

Mailbox Registers

Each FIFO has a 36-bit bypass register to pass command and

control information between Port A and Port B without putting

it in queue. The Mailbox Select (MBA, MBB) inputs choose

between a mail register and a FIFO for a port data transfer

operation. The usable width of both the Mail1 and Mail2 regis-

ters matches the selected bus size for Port B.

A LOW-to-HIGH transition on CLKA writes A₀

data to the

35

Mail1 Register when a Port A write is selected by CSA LOW,

W/RA HIGH, ENA HIGH, and MBA HIGH. If the selected Port

A bus size is also 36 bits, then the usable width of the Mail1

Register employs data lines A_{0 35}. If the selected Port A bus

size is 18 bits, then the usable width of the Mail1 Register

A LOW-to-HIGH transition on a Full/Input Ready flag synchro-

nizing clock begins the first synchronization cycle of a read if

the clock transition occurs at time t_SKEW1or greater after the

read. Otherwise, the subsequent clock cycle will be the first

synchronization cycle.

employs data lines A_{0 17}. (In this case, A₁₈

are “Don’t

Care” inputs.) If the selected Port A bus size is 9³b⁵its, then the

usable width of the Mail1 Register employs data lines A_{0 8}. (In

this case, A_{9 35}are “Don’t Care” inputs.)

Almost Empty Flags (AEA, AEB)

The Almost Empty flag of a FIFO is synchronized to the port

clock that reads data from its array. The state machine that

controls an Almost Empty flag monitors a write pointer and

read pointer comparator that indicates when the FIFO SRAM

A LOW-to-HIGH transition on CLKB writes B₀

data to the

35

Mail2 Register when a Port B write is selected by CSB LOW,

Document #: 38-06025 Rev. **

Page 31 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

W/RB LOW, ENB HIGH and MBB HIGH. If the selected Port B

bus size is also 36 bits, then the usable width of the Mail2

Register employs data lines B_0–35. If the selected Port B bus

size is 18 bits, then the usable width of the Mail2 Register

employs data lines B_0–17. (In this case, B_18–35are “Don’t Care”

inputs.) If the selected Port B bus size is 9 bits, then the usable

width of the Mail2 Register employs data lines B_{0 8}. (In this

case, B_{9 35}are “Don’t Care” inputs.)

Master Reset, by the time the Full/Input Ready flag is set

HIGH.

Bus-Matching operations are not available when transferring

data via mailbox registers. Furthermore, both the word- and

byte-size bus selections limit the width of the data bus that can

be used for mail register operations. In this case, only those

byte lanes belonging to the selected word- or byte-size bus can

carry mailbox data. The remaining data outputs will be inde-

terminate. The remaining data inputs will be don’t care inputs.

For example, when a word-size bus is selected, then mailbox

data can be transmitted only between A_0–17and B_0–17. When

a byte-size bus is selected, then mailbox data can be transmit-

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Any Attempt to write to a mail register

are ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox

Select input is LOW and from the mail register when the port

Mailbox Select input is HIGH.

ted only between A_0–8and B_0–8

.

Bus-Matching FIFO1 Reads

Data is read from the FIFO1 RAM in 36-bit long-word incre-

ments. If a long-word bus size is implemented, the entire long-

word immediately shifts to the FIFO1 output register. If byte or

word size is implemented on Port B, only the first one or two

bytes appear on the selected portion of the FIFO1 output reg-

ister, with the rest of the long-word stored in auxiliary registers.

In this case, subsequent FIFO1 reads output the rest of the

long word to the FIFO1 output register.

The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-

HIGH transition on CLKB when a Port B read is selected by

CSB LOW, W/RB HIGH, ENB HIGH AND MBB HIGH. For a

36-bit bus size, 36 bits of mailbox data are placed on B_0–35

.

For an 18-bit bus size, 18 bits of mailbox data are placed on

B_0–17. (In this case, B_18–35are indeterminate.) For a 9-bit bus

size, 9 bits of mailbox data are placed on B_0–8. (In this case,

B_9–35are indeterminate.)

When reading data from FIFO1 in the byte or word format, the

unused B_0–35outputs are indeterminate.

The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH

transition on CLKA when a Port A read is selected by CSA

LOW, W/RA LOW, ENA HIGH, MBA HIGH.

Bus-Matching FIFO2 Writes

For a 36-bit bus size, 36 bits of mailbox data are placed on

A_0–35. For an 18-bit bus size, 18 bits of mailbox data are placed

on A_0–17. (In this case, A_18–35are indeterminate.) For a 9-bit

bus size, 9 bits of mailbox data are placed on A_0–8. (In this

case, A_9–35are indeterminate.)

Data is written to the FIFO2 RAM in 36-bit long-word incre-

ments. Data written to FIFO2 with a byte or word bus size

stores the initial bytes or words in auxiliary registers. The

CLKB rising edge that writes the fourth byte or the second

word of long-word to FIFO2 also stores the entire long word in

FIFO2 RAM.

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Select feature has no effect on the mailbox data.

Reading from FIFO2 on Port A can only be in 36-bit format

Retransmit (RT1, RT2)

Bus Sizing

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. Retransmit func-

tion applies to CY standard mode only.

The Port B bus can be configured in a 36-bit long-word, 18-bit

word, or 9-bit byte format for data read from FIFO1 or written

to FIFO2. The levels applied to the Port B Bus Size Select

(SIZE) and the Bus Match Select (BM) determine the Port B

bus size. These levels should be static throughout FIFO oper-

ation. Both bus size selections are implemented at the com-

pletion of Master Reset, by the time the Full/Input Ready flag

is set HIGH.

The retransmit feature is intended for use when a number of

writes equal to or less than the depth of the FIFO have oc-

curred and at least one word has been read since the last reset

cycle. A LOW pulse on RT1, (RT2) resets the internal read

pointer to the first physical location of the FIFO. CLKA and

CLKB may be free running but ENB (ENA) must be disabled

during and t_RTRafter the retransmit pulse. With every valid

read cycle after retransmit, previously accessed data is read

and the read pointer is incremented until it is equal to the write

pointer. Flags are governed by the relative locations of the

read and write pointers and are updated during a retransmit

cycle. Data written to the FIFO after activation of RT1, (RT2)

are transmitted also. The full depth of the FIFO can be repeat-

edly retransmitted.

Two different methods for sequencing data transfer are avail-

able for Port B when the bus size selection is either byte- or

word-size. They are referred to as Big Endian (most significant

byte first) and Little Endian (least significant byte first). The

level applied to the Big Endian Select (BE) input during the

LOW-to-HIGH transition of MRS1 and MRS2 selects the endi-

an method that will be active during FIFO operation. BE is a

“Don’t Care” input when the bus size selected for Port B is long

word. The endian method is implemented at the completion of

Document #: 38-06025 Rev. **

Page 32 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

.

A_27–35

A_0–8

A_18–26

A_9–17

BYTE ORDER ON

PORT A:

Write to FIFO

A

D

B

C

B_9–17

B_0–8

B_27–35

B_18–26

Read from

FIFO

BE

BM

SIZE

C

D

A

B

X

L

X

(a) LONG-WORD SIZE

B_27–35

B_9–17

B_0–8

B_18–26

1st: Read from

FIFO

BE

BM

SIZE

A

B_9–17

B

B_0–8

H

L

B_27–35

B_18–26

2nd: Read from

FIFO

C

D

(b) WORD SIZE – BIG ENDIAN

B_27–35

B_9–17

B_0–8

B_18–26

1st: Read from

FIFO

BE

BM

SIZE

C

B_9–17

D

B_0–8

L

H

L

B_27–35

B_18–26

2nd: Read from

FIFO

A

B

(c) WORD SIZE – LITTLE ENDIAN

B_9–17

B_0–8

B_27–35

B_18–26

1st: Read from

FIFO

BE

BM

SIZE

A

B_0–8

H

2nd: Read from

FIFO

B

B_0–8

3rd: Read from

FIFO

C

B_0–8

4th: Read from

FIFO

D

(d) BYTE SIZE – BIG ENDIAN

B_9–17

B_0–8

B_27–35

B_18–26

1st: Read from

FIFO

BE

BM

SIZE

D

B_0–8

L

H

2nd: Read from

FIFO

C

B_0–8

3rd: Read from

FIFO

B

B_0–8

4th: Read from

FIFO

A

(e) BYTE SIZE – LITTLE ENDIAN

Document #: 38-06025 Rev. **

Page 33 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Table 1. Flag Programming

FS1/

SEN

FS0/

SD

SPM

H

L

MRS1

MRS2

X1 and Y1 Registers^[59]

X2 andY2 Registers^[60]

H

L

H

L

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

64

X

64

16

X

L

X

16

H

L

8

X

L

X

Parallel programming via Port A

Serial programming via SD

Reserved

8

Parallel programming via Port A

Serial programming via SD

Reserved

L

H

L

H

L

Reserved

L

Reserved

..

Table 2. Port A Enable Function

CSA

H

L

W/RA

ENA

X

MBA

X

CLKA

A_0–35

Port Function

X

H

L

X

↑

In high-impedance state

Active, FIFO2 output register

Active, Mail2 register

None

L

X

L

H

L

FIFO1 write

Mail1 write

L

H

↑

L

X

↑

None

L

H

L

FIFO2 read

None

L

H

X

↑

L

H

Active, Mail2 register

Mail2 read (set MBF2 HIGH)

Table 3. Port B Enable Function

CSB

W/RB

ENB

X

MBB

X

CLKB

B_0–35

Port Function

H

L

X

L

X

↑

In high-impedance state

Active, FIFO1 output register

Active, Mail1 register

None

L

X

L

H

L

FIFO2 write

Mail2 write

L

H

↑

H

L

X

↑

None

H

L

FIFO1 read

None

L

H

X

↑

L

H

Active, Mail1 register

Mail1 read (set MBF1 HIGH)

Notes:

59. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

60. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

Document #: 38-06025 Rev. **

Page 34 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Table 4. FIFO1 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory ^{[2, 61, 62, 63, 64]}

Synchronized to CLKB

Synchronized to CLKA

CY7C43644AV

CY7C43664AV

CY7C43684AV

EFB/ORB

AEB

AFA

H

FFA/IRA

0

L

H

L

H

1 TO X1

H

(X1+1) to

H

[1024–(Y1+1)]

[4096–(Y1+1)]

[16384–(Y1+1)]

(1024–Y1) to 1023 (4096–Y1) to 4095

1024 4096

(16384–Y1) to

H

L

H

L

16383

16384

Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory ^{[2, 62, 63, 65, 66]}

Synchronized to CLKA

Synchronized to CLKB

CY7C43644AV

CY7C43664AV

CY7C43684AV

EFA/ORA

AEA

AFB

H

FFB/IRB

0

L

H

L

H

1 TO X2

H

(X2+1) to

H

[1024–(Y2+1)]

[4096–(Y2+1)]

[16384–(Y2+1)]

(1024–Y2) to 1023 (4096–Y2) to 4095

(16384–Y2) to

H

L

H

L

16383

1024 4096

16384

Table 6. Data Size for Long-Word Writes to FIFO2

Size Mode ^[67]

Data Written to FIFO2

Data Read From FIFO2

BM

L

SIZE

X

BE

X

B_27–35

A

B_18–26

B

B_9–17

C

B_0–8

D

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

D

Table 7. Data Size for Word Writes to FIFO2

Size Mode ^[67]

Write No. Data Written to FIFO2

Data Read From FIFO2

BM

H

SIZE

L

BE

H

B_9–17

B_0–8

B

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

D

1

2

1

2

A

C

A

D

H

L

D

A

B

C

D

B

Notes:

61. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset

or port A programming.

62. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

63. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to

the output register (no read operation necessary), it is not included in the FIFO memory count.

64. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.

65. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset

or port A programming.

66. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.quested to the output register (no

read operation necessary), it is not included in the FIFO memory count.

67. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Document #: 38-06025 Rev. **

Page 35 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Table 8. Data Size for Byte Writes to FIFO2

Data Written to

FIFO2

Size Mode^[67]

Write No.

Data Read From FIFO2

BM

H

SIZE

H

BE

H

B_0–8

A

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

D

1

2

3

4

1

2

3

4

B

C

D

H

L

D

A

B

C

D

C

B

A

Table 9. Data Size for FIFO Long-Word Reads from FIFO1

Size Mode ^[67]

Data Written to FIFO1

Data Read From FIFO1

BM

L

SIZE

X

BE

X

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

B_27–35

A

B_18–26

B

B_9–17

C

B_0–8

D

Table 10. Data Size for Word Reads from FIFO1

Size Mode^[67]

Data Read From

FIFO1

Data Written to FIFO1

Read No.

BM

H

SIZE

L

BE

H

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

B_9–17

B_0–8

B

D

1

2

1

2

A

C

A

D

H

L

A

B

C

D

B

Table 11. Data Size for Byte Reads from FIFO1

Size Mode ^[67]

Data Read From

FIFO1

Data Written to FIFO1

Read No.

BM

H

SIZE

H

BE

H

A_27–35

A

A_18–26

B

A_9–17

C

A_0–8

D

B_0–8

A

1

2

3

4

1

2

3

4

B

C

D

H

L

A

B

C

D

C

B

A

Document #: 38-06025 Rev. **

Page 36 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Ordering Information

3.3V 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns)

Package

Name

Package

Type

Operating

Range

Ordering Code

CY7C43644AV–7AC

CY7C43644AV–10AC

CY7C43644AV–15AC

7

A128

128-Lead Thin Quad Flat Package

Commercial

10

15

3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns)

Package

Name

Package

Type

Operating

Range

Ordering Code

CY7C43664AV–7AC

CY7C43664AV–10AC

CY7C43664AV–15AC

7

A128

128-Lead Thin Quad Flat Package

Commercial

10

15

3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching

Speed

(ns)

Package

Name

Package

Type

Operating

Range

Ordering Code

CY7C43684AV–7AC

CY7C43684AV–10AC

CY7C43684AV–15AC

CY7C43684AV–15AI

7

A128

128-Lead Thin Quad Flat Package

Commercial

Industrial

10

15

Shaded area contains advance information.

Document #: 38-06025 Rev. **

Page 37 of 39

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Package Diagram

128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128

51-85101-A

Document #: 38-06025 Rev. **

Page 38 of 39

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C43644AV

CY7C43664AV

CY7C43684AV

PRELIMINARY

Document Title: CY7C43644AV, CY7C43664AV, CY7C43684AV 3.3V 1K/4K/16K x 36 x2 Bidirectional Sync FIFO w/Bus

Matching

Document Number: 38-06025

Orig. of

Change

REV.

ECN NO.

Issue Date

Description of Change

**

107291

05/23/01

SZV

Change from Spec #: 38-00777 to 38-06025

Document #: 38-06025 Rev. **

Page 39 of 39


型号：	CY7C43684AV-15AI
厂家：	CYPRESS
描述：	Bi-Directional FIFO, 16KX36, 10ns, Synchronous, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 时钟先进先出芯片内存集成电路
文件：	总39页 (文件大小：652K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C43684AV-15AI [CYPRESS]

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