CY7C455-14JI [CYPRESS]
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| 型号： | CY7C455-14JI |
| 厂家： | 
CYPRESS |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C455
CY7C456
CY7C457
512 x 18, 1K x 18, and 2K x 18 Cascadable
Clocked FIFOs with Programmable Flags
• Depth Expansion Capability
• 52-pin PLCC and 52-pin PQFP
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
Functional Description
• 512 x 18 (CY7C455)
The CY7C455, CY7C456, and CY7C457 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features include
Almost Full/Empty flags and generation/checking of parity.
These FIFOs provide solutions for a wide variety of data buff-
ering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
• 1,024 x 18 (CY7C456)
• 2,048 x 18 (CY7C457)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — I =90 mA
CC
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE pins
)
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
D
0 – 17
Logic BlockDiagram
Pin Configurations
INPUT
REGISTER
PLCC
Top View
CKW
ENW
7
6
5
4
3
2
1 52 51 50 49 48 47
FLAG/PARITY
PROGRAM
REGISTER
PARITY
D
D
D
D
D
D
8
9
10
46
45
44
43
42
41
40
39
13
2
WRITE
CONTROL
D
D
14
1
0
15
16
17
XI 11
HF
ENW 12
FLAG
LOGIC
E/F
13
14
15
16
17
18
19
20
CKW
HF
FL/RT
MR
7C455
7C456
7C457
PAFE/XO
RAM
ARRAY
512 x 18
1024 x 18
2048 x 18
E/F
CKR
38 ENR
37 OE
XO/PAFE
WRITE
POINTER
READ
POINTER
Q
0
Q
1
36
35
34
Q
Q
Q
/PG2/PE2
17
Q
2
16
15
MR
RESET
LOGIC
Q
3
21 22 23 24 25 26 27 28 29 30 31 32 33
FL/RT
EXPANSION
LOGIC
XI
THREE–STATE
OUTPUT REGISTER
READ
CONTROL
RETRANSMIT
LOGIC
OE
Q
, Q /PG1/PE1
8
, Q17/PG2/PE2
c455-1
c455-2
0 –
7
CKR
ENR
Q
9– 16
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 1992 - Revised January 3, 1997
CY7C455
CY7C456
CY7C457
Pin Configurations (continued)
Functional Description (continued)
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit the
data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.When ENW is asserted, data is written into
the FIFO on the rising edge of the CKW signal. While ENW is
held active, data is continually written into the FIFO on each
CKW cycle. The output port is controlled in a similar manner
by a free-running read clock (CKR) and a read enable pin
(ENR). In addition, the CY7C455, CY7C456, and CY7C457
have an output enable pin (OE). The read (CKR) and write
(CKW) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 83.3 MHz are
achievable in the standalone configuration, and up to 83.3
MHz is achievable when FIFOs are cascaded for depth expan-
sion.
PQFP
Top View
52 51 50 49 48 47 46 4544 43 42 41 40
D
13
D
D
1
1
2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
28
27
2
D
14
D
15
D
0
XI
ENW
CKW
HF
E/F
D
16
D
17
FL/RT
7C455
7C456
7C457
MR
CKR
ENR
XO/PAFE
9
Q
0
OE
10
11
12
13
Q
1
Q /PG2/PE2
17
Q
2
Q
16
Depth expansion is possible using the cascade input (XI), cas-
cade output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
Q
3
Q
15
14 1516 17 18 19 20 21 22 23 24 25 26
c455-3
device. The FL pin of the first device is tied to V
.
SS
The CY7C455, CY7C456, and CY7C457 provide three status
pins. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than or Equal to Half Full, Greater
than Half Full, Almost Full, and Full (see Table 1). The Almost
Empty/Full flag (PAFE) shares the XO pin on the CY7C455,
CY7C456, and CY7C457. This flag is valid in the standalone
and width-expansion configurations. In the depth expansion,
this pin provides the expansion out (XO) information that is
used to signal the next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to
either the read clock (CKR) or the write clock (CKW). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the CKR. The flags denoting
Half Full, Almost Full, and Full states are updated exclusively
by CKW. The synchronous flag architecture guarantees that
the flags maintain their status for some minimum time. This
time is typically equal to approximately one cycle time.
The CY7C455/6/7 uses center power and ground for reduced
noise. All configurations are fabricated using an advanced
0.65u CMOS technology. Input ESD protection is greater
than 2001V, and latch-up is prevented by the use of guard
rings.
2
CY7C455
CY7C456
CY7C457
Selection Guide
7C455/6/7–12
7C455/6/7–14
7C455/6/7–20
7C455/6/7–30
Maximum Frequency (MHz)
83.3
83.3
9
71.4
71.4
10
50
50
15
20
9
33.3
33.3
20
Maximum Cascadable Frequency
Maximum Access Time (ns)
Minimum Cycle Time (ns)
12
5
14
30
Minimum Clock HIGH Time (ns)
Minimum Clock LOW Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
6.5
6.5
5
12
5
9
12
4
6
7
0
0
0
0
9
10
15
140
160
20
Maximum Current
(mA)
Commercial
Industrial
160
180
160
180
120
140
Selection Guide (continued)
CY7C455
512 x 18
CY7C456
CY7C457
2,048 x 18
Density
1,024 x 18
Yes
OE, Depth Cascadable
Package
Yes
Yes
52-Pin PLCC/PQFP
52-Pin PLCC/PQFP
52-Pin PLCC/PQFP
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................–55°C to +125°C
Ambient
Range
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Commercial
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
[1]
Industrial
Note:
1.
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
TA is the “instant on” case temperature.
3
CY7C455
CY7C456
CY7C457
Pin Definitions
Signal Name I/O
Description
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
D
I
) into
0 − 17
0 − 17
the FIFO’s memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO’s
programming register. D , are ignored if the device is configured for parity generation.
8
17
Q
Q
O
O
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
,
0 − 7
0 − 7
Q
) out of the FIFO’s memory. If MR is active at the rising edge of CKR, data is read from the
9 − 16
9 − 16
programming register.
Q /PG1/PE1
Q
Function varies according to mode:
Parity disabled – same function as Q
8
17
/PG2/PE2
and Q
0 − 7 9 − 16
Parity enabled, generation – parity generation bit (PG )
x
Parity enabled, check – Parity Error Flag (PE )
x
ENW
ENR
CKW
I
I
I
Enable Write: Enables the CKW input (for both non-program and program modes).
Enable Read: Enables the CKR input (for both non-program and program modes).
Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
O
O
O
Half Full Flag: Synchronized to CKW.
E/F
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW.
PAFE/XO
Dual-Mode Pin:
Not Cascaded – programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR.
Cascaded – expansion out signal, connected to XI of next device.
XI
I
I
Expansion-In Pin:
Not Cascaded – XI is tied to V
Cascaded – expansion Input, connected to XO of previous device.
.
SS
FL/RT
First Load/Retransmit Pin:
Cascaded – the first device in the daisy chain will have FL tied to V ; all other devices will have FL tied
SS
to V (Figure 1).
CC
Not Cascaded – tied to V
.
CC
Retransmit function is also available in standalone mode by strobing RT.
MR
OE
I
I
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D
and D
is written into the programmable register
0 - 9,10, or 11
15-17
on the rising edge of CKW. Program register contents appear on Q
edge of CKR.
and Q
after the rising
0 - 9,10, or 11
15-17
Output Enable for Q
, Q
, Q /PG1/PE1 and Q /PG2/PE2 pins.
9 − 16 8 17
0 − 7
4
CY7C455
CY7C456
CY7C457
Electrical Characteristics Over the Operating Range
7C455/6/7– 7C455/6/7– 7C455/6/7– 7C455/6/7–
12 14 20 30
Parameter
Description
Test Conditions
Min. Max Min. Max Min. Max Min. Max Unit
V
Output HIGH
Voltage
V
V
= Min., I = –2.0 mA 2.4
2.4
2.4
2.4
V
OH
CC
CC
OH
V
Output LOW
Voltage
= Min., I = 8.0 mA
0.4
0.4
0.4
0.4
V
OL
OL
[2]
V
V
Input HIGH Voltage
Input LOW Voltage
2.2
–0.5
–10
V
2.2
V
2.2
V
2.2
V
CC
V
V
IH
CC
CC
CC
[2]
0.8
–0.5 0.8 –0.5 0.8 –0.5 0.8
IL
I
Input Leakage
Current
V
V
= Max.
+10 –10 +10 –10 +10 –10 +10
–90 –90 –90
+10 –10 +10 –10 +10 –10 +10
µA
IX
CC
CC
[3]
I
Output Short
Circuit Current
= Max., V
= GND –90
OUT
mA
OS
I
I
Output OFF, High Z OE > V , V < V < V
Current
–10
µA
OZL
OZH
IH
SS
O
CC
[4]
I
I
I
Operating Current
V
= Max.,
= 0 mA
Com’l
Ind
160
180
90
160
180
90
140
160
90
120 mA
140 mA
CC1
CC
I
OUT
[5]
Operating Current
Standby Current
V
= Max.,
= 0 mA
Com’l
Ind
90
mA
CC2
CC
I
OUT
100
40
100
40
100
40
100 mA
[6]
SB
V
= Max.,
= 0 mA
Com’l
Ind
40
40
mA
mA
CC
I
OUT
40
40
40
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
10
12
pF
pF
IN
A
V
= 5.0V
CC
C
OUT
AC Test Loads and Waveforms[8, 9, 10, 11, 12]
R1 500
Ω
5V
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
R2
333
C
L
Ω
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
c455-4
c455-5
Equivalent to:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2V
Notes:
2. The VIH and VIL specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or VSS
.
3. Test no more than one output at a time for not more than one second.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (fMAX), while data inputs
switch at fMAX/2. Outputs are unloaded.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX).
7. Tested initially and after any design or process changes that may affect these parameters.
8. CL = 30 pF for all AC parameters except for tOHZ
.
9. CL = 5 pF for tOHZ
.
10. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ
.
11. tOE and tOLZ are measured at ± 100 mV from the steady state.
12.
tOHZ is measured at +500 mV from VOL and – 500 mV from VOH.
5
CY7C455
CY7C456
CY7C457
[13]
Switching Characteristics Over the Operating Range
7C455/6/7– 7C455/6/7– 7C455/6/7– 7C455/6/7–
12 14 20 30
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
Write Clock Cycle
Read Clock Cycle
Clock HIGH
12
12
5
14
14
20
20
9
30
30
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKW
CKR
CKH
CKL
A
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6.5
6.5
Clock LOW
5
9
Data Access Time
9
10
15
20
Previous Output Data Hold After Read HIGH
Previous Flag Hold After Read/Write HIGH
Data Set-Up
0
0
4
0
4
0
0
0
5
0
5
0
0
0
6
0
6
0
0
0
7
0
7
0
OH
FH
SD
Data Hold
HD
Enable Set-Up
SEN
HEN
OE
Enable Hold
OE LOW to Output Data Valid
OE LOW to Output Data in Low Z
OE HIGH to Output Data in High Z
Read HIGH to Parity Generation
Read HIGH to Parity Error Flag
Flag Delay
9
10
15
20
[7, 14]
0
0
0
0
OLZ
OHZ
PG
[7, 14]
9
9
9
9
10
10
10
10
15
15
15
15
20
20
20
20
PE
FD
[15]
Opposite Clock After Clock
Opposite Clock Before Clock
Master Reset Pulse Width (MR LOW)
Last Valid Clock LOW Set-Up to MR LOW
Data Hold From MR LOW
0
12
14
0
0
14
14
0
0
20
20
0
0
30
30
0
SKEW1
SKEW2
PMR
[16]
SCMR
OHMR
MRR
0
0
0
0
Master Reset Recovery
12
14
20
30
(MR HIGH Set-Up to First Enabled Write/Read)
t
t
t
t
t
t
t
t
t
MR HIGH to Flags Valid
12
12
14
14
20
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
MRF
AMR
SMRP
HMRP
FTP
MR HIGH to Data Outputs LOW
Program Mode—MR LOW Set-Up
Program Mode—MR LOW Hold
Program Mode—Write HIGH to Read HIGH
Program Mode—Data Access Time
Program Mode—Data Hold Time from MR HIGH
Retransmit Pulse Width
12
9
14
10
14
20
15
20
30
20
30
12
12
14
20
30
AP
0
0
0
0
OHP
PRT
12
12
14
14
20
20
30
30
Retransmit Recovery Time
RTR
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and
Waveforms and capacitance as in notes 8 and 9, unless otherwise specified.
14. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device.
15. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle
(for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the
opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is
the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal
to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
16. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 15 for definition of clock and opposite clock.
6
CY7C455
CY7C456
CY7C457
Switching Waveforms
t
CKW
Write Clock Timing Diagram
t
t
CKL
CKH
CKW
ENABLED WRITE
DISABLED WRITE
t
t
HD
SD
D
0 − 17
VALID DATA IN
t
t
HEN
SEN
ENW
t
t
t
FH
SEN
HEN
E/F,PAFE,HF
t
FH
t
FD
t
FD
c455-6
Read Clock Timing Diagram
t
CKR
t
t
CKL
CKH
CKR
ENABLED READ
DISABLED READ
NEW WORD
t
A
t
OH
Q
0 − 17
PREVIOUS WORD
t
t
HEN
SEN
ENR
t
t
t
FH
SEN
HEN
E/F,PAFE
t
FH
t
FD
t
FD
c455-7
[17, 18, 19, 20]
MasterReset (Defaultwith Free-RunningClocks) Timing Diagram
t
PMR
MR
t
SCMR
t
MRR
CKW
FIRST
WRITE
ENW
t
SCMR
t
MRR
CKR
ENR
t
t
OHMR
AMR
ALL DATA
OUTPUTS LOW
Q
0 − 17
VALID DATA
t
t
MRF
E/F,PAFE
HF
MRF
c455-8
Notes:
17. To only perform reset (no programming), the following criteria must be met: ENW or CKW must be inactive while MR is LOW.
18. To only perform reset (no programming), the following criteria must be met: ENR or CKR must be inactive while MR is LOW.
19. All data outputs (Q0 - 17) go LOW as a result of the rising edge of MR after tAMR
.
20. In this example, Q0 - 17 will remain valid until tOHMR if either the first read shown did not occur or if the read occurred soon enough such that the valid
data was caused by it.
7
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[19, 20]
Master Reset (ProgrammingMode) TimingDiagram
t
t
HMRP
SMRP
MR
t
SCMR
t
t
MRR
CKH
LAST
VALID
WRITE
PGM
WRITE
FIRST
WRITE
CKW
ENW
SECOND
WRITE
t
FTP
LOW
t
t
HD
SD
LAST
WORD
PGM
WORD
D
0 − 17
WORD 1
WORD 2
t
t
t
HMRP
SCMR
SMRP
CKR
ENR
LAST
VALID
READ
PGM
READ
t
CKH
LOW
t
t
AP
t
t
AMR
OHMR
OHP
ALL DATA
OUTPUTS LOW
Q
0 − 17
VALID DATA
PGM WORD
c455-9
[19, 20]
gram
Master Reset (ProgrammingMode with Free-Running Clocks) Timing Dia
t
t
HMRP
SMRP
t
CKW
MR
t
t
t
t
MRR
SCMR
CKH
CKL
CKW
LAST
VALID
WRITE
PGM
WRITE
FIRST
WRITE
SECOND
WRITE
t
t
HEN
SEN
ENW
0 − 17
CKR
t
FTP
LAST
WORD
PGM
WORD
D
WORD 1
WORD 2
t
CKR
t
t
t
t
HMRP
MRR
SCMR
SMRP
PGM
READ
LAST
VALID
READ
t
t
CKL
CKH
t
t
SEN
HEN
ENR
t
AMR
t
t
AP
t
OHMR
OHP
ALL DATA
OUTPUTS LOW
Q
VALID DATA
PGM WORD
0 − 17
c455-10
8
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[21, 24, 25]
Read to Empty Timing Diagram
COUNT
3
2
1
0
1
1 (NO CHANGE)
LATENT CYCLE
0
R1
ENABLED
READ
R2
R3
ENABLED
READ
R4
R5
ENABLED
READ
ENABLED
READ
CKR
ENR
FLAG
UPDATE
READ
t
t
SKEW2
SKEW1
CKW
ENW
W1
ENABLED
WRITE
LOW
t
FD
t
FD
t
FD
E/F
c455-12
[21, 22, 23, 24]
Read to EmptyTiming Diagram with Free-RunningClocks
LATENT CYCLE
1
0
1
0
COUNT
CKR
R4
R1
R2
R3
IGNORED
READ
R5
R6
FLAG
UPDATE
READ
ENABLED
IGNORED
ENABLED
IGNORED
READ
READ
READ
READ
t
SKEW2
ENR
t
t
SKEW2
SKEW1
CKW
W1
W2
W4
W5
W6
W3
ENABLED
WRITE
ENW
HF
HIGH
LOW
t
FD
t
FD
t
FD
E/F
PAFE
c455-11
Notes:
21. “Count” is the number of words in the FIFO.
22. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
23. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes
W3 in the flag update.
24. CKR is clock and CKW is opposite clock.
25. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs tSKEW2 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state. It is
important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count or the
FIFO’s data outputs.
9
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[21, 24, 26]
17
Read to Almost Empty Timing Diagram with Free-Running Clocks
COUNT
17
16
17
18
16
15
R1
ENABLED
READ
R2
R3
R4
ENABLED
READ
R5
ENABLED
READ
R6
ENABLED
READ
CKR
ENR
t
t
SKEW2
SKEW1
CKW
W2
ENABLED
WRITE
W3
ENABLED
WRITE
W1
W4
W51
W6
ENW
HF
HIGH
HIGH
E/F
t
FD
t
FD
t
FD
PAFE
c455-14
[21, 24, 26, 27, 28]
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks
18 (no change)
FLAG UPDATE CYCLE
COUNT
17
16
17
18
17
16
15
CKR
R4
R1
ENABLED
READ
R2
R3
R5
ENABLED
READ
R6
ENABLED
READ
R7
ENABLED
READ
FLAG
UPDATE
READ
ENR
t
t
SKEW2
SKEW1
CKW
ENW
W2
ENABLED
WRITE
W3
ENABLED
WRITE
W1
W4
W5
W6
W7
HIGH
HIGH
HF
E/F
t
FD
t
FD
t
FD
PAFE
c455-13
Notes:
26. The FIFO in this example is assumed to be programmed to its default flag values. Almost Empty is 16 words from Empty; Almost Full is 16 locations from Full.
27. R4 only updates the flag status. It does not affect the count because ENR is HIGH.
28. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 Á18; two enabled writes: W2, W3) before a read (R4)
can update flags to the Less Than Half Full state.
10
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[21, 29, 30, 31]
Write to Half Full Timing Diagram withFree-RunningClocks
1024
[512]
[256]
1025
[513]
[257]
1024
[512]
[256]
1023
[511]
[255]
1024
[512]
[256]
1025
[513]
[257]
1026
[514]
[258]
COUNT
CKW
W1
W2
W3
W4
W5
W6
ENABLED
ENABLED
ENABLED
ENABLED
WRITE
WRITE
WRITE
WRITE
ENW
CKR
ENR
t
t
SKEW2
SKEW1
R2
ENABLED
READ
R3
R1
R4
R5
R6
ENABLED
READ
t
FD
t
FD
t
FD
HF
E/F
HIGH
HIGH
PAFE
c455-15
[21, 29, 30, 31, 32, 33]
Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks
1023 [511]
[255] (no change)
1024
[512]
[256]
1025
[513]
[257]
1024
[512]
[256]
1023
[511]
[255]
1024
[512]
[256]
1025
[513]
[257]
1026
[514]
[258]
FLAG UPDATE CYCLE
COUNT
W4
CKW
W1
ENABLED
WRITE
W2
W3
W5
ENABLED
WRITE
W6
ENABLED
WRITE
W7
ENABLED
WRITE
FLAG
UPDATE
WRITE
ENW
t
t
SKEW2
SKEW1
CKR
ENR
R3
ENABLED
READ
R2
ENABLED
READ
R1
R4
R5
R6
R7
t
FD
t
FD
t
FD
HF
HIGH
E/F
c455–16
PAFE
HIGH
Notes:
29. CKW is clock and CKR is opposite clock.
30. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates
Half Full for the CY7C448 and CY7C458.
31. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the HF to be true (LOW).
32. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH.
33. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (i.e., 1,025 Á1,023; two enabled reads: R2 and R3)
before a write (W4) can update flags to less than Half Full.
11
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[21, 26, 29, 34, 35]
Write to Almost Full TimingDiagram
2030
[1016]
[494]
2031
[1017]
[495]
2032
[1018]
[496]
2031
[1017]
[495]
2030
[1016]
[494]
2031 [1017]
[495]
2032
[496]
2033
COUNT
[497]
2030 [1016]
[494]
2031 [1017]
[495]
2032 [1018]
[496]
CKW
W1
W2
W3
W4
W5
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
WRITE
WRITE
WRITE
WRITE
WRITE
FLAG UPDATE
ENW
LOW
t
t
SKEW2
SKEW1
R1
ENABLED
READ
R2
ENABLED
READ
CKR
ENR
LOW
t
FD
t
FD
t
FD
t
FD
PAFE
HF
LOW
HIGH
E/F
c455-18
[21, 26, 29]
Write to Almost Full Timing Diagram with Free-RunningClocks
2031
[1017]
[495]
2032
[1018]
[496]
2031
[1017]
[495]
2030
[1016]
[494]
2031
[1017]
[495]
2032
[1018]
[496]
2033
[1019]
[497]
COUNT
CKW
W1
ENABLED
WRITE
W2
W3
W4
ENABLED
WRITE
W5
ENABLED
WRITE
W6
ENABLED
WRITE
ENW
CKR
t
t
SKEW2
SKEW1
R2
ENABLED
READ
R3
R6
R1
R4
R5
ENABLED
READ
ENR
HF
LOW
HIGH
E/F
t
FD
t
FD
t
FD
PAFE
c455-17
Notes:
34. W2 updates the flag to the Almost Full state by asserting PAFE. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when
updating flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be enabled
to update flags.
35. The dashed lines show W3 as a flag update write rather than an enabled write because ENW is HIGH.
12
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[21, 26, 29]
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks
2030 [1016]
[494] (no change)
2031
[1017]
[495]
2032
[1018]
[496]
2031
[1017]
[495]
2030
[1016]
[494]
2031
[1017]
[495]
2032
[1018]
[496]
2033
[1019]
[497]
FLAG UPDATE CYCLE
COUNT
W1
ENABLED
WRITE
W2
W3
W4
W5
ENABLED
WRITE
W6
ENABLED
WRITE
W7
ENABLED
WRITE
CKW
FLAG
UPDATE
WRITE
ENW
CKR
t
t
SKEW2
SKEW1
R1
R4
R5
R6
R7
R2
ENABLED
READ
R3
ENABLED
READ
ENR
HF
LOW
E/F
HIGH
t
FD
t
FD
t
FD
PAFE
c455-19
[21, 29, 36]
Write to Full Flag Timing Diagram with Free-Running Clocks
LATENT CYCLE
2048
[1024]
[512]
2047
[1023]
[511]
2048
[1024]
[512]
2047
[1023]
[511]
2048
[1024]
[512]
2048
[1024]
[512]
COUNT
W1
ENABLED
WRITE
W2
IGNORED
WRITE
W3
W4
W5
ENABLED
WRITE
W6
IGNORED
WRITE
CKW
IGNORED
WRITE
FLAG
UPDATE
WRITE
t
SKEW2
ENW
CKR
t
t
SKEW2
SKEW1
R2
R3
R6
R1
R4
R5
ENABLED
READ
ENR
HF
LOW
LOW
t
FD
t
FD
t
FD
E/F
PAFE
c455-20
Note:
36. W2 is ignored because the FIFO is full (count = 2,048 [1,024] [512]). It is important to note that W3 is also ignored because R3, the first enabled read after
full, occurs less than tSKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than tSKEW2 before W4,
W4 includes R3 in the flag update.
13
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[37, 38]
Even Parity GenerationTimingDiagram
CKR
ENABLED READ
DISABLED READ
t
PG
PE , (PE )
1
2
Q
0− 7
)
PREVIOUS WORD:
EVEN NUMBER OF 1s
NEW WORD:
ODD NUMBER OF 1s
(Q
9 − 16
ENR
c455-21
[37, 39]
Even Parity GenerationTimingDiagram
CKR
ENABLED READ
DISABLED READ
t
PE , (PE )
PG
1
2
Q
NEW WORD:
EVEN NUMBER OF 1s
0− 7
)
PREVIOUS WORD:
ODD NUMBER OF 1s
(Q
9 − 16
ENR
c455-22
Notes:
37. In this example, the FIFO is assumed to be programmed to generate even parity. The Q0−7 word is shown. The example is similar for the Q9-16 word.
38. If Q0−7 “new word” also has an even number of 1s, then PG1 stays LOW.
39. If Q0−7 “new word” also has odd number of 1s, then PG1 stays HIGH.
14
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
[40]
Even ParityChecking
CKW
WRITE M
WRITE M+1
WRITE M+2
ENW
WORD M:
EVEN NUMBER
OF 1“s
WORD M+ 1:
ODD NUMBER
OF 1“s
WORD M+ 2:
EVEN NUMBER
OF 1“s
D
0− 7
CKR
ENR
READ M
READ M+1
READ M+2
t
PE
t
PE
PE
1
(PE )
2
8 LSBs OF
WORD M-1
8 LSBs OF
WORD M
8 LSBs OF
WORD M+1
8 LSBs OF
WORD M+2
Q
0− 7
)
(Q
9− 16
c455-23
[41, 42]
Output Enable Timing
CKR
READ M+1
LOW
ENR
OE
t
t
OE
OHZ
VALID DATA
WORD M
VALID DATA
WORD M+1
Q
0− 17
t
c455–24
OLZ
[43, 44]
Retransmit Timing
FL/RT
t
PRT
t
RTR
REN/WEN
E/F, HF, PAFE
42X5–21
Notes:
40. In this example, the FIFO is assumed to be programmed to check for even parity. The Q0-7 word is shown.
41. This example assumes that the time from the CKR rising edge to valid word M+1 > tA. The Q0-7 word is shown.
42. If ENR was HIGH around the rising edge of CKR (i.e., read disabled), the valid data at the far right would once again be word M instead of word M+1.
43. Clocks are free running in this case.
44. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR
.
15
CY7C455
CY7C456
CY7C457
When free-running clocks are tied to CKW and CKR, program-
ming can still occur during a master reset cycle with the adher-
ence to a few additional timing parameters. The enable pins
Architecture
The CY7C455/6/7 consists of an array of 512, 1024, or 2048
words of 18 bits each (implemented by a dual-port array of
SRAM cells), a read pointer, a write pointer, control signals
(CKR, CKW, ENR, ENW, and MR), and flags (HF, E/F, PAFE).
The CY7C455/6/7 also includes the control signals OE, FL, XI,
and XO for depth expansion.
must be set-up t
before the rising edge of CKW or CKR.
SEN
Hold times of t
must also be met for ENW and ENR.
HEN
Data present on D
during a program write will determine the
−
0 9
distance from Empty (Full) that the Almost Empty (Almost Full)
flags will become active. See Table 1 for a description of the
six possible FIFO states. P in Table 1 refers to the decimal
Resetting the FIFO
equivalent of the binary number represented by D
.
0−7, 8 or 9
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty condition
signified by E/F and PAFE being LOW and HF being HIGH. All
Programming options for the CY7C455/6/7 are listed in
Table 4.
The programmable PAFE function on the CY7C455/6/7 is only
valid when not cascaded. If the user elects not to program the
FIFO’s flags, the default is as follows: the Almost Empty con-
dition (Almost Full condition) is activated when the FIFO con-
tains 16 or less words (empty locations).
data outputs (Q
) go low at the rising edge of MR. In order
0−17
for the FIFO to reset to its default state, a falling edge must
occur on MR and the user must not read or write while MR is
LOW (unless ENR and ENW are HIGH or unless the device is
being programmed). Upon completion of the master reset cy-
Parity is programmed with the D bits. See Table 4 for a
−
15 17
cle, all data outputs will go LOW t
All flags are guaranteed to be valid t
HIGH.
after MR is deasserted.
AMR
summary of the various parity programming options. Data
present on D during a program write will determine
after MR is taken
MRF
15 17
−
whether the FIFO will generate or check even/odd parity for the
data present on D and D thereafter. If the user elects
FIFO Operation
0−7
9−16
not to program the FIFO, the parity function is disabled. Flag
operation and parity are described in greater detail in subse-
quent sections.
When the ENW signal is active (LOW), data present on the
pins is written into the FIFO on each rising edge of the
D
0−17
CKW signal. Similarly, when the ENR signal is active, data in
the FIFO memory will be presented on the Q outputs. New
Flag Operation
0−17
data will be presented on each rising edge of CKR while ENR
is active. ENR must set up t before CKR for it to be a valid
The CY7C455/6/7 provides three status pins when not cas-
caded. The three pins, E/F, PAFE, and HF, allow decoding of
six FIFO states (Table 1). PAFE is not available when the
CY7C455/6/7 is cascaded for depth expansion. All flags are
synchronous, meaning that the change of states is relative to
one of the clocks (CKR or CKW, as appropriate).
ty and Almost Empty flag states are exclusively updated by
each rising edge of the read clock (CKR). For example, when
the FIFO contains 1 word, the next read (rising edge of CKR
while ENR=LOW) causes the flag pins to output a state that
represents Empty. The Half Full, Almost Full, and Full flag
states are updated exclusively by the write clock (CKW). For
example, if the CY7C457 contains 2,047 words (2,048 words
indicate Full for the CY7C457), the next write (rising edge of
CKW while ENW=LOW) causes the flag pins to output a state
that is decoded as Full.
SEN
read. ENW must occur t
write.
before CKW for it to be a valid
SEN
An output enable (OE) pin is provided to three-state the Q
0−17
outputs when OE is asserted. When OE is enabled (low), data
in the output register will be available to the Q outputs after
[46]
The Emp-
0−17
t
. If devices are cascaded, the OE function will only output
OE
data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
outputs
0–17
Programming
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half
Full, Almost Full, Full) are exclusively updated by CKW, careful
attention must be given to the flag operation. The user must
be aware that if a boundary (Empty, Almost Empty, Half Full,
Almost Full, or Full) is crossed due to an operation from a clock
that the flag is not synchronized to (i.e., CKW does not affect
Empty or Almost Empty), a flag update cycle is necessary to
represent the FIFO’s new state. The signal to which a flag is
not synchronized will be referred to as the opposite clock
(CKW is opposite clock for Empty and Almost Empty flags;
CKR is the opposite clock for Half Full, Almost Full, and Full
flags). Until a proper flag update cycle is executed, the syn-
chronous flags will not show the new state of the FIFO.
The CY7C455/6/7 is programmed during a master reset cycle.
If MR and ENW are LOW, a rising edge on CKW will write the
[45]
D
and D
inputs into the programming register
.
0−7,8,or9
15–17
MR must be set up a minimum of t
before the program
SMRP
write rising edge and held t
after the program write falling
HMRP
edge. The user has the ability to also perform a program read
during the master reset cycle. This will occur at the rising edge
of CKR when MR and ENR are asserted. The program read
must be performed a minimum of t
after a program write,
FTP
and the program word will be available t after the read oc-
AP
curs. If a program write does not occur, a program read may
occur a minimum of t
after MR is asserted. This will read
SMRP
the default program value.
Notes:
45. CKW will write D0–9 into the programming register. CKR will read D0–9 during a programming register read.
46. The synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to.
16
CY7C455
CY7C456
CY7C457
When updating flags, the FIFO must make a decision as to
whether or not the opposite clock was recognized when a clock
updates the flag. For example (when updating the Empty flag),
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (i.e., the Full
flag can only be updated by a clock pulse on the CKW pin). A
full FIFO that is read will be described with a Full flag until a
rising edge is presented to the CKW pin. When making the
transition from Full to Almost Full (or Full to Greater Than Half
Full), a clock cycle on CKW is necessary to update the flags
to the current state. In such a state (flags showing Full even
through data has been read from the FIFO), two write cycles
are required to write data into the FIFO. The first write serves
only to update the flags to the Almost Full or Greater Than Half
Full state, while the second write inputs the data. This first
write cycle is known as the latent or flag update cycle because
it does not affect the data in the FIFO or the count (number of
words in the FIFO). It simply deasserts the Full flag. The flag
is updated regardless of the ENW state. Therefore, the update
occurs even when ENW is deasserted (HIGH), so that a valid
write is not necessary to update the flags to correctly describe
if a write occurs at least t
anteed not to be included when CKR updates the flag. If a write
after a read, the write is guar-
SKEW1
occurs at least t before a read, the write is guaranteed
SKEW2
to be included when CKR updates flag. If a write occurs within
after or t before CKR, then the decision of wheth-
t
SKEW1
SKEW2
er or not to include the write when the flag is updated by CKR
is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the
boundary flags (Empty, Full). Both operations are described
below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
the FIFO. In this example, the read must occur at least t
The Empty flag is synchronized to the CKR signal (i.e., the
Empty flag can only be updated by a clock pulse on the CKR
pin). An empty FIFO that is written to will be described with an
Empty flag state until a rising edge is presented to the CKR
pin. When making the transition from Empty to Almost Empty
(or Empty to Less than or Equal to Half Full), a clock cycle on
CKR is necessary to update the flags to the current state. In
such a state (flags showing Empty even though data has been
written to the FIFO), two read clock cycles are required to read
data out of the FIFO. The first read serves only to update the
flags to the Almost Empty or Less than or Equal to Half Full
state, while the second read outputs the data. This first read
cycle is known as the latent or flag update cycle because it
does not affect the data in the FIFO or the count (number of
words in FIFO). It simply deasserts the Empty flag. The flag is
updated regardless of the ENR state. Therefore, the update
occurs even when ENR is deasserted (HIGH), so that a valid
read is not necessary to update the flags to correctly describe
SKEW2
before the flag update cycle in order for the FIFO to guarantee
that the read will be included in the count when CKW updates
the flags. When a free-running clock is connected to CKW, the
flag updates each cycle. Full flag operation is similar to the
Empty flag operation described in Table 2.
Non-Boundary Flags (Almost Empty, Half Full, Almost Full)
The CY7C455/6/7 features programmable Almost Empty and
Almost Full flags. Each flag can be programmed a specific
distance from the corresponding boundary flags (Empty or
Full). The flags can be programmed to be activated at the
Empty or Full boundary, or at any distance from the Empty/Full
boundary. When the FIFO contains the number of words or
fewer for which the flags have been programmed, the PAFE
flag will be asserted signifying that the FIFO is Almost Empty.
When the FIFO is within that same number of empty locations
from being Full, the PAFE will also be asserted signifying that
the FIFO is Almost Full. The HF flag is decoded to distinguish
the states.
the FIFO. In this example, the write must occur at least t
SKEW2
before the flag update cycle in order for the FIFO to guarantee
that the write will be included in the count when CKR updates
the flags. When a free-running clock is connected to CKR, the
flag is updated each cycle. Table 2 shows an example of a
sequence of operations that update the Empty flag.
The default distance from where PAFE becomes active to the
boundary (Empty, Full) is 16 words/locations. The Almost Full
and Almost Empty flags can be programmed so that they are
only active at Full and Empty boundaries. However, the oper-
ation will remain consistent with the non-boundary flag opera-
tion that is discussed below.
.
[47]
Table 1. Flag Truth Table
7C455
Words in FIFO
7C456
7C457
E/F PAFE
HF
1
1
1
0
State
Empty
Almost Empty
Words in FIFO
Words in FIFO
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1 => P
1 => P
1 => P
Less than or Equal to Half Full P + 1 => 256
P + 1 => 512
513 => 1023 – P
1024 – P => 1023
1024
P + 1 => 1024
1025 => 2047 – P
2048 – P => 2047
2048
Greater than Half Full
Almost Full
Full
257 => 511 – P
512 – P => 511
512
0
0
0
Notes:
47. P is the decimal value of the binary number represented by D0–7 for the CY7C455, D0–8 for the CY7C456, and D0–9 for the CY7C457. P = 0 signifies that
the Almost Empty state = Empty state.
17
CY7C455
CY7C456
CY7C457
Table 2. Empty Flag (Boundary Flag) Operation Example
Status Before Operation
Number
Status After Operation
Number
Current
State of
FIFO
of
Words
Next
of
State
Words
E/F AFE HF in FIFO
Operation
of FIFO E/F AFE HF in FIFO
Comments
Empty
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
2
2
1
0
1
1
Write
(ENW = 0)
Empty
Empty
AE
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
2
1
0
1
1
0
Write
Write
Empty
Empty
AE
Write
(ENW = 0)
Read
(ENR = X)
Flag Update
Read
Read
(ENR = 0)
AE
AE
Read
(ENR = 0)
Empty
Empty
AE
Read (transition from
Almost Empty to Empty)
Empty
Empty
AE
Write
(ENR = 0)
Write
Read
(ENR = X)
Flag Update
Read
Empty
Read (transition from
(ENR = 0)
Almost Empty to Empty)
Almost Empty is only updated by CKR while Half Full and Al-
most Full are updated by CKW. Non-boundary flags employ
flag update cycles similar to the boundary flag latent cycles in
order to update the FIFO status. For example, if the FIFO just
reaches the Greater than Half Full state, and then two words
are read from the FIFO, a write clock (CKW) will be required
to update the flags to the Less than Half Full state. However,
unlike the boundary flag latent cycle, the state of the enable
pin (ENW in this case) affects the operation. Therefore, set-up
ignored. The parity bits are stored internally as D and D ,
8 17
and during a subsequent read will be available on the PG1
and PG2 pins along with the data words from which the
parity was generated (Q
and Q
). For example, if par-
0–7
9–16
ity generate is set to ODD and the D
inputs have an
0–7
EVEN number of 1s, PG1 will be HIGH.
Parity Check (PE mode)
If the FIFO is programmed for parity checking, it will compare
the parity of D and D with the program register. For
and hold times for the enable pins must be met (t
and t
).
SEN
HEN
0–8
9–17
If the enable pin is active during the flag update cycle, the
count and data are updated in addition to PAFE and HF. If the
enable pin is not asserted during the flag update cycle, only
the flags are updated. Table 3 shows an example of a se-
quence of operations that update the Almost Empty and Al-
most Full flags
example, D and D will be set according to the result of
8
17
the parity check on each word. When these words are later
read, PE and PE will reflect the result of the parity check.
1
2
If a parity error occurs in D , D will be set LOW internally.
0–8
8
When this word is later read, PE will be LOW.
1
Retransmit
The CY7C455/6/7 also features even or odd parity checking
and generation. D
are used during a program write to
15–17
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
describe the parity option desired. Table 4 summarizes pro-
grammable parity options. If the user elects not to program
the device, then parity is disabled. Parity information is pro-
vided on two multi-mode output pins (Q /PG1/PE1 and
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse onRT
resets the internal read pointer to the first physical location of the
FIFO. WCLK and RCLK may be free running but must be disabled
8
Q
/PG2/PE2). The three possible modes are described in
17
the following paragraphs.
Programmable Parity
Parity Disabled (Q /Q mode)
during and t
after the retransmit pulse. With every valid read cycle
8
17
RTR
after retransmit, previously accessed data is read and the read point-
er is incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO after ac-
tivation of RT are transmitted also.
When parity is disabled (or the user does not program parity
option) the FIFO stores all 18 bits present on D inputs
0–17
internally and will output all 18 bits on Q
.
0–17
Parity Generate (PG mode)
This mode is used to generate either even or odd parity (as
programmed) from D and D . D and D inputs are
The full depth of the FIFO can be repeatedly retransmitted.
0–7
9–16
8
17
18
CY7C455
CY7C456
CY7C457
next device, with XO of the last device connected to XI of
the first device. The first device has its first load pin (FL)
Width Expansion Modes
During width expansion all flags (programmable and nonpro-
grammable) are available. These FIFOs can be expanded in
width to provide word width greater than 18 in increments of
18. During width expansion mode all control line inputs are
common. When the FIFO is being read near the Empty (Full)
boundary, it is important to note that both sets of flags should
be checked to see if they have been updated to the Not Empty
(Not Full) condition to insure that the next read (write) will per-
form the same operation on all devices.
tied to V while all other devices must have this pin tied to
SS
V
. The first device will be the first to be write and read
CC
enabled after a master reset.
Proper operation also requires that all cascaded devices have
common CKW, CKR, ENW, ENR, D
, Q
, and MR pins.
0–17
0–17
When cascaded, one device at a time will be read enabled
so as to avoid bus contention. By asserting XO when ap-
propriate, the currently enabled FIFO alerts the next FIFO
that it should be enabled. The next rising edge on CKR puts
Checking all sets of flags is critical so that data is not read from
the FIFOs “staggered” by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
Q
outputs of the first device into a high-impedance
0–17
state. This occurs regardless of the state of ENR or the next
FIFO’s Empty flag. Therefore, if the next FIFO is empty or
close together. If the read occurs less than t
after the
undergoing a latent cycle, the Q
bus will be in a high-im-
SKEW2
0–17
first write to two width-expanded devices, A and B, device
A may go Almost Empty (read recognized as flag update)
while device B stays Empty (read ignored). This occurs be-
cause a read can be either recognized or ignored if it oc-
pedance state until the next device receives its first read,
which brings its data to the Q bus.
0–17
Program Write/Read of Cascaded Devices
curs within t
of a write. The next read cycle outputs
SKEW2
Programming of cascaded FIFOs is the same as for a single
device. Because the controls of the FIFOs are in parallel when
cascaded, they all get programmed the same. During program
mode, only parity is programmed since Almost Full and Almost
Empty flags are not available when CY7C455/6/7 is cascaded.
Only the “first device” (FIFO with FL=LOW) will output its pro-
the first half of the first word on device A while device B
updates its flags to Almost Empty. Subsequent reads will
continue to output “staggered” data assuming more data
has been written to FIFOs.
Depth Expansion Mode
gram register contents on Q
during a program read.
0–7
The CY7C455/6/7 can operate up to 83.3 MHz when cascad-
ed. Depth expansion is accomplished by connecting expan-
sion out (XO) of the first device to expansion in (XI) of the
Q
of all other devices will remain in a high-impedance
0–17
state to avoid bus contention.
CKW
ENW
CKR
ENR
XI
D
0 – 17
Q
0 – 17
CKW
CKR
CY7C455,6,7
ENW
ENR
MR
OE
HF
DATA OUT
DATA IN
E/F
Q
0– 17
D
0– 17
FL/RT
PAFE/XO
V
SS
MR
XI
D
0 – 17
Q
0 – 17
CKR
CKW
CY7C455,6,7
ENW
ENR
HF
MR
FULL
EMPTY
E/F
OE
FL/RT
PAFE/XO
V
CC
c455-25
Figure 1. Depth Expansion with CY7C455/6/7
19
CY7C455
CY7C456
CY7C457
[48]
Table 3. Almost Empty Flag (Non-Boundary Flag) Operation Example
Status Before Operation Status After Operation
Number
of Words
Number
ofwords
E/F PAFE HF in FIFO
Current
NextState
of FIFO
State of FIFO E/F AFE HF in FIFO Operation
Comments
AE
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
32
33
34
33
33
Write
(ENW = 0)
AE
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
33
34
33
33
32
Write
AE
Write
(ENW = 0)
AE
Write
AE
Read
(ENR = 0)
<HF
<HF
AE
Flag Update and
Read
<HF
<HF
Read
(ENR = 1)
Ignored Read
(ENR = 1)
Read
(ENR = 0)
Read (transition from
<HF to AE)
Table 4. Programmable Parity Options
D17
0
D16
X
D15
X
Condition
Parity disabled.
1
0
0
Generate even parity on PG output pin.
Generate odd parity on PG output pin.
1
0
1
1
1
0
Check for even parity. Indicate error on PE output pin.
Check for odd parity. Indicate error on PE output pin.
1
1
1
Note:
48. Applies to CY7C455/6/7 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains 32 or fewer words.
20
CY7C455
CY7C456
CY7C457
Ordering Information
512x18 Clocked FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
CY7C455–12JC
CY7C455–12NC
CY7C455–12JI
CY7C455–14JC
CY7C455–14NC
CY7C455–14JI
CY7C455–20JC
CY7C455–20NC
CY7C455–20JI
CY7C455–30JC
CY7C455–30NC
CY7C455–30JI
12
J69
N52
J69
J69
N52
J69
J69
N52
J69
J69
N52
J69
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
14
20
30
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
1Kx18 Clocked FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
12
CY7C456–12JC
CY7C456–12NC
CY7C456–12JI
CY7C456–14JC
CY7C456–14NC
CY7C456–14JI
CY7C456–20JC
CY7C456–20NC
CY7C456–20JI
CY7C456–30JC
CY7C456–30NC
CY7C456–30JI
J69
N52
J69
J69
N52
J69
J69
N52
J69
J69
N52
J69
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
14
20
30
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
2Kx18 Clocked FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
12
CY7C457–12JC
CY7C457–12NC
CY7C457–12JI
CY7C457–14JC
CY7C457–14NC
CY7C457–14JI
CY7C457–20JC
CY7C457–20NC
CY7C457–20JI
CY7C457–30JC
CY7C457–30NC
CY7C457–30JI
J69
N52
J69
J69
N52
J69
J69
N52
J69
J69
N52
J69
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
14
20
30
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
Document #: 38–00211–E
21
CY7C455
CY7C456
CY7C457
Package Diagrams
52-LeadPlastic Leaded ChipCarrier J69
52-Lead Plastic QuadFlatpackN52
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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