CY7C470-25JI [CYPRESS]
8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags; 8K ×9先进先出， 16K ×9先进先出32K ×9 FIFO ，具有可编程标志
| 型号： | CY7C470-25JI |
| 厂家： | 
CYPRESS |
| 描述： | 8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags |
| 文件： | 总15页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C474
CY7C470
CY7C472
CY7C474
8K x 9 FIFO, 16K x 9 FIFO
32K x 9 FIFO with Programmable Flags
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO
memory is organized such that the data is read in the same
Features
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent of
depth/width
sequential order that it was written. Three status pins—Emp-
ty/Full (E/F), Programmable Almost Full/Empty (PAFE), and
Half Full (HF)—are provided to the user. These pins are de-
coded to determine one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half Full, Almost Full, and
Full.
• Low operating power
— I (max.) = 70 mA
CC
The read and write operations may be asynchronous; each
can occur at a rate of 33.3 MHz. The write operation occurs
when the write (W) signal goes LOW. Read occurs when read
(R) goes LOW. The nine data outputs go into a high-imped-
ance state when R is HIGH.
• Programmable Almost Full/Empty flag
• Empty, Almost Empty, Half Full, Almost Full, and Full
status flags
• Programmable retransmit
• Expandable in width
• 5V ± 10% supply
The user can store the value of the read pointer for retransmit
by using the MARK pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer
to the value stored in the mark pointer.
• TTL compatible
• Three-state outputs
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFO to resend the
data. With the mark feature, retransmit can start from any word
in the FIFO.
• Proprietary 0.8-micron CMOS technology
Functional Description
The CYC47X FIFO series consists of high-speed, low-power,
first-in first-out (FIFO) memories with programmable flags and
retransmit mark. The CY7C470, CY7C472, and CY7C474 are
8K, 16K, and 32K words by 9 bits wide, respectively. They are
The CYC47X series is fabricated using a proprietary 0.8-mi-
cron N-well CMOS technology. Input ESD protection is greater
than 2001V and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Logic Block Diagram
Pin Configurations
DATAINPUTS
(D –D )
DIP
PLCC/LCC
Top View
0
8
Top View
V
cc
W
1
28
D
D
D
D
2
3
4
27
26
8
3
2
4
5
6
4
3
2
1
32 31 30
29
D
D
D
D
5
6
7
6
D
2
PROGRAMMABLE
FLAG REGISTER
28
27
7
25
24
23
22
21
D
1
NC
D
D
D
7
5
1
D
0
RT
8
9
26
25
24
23
0
6
RT
7C470
7C472
7C474
7C470
7C472
7C474
MARK
PAFE
MR
E/F
MARK
PAFE
MR
E/F
HF
7
FLAG
LOGIC
10
11
E/F
PAFE
8
Q
0
Q
0
9
HF
HF
Q
20
19
18
17
16
15
Q
1
7
Q
1
12
13
22
21
Q
7
10
11
12
13
NC
RAM ARRAY
8K x 9
16K x 9
R
Q
WRITE
POINTER
6
Q
6
READ
POINTER
Q
2
Q
2
W
RT
14 15 16 17 18 19 20
Q
Q
3
8
5
4
MARK
32K x 9
Q
Q
R
GND
14
7C470–2
MARK
POINTER
7C470–3
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q –Q )
0
8
MR
RESET
LOGIC
7C470–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1990 – Revised April 1995
CY7C470
CY7C472
CY7C474
Selection Guide
7C470–15
7C472–15
7C474–15
7C470–20
7C472–20
7C474–20
7C470–25
7C472–25
7C474–25
7C470–40
7C472–40
7C474–40
Frequency (MHz)
33.3
15
33.3
20
28.5
25
20
40
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
105
Military/Industrial
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
DC Input Voltage............................................ –3.0V to +7.0V
Power Dissipation..........................................................1.0W
Output Current, into Outputs (LOW) ............................20 mA
–40°C to +85°C
–55°C to +125°C
[1]
Military
[2]
Electrical Characteristics Over the Operating Range
7C470–15
7C472–15
7C474–15
7C470–20
7C472–20
7C474–20
7C470–25
7C472–25
7C474–25
Parame-
ter
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
= Min., I = –2.0 mA
Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
V
2.4
2.4
2.4
V
V
V
OH
CC
CC
OH
= Min., I = 8.0 mA
0.4
0.8
0.4
0.4
0.8
OL
IH
OL
Com’l
Mil/Ind
2.2
2.2
2.2
2.2
V
Input LOW Voltage
0.8
V
IL
I
I
I
Input Leakage Current
Output Leakage Current
Operating Current
GND ≤ V ≤ V
CC
–10 +10 –10 +10 –10 +10
–10 +10 –10 +10 –10 +10
µA
µA
mA
IX
I
R ≥ V , GND ≤ V ≤ V
OZ
CC
IH
O
CC
V
= Max.,
= 0 mA
Com’l
105
90
95
CC
I
OUT
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
110
30
I
I
I
Standby Current
All Inputs =
Min.
25
25
mA
mA
mA
SB1
SB2
V
IH
30
Power-Down Current
Output Short Circuit Current
All Inputs =
20
20
V
–0.2V
CC
25
25
[3]
OS
V
= Max., V
= GND
–90
–90
–90
CC
OUT
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second.
2
CY7C470
CY7C472
CY7C474
[2]
Electrical Characteristics Over the Operating Range (continued)
7C470–40
7C472–40
7C474–40
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –2.0 mA
Min. Max.
Unit
V
V
V
V
2.4
0.4
2.2
2.2
0.8
OH
OL
IH
CC
CC
OH
V
V
= Min., I = 8.0 mA
V
OL
Com’l
V
Mil/Ind
V
Input LOW Voltage
V
IL
I
I
I
Input Leakage Current
Output Leakage Current
Operating Current
GND ≤ V ≤ V
CC
–10
–10
+10
+10
70
µA
µA
mA
IX
I
R ≥ V , GND ≤ V ≤ V
OZ
CC
IH
O
CC
V
= Max., I
= 0 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
CC
OUT
75
I
I
I
Standby Current
All Inputs = V Min.
25
mA
mA
mA
SB1
SB2
IH
30
Power-Down Current
Output Short Circuit Current
All Inputs = V –0.2V
20
CC
25
[3]
OS
V
= Max., V
= GND
–90
CC
OUT
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
10
Unit
C
C
pF
pF
IN
A
V
= 4.5V
CC
12
OUT
AC Test Loads and Waveforms
R1 500Ω
R1 500Ω
ALL INPUT PULSES
90%
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
10%
≤ 5 ns
R2
333Ω
R2
333Ω
30 pF
5 pF
≤ 5 ns
INCLUDING
JIGAND
INCLUDING
JIG AND
SCOPE
7C470–6
7C470–4
7C470–5
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C470
CY7C472
CY7C474
[5, 6]
Switching Characteristics Over the Operating Range
7C470–15
7C472–15
7C474–15
7C470–20
7C472–20
7C474–20
7C470–25
7C472–25
7C474–25
7C470–40
7C472–40
7C474–40
Parameter
Description
Cycle Time
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCY
30
30
35
50
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Access Time
15
20
25
40
25
A
Recovery Time
Pulse Width
15
15
3
10
20
3
10
25
3
10
40
3
RV
PW
LZR
Read LOW to Low Z
Valid Data from Read HIGH
Read HIGH to High Z
Write HIGH to Low Z
Data Set-Up Time
Data Hold Time
E/F Delay
[7]
DV
3
3
3
3
[7]
15
15
18
HZ
5
11
0
5
12
0
5
15
0
5
20
0
HWZ
SD
HD
15
25
25
25
20
30
30
30
25
35
35
35
40
50
50
50
EFD
EFL
HFD
AFED
RAE
MR to E/F LOW
HF Delay
PAFE Delay
Effective Read from
Write HIGH
15
15
20
20
25
25
40
40
t
Effective Write from
Read HIGH
ns
WAF
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
6. See the last page of this specification for Group A subgroup testing information.
7.
tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads. tHZR transition is measured at +500 mV from VOL and –500 mV from VOH. tDVR transition is measured
at the 1.5V level. tHWZ and tLZR transition is measured at ±100 mV from the steady state.
4
CY7C470
CY7C472
CY7C474
Switching Waveforms
Asynchronous Read and Write
t
t
PW
CY
t
A
t
RV
t
A
R
t
t
t
HZR
LZR
DVR
DATA VALID
DATA VALID
Q –Q
0
8
t
CY
t
t
t
PW
PW
RV
W
t
t
t
t
HD
SD
HD
SD
DATA VALID
DATA VALID
D –D
0
8
7C470–7
MasterReset (No Write to Programmable Flag Register)
t
CY
t
t
RV
PW
MR
t
RV
R, W
t
HFD
HF
E/F
t
EFL
PAFE
t
AFED
7C470–8
[8,9]
Master Reset (Write to Programmable Flag Register)
t
t
CY
CY
t
RV
t
t
RV
PW
MR
t
t
t
t
PW
RV
RV
W(R)
t
CY
HD
VALID
D –D
0
8
(Q –Q )
0
8
7C470–9
Notes:
8. Waveform labels in parentheses pertain to writing the programmable flag register from the output port (Q0 – Q8).
9. Master Reset (MR) must be pulsed LOW once prior to programming.
5
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
E/FFlag (Last Write to First Read Full Flag)
FULL
FULL–1
FULL–1
W
R
t
t
EFD
EFD
E/F
HF
LOW
7C470–10
E/F Flag (Last Read to First Write Empty Flag)
EMPTY+1
R
EMPTY
EMPTY+1
W
t
t
EFD
EFD
E/F
HF
HIGH
7C470–11
Half Full Flag
HALF–FULL
HALF–FULL +1
HALF–FULL
W
R
t
t
HFD
HFD
HF
7C470–12
6
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
PAFE Flag (Almost Full)
W
R
t
t
AFED
AFED
PAFE
HF
LOW
7C470–13
PAFE Flag (Almost Empty)
R
W
t
t
AFED
AFED
PAFE
HF
HIGH
7C470–14
[10]
Retransmit
t
t
CY
CY
W,R
RT
t
A
t
t
t
RV
t
RV
PW
LZR
t
CY
Q –Q
0
DATA VALID
8
FLAGS[10]
FLAGS VALID
7C470–15
Note:
10. The flags may change state during retransmit, but they will be valid a tCY later, except for the CY7C47X–20 (Military), whose flags will be valid after tCY + 10 ns.
7
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
Mark
t
t
CY
CY
W,R
MARK
t
t
t
RV
RV
PW
7C470–16
Empty Flag and Read Data Flow-Through Mode
DATA IN
W
t
RAE
R
t
PW
t
EFD
E/F
t
A
t
EFD
t
HWZ
DATA OUT
DATA VALID
7C470–17
8
CY7C470
CY7C472
CY7C474
Switching Waveforms (Continued)
Full Flag and Write Data Flow-Through Mode
R
t
t
PW
WAF
W
t
EFD
t
EFD
E/F
t
t
HD
SD
DATA IN
DATA VALID
t
A
DATA OUT
DATA VALID
7C470–18
Retransmit
Architecture
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and resent if necessary. Retransmission can start
from anywhere in the FIFO and be repeated without limitation.
The CY7C470, CY7C472, and CY7C474 FIFOs consist of an
array of 8,192, 16,384, and 32,768 words of 9 bits each, re-
spectively. The control consists of a read pointer, a write point-
er, a retransmit pointer, control signals (i.e., write, read, mark,
retransmit, and master reset), and flags (i.e., Empty/Full, Half
Full, and Programmable Almost Full/Empty).
The retransmit methodology is as follows: mark the current
value of the read pointer, after an error in subsequent read
operations return to that location and resume reading. This
effectively resends all of the data from the mark point. When
MARK is LOW, the current value of the read pointer is stored. This
operation marks the beginning of the packet to be resent. When RT
is LOW, the read pointer is updated with the mark location. During
each subsequent read cycle, data is read and the read pointer incre-
mented.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition signi-
fied by the Empty flag (E/F) and Almost Full/Empty flag (PAFE) being
LOW, and Half Full flag (HF) being HIGH. The read pointer, write
pointer, and retransmit pointer are reset to zero. For a valid reset,
Read (R) and Write (W) must be HIGH t
/t
before the falling
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the
mark pointer, because further write operations will overwrite
data.
RPW WPW
edge and t
after the rising edge of MR.
RMR
Writing Data to the FIFO
[11]
Data can be written to the FIFO when it is not FULL . A falling
edgeofW initiatesa writecycle. Data appearingat the inputs (D –D )
Programmable Almost Full/Empty Flag
0
8
t
before and t after the rising edge of W will be stored sequen-
The CY7C470/2/4 offer a variable offset for the Almost Empty
and the Almost Full condition. The offset is loaded into the
programmable flag register (PFR) during a master reset cycle.
SD
HD
tially in the FIFO.
Reading Data from the FIFO
While MR is LOW, the PFR can be loaded from Q –Q by pulsing
8
0
[12]
R LOW or from D –D by pulsing W LOW. The offset options are
Data can be read from the FIFO when it is not empty . A
falling edge of R initiates a read cycle. Data outputs (Q –Q ) are in a
high-impedance conditionwhentheFIFO isemptyandbetweenread
operations (R HIGH). The falling edge of R during the last read cycle
beforethe emptycondition triggers ahigh-to-low transition of E/F, pro-
8
0
listed in Table 2. See Table 1 for a description of the six FIFO states.
If the PFR is not loaded during master reset (R and W HIGH) the
default offset will be 256 words from Full and Empty.
0
8
hibiting any further read operations until t
after a valid write.
RFF
Notes:
11. When the FIFO is less than half full, the flags make a LOW-to-HIGH transition on the rising edge of W and make the HIGH-to-LOW transition on the falling edge
of R. If the FIFO is more than half full, the flags make the LOW-to-HIGH transition on the rising edge of R and HIGH-to-LOW transition on the falling edge of W.
12. Full and empty states can be decoded from the Half-Full (HF) and Empty/Full (E/F) flags.
9
CY7C470
CY7C472
CY7C474
[13]
Table 1. Flag Truth Table
CY77C470
(8K x 9)
Number of Words
in FIFO
CY77C472
(16K x 9)
Number of Words in
FIFO
CY77C474
(32K x 9)
Number of Words in
FIFO
HF
1
E/F PAFE
State
0
1
1
1
1
0
0
0
1
1
0
0
Empty
0
0
0
1
Almost Empty
Less than Half Full
Greater than Half Full
Almost Full
1
(P – 1)
1
(P – 1)
1
P
(P – 1)
1
P
4096
P
8192
16384
0
4097
(8192 – P)
8193
(16384 – P)
16385
(32768 – P)
0
(8192 – P+1)
8192
8191
(16384 – P+1)
16384
16383
(32768 – P+1)
32768
32767
0
Full
[14]
Table 2. Programmable Almost Full/Empty Options
D3
0
D2
0
D1
0
D0
0
PAFE Active when:
P
256 or less locations from Empty/Full (default)
16 or less locations from Empty/Full
32 or less locations from Empty/Full
64 or less locations from Empty/Full
128 or less locations from Empty/Full
256 or less locations from Empty/Full (default)
512 or less locations from Empty/Full
1024 or less locations from Empty/Full
2048 or less locations from Empty/Full
256
16
0
0
0
1
0
0
1
0
32
0
0
1
1
64
0
1
0
0
128
256
512
1024
2048
4098
8192
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
[15]
1
0
0
1
4098 or less locations from Empty/Full
[16]
1
0
1
0
8192 or less locations from Empty/Full
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
10
CY7C470
CY7C472
CY7C474
Typical AC and DC Characteristics
NORMALIZED t vs. AMBIENT
A
TEMPERATURE
TYPICAL t CHANGE vs.
OUTPUT LOADING
A
NORMALIZED t vs.SUPPLY
A
VOLTAGE
1.20
1.60
20.00
1.40
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
15.00
10.00
5.00
V
=5.0V
T =25°C
V
=5.0V
5.00
CC
A
CC
T =25°C
A
0.00
4.00
4.50
5.00
5.50
6.00
–55.00
65.00
125.00
0.00
500.00
CAPACITANCE (pF)
1000.00
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs.FREQUENCY
NORMALIZED SUPPLY CURRENT
vs.SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
1.20
1.10
1.00
0.90
0.80
0.70
0.60
V
CC
=5.0V
1.20
1.00
0.80
0.60
T =25°C
1.10
1.00
0.90
0.80
A
V
IN
=3.0V
V
=3.0V
V =3.0V
IN
IN
T =25°C
T =25°C
A
A
f = 33 MHz
f = 33 MHz
4.00
4.50
5.00
5.50
6.00
–55.00
5.00
65.00
125.00
15.00 20.00 25.00 30.00 35.00
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
50.00
100.00
80.00
60.00
40.00
20.00
0.00
40.00
30.00
20.00
10.00
0.00
V
CC
=5.0V
V
=5.0V
CC
T =25°C
A
T =25°C
A
0.00
1.00
2.00
3.00
4.00
0.00
1.00
2.00
3.00
4.00
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
11
CY7C470
CY7C472
CY7C474
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C470–15JC
CY7C470–15PC
CY7C470–15JI
Package Type
15
J65
P15
J65
D43
L55
J65
P15
J65
D43
L55
J65
P15
J65
D43
L55
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
20
25
CY7C470–20DMB
CY7C470–20LMB
CY7C470–25JC
CY7C470–25PC
CY7C470–25JI
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
CY7C470–25DMB
CY7C470–25LMB
CY7C470–40JC
CY7C470–40PC
CY7C470–40JI
40
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
Industrial
Military
CY7C470–40DMB
CY7C470–40LMB
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C472–15JC
CY7C472–15PC
CY7C472–15JI
Package Type
15
J65
P15
J65
D43
L55
J65
P15
J65
D43
L55
J65
P15
J65
D43
L55
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
20
25
CY7C472–20DMB
CY7C472–20LMB
CY7C472–25JC
CY7C472–25PC
CY7C472–25JI
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
CY7C472–25DMB
CY7C472–25LMB
CY7C472–40JC
CY7C472–40PC
CY7C472–40JI
40
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
Industrial
Military
CY7C472–40DMB
CY7C472–40LMB
12
CY7C470
CY7C472
CY7C474
Ordering Information (continued)
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C474–15JC
CY7C474–15PC
CY7C474–15JI
Name
Package Type
15
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
P15
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
20
25
CY7C474–20DMB
CY7C474–20LMB
CY7C474–25JC
CY7C474–25PC
CY7C474–25JI
D43
L55
J65
Commercial
P15
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
Military
CY7C474–25DMB
CY7C474–25LMB
CY7C474–40JC
CY7C474–40PC
CY7C474–40JI
D43
L55
J65
40
Commercial
P15
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Sidebraze CerDIP
32-Pin Rectangular Leadless Chip Carrier
Industrial
Military
CY7C474–40DMB
CY7C474–40LMB
D43
L55
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
Parameter
Subgroups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
V
t
OH
CY
V
1, 2, 3
t
A
OL
V
1, 2, 3
t
IH
RV
V Max.
1, 2, 3
t
PW
IL
I
1, 2, 3
t
LZR
IX
I
I
1, 2, 3
t
t
OS
CC
DVR
HZR
HWZ
1, 2, 3
t
t
SD
HD
t
t
EFD
HFD
t
t
AFED
t
RAE
WAF
t
Document #: 38–00142–H
13
CY7C470
CY7C472
CY7C474
Package Diagrams
28-Lead (600-Mil) Sidebraze DIP D43
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
32-Lead Plastic Leaded Chip Carrier
14
CY7C470
CY7C472
CY7C474
Package Diagrams
28-Lead (600-Mil) Molded DIP P15
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明