CY7C63722C-XC_技术文档

CY7C63722C

CY7C63723C

CY7C63743C

enCoRe™ USB Combination Low-Speed

USB and PS/2 Peripheral Controller

• I/O ports

1.0

Features

— Up to 16 versatile GPIO pins, individually

• enCoRe™ USB - enhanced Component Reduction

configurable

— Internaloscillatoreliminatestheneedforanexternal

crystal or resonator

—High current drive on any GPIO pin: 50 mA/pin

current sink

— Interface can auto-configure to operate as PS/2 or

USB without the need for external components to

switch between modes (no General Purpose I/O

[GPIO] pins needed to manage dual mode capability)

— Each GPIO pin supports high-impedance inputs,

internal pull-ups, open drain outputs or traditional

CMOS outputs

—Maskable interrupts on all I/O pins

• SPI serial communication block

— Master or slave operation

—Internal 3.3V regulator for USB pull-up resistor

—Configurable GPIO for real-world interface without

external components

— 2 Mbit/s transfers

• Flexible, cost-effective solution for applications that

combine PS/2 and low-speed USB, such as mice, game-

pads, joysticks, and many others.

• USB Specification Compliance

—Conforms to USB Specification, Version 2.0

— Conforms to USB HID Specification, Version 1.1

• Four 8-bit Input Capture registers

— Two registers each for two input pins

— Capture timer setting with five prescaler settings

—Separate registers for rising and falling edge capture

— Simplifies interface to RF inputs for wireless

applications

— Supports one low-speed USB device address and

three data endpoints

• Internal low-power wake-up timer during suspend

mode

— Integrated USB transceiver

—3.3V regulated output for USB pull-up resistor

• 8-bit RISC microcontroller

— Periodic wake-up with no external components

• Optional 6-MHz internal oscillator mode

—Allows fast start-up from suspend mode

• Watchdog Reset (WDR)

—Harvard architecture

— 6-MHz external ceramic resonator or internal clock

mode

• Low-voltage Reset at 3.75V

— 12-MHz internal CPU clock

—Internal memory

• Internal brown-out reset for suspend mode

• Improved output drivers to reduce EMI

• Operating voltage from 4.0V to 5.5VDC

• Operating temperature from 0°C to 70°C

• CY7C63723C available in 18-pin SOIC, 18-pin PDIP

• CY7C63743C available in 24-pin SOIC, 24-pin PDIP,

24-pin QSOP

• CY7C63722C available in DIE form

— 256 bytes of RAM

—8 Kbytes of EPROM

— Interface can auto-configure to operate as PS/2 or

USB

— No external components for switching between PS/2

and USB modes

• Industry standard programmer support

—No GPIO pins needed to manage dual mode

capability

Cypress Semiconductor Corporation

Document #: 38-08022 Rev. *C

•

198 Champion Court

•

San Jose

•

CA 95134

•

408-943-2600

Revised February 25, 2006

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2.0

Logic Block Diagram

XTALIN/P2.1

XTALOUT

Wake-Up

Timer

Xtal

Oscillator

Internal

Oscillator

RAM

256 Byte

12-bit

Timer

Capture

Timers

SPI

8-bit

RISC

Core

EPROM

8K Byte

Brown-out

Reset

Interrupt

Controller

USB

Engine

Port 0

GPIO

Port 1

GPIO

Watch

Dog

Timer

USB &

PS/2

Xcvr

3.3V

Regulator

Low

Voltage

Reset

P1.0–P1.7 P0.0–P0.7

D+,D–

VREG/P2.0

MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator

can be used to provide a higher precision reference for USB

operation. This clock generator reduces the clock-related

noise emissions (EMI). The clock generator provides the 6-

and 12-MHz clocks that remain internal to the microcontroller.

3.0

3.1

Functional Overview

enCoRe USB—The New USB Standard

Cypress has reinvented its leadership position in the

low-speed USB market with a new family of innovative

microcontrollers. Introducing...enCoRe USB—“enhanced

Component Reduction.” Cypress has leveraged its design

expertise in USB solutions to create a new family of low-speed

USB microcontrollers that enables peripheral developers to

design new products with a minimum number of components.

At the heart of the enCoRe USB technology is the break-

through design of a crystalless oscillator. By integrating the

oscillator into our chip, an external crystal or resonator is no

longer needed. We have also integrated other external compo-

nents commonly found in low-speed USB applications such as

pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of

this adds up to a lower system cost.

The CY7C637xxC has 8 Kbytes of EPROM and 256 bytes of

data RAM for stack space, user variables, and USB FIFOs.

These parts include low-voltage reset logic, a Watchdog timer,

a vectored interrupt controller, a 12-bit free-running timer, and

capture timers. The low-voltage reset (LVR) logic detects

when power is applied to the device, resets the logic to a

known state, and begins executing instructions at EPROM

address 0x0000. LVR will also reset the part when V_CCdrops

below the operating voltage range. The Watchdog timer can

be used to ensure the firmware never gets stalled for more

than approximately 8 ms.

The microcontroller supports 10 maskable interrupts in the

vectored interrupt controller. Interrupt sources include the USB

Bus-Reset, the 128-µs and 1.024-ms outputs from the

free-running timer, three USB endpoints, two capture timers,

an internal wake-up timer and the GPIO ports. The timers bits

cause periodic interrupts when enabled. The USB endpoints

interrupt after USB transactions complete on the bus. The

capture timers interrupt whenever a new timer value is saved

due to a selected GPIO edge event. The GPIO ports have a

level of masking to select which GPIO inputs can cause a

GPIO interrupt. For additional flexibility, the input transition

polarity that causes an interrupt is programmable for each

GPIO pin. The interrupt polarity can be either rising or falling

edge.

The CY7C637xxC is an 8-bit RISC one-time-programmable

(OTP) microcontroller. The instruction set has been optimized

specifically for USB and PS/2 operations, although the micro-

controllers can be used for a variety of other embedded appli-

cations.

The CY7C637xxC features up to 16 GPIO pins to support

USB, PS/2 and other applications. The I/O pins are grouped

into two ports (Port 0 to 1) where each pin can be individually

configured as inputs with internal pull-ups, open drain outputs,

or traditional CMOS outputs with programmable drive strength

of up to 50 mA output drive. Additionally, each I/O pin can be

used to generate a GPIO interrupt to the microcontroller. Note

the GPIO interrupts all share the same “GPIO” interrupt vector.

The free-running 12-bit timer clocked at 1 MHz provides two

interrupt sources as noted above (128 µs and 1.024 ms). The

timer can be used to measure the duration of an event under

firmware control by reading the timer at the start and end of an

The CY7C637xxC microcontrollers feature an internal oscil-

lator. With the presence of USB traffic, the internal oscillator

can be set to precisely tune to USB timing requirements (6

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event, and subtracting the two values. The four capture timers

save a programmable 8 bit range of the free-running timer

when a GPIO edge occurs on the two capture pins (P0.0,

P0.1).

The USB D+ and D– USB pins can alternately be used as PS/2

SCLK and SDATA signals, so that products can be designed

to respond to either USB or PS/2 modes of operation. PS/2

operation is supported with internal pull-up resistors on SCLK

and SDATA, the ability to disable the regulator output pin, and

an interrupt to signal the start of PS/2 activity. No external

components are necessary for dual USB and PS/2 systems,

and no GPIO pins need to be dedicated to switching between

modes. Slow edge rates operate in both modes to reduce EMI.

The CY7C637xxC includes an integrated USB serial interface

engine (SIE) that supports the integrated peripherals. The

hardware supports one USB device address with three

endpoints. The SIE allows the USB host to communicate with

the function integrated into the microcontroller. A 3.3V

regulated output pin provides a pull-up source for the external

USB resistor on the D– pin.

4.0

Pin Configurations

Top View

CY7C63723C

18-pin SOIC/PDIP

CY7C63743C

24-pin SOIC/PDIP/QSOP

CY7C63722C-XC

DIE

P0.4

P0.5

P0.6

P0.7

P1.1

P0.0

P0.1

P0.2

P0.3

P1.0

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

P0.4

P0.0

P0.1

P0.2

P0.3

P1.0

P1.2

P1.4

P1.6

VSS

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

15

P0.5

P0.6

P0.3

P1.0

P1.2

P1.4

P1.6

VSS

4

5

6

7

8

9

22 P0.7

21 P1.1

P0.7

P1.1

P1.3

P1.5

P1.7

D+/SCLK

D–/SDATA

20

19

18

P1.3

P1.5

P1.7

VSS

VPP

VREG/P2.0

D+/SCLK

D–/SDATA

VCC

XTALIN/P2.1

XTALOUT

9

VPP

10

11

12

VSS

VCC

XTALOUT

14

13

10

VREG/P2.0

XTALIN/P2.1

17

D+/SCLK

5.0

Pin Definitions

CY7C63723C CY7C63743C CY7C63722C

Name

I/O

18-Pin

24-Pin

25-Pad

Description

D–/SDATA,

D+/SCLK

I/O

12

13

USB differential data lines (D– and D+), or PS/2 clock

and data signals (SDATA and SCLK)

15

16

17

P0[7:0]

P1[7:0]

I/O

1, 2, 3, 4,

GPIO Port 0 capable of sinking up to 50 mA/pin, or

15, 16, 17, 18 21, 22, 23, 24 22, 23, 24, 25 sinking controlled low or high programmable current.

Can also source 2 mA current, provide a resistive

pull-up, or serve as a high-impedance input. P0.0 and

P0.1 provide inputs to Capture Timers A and B, respec-

tively.

5, 14

5, 6, 7, 8,

IO Port 1 capable of sinking up to 50 mA/pin, or sinking

17, 18, 19, 20 18, 19, 20, 21 controlled low or high programmable current. Can also

source 2 mA current, provide a resistive pull-up, or

serve as a high-impedance input.

XTALIN/P2.1

XTALOUT

V_PP

IN

9

10

7

12

13

10

13

14

11

6-MHz ceramic resonator or external clock input, or

P2.1 input

OUT

6-MHz ceramic resonator return pin or internal oscillator

output

Programming voltage supply, ground for normal

operation

V_CC

11

8

14

11

15

12

Voltage supply

VREG/P2.0

Voltage supply for 1.3-kΩ USB pull-up resistor (3.3V

nominal). Also serves as P2.0 input.

V_SS

6

9

9, 10

Ground

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The return from interrupt (RETI) instruction decrements the

program stack pointer, then restores the second byte from

memory addressed by the PSP. The program stack pointer is

decremented again and the first byte is restored from memory

addressed by the PSP. After the program counter and flags

have been restored from stack, the interrupts are enabled. The

effect is to restore the program counter and flags from the

program stack, decrement the program stack pointer by two,

and reenable interrupts.

6.0

Programming Model

Refer to the CYASM Assembler User’s Guide for more details

on firmware operation with the CY7C637xxC microcontrollers.

6.1

Program Counter (PC)

The 14-bit program counter (PC) allows access for up to 8

Kbytes of EPROM using the CY7C637xxC architecture. The

program counter is cleared during reset, such that the first

instruction executed after a reset is at address 0x0000. This

instruction is typically a jump instruction to a reset handler that

initializes the application.

The call subroutine (CALL) instruction stores the program

counter and flags on the program stack and increments the

PSP by two.

The return from subroutine (RET) instruction restores the

program counter, but not the flags, from program stack and

decrements the PSP by two.

The lower 8 bits of the program counter are incremented as

instructions are loaded and executed. The upper six bits of the

program counter are incremented by executing an XPAGE

instruction. As a result, the last instruction executed within a

256-byte “page” of sequential code should be an XPAGE

instruction. The assembler directive “XPAGEON” will cause

the assembler to insert XPAGE instructions automatically. As

instructions can be either one or two bytes long, the assembler

may occasionally need to insert a NOP followed by an XPAGE

for correct execution.

Note that there are restrictions in using the JMP, CALL, and

INDEX instructions across the 4-KByte boundary of the

program memory. Refer to the CYASM Assembler User’s

Guide for a detailed description.

6.5

8-bit Data Stack Pointer (DSP)

The data stack pointer (DSP) supports PUSH and POP

instructions that use the data stack for temporary storage. A

PUSH instruction will pre-decrement the DSP, then write data

to the memory location addressed by the DSP. A POP

instruction will read data from the memory location addressed

by the DSP, then post-increment the DSP.

The program counter of the next instruction to be executed,

carry flag, and zero flag are saved as two bytes on the program

stack during an interrupt acknowledge or a CALL instruction.

The program counter, carry flag, and zero flag are restored

from the program stack only during a RETI instruction.

Please note the program counter cannot be accessed directly

by the firmware. The program stack can be examined by

reading SRAM from location 0x00 and up.

During a reset, the Data Stack Pointer will be set to zero. A

PUSH instruction when DSP equals zero will write data at the

top of the data RAM (address 0xFF). This would write data to

the memory area reserved for a FIFO for USB endpoint 0. In

non-USB applications, this works fine and is not a problem.

6.2

8-bit Accumulator (A)

For USB applications, the firmware should set the DSP to an

appropriate location to avoid a memory conflict with RAM

dedicated to USB FIFOs. The memory requirements for the

USB endpoints are shown in Section 8.2. For example,

assembly instructions to set the DSP to 20h (giving 32 bytes

for program and data stack combined) are shown below.

The accumulator is the general-purpose, do everything

register in the architecture where results are usually calcu-

lated.

6.3

8-bit Index Register (X)

The index register “X” is available to the firmware as an

auxiliary accumulator. The X register also allows the processor

to perform indexed operations by loading an index value

into X.

MOV A,20h

; Move 20 hex into Accumulator (must be

D8h or less to avoid USB FIFOs)

SWAP A,DSP ; swap accumulator value into DSP register

6.6

Address Modes

6.4

8-bit Program Stack Pointer (PSP)

The CY7C637xxC microcontrollers support three addressing

modes for instructions that require data operands: data, direct,

and indexed.

During a reset, the program stack pointer (PSP) is set to zero.

This means the program “stack” starts at RAM address 0x00

and “grows” upward from there. Note that the program stack

pointer is directly addressable under firmware control, using

the MOV PSP,A instruction. The PSP supports interrupt

service under hardware control and CALL, RET, and RETI

instructions under firmware control.

6.6.1

Data

The “Data” address mode refers to a data operand that is

actually a constant encoded in the instruction. As an example,

consider the instruction that loads A with the constant 0x30:

During an interrupt acknowledge, interrupts are disabled and

the program counter, carry flag, and zero flag are written as

two bytes of data memory. The first byte is stored in the

memory addressed by the program stack pointer, then the

PSP is incremented. The second byte is stored in memory

addressed by the program stack pointer and the PSP is incre-

mented again. The net effect is to store the program counter

and flags on the program “stack” and increment the program

stack pointer by two.

• MOV A, 30h

This instruction will require two bytes of code where the first

byte identifies the “MOV A” instruction with a data operand as

the second byte. The second byte of the instruction will be the

constant “0xE8h”. A constant may be referred to by name if a

prior “EQU” statement assigns the constant value to the name.

For example, the following code is equivalent to the example

shown above.

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• DSPINIT: EQU 30h

• MOV A,DSPINIT

6.6.3

Indexed

“Indexed” address mode allows the firmware to manipulate

arrays of data stored in SRAM. The address of the data

operand is the sum of a constant encoded in the instruction

and the contents of the “X” register. In normal usage, the

constant will be the “base” address of an array of data and the

X register will contain an index that indicates which element of

the array is actually addressed.

6.6.2

Direct

“Direct” address mode is used when the data operand is a

variable stored in SRAM. In that case, the one byte address of

the variable is encoded in the instruction. As an example,

consider an instruction that loads A with the contents of

memory address location 0x10h:

• array: EQU 10h

• MOV X,3

• MOV A, [10h]

• MOV A, [x+array]

In normal usage, variable names are assigned to variable

addresses using “EQU” statements to improve the readability

of the assembler source code. As an example, the following

code is equivalent to the example shown above.

This would have the effect of loading A with the fourth element

of the SRAM “array” that begins at address 0x10h. The fourth

element would be at address 0x13h.

• buttons: EQU 10h

• MOV A, [buttons]

7.0

Instruction Set Summary

Refer to the CYASM Assembler User’s Guide for detailed

information on these instructions. Note that conditional jump

instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is

taken, four cycles if no jump.

MNEMONIC

HALT

Operand

Opcode

00

Cycles

MNEMONIC

Operand

acc

Opcode

20

Cycles

7

4

6

7

4

6

7

4

6

7

4

6

7

4

6

7

4

6

7

4

6

7

5

7

8

4

NOP

4

7

8

4

7

8

5

4

5

6

7

8

7

8

7

8

6

ADD A,expr

data

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

INC A

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

ADD A,[expr]

ADD A,[X+expr]

ADC A,expr

direct

index

data

INC X

x

INC [expr]

direct

index

acc

INC [X+expr]

DEC A

ADC A,[expr]

ADC A,[X+expr]

SUB A,expr

direct

index

data

DEC X

x

DEC [expr]

DEC [X+expr]

IORD expr

IOWR expr

POP A

direct

index

address

SUB A,[expr]

SUB A,[X+expr]

SBB A,expr

direct

index

data

SBB A,[expr]

SBB A,[X+expr]

OR A,expr

direct

index

data

POP X

PUSH A

OR A,[expr]

direct

index

data

PUSH X

OR A,[X+expr]

AND A,expr

SWAP A,X

SWAP A,DSP

MOV [expr],A

MOV [X+expr],A

OR [expr],A

OR [X+expr],A

AND [expr],A

AND [X+expr],A

XOR [expr],A

XOR [X+expr],A

IOWX [X+expr]

AND A,[expr]

AND A,[X+expr]

XOR A,expr

direct

index

data

direct

index

direct

index

direct

index

direct

index

XOR A,[expr]

XOR A,[X+expr]

CMP A,expr

direct

index

data

CMP A,[expr]

CMP A,[X+expr]

MOV A,expr

direct

index

data

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MNEMONIC

MOV A,[expr]

Operand

direct

Opcode

Cycles

MNEMONIC

Operand

Opcode

3A

Cycles

1A

5

6

CPL

ASL

ASR

RLC

RRC

RET

DI

4

8

4

8

MOV A,[X+expr]

MOV X,expr

MOV X,[expr]

reserved

XPAGE

index

1B

3B

3C

3D

3E

3F

70

72

73

data

1C

4

5

direct

1D

1E

1F

4

MOV A,X

MOV X,A

MOV PSP,A

CALL

40

4

41

4

EI

60

4

RETI

addr

50 - 5F

80-8F

90-9F

A0-AF

B0-BF

10

JMP

5

JC

addr

C0-CF

D0-DF

E0-EF

F0-FF

5 (or 4)

7

CALL

10

JNC

JACC

JZ

5 (or 4)

JNZ

INDEX

14

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8.0

8.1

Memory Organization

Program Memory Organization^[1]

After reset

Address

14 -bit PC

0x0000

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

Program execution begins here after a reset

USB Bus Reset interrupt vector

128-µs timer interrupt vector

1.024-ms timer interrupt vector

USB endpoint 0 interrupt vector

USB endpoint 1 interrupt vector

USB endpoint 2 interrupt vector

SPI interrupt vector

Capture timer A interrupt Vector

Capture timer B interrupt vector

GPIO interrupt vector

Wake-up interrupt vector

Program Memory begins here

0x1FDF

8 KB PROM ends here (8K - 32 bytes). See Note below

Figure 8-1. Program Memory Space with Interrupt Vector Table

Note:

1. The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.

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8.2

Data Memory Organization

The CY7C637xxC microcontrollers provide 256 bytes of data

RAM. In normal usage, the SRAM is partitioned into four

areas: program stack, data stack, user variables and USB

endpoint FIFOs as shown below.

After reset

8-bit DSP 8-bit PSP

Address

0x00

Program Stack Growth

Data Stack Growth

(User’s firmware moves DSP)

8-bit DSP

User Selected

User Variables

0xE8

0xF0

USB FIFO for Address A endpoint 2

USB FIFO for Address A endpoint 1

USB FIFO for Address A endpoint 0

0xF8

0xFF

Top of RAM Memory

Figure 8-2. Data Memory Organization

port. Note that specifying address 0 with IOWX (e.g., IOWX

0h) means the I/O port is selected solely by the contents of X.

8.3

I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O

Write (IOWR, IOWX) instructions. IORD reads the selected

port into the accumulator. IOWR writes data from the accumu-

lator to the selected port. Indexed I/O Write (IOWX) adds the

contents of X to the address in the instruction to form the port

address and writes data from the accumulator to the specified

Note: All bits of all registers are cleared to all zeros on

reset, except the Processor Status and Control Register

(Figure 20-1). All registers not listed are reserved, and should

never be written by firmware. All bits marked as reserved

should always be written as 0 and be treated as undefined by

reads.

Table 8-1. I/O Register Summary

Register Name

Port 0 Data

I/O Address

0x00

Read/Write

Function

Fig.

12-2

12-3

12-8

21-4

21-5

21-6

21-7

12-4

12-5

12-6

12-7

R/W

R

GPIO Port 0

GPIO Port 1

Port 1 Data

0x01

Port 2 Data

0x02

Auxiliary input register for D+, D–, VREG, XTALIN

Interrupt enable for pins in Port 0

Port 0 Interrupt Enable

Port 1 Interrupt Enable

Port 0 Interrupt Polarity

Port 1 Interrupt Polarity

Port 0 Mode0

0x04

W

0x05

W

Interrupt enable for pins in Port 1

0x06

W

Interrupt polarity for pins in Port 0

0x07

W

Interrupt polarity for pins in Port 1

0x0A

0x0B

0x0C

0x0D

W

Controls output configuration for Port 0

Port 0 Mode1

W

Port 1 Mode0

W

Controls output configuration for Port 1

Port 1 Mode1

W

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Table 8-1. I/O Register Summary (continued)

Register Name

I/O Address

Read/Write

Function

Fig.

USB Device Address

EP0 Counter Register

EP0 Mode Register

EP1 Counter Register

EP1 Mode Register

EP2 Counter Register

EP2 Mode Register

USB Status & Control

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x1F

R/W

USB Device Address register

14-1

14-4

14-2

14-4

14-3

14-4

14-3

13-1

USB Endpoint 0 counter register

USB Endpoint 0 configuration register

USB Endpoint 1 counter register

USB Endpoint 1 configuration register

USB Endpoint 2 counter register

USB Endpoint 2 configuration register

USB status and control register

Global Interrupt Enable

Endpoint Interrupt Enable

Timer (LSB)

0x20

0x21

0x24

0x25

0x26

R/W

R

Global interrupt enable register

USB endpoint interrupt enables

21-1

21-2

Lower 8 bits of free-running timer (1 MHz)

Upper 4 bits of free-running timer

Watchdog Reset clear

18-1

18-2

-

Timer (MSB)

R

WDR Clear

W

Capture Timer A Rising

Capture Timer A Falling

Capture Timer B Rising

Capture Timer B Falling

Capture TImer Configuration

Capture Timer Status

0x40

0x41

0x42

0x43

0x44

0x45

R

Rising edge Capture Timer A data register

Falling edge Capture Timer A data register

Rising edge Capture Timer B data register

Falling edge Capture Timer B data register

Capture Timer configuration register

Capture Timer status register

19-2

19-3

19-4

19-5

19-7

19-6

R

R/W

R

SPI Data

0x60

0x61

R/W

SPI read and write data register

SPI status and control register

17-2

17-3

SPI Control

Clock Configuration

0xF8

0xFF

R/W

Internal / External Clock configuration register

Processor status and control

9-2

Processor Status & Control

20-1

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9.0

Clocking

The chip can be clocked from either the internal on-chip clock,

or from an oscillator based on an external resonator/crystal, as

shown in Figure 9-1. No additional capacitance is included on

chip at the XTALIN/OUT pins. Operation is controlled by the

Clock Configuration Register, Figure 9-2.

Int Clk Output Disable

XTALOUT

Internal Osc

Ext Clk Enable

Clock

Doubler

Clk2x (12 MHz)

(to Microcontroller)

XTALIN

Clk1x (6 MHz)

(to USB SIE)

Port 2.1

Figure 9-1. Clock Oscillator On-chip Circuit

Bit #

7

6

5

4

3

2

1

0

Bit Name

Ext. Clock

Resume

Delay

Wake-up Timer Adjust Bit [2:0]

Low-voltage Precision

Internal

Clock

Output

Disable

External

Oscillator

Enable

Reset

USB

Clocking

Enable

Disable

Read/Write

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Figure 9-2. Clock Configuration Register (Address 0xF8)

Bit 7: Ext. Clock Resume Delay

Bit [6:4]: Wake-up Timer Adjust Bit [2:0]

External Clock Resume Delay bit selects the delay time

when switching to the external oscillator from the internal

oscillator mode, or when waking from suspend mode with

the external oscillator enabled.

1 = 4 ms delay.

0 = 128 µs delay.

The Wake-up Timer Adjust Bits are used to adjust the

Wake-up timer period.

If the Wake-up interrupt is enabled in the Global Interrupt

Enable Register, the microcontroller will generate wake-up

interrupts periodically. The frequency of these periodical

wake-up interrupts is adjusted by setting the Wake-up Tim-

er Adjust Bit [2:0], as described in Section 11.2. One com-

mon use of the wake-up interrupts is to generate periodical

wake-up events during suspend mode to check for chang-

es, such as looking for movement in a mouse, while main-

taining a low average power.

The delay gives the oscillator time to start up. The shorter

time is adequate for operation with ceramic resonators,

while the longer time is preferred for start-up with a crystal.

(These times do not include an initial oscillator start-up

time which depends on the resonating element. This time

is typically 50–100 µs for ceramic resonators and 1–10 ms

for crystals). Note that this bit only selects the delay time for

the external clock mode. When waking from suspend mode

with the internal oscillator (Bit 0 is LOW), the delay time is

only 8 µs in addition to a delay of approximately 1 µs for the

oscillator to start.

Bit 3: Low-voltage Reset Disable

When V_CCdrops below V_LVR(see Section 25.0 for the val-

ue of V_LVR) and the Low-voltage Reset circuit is enabled,

the microcontroller enters a partial suspend state for a pe-

riod of t_START(see Section 26.0 for the value of t_START).

Program execution begins from address 0x0000 after this

t

_STARTdelay period. This provides time for V_CCto stabilize

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before the part executes code. See Section 10.1 for more

details.

mov A, 1h

iowr F8h

; Set Bit 0 HIGH (External Oscil-

lator Enable bit). Bit 7 cleared

gives faster start-up

; Write to Clock Configuration

Register

1 = Disables the LVR circuit.

0 = Enables the LVR circuit.

3. Internal clocking is halted, the internal oscillator is disabled,

and the external clock oscillator is enabled.

Bit 2: Precision USB Clocking Enable

The Precision USB Clocking Enable only affects operation

in internal oscillator mode. In that mode, this bit must be

set to 1 to cause the internal clock to automatically pre-

cisely tune to USB timing requirements (6 MHz ±1.5%).

The frequency may have a looser initial tolerance at pow-

er-up, but all USB transmissions from the chip will meet the

USB specification.

4. After the external clock becomes stable, chip clocks are

re-enabled using the external clock signal. (Note that the

time for the external clock to become stable depends on the

external resonating device; see next section.)

5. After an additional delay the CPU is released to run. This

delay depends on the state of the Ext. Clock Resume Delay

bit of the Clock Configuration Register. The time is 128 µs

if the bit is 0, or 4 ms if the bit is 1.

1 = Enabled. The internal clock accuracy is 6 MHz ±1.5%

after USB traffic is received.

6. Once the chip has been set to external oscillator, it can only

return to internal clock when waking from suspend mode.

Clearing bit 0 of the Clock Configuration Register will not

re-enable internal clock mode until suspend mode is

entered. See Section 11.0 for more details on suspend

mode operation.

0 = Disabled. The internal clock accuracy is 6 MHz ±5%.

Bit 1: Internal Clock Output Disable

The Internal Clock Output Disable is used to keep the inter-

nal clock from driving out to the XTALOUT pin. This bit has

no effect in the external oscillator mode.

If the Internal Clock is enabled, the XTALIN pin can serve as

a general purpose input, and its state can be read at Port 2,

Bit 1 (P2.1). Refer to Figure 12-8 for the Port 2 Data Register.

In this mode, there is a weak pull-down at the XTALIN pin. This

input cannot provide an interrupt source to the CPU.

1 = Disable internal clock output. XTALOUT pin will drive

HIGH.

0 = Enable the internal clock output. The internal clock is

driven out to the XTALOUT pin.

Bit 0: External Oscillator Enable

9.2

External Oscillator

At power-up, the chip operates from the internal clock by

default. Setting the External Oscillator Enable bit HIGH dis-

ables the internal clock, and halts the part while the external

resonator/crystal oscillator is started. Clearing this bit has

no immediate effect, although the state of this bit is used

when waking out of suspend mode to select between inter-

nal and external clock. In internal clock mode, XTALIN pin

will be configured as an input with a weak pull-down and

can be used as a GPIO input (P2.1).

The user can connect a low-cost ceramic resonator or an

external oscillator to the XTALIN/XTALOUT pins to provide a

precise reference frequency for the chip clock, as shown in

Figure 9-1. The external components required are a ceramic

resonator or crystal and any associated capacitors. To run

from the external resonator, the External Oscillator Enable bit

of the Clock Configuration Register must be set to 1, as

explained in the previous section.

Start-up times for the external oscillator depend on the

resonating device. Ceramic resonator based oscillators

typically start in less than 100 µs, while crystal based oscil-

lators take longer, typically 1 to 10 ms. Board capacitance

should be minimized on the XTALIN and XTALOUT pins by

keeping the traces as short as possible.

1 = Enable the external oscillator. The clock is switched to

external clock mode, as described in Section 9.1.

0 = Enable the internal oscillator.

9.1

Internal/External Oscillator Operation

The internal oscillator provides an operating clock, factory set

to a nominal frequency of 6 MHz. This clock requires no

external components. At power-up, the chip operates from the

internal clock. In this mode, the internal clock is buffered and

driven to the XTALOUT pin by default, and the state of the

XTALIN pin can be read at Port 2.1. While the internal clock is

enabled, its output can be disabled at the XTALOUT pin by

setting the Internal Clock Output Disable bit of the Clock

Configuration Register.

An external 6-MHz clock can be applied to the XTALIN pin if

the XTALOUT pin is left open.

10.0

Reset

The USB Controller supports three types of resets. The effects

of the reset are listed below. The reset types are:

1. Low-voltage Reset (LVR)

2. Brown Out Reset (BOR)

3. Watchdog Reset (WDR)

Setting the External Oscillator Enable bit of the Clock Config-

uration Register HIGH disables the internal clock, and halts

the part while the external resonator/crystal oscillator is

started. The steps involved in switching from Internal to

External Clock mode are as follows:

The occurrence of a reset is recorded in the Processor Status

and Control Register (Figure 20-1). Bits 4 (Low-voltage or

Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to

record the occurrence of LVR/BOR and WDR respectively.

The firmware can interrogate these bits to determine the cause

of a reset.

1. At reset, chip begins operation using the internal clock.

2. Firmware sets Bit 0 of the Clock Configuration Register. For

example,

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The microcontroller begins execution from ROM address

0x0000 after a LVR, BOR, or WDR reset. Although this looks

like interrupt vector 0, there is an important difference. Reset

processing does NOT push the program counter, carry flag,

and zero flag onto program stack. Attempting to execute either

a RET or RETI in the reset handler will cause unpredictable

execution results.

Reset Disable bit in the Clock Configuration Register

(Figure 9-2). In addition, the LVR is automatically disabled in

suspend mode to save power. If the LVR was enabled before

entering suspend mode, it becomes active again once the

suspend mode ends.

When LVR is disabled during normal operation (i.e., by writing

‘0’ to the Low-voltage Reset Disable bit in the Clock Configu-

ration Register), the chip may enter an unknown state if V_CC

drops below V_LVR. Therefore, LVR should be enabled at all

times during normal operation. If LVR is disabled (i.e., by

firmware or during suspend mode), a secondary low-voltage

monitor, BOR, becomes active, as described in the next

section. The LVR/BOR Reset bit of the Processor Status and

Control Register (Figure 20-1), is set to ‘1’ if either a LVR or

BOR has occurred.

The following events take place on reset. More details on the

various resets are given in the following sections.

1. All registers are reset to their default states (all bits cleared,

except in Processor Status and Control Register).

2. GPIO and USB pins are set to high-impedance state.

3. The VREG pin is set to high-impedance state.

4. Interrupts are disabled.

5. USBoperationisdisabledand must be enabled byfirmware

if desired, as explained in Section 14.1.

10.2

Brown Out Reset (BOR)

The Brown Out Reset (BOR) circuit is always active and

behaves like the POR. BOR is asserted whenever the V_CC

voltage to the device is below an internally defined trip voltage

of approximately 2.5V. The BOR re-enables LVR. That is, once

6. For a BOR or LVR, the external oscillator is disabled and

Internal Clock mode is activated, followed by a time-out

period t_STARTfor V_CCto stabilize. A WDR does not change

the clock mode, and there is no delay for V_CCstabilization

on a WDR. Note that the External Oscillator Enable (Bit 0,

Figure 9-2) will be cleared by a WDR, but it does not take

effect until suspend mode is entered.

V_CCdrops and trips BOR, the part remains in reset until V_CC

rises above V_LVR. At that point, the t_STARTdelay occurs before

normal operation resumes, and the microcontroller starts

executing code from address 0x00 after the t_STARTdelay.

7. The Program Stack Pointer (PSP) and Data Stack Pointer

(DSP) reset to address 0x00. Firmware should move the

DSP for USB applications, as explained in Section 6.5.

In suspend mode, only the BOR detection is active, giving a

reset if V_CCdrops below approximately 2.5V. Since the device

is suspended and code is not executing, this lower reset

voltage is safe for retaining the state of all registers and

memory. Note that in suspend mode, LVR is disabled as

discussed in Section 10.1.

8. Program execution begins at address 0x0000 after the

appropriate time-out period.

10.1

Low-voltage Reset (LVR)

10.3

Watchdog Reset (WDR)

When V_CCis first applied to the chip, the internal oscillator is

started and the Low-voltage Reset is initially enabled by

default. At the point where V_CChas risen above V_LVR(see

Section 25.0 for the value of V_LVR), an internal counter starts

counting for a period of t_START(see Section 26.0 for the value

of t_START). During this t_STARTtime, the microcontroller enters

a partial suspend state to wait for V_CCto stabilize before it

begins executing code from address 0x0000.

The Watchdog Timer Reset (WDR) occurs when the internal

Watchdog timer rolls over. Writing any value to the write-only

Watchdog Reset Register at address 0x26 will clear the timer.

The timer will roll over and WDR will occur if it is not cleared

within t_WATCH(see Figure 10-1) of the last clear. Bit 6

(Watchdog Reset bit) of the Processor Status and Control

Register is set to record this event (see Section 20.0 for more

details). A Watchdog Timer Reset typically lasts for 2–4 ms,

after which the microcontroller begins execution at ROM

address 0x0000.

As long as the LVR circuit is enabled, this reset sequence

repeats whenever the V_CCpin voltage drops below V_LVR. The

LVR can be disabled by firmware by setting the Low-voltage

t_{WATCH = 10.1 to}

14.6 ms

WDR

(at F

= 6 MHz)

OSC

2–4 ms

At least 10.1 ms

since last write to WDR

WDR goes HIGH

for 2–4 ms

Execution begins at

ROM Address 0x0000

Figure 10-1. Watchdog Reset (WDR, Address 0x26)

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11.1

Clocking Mode on Wake-up from Suspend

11.0

Suspend Mode

When exiting suspend on a wake-up event, the device can be

configured to run in either Internal or External Clock mode.

The mode is selected by the state of the External Oscillator

Enable bit in the Clock Configuration Register (Figure 9-2).

Using the Internal Clock saves the external oscillator start-up

time and keeps that oscillator off for additional power savings.

The external oscillator mode can be activated when desired,

similar to operation at power-up.

The CY7C637xxC parts support a versatile low-power

suspend mode. In suspend mode, only an enabled interrupt or

a LOW state on the D–/SDATA pin will wake the part. Two

options are available. For lowest power, all internal circuits can

be disabled, so only an external event will resume operation.

Alternatively, a low-power internal wake-up timer can be used

to trigger the wake-up interrupt. This timer is described in

Section 11.2, and can be used to periodically poll the system

to check for changes, such as looking for movement in a

mouse, while maintaining a low average power.

The sequence of events for these modes is as follows:

Wake in Internal Clock Mode:

The CY7C637xxC is placed into a low-power state by setting

the Suspend bit of the Processor Status and Control Register

(Figure 20-1). All logic blocks in the device are turned off

except the GPIO interrupt logic, the D–/SDATA pin input

receiver, and (optionally) the wake-up timer. The clock oscil-

lators, as well as the free-running and Watchdog timers are

shut down. Only the occurrence of an enabled GPIO interrupt,

wake-up interrupt, SPI slave interrupt, or a LOW state on the

D–/SDATA pin will wake the part from suspend (D– LOW

indicates non-idle USB activity). Once one of these resuming

conditions occurs, clocks will be restarted and the device

returns to full operation after the oscillator is stable and the

selected delay period expires. This delay period is determined

by selection of internal vs. external clock, and by the state of

the Ext. Clock Resume Delay as explained in Section 9.0.

1. Before entering suspend, clear bit 0 of the Clock Configu-

ration Register. This selects Internal clock mode after sus-

pend.

2. Enter suspend mode by setting the suspend bit of the

Processor Status and Control Register.

3. After a wake-up event, the internal clock starts immediately

(within 2 µs).

4. A time-out period of 8 µs passes, and then firmware

execution begins.

5. At some later point, to activate External Clock mode, set bit

0 of the Clock Configuration Register. This halts the internal

clocks while the external clock becomes stable. After an

additional time-out (128 µs or 4 ms, see Section 9.0),

firmware execution resumes.

In suspend mode, any enabled and pending interrupt will wake

the part up. The state of the Interrupt Enable Sense bit (Bit 2,

Figure 20-1) does not have any effect. As a result, any inter-

rupts not intended for waking from suspend should be disabled

through the Global Interrupt Enable Register and the USB End

Point Interrupt Enable Register (Section 21.0).

Wake in External Clock Mode:

1. Before entering suspend, the external clock must be select-

ed by setting bit 0 of the Clock Configuration Register. Make

sure this bit is still set when suspend mode is entered. This

selects External clock mode after suspend.

2. Enter suspend mode by setting the suspend bit of the

Processor Status and Control Register.

If a resuming condition exists when the suspend bit is set, the

part will still go into suspend and then awake after the appro-

priate delay time. The Run bit in the Processor Status and

Control Register must be set for the part to resume out of

suspend.

3. After a wake-up event, the external oscillator is started. The

clock is monitored for stability (this takes approximately

50–100 µs with a ceramic resonator).

Once the clock is stable and the delay time has expired, the

microcontroller will execute the instruction following the I/O

write that placed the device into suspend mode before

servicing any interrupt requests.

4. After an additional time-out period (128 µs or 4 ms, see

Section 9.0), firmware execution resumes.

11.2

Wake-up Timer

To achieve the lowest possible current during suspend mode,

all I/O should be held at either V_CCor ground. In addition, the

GPIO bit interrupts (Figure 21-4 and Figure 21-5) should be

disabled for any pins that are not being used for a wake-up

interrupt. This should be done even if the main GPIO Interrupt

Enable (Figure 21-1) is off.

The wake-up timer runs whenever the wake-up interrupt is

enabled, and is turned off whenever that interrupt is disabled.

Operation is independent of whether the device is in suspend

mode or if the global interrupt bit is enabled. Only the Wake-up

Timer Interrupt Enable bit (Figure 21-1) controls the wake-up

timer.

Typical code for entering suspend is shown below:

Once this timer is activated, it will give interrupts after its

time-out period (see below). These interrupts continue period-

ically until the interrupt is disabled. Whenever the interrupt is

disabled, the wake-up timer is reset, so that a subsequent

enable always results in a full wake-up time.

...

; All GPIO set to low-power state (no floating

pins, and bit interrupts disabled unless

using for wake-up)

...

; Enable GPIO and/or wake-up timer

interrupts if desired for wake-up

; Select clock mode for wake-up (see

Section 11.1)

The wake-up timer can be adjusted by the user through the

Wake-up Timer Adjust bits in the Clock Configuration Register

(Figure 9-2). These bits clear on reset. In addition to allowing

the user to select a range for the wake-up time, a firmware

algorithm can be used to tune out initial process and operating

condition variations in this wake-up time. This can be done by

timing the wake-up interrupt time with the accurate 1.024-ms

timer interrupt, and adjusting the Timer Adjust bits accordingly

to approximate the desired wake-up time.

mov a, 09h

iowr FFh

; Set suspend and run bits

; Write to Status and Control Register –

Enter suspend, wait for GPIO/wake-up

interrupt or USB activity

nop

...

; This executes before any ISR

; Remaining code for exiting suspend

routine

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Table 11-1. Wake-up Timer Adjust Settings

Adjust Bits [2:0]

(Bits [6:4] in Figure 9-2)

Wake-up Time

000 (reset state)

1 * t_WAKE

2 * t_WAKE

001

010

011

100

101

110

111

4 * t_WAKE

8 * t_WAKE

16 * t_WAKE

32 * t_WAKE

64 * t_WAKE

128 * t_WAKE

See Section 26.0 for the value of t_WAKE

12.0

General Purpose I/O Ports

Ports 0 and 1 provide up to 16 versatile GPIO pins that can be

read or written (the number of pins depends on package type).

Figure 12-1 shows a diagram of a GPIO port pin.

V_CC

2

GPIO

Mode

SPI Bypass (P0.5–P0.7 only)

(=1 if SPI inactive, or for non-SPI pins)

Q3

Q1

Data

Internal

Data Bus

14 kΩ

Out

Register

GPIO

Q2

Port Write

(Data Reg must be 1

for SPI outputs)

Threshold Select

Port Read

Interrupt

To Capture Timers (P0.0, P0.1)

and SPI (P0.4–P0.7))

Polarity

Interrupt

Logic

To Interrupt

Controller

Interrupt

Enable

Figure 12-1. Block Diagram of GPIO Port (one pin shown)

Port 0 is an 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0

Each GPIO pin is configured independently. The driving state

of each GPIO pin is determined by the value written to the pin’s

Data Register and by two associated pin’s Mode0 and Mode1

bits.

in the CY7C63723C, or all 8 bits, P1.7–P1.0 in the

CY7C63743C parts. Each bit can also be selected as an

interrupt source for the microcontroller, as explained in Section

21.0.

The Port 0 Data Register is shown in Figure 12-2, and the Port

1 Data Register is shown in Figure 12-3. The Mode0 and

Mode1 bits for the two GPIO ports are given in Figure 12-4

through Figure 12-7.

The data for each GPIO pin is accessible through the Port

Data register. Writes to the Port Data register store outgoing

data state for the port pins, while reads from the Port Data

register return the actual logic value on the port pins, not the

Port Data register contents.

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Bit [7:0]: P1[7:0] Mode 0

Bit #

7

6

5

4

3

2

1

0

1 = Port Pin Mode 0 is logic HIGH

0 = Port Pin Mode 0 is logic LOW

Bit Name

P0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0

Figure 12-2. Port 0 Data (Address 0x00)

Bit [7:0]: P0[7:0]

0

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

P1[7:0] Mode1

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

1 = Port Pin is logic HIGH

0 = Port Pin is logic LOW

Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)

Bit [7:0]: P1[7:0] Mode 1

Bit #

Bit Name

Notes

7

6

5

4

3

2

1

0

1 = Port Pin Mode 1 is logic HIGH

0 = Port Pin Mode 1 is logic LOW

P1

Pins 7:2 only in CY7C63743C

Pins1:0in

all parts

Each pin can be independently configured as high-impedance

inputs, inputs with internal pull-ups, open drain outputs, or

traditional CMOS outputs with selectable drive strengths.

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0

Figure 12-3. Port 1 Data (Address 0x01)

Bit [7:0]: P1[7:0]

0

The driving state of each GPIO pin is determined by the value

written to the pin’s Data Register and by its associated Mode0

and Mode1 bits. Table 12-1 lists the configuration states

based on these bits. The GPIO ports default on reset to all

Data and Mode Registers cleared, so the pins are all in a

high-impedance state. The available GPIO output drive

strength are:

1 = Port Pin is logic HIGH

0 = Port Pin is logic LOW

• Hi-Z Mode (Mode1 = 0 and Mode0 = 0)

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Q1, Q2, and Q3 (Figure 12-1) are OFF. The GPIO pin is not

driven internally. Performing a read from the Port Data Reg-

ister return the actual logic value on the port pins.

P0[7:0] Mode0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

• Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data

Register = 0)

Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of

sinking 2 mA of current.

Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A)

• Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s

Bit [7:0]: P0[7:0] Mode 0

Data Register = 0)

1 = Port 0 Mode 0 is logic HIGH

0 = Port 0 Mode 0 is logic LOW

Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of

sinking 8 mA of current.

• High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data

Register = 0)

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of

sinking 50 mA of current.

P0[7:0] Mode1

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

• High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s

Data Register = 1)

Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of

sourcing 2 mA of current.

Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B)

Bit [7:0]: P0[7:0] Mode 1

• Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data

Register = 1)

1 = Port Pin Mode 1 is logic HIGH

0 = Port Pin Mode 1 is logic LOW

Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up

with an internal 14-kΩ resistor.

Note that open drain mode can be achieved by fixing the Data

and Mode1 Registers LOW, and switching the Mode0 register.

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

P1[7:0] Mode0

Input thresholds are CMOS, or TTL as shown in the table (See

Section 25.0 for the input threshold voltage in TTL or CMOS

modes). Both input modes include hysteresis to minimize

noise sensitivity. In suspend mode, if a pin is used for a

wake-up interrupt using an external R-C circuit, CMOS mode

is preferred for lowest power.

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C)

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13.0

USB Serial Interface Engine (SIE)

Table 12-1. Ports 0 and 1 Output Control Truth Table

Data

Mode1 Mode0 Output Drive

Strength

Input

The SIE allows the microcontroller to communicate with the

USB host. The SIE simplifies the interface between the micro-

controller and USB by incorporating hardware that handles the

following USB bus activity independently of the microcon-

troller:

Register

Threshold

0

1

0

Hi-Z

CMOS

TTL

0

1

Hi-Z

Medium

CMOS

• Translate the encoded received data and format the data to

be transmitted on the bus.

(8 mA) Sink

• CRC checking and generation. Flag the microcontroller if

errors exist during transmission.

• Address checking. Ignore the transactions not addressed

to the device.

• Send appropriate ACK/NAK/STALL handshakes.

• Token type identification (SETUP, IN, or OUT). Set the ap-

propriate token bit once a valid token is received.

• Place valid received data in the appropriate endpoint FIFOs.

• Send and update the data toggle bit (Data1/0).

• Bit stuffing/unstuffing.

1

0

High Drive

CMOS

Low (2 mA)

Sink

1

0

1

0

Resistive

CMOS

High (50 mA)

Sink

1

High Drive

CMOS

12.1

Auxiliary Input Port

Firmware is required to handle the rest of the USB interface

with the following tasks:

Port 2 serves as an auxiliary input port as shown in

Figure 12-8. The Port 2 inputs all have TTL input thresholds.

• Coordinate enumeration by decoding USB device requests.

• Fill and empty the FIFOs.

• Suspend/Resume coordination.

Bit #

7

6

5

4

3

2

1

0

• Verify and select Data toggle values.

Bit Reserved D+

D–

Reserved P2.1 P2.0

Name

(SCLK) (SDATA) (Internal VREG

13.1

USB Enumeration

State

Clock

Mode State

Only)

A typical USB enumeration sequence is shown below. In this

description, ‘Firmware’ refers to embedded firmware in the

CY7C637xxC controller.

Read/

Write

-

R

0

R

0

-

R

1. The host computer sends a SETUP packet followed by a

DATA packet to USB address 0 requesting the Device de-

scriptor.

Reset

0

Figure 12-8. Port 2 Data Register (Address 0x02)

Bit [7:6]: Reserved

Bit [5:4]: D+ (SCLK) and D– (SDATA) States

2. Firmware decodes the request and retrieves its Device

descriptor from the program memory tables.

3. The host computer performs a control read sequence and

Firmware responds by sending the Device descriptor over

the USB bus, via the on-chip FIFO.

The state of the D+ and D– pins can be read at Port 2 Data

Register. Performing a read from the port pins returns their

logic values.

4. After receiving the descriptor, the host sends a SETUP

packet followed by a DATA packet to address 0 assigning

a new USB address to the device.

1 = Port Pin is logic HIGH

0 = Port Pin is logic LOW

5. Firmware stores the new address in its USB Device

Address Register after the no-data control sequence

completes.

Bit [3:2]: Reserved

Bit 1: P2.1 (Internal Clock Mode Only)

6. The host sends a request for the Device descriptor using

the new USB address.

In the Internal Clock mode, the XTALIN pin can serve as a

general purpose input, and its state can be read at Port 2,

Bit 1 (P2.1). See Section 9.1 for more details.

7. Firmware decodes the request and retrieves the Device

descriptor from program memory tables.

1 = Port Pin is logic HIGH

0 = Port Pin is logic LOW

8. The host performs a control read sequence and Firmware

responds by sending its Device descriptor over the USB

bus.

Bit 0: P2.0/VREG Pin State

9. The host generates control reads from the device to request

the Configuration and Report descriptors.

In PS/2 mode, the VREG pin can be used as an input and

its state can be read at port P2.0. Section 15.0 for more

details.

10.Once the device receives a Set Configuration request, its

functions may now be used.

1 = Port Pin is logic HIGH

0 = Port Pin is logic LOW

11.Firmware should take appropriate action for Endpoint 1

and/or 2 transactions, which may occur from this point.

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1 = PS/2 interrupt mode. A PS/2 activity interrupt will occur

if the SDATA pin is continuously LOW for 128 to 256 µs.

13.2

USB Port Status and Control

USB status and control is regulated by the USB Status and

0 = USB interrupt mode (default state). In this mode, a USB

bus reset interrupt will occur if the single ended zero (SE0,

D– and D+ are LOW) exists for 128 to 256 µs.

Control Register as shown in Figure 13-1.

Bit #

7

6

5

4

3

2:0

See Section 21.3 for more details.

Bit 4: Reserved. Must be written as a ‘0’.

Bit 3: USB Bus Activity

Bit PS/2 VREG USB Reserved USB

Name Pull-up Enable Reset-

D+/D–

Forcing

Bit

Bus

Activity

Enable

PS/2

Activity

Interrupt

Mode

The Bus Activity bit is a “sticky” bit that detects any non-idle

USB event has occurred on the USB bus. Once set to HIGH

by the SIE to indicate the bus activity, this bit retains its

logical HIGH value until firmware clears it. Writing a ‘0’ to

this bit clears it; writing a ‘1’ preserves its value. The user

firmware should check and clear this bit periodically to de-

tect any loss of bus activity. Firmware can clear the Bus

Activity bit, but only the SIE can set it. The 1.024-ms timer

interrupt service routine is normally used to check and clear

the Bus Activity bit.

Read/ R/W R/W

R/W

-

R/W

0

R/W

Write

Reset

0

0 0 0

Figure 13-1. USB Status and Control Register (Address

0x1F)

Bit 7: PS/2 Pull-up Enable

1 = There has been bus activity since the last time this bit

was cleared. This bit is set by the SIE.

This bit is used to enable the internal PS/2 pull-up resistors

on the SDATA and SCLK pins. Normally the output high

level on these pins is V_CC, but note that the output will be

clamped to approximately 1 Volt above V_REGif the VREG

Enable bit is set, or if the Device Address is enabled (bit 7

of the USB Device Address Register, Figure 14-1).

0 = No bus activity since last time this bit was cleared (by

firmware).

Bit [2:0]: D+/D– Forcing Bit [2:0]

1 = Enable PS/2 Pull-up resistors. The SDATA and SCLK

pins are pulled up internally to V_CCwith two resistors of

approximately 5 kΩ (see Section 25.0 for the value of

R_PS2).

Forcing bits allow firmware to directly drive the D+ and D–

pins, as shown in Table 13-1. Outputs are driven with con-

trolled edge rates in these modes for low EMI. For forcing

the D+ and D– pins in USB mode, D+/D– Forcing Bit 2

should be 0. Setting D+/D– Forcing Bit 2 to ‘1’ puts both

pins in an open-drain mode, preferred for applications such

as PS/2 or LED driving.

0 = Disable PS/2 Pull-up resistors.

Bit 6: V_REGEnable

A 3.3V voltage regulator is integrated on chip to provide a

voltage source for a 1.5-kΩ pull-up resistor connected to

the D– pin as required by the USB Specification. Note that

the VREG output has an internal series resistance of ap-

proximately 200Ω, the external pull-up resistor required is

approximately 1.3-kΩ (see Figure 16-1).

Table 13-1. Control Modes to Force D+/D– Outputs

D+/D–Forcing

Bit [2:0]

Control Action

Application

000

001

010

011

100

101

110

111

Not forcing (SIE controls driver) Any Mode

Force K (D+ HIGH, D– LOW)

Force J (D+ LOW, D– HIGH)

Force SE0 (D– LOW, D+ LOW)

Force D– LOW, D+ LOW

Force D– LOW, D+ HiZ

USB Mode

1 = Enable the 3.3V output voltage on the VREG pin.

0 = Disable. The VREG pin can be configured as an input.

Bit 5: USB-PS/2 Interrupt Select

PS/2 Mode^[2]

This bit allows the user to select whether an USB bus reset

interrupt or a PS/2 activity interrupt will be generated when

the interrupt conditions are detected.

Force D– HiZ, D+ LOW

Force D– HiZ, D+ HiZ

Note:

2. For PS/2 operation, the D+/D– Forcing Bit [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.

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The SIE provides a locking feature to prevent firmware from

overwriting bits in the USB Endpoint 0 Mode Register. Writes

to the register have no effect from the point that Bit[6:0] of the

register are updated (by the SIE) until the firmware reads this

register. The CPU can unlock this register by reading it.

14.0

USB Device

The CY7C637xxC supports one USB Device Address with

three endpoints: EP0, EP1, and EP2.

Because of these hardware-locking features, firmware should

perform an read after a write to the USB Endpoint 0 Mode

Register and USB Endpoint 0 Count Register (Figure 14-4) to

verify that the contents have changed as desired, and that the

SIE has not updated these values.

14.1

USB Address Register

The USB Device Address Register contains a 7-bit USB

address and one bit to enable USB communication. This

register is cleared during a reset, setting the USB device

address to zero and marking this address as disabled.

Figure 14-1 shows the format of the USB Address Register.

Bit [7:4] of this register are cleared by any non-locked write to

this register, regardless of the value written.

Bit #

7

6

5

4

3

2

1

0

Bit 7: SETUP Received

Bit Name

Device

Address

Enable

Device Address

1 = A valid SETUP packet has been received. This bit is

forced HIGH from the start of the data packet phase of the

SETUP transaction until the start of the ACK packet re-

turned by the SIE. The CPU is prevented from clearing this

bit during this interval. While this bit is set to ‘1’, the CPU

cannot write to the EP0 FIFO. This prevents firmware from

overwriting an incoming SETUP transaction before firm-

ware has a chance to read the SETUP data.

Read/Write

Reset

R/W R/W R/W R/W R/W R/W R/W R/W

0

Figure 14-1. USB Device Address Register (Address 0x10)

In either USB or PS/2 mode, this register is cleared by both

hardware resets and the USB bus reset. See Section 21.3 for

more information on the USB Bus Reset – PS/2 interrupt.

0 = No SETUP received. This bit is cleared by any

non-locked writes to the register.

Bit 6: IN Received

Bit 7: Device Address Enable

1 = A valid IN packet has been received. This bit is updated

to ‘1’ after the last received packet in an IN transaction. This

bit is cleared by any non-locked writes to the register.

This bit must be enabled by firmware before the serial in-

terface engine (SIE) will respond to USB traffic at the ad-

dress specified in Bit [6:0].

0 = No IN received. This bit is cleared by any non-locked

writes to the register.

1 = Enable USB device address.

0 = Disable USB device address.

Bit 5: OUT Received

1 = A valid OUT packet has been received. This bit is up-

dated to ‘1’ after the last received packet in an OUT trans-

action. This bit is cleared by any non-locked writes to the

register.

Bit [6:0]: Device Address Bit [6:0]

These bits must be set by firmware during the USB enumer-

ation process (i.e., SetAddress) to the non-zero address

assigned by the USB host.

0 = No OUT received. This bit is cleared by any non-locked

writes to the register.

14.2

USB Control Endpoint

Bit 4: ACKed Transaction

All USB devices are required to have an endpoint number 0

(EP0) that is used to initialize and control the USB device. EP0

provides access to the device configuration information and

allows generic USB status and control accesses. EP0 is

bidirectional as the device can both receive and transmit data.

EP0 uses an 8-byte FIFO at SRAM locations 0xF8-0xFF, as

shown in Section 8.2.

The ACKed Transaction bit is set whenever the SIE engag-

es in a transaction to the register's endpoint that completes

with an ACK packet.

1 = The transaction completes with an ACK.

0 = The transaction does not complete with an ACK.

The EP0 endpoint mode register uses the format shown in

Figure 14-2.

Bit [3:0]: Mode Bit[3:0]

The endpoint modes determine how the SIE responds to

USB traffic that the host sends to the endpoint. For exam-

ple, if the endpoint Mode Bits [3:0] are set to 0001 which is

NAK IN/OUT mode as shown in Table 22-1, the SIE will

send NAK handshakes in response to any IN or OUT token

sent to this endpoint. In this NAK IN/OUT mode, the SIE will

send an ACK handshake when the host sends a SETUP

token to this endpoint. The mode encoding is shown in

Table 22-1. Additional information on the mode bits can be

found in Table 22-2 and Table 22-3. These modes give the

firmware total control on how to respond to different tokens

sent to the endpoints from the host.

Bit #

Bit

7

6

5

4

3:0

SETUP

IN

OUT

ACKed

Mode Bit

Name Received Received Received Transaction

Read/

Write

R/W

Reset

0

0 0 0 0

Figure 14-2. Endpoint 0 Mode Register (Address 0x12)

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In addition, the Mode Bits are automatically changed by the

SIE in response to many USB transactions. For example, if

the Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK

IN mode as shown in Table 22-1, the SIE will change the

endpoint Mode Bit [3:0] to NAK IN/OUT (0001) mode after

issuing an ACK handshake in response to an OUT token.

Firmware needs to update the mode for the SIE to respond

appropriately.

14.4

USB Endpoint Counter Registers

There are three Endpoint Counter registers, with identical

formats for both control and non-control endpoints. These

registers contain byte count information for USB transactions,

as well as bits for data packet status. The format of these

registers is shown in Figure 14-4.

Bit #

Bit Name Data

Toggle Valid

7

6

5

4

3

2

1

0

14.3

USB Non-control Endpoints

Data Reserved

Byte Count

The CY7C637xxC feature two non-control endpoints, endpoint

1 (EP1) and endpoint 2 (EP2). The EP1 and EP2 Mode

Registers do not have the locking mechanism of the EP0

Mode Register. The EP1 and EP2 Mode Registers use the

format shown in Figure 14-3. EP1 uses an 8-byte FIFO at

SRAM locations 0xF0–0xF7, EP2 uses an 8-byte FIFO at

SRAM locations 0xE8–0xEF as shown in Section 8.2.

Read/Writ R/W

R/W

-

R/ R/ R/ R/

W

0

e

W

0

W

0

W

0

Reset

0

Figure 14-4. Endpoint 0,1,2 Counter Registers

(Addresses 0x11, 0x13 and 0x15)

Bit 7: Data Toggle

Bit #

7

6

5

4

3

2

1

0

This bit selects the DATA packet's toggle state. For IN

transactions, firmware must set this bit to the select the

transmitted Data Toggle. For OUT or SETUP transactions,

the hardware sets this bit to the state of the received Data

Toggle bit.

Bit STALL Reserved ACKed

Mode Bit

Name

Transaction

R/C

Read/ R/W

-

R/W R/W R/W R/W

Write

1 = DATA1

0 = DATA0

Reset

0

Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Ad-

dresses 0x14 and 0x16)

Bit 6: Data Valid

Bit 7: STALL

This bit is used for OUT and SETUP tokens only. This bit is

cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred.

This bit does not update for some endpoint mode settings.

Refer to Table 22-3 for more details.

1 = The SIE will stall an OUT packet if the Mode Bits are set

to ACK-OUT, and the SIE will stall an IN packet if the mode

bits are set to ACK-IN. See Section 22.0 for the available

modes.

1 = Data is valid.

0 = This bit must be set to LOW for all other modes.

0 = Data is invalid. If enabled, the endpoint interrupt will

occur even if invalid data is received.

Bit [6:5]: Reserved. Must be written to zero during register

writes.

Bit [5:4]: Reserved

Bit 4: ACKed Transaction

Bit [3:0]: Byte Count Bit [3:0]

The ACKed transaction bit is set whenever the SIE engag-

es in a transaction to the register's endpoint that completes

with an ACK packet.

Byte Count Bits indicate the number of data bytes in a

transaction: For IN transactions, firmware loads the count

with the number of bytes to be transmitted to the host from

the endpoint FIFO. Valid values are 0 to 8 inclusive. For

OUT or SETUP transactions, the count is updated by hard-

ware to the number of data bytes received, plus 2 for the

CRC bytes. Valid values are 2 to 10 inclusive.

1 = The transaction completes with an ACK.

0 = The transaction does not complete with an ACK.

Bit [3:0]: Mode Bit [3:0]

For Endpoint 0 Count Register, whenever the count up-

dates from a SETUP or OUT transaction, the count register

locks and cannot be written by the CPU. Reading the reg-

ister unlocks it. This prevents firmware from overwriting a

status update on incoming SETUP or OUT transactions be-

fore firmware has a chance to read the data.

The EP1 and EP2 Mode Bits operate in the same manner

as the EP0 Mode Bits (see Section 14.2).

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VREG pin is effectively disconnected when the CY7C637xxC

device transmits USB from the internal SIE. This means that

the VREG pin does not provide a stable voltage during

transmits, although this does not affect USB signaling.

15.0

USB Regulator Output

The VREG pin provides a regulated output for connecting the

pull-up resistor required for USB operation. For USB, a 1.5-kΩ

resistor is connected between the D– pin and the V_REG

voltage, to indicate low-speed USB operation. Since the

VREG output has an internal series resistance of approxi-

mately 200Ω, the external pull-up resistor required is R_PU(see

Section 25.0).

16.0

PS/2 Operation

The CY7C637xxC parts are optimized for combination USB or

PS/2 devices, through the following features:

The regulator output is placed in a high-impedance state at

reset, and must be enabled by firmware by setting the VREG

Enable bit in the USB Status and Control Register

(Figure 13-1). This simplifies the design of a combination

PS/2-USB device, since the USB pull-up resistor can be left in

place during PS/2 operation without loading the PS/2 line. In

this mode, the V_REGpin can be used as an input and its state

can be read at port P2.0. Refer to Figure 12-8 for the Port 2

data register. This input has a TTL threshold.

1. USB D+ and D– lines can also be used for PS/2 SCLK and

SDATA pins, respectively. With USB disabled, these lines

can be placed in a high-impedance state that will pull up to

V

_CC. (Disable USB by clearing the Address Enable bit of

the USB Device Address Register, Figure 14-1).

2. An interrupt is provided to indicate a long LOW state on the

SDATA pin. This eliminates the need to poll this pin to check

for PS/2 activity. Refer to Section 21.3 for more details.

3. Internal PS/2 pull-up resistors can be enabled on the SCLK

and SDATA lines, so no GPIO pins are required for this task

(bit 7, USB Status and Control Register, Figure 13-1).

In suspend mode, the regulator is automatically disabled. If

VREG Enable bit is set (Figure 13-1), the VREG pin is pulled

up to V_CCwith an internal 6.2-kΩ resistor. This holds the

proper V_OHstate in suspend mode

4. The controlled slew rate outputs from these pins apply to

both USB and PS/2 modes to minimize EMI.

Note that enabling the device for USB (by setting the Device

Address Enable bit, Figure 14-1) activates the internal

regulator, even if the VREG Enable bit is cleared to 0. This

insures proper USB signaling in the case where the VREG pin

is used as an input, and an external regulator is provided for

the USB pull-up resistor. This also limits the swing on the D–

and D+ pins to about 1V above the internal regulator voltage,

so the Device Address Enable bit normally should only be set

for USB operating modes.

5. The state of the SCLK and SDATA pins can be read, and

can be individually driven LOW in an open drain mode. The

pins are read at bits [5:4] of Port 2, and are driven with the

Control Bits [2:0] of the USB Status and Control Register.

6. The V_REGpin can be placed into a high-impedance state,

so that a USB pull-up resistor on the D–/SDATA pin will not

interfere with PS/2 operation (bit 6, USB Status and Control

Register).

The regulator output is only designed to provide current for the

USB pull-up resistor. In addition, the output voltage at the

The PS/2 on-chip support circuitry is illustrated in Figure 16-1.

Port 2.0

VREG Enable

200Ω

VREG

3.3V

Regulator

V_CC

PS/2 Pull-up

Enable

1.3 kΩ

5 kΩ

D+/SCLK

USB - PS/2

Driver

D–/SDATA

Port 2.5

Port 2.4

On-chip Off-chip

Figure 16-1. Diagram of USB-PS/2 System Connections

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both transmit and receive data for maximum flexibility and

throughput. The CY7C637xxC can be configured as either an

SPI Master or Slave. The external interface consists of

Master-Out/Slave-In (MOSI), Master-In/Slave-Out (MISO),

Serial Clock (SCK), and Slave Select (SS).

17.0

Serial Peripheral Interface (SPI)

SPI is a four-wire, full-duplex serial communication interface

between a master device and one or more slave devices. The

CY7C637xxC SPI circuit supports byte serial transfers in

either Master or Slave modes. The block diagram of the SPI

circuit is shown in Figure 17-1. The block contains buffers for

SPI modes are activated by setting the appropriate bits in the

SPI Control Register, as described below.

Data Bus Write

TX Buffer

MOSI

Master

/ Slave

Control

8 bit shift register

RX Buffer

MISO

SCK

SS

4

Internal SCK

Data Bus

Figure 17-1. SPI Block Diagram

Read

The SPI Data Register below serves as a transmit and receive

buffer.

When operating as a Master, an active LOW Slave Select (SS)

must be generated to enable a Slave for a byte transfer. This

Slave Select is generated under firmware control, and is not

part of the SPI internal hardware. Any available GPIO can be

used for the Master’s Slave Select output.

Bit #

Bit Name

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset

Figure 17-2. SPI Data Register (Address 0x60)

Bit [7:0]: Data I/O[7:0]

7

6

5

4

3

2

1

0

Data I/O

When the Master writes to the SPI Data Register, the data is

loaded into the transmit buffer. If the shift register is not busy

shifting a previous byte, the TX buffer contents will be automat-

ically transferred into the shift register and shifting will begin.

If the shift register is busy, the new byte will be loaded into the

shift register only after the active byte has finished and is trans-

ferred to the receive buffer. The new byte will then be shifted

out. The Transmit Buffer Full (TBF) bit will be set HIGH until

the transmit buffer’s data-byte is transferred to the shift

register. Writing to the transmit buffer while the TBF bit is HIGH

will overwrite the old byte in the transmit buffer.

0

Writes to the SPI Data Register load the transmit buffer,

while reads from this register read the receive buffer con-

tents.

1 = Logic HIGH

0 = Logic LOW

The byte shifting and SCK generation are handled by the

hardware (based on firmware selection of the clock source).

Data is shifted out on the MOSI pin (P0.5) and the serial clock

is output on the SCK pin (P0.7). Data is received from the slave

on the MISO pin (P0.6). The output pins must be set to the

desired drive strength, and the GPIO data register must be set

to 1 to enable a bypass mode for these pins. The MISO pin

must be configured in the desired GPIO input mode. See

Section 12.0 for GPIO configuration details.

17.1

Operation as an SPI Master

Only an SPI Master can initiate a byte/data transfer. This is

done by the Master writing to the SPI Data Register. The

Master shifts out 8 bits of data (MSB first) along with the serial

clock SCK for the Slave. The Master’s outgoing byte is

replaced with an incoming one from a Slave device. When the

last bit is received, the shift register contents are transferred

to the receive buffer and an interrupt is generated. The receive

data must be read from the SPI Data Register before the next

byte of data is transferred to the receive buffer, or the data will

be lost.

17.2

Master SCK Selection

The Master’s SCK is programmable to one of four clock

settings, as shown in Figure 17-1. The frequency is selected

with the Clock Select Bits of the SPI control register. The

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hardware provides 8 output clocks on the SCK pin (P0.7) for

each byte transfer. Clock phase and polarity are selected by

the CPHA and CPOL control bits (see Figure 17-1 and 17-4).

Bit #

Bit Name TCMP TBF Comm CPOL CPHA SCK

Mode[1:0] Select

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset

Figure 17-3. SPI Control Register (Address 0x61)

Bit 7: TCMP

7

6

5

4

3

2

1

0

The master SCK duty cycle is nominally 33% in the fastest (2

Mbps) mode, and 50% in all other modes.

0

17.3

Operation as an SPI Slave

In slave mode, the chip receives SCK from an external master

on pin P0.7. Data from the master is shifted in on the MOSI pin

(P0.5), while data is being shifted out of the slave on the MISO

pin (P0.6). In addition, the active LOW Slave Select must be

asserted to enable the slave for transmit. The Slave Select pin

is P0.4. These pins must be configured in appropriate GPIO

modes, with the GPIO data register set to 1 to enable bypass

mode selected for the MISO pin.

1 = TCMP is set to 1 by the hardware when 8-bit transfer is

complete. The SPI interrupt is asserted at the same time

TCMP is set to 1.

0 = This bit is only cleared by firmware.

Bit 6: TBF

In Slave mode, writes to the SPI Data Register load the

Transmit buffer. If the Slave Select is asserted (SS LOW) and

the shift register is not busy shifting a previous byte, the

transmit buffer contents will be automatically transferred into

the shift register. If the shift register is busy, the new byte will

be loaded into the shift register only after the active byte has

finished and is transferred to the receive buffer. The new byte

is then ready to be shifted out (shifting waits for SCK from the

Master). If the Slave Select is not active when the transmit

buffer is loaded, data is not transferred to the shift register until

Slave Select is asserted. The Transmit Buffer Full (TBF) bit will

be set to ‘1’ until the transmit buffer’s data-byte is transferred

to the shift register. Writing to the transmit buffer while the TBF

bit is HIGH will overwrite the old byte in the Transmit Buffer.

Transmit Buffer Full bit.

1 = Indicates data in the transmit buffer has not transferred

to the shift register.

0 = Indicates data in the transmit buffer has transferred to

the shift register.

Bit [5:4] Comm Mode[1:0]

00 = All communications functions disabled (default).

01 = SPI Master Mode.

10 = SPI Slave Mode.

11 = Reserved.

If the Slave Select is deasserted before a byte transfer is

complete, the transfer is aborted and no interrupt is generated.

Whenever Slave Select is asserted, the transmit buffer is

automatically reloaded into the shift register.

Bit 3: CPOL

SPI Clock Polarity bit.

1 = SCK idles HIGH.

0 = SCK idles LOW.

Clock phase and polarity must be selected to match the SPI

master, using the CPHA and CPOL control bits (see

Figure 17-3 and Figure 17-4).

Bit 2: CPHA

SPI Clock Phase bit (see Figure 17-4)

The SPI slave logic continues to operate in suspend, so if the

SPI interrupt is enabled, the device can go into suspend during

a SPI slave transaction, and it will wake up at the interrupt that

signals the end of the byte transfer.

Bit [1:0]: SCK Select

Master mode SCK frequency selection (no effect in Slave

Mode):

00 = 2 Mbit/s

17.4

SPI Status and Control

01 = 1 Mbit/s

The SPI Control Register is shown in Figure 17-3. The timing

diagram in Figure 17-4 shows the clock and data states for the

various SPI modes.

10 = 0.5 Mbit/s

11 = 0.0625 Mbit/s

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SCK (CPOL = 0)

SCK (CPOL = 1)

SS

CPHA = 0:

MOSI/MISO

x

MSB

LSB

Data Capture Strobe

Interrupt Issued

CPHA = 1:

x

MOSI/MISO

MSB

LSB

Data Capture Strobe

Interrupt Issued

Figure 17-4. SPI Data Timing

operation. When SPI master or slave modes are activated, the

appropriate bypass signals are driven by the hardware for

outputs, and are held at 1 for inputs. Note that the corre-

sponding data bits in the Port 0 Data Register must be set

to 1 for each pin being used for an SPI output. In addition,

the GPIO modes are not affected by operation of the SPI

block, so each pin must be programmed by firmware to the

desired drive strength mode.

17.5

SPI Interrupt

For SPI, an interrupt request is generated after a byte is

received or transmitted. See Section 21.3 for details on the SPI

interrupt.

17.6

SPI Modes for GPIO Pins

The GPIO pins used for SPI outputs (P0.5–P0.7) contain a

bypass mode, as shown in the GPIO block diagram

(Figure 12-1). Whenever the SPI block is inactive (Mode[5:4]

= 00), the bypass value is 1, which enables normal GPIO

For GPIO pins that are not used for SPI outputs, the SPI

bypass value in Figure 12-1 is always 1, for normal GPIO

operation.

Table 17-1. SPI Pin Assignments

SPI Function

GPIO Pin

Comment

Slave Select (SS)

P0.4

For Master Mode, Firmware sets SS, may use any GPIO pin.

For Slave Mode, SS is an active LOW input.

Master Out, Slave In (MOSI)

Master In, Slave Out (MISO)

SCK

P0.5

P0.6

P0.7

Data output for master, data input for slave.

Data input for master, data output for slave.

SPI Clock: Output for master, input for slave.

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Bit [7:0]: Timer lower eight bits

18.0

12-bit Free-running Timer

The 12-bit timer operates with a 1-µs tick, provides two inter-

rupts (128-µs and 1.024-ms) and allows the firmware to

directly time events that are up to 4 ms in duration. The lower

eight bits of the timer can be read directly by the firmware.

Reading the lower eight bits latches the upper four bits into a

temporary register. When the firmware reads the upper four

bits of the timer, it is actually reading the count stored in the

temporary register. The effect of this is to ensure a stable 12-bit

timer value can be read, even when the two reads are

separated in time.

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Reserved

Timer [11:8]

-

R

0

R

0

R

0

R

0

Figure 18-2. Timer MSB Register (Address 0x25)

Bit [7:4]: Reserved

Bit [3:0]: Timer upper four bits

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Timer [7:0]

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Figure 18-1. Timer LSB Register (Address 0x24)

1.024-ms interrupt

128-µs interrupt

11 10

9

8

7

6

5

4

3

2

1

0

1 MHz clock

L3 L2 L1 L0

D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

To Timer Registers

8

Figure 18-3. Timer Block Diagram

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capture eight bits of the free-running timer into its Capture

Timer Data Register if a rising or falling edge event that

matches the specified rising or falling edge condition at the pin.

A prescaler allows selection of the capture timer tick size.

Interrupts can be individually enabled for the four capture

registers. A block diagram is shown in Figure 19-1.

19.0

Timer Capture Registers

Four 8-bit capture timer registers provide both rising- and

falling-edge event timing capture on two pins. Capture Timer

A is connected to Pin 0.0, and Capture Timer B is connected

to Pin 0.1. These can be used to mark the time at which a rising

or falling event occurs at the two GPIO pins. Each timer will

Free-running Timer

1 MHz

11 10

9

8

7

6

5

4

3

2

1

0

Clock

Prescaler

Mux

First Edge Hold

Bit 7, Reg 0x44

8-bit Capture Registers

Timer A Rising Edge Time

Rising

Edge

GPIO

P0.0

Detect

Timer A Falling Edge Time

Falling

Edge

Detect

Timer B Rising Edge Time

Timer B Falling Edge Time

Rising

Edge

Detect

GPIO

P0.1

Falling

Edge

Detect

Capture A Rising Int Enable

Bit 0, Reg 0x44

Capture Timer A Interrupt Request

Capture Timer B Interrupt Request

Capture A Falling Int Enable

Bit 1, Reg 0x44

Capture B Rising Int Enable

Bit 2, Reg 0x44

Capture B Falling Int Enable

Bit 3, Reg 0x44

Figure 19-1. Capture Timers Block Diagram

The four Capture Timer Data Registers are read-only, and are

shown in Figure 19-2 through Figure 19-5.

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Capture A Rising Data

Out of the 12-bit free running timer, the 8-bit captured in the

Capture Timer Data Registers are determined by the Prescale

Bit [2:0] in the Capture Timer Configuration Register

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

(Figure 19-7).

.

Figure 19-2. Capture Timer A-Rising, Data Register

(Address 0x40)

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Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Bit #

7

6

5

4

3

2

1

0

Capture A Falling Data

Bit First Prescale Bit Capture Capture Capture Capture

Name Edge

[2:0]

B

A

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Hold

Falling Rising Falling Rising

Int Int Int Int

Enable Enable Enable Enable

Figure 19-3. Capture Timer A-Falling, Data Register

(Address 0x41)

Read/ R/W R/W R/W R/W R/W

Write

R/W

Reset

0

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Capture B Rising Data

Figure 19-7. Capture Timer Configuration Register

(Address 0x44)

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Bit 7: First Edge Hold

1 = The time of the first occurrence of an edge is held in the

Capture Timer Data Register until the data is read. Subse-

quent edges are ignored until the Capture Timer Data Reg-

ister is read.

Figure 19-4. Capture Timer B-Rising, Data Register

(Address 0x42)

0 = The time of the most recent edge is held in the Capture

Timer Data Register. That is, if multiple edges have oc-

curred before reading the capture timer, the time for the last

one will be read (default state).

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Capture B Falling Data

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

The First Edge Hold function applies globally to all four cap-

ture timers.

Figure 19-5. Capture Timer B-Falling, Data Register

(Address 0x43)

Bit [6:4]: Prescale Bit [2:0]

Three prescaler bits allow the capture timer clock rate to be

selected among 5 choices, as shown in Table 19-1 below.

Bit #

7

6

5

4

3

2

1

0

Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable

Bit

Reserved

Capture Capture Capture Capture

Name

B

A

Each of the four Capture Timer registers can be individually

enabled to provide interrupts.

Falling Rising Falling Rising

Event

Both Capture A events share a common interrupt request,

as do the two Capture B events. In addition to the event

enables, the main Capture Interrupt Enables bit in the Glo-

bal Interrupt Enable register (Section 21.0) must be set to

activate a capture interrupt.

Read/

Write

-

R

Reset

0

Figure 19-6. Capture Timer Status Register (Address 0x45)

1 = Enable interrupt

Bit [7:4]: Reserved.

0 = Disable interrupt

Table 19-1. Capture Timer Prescalar Settings (Step size

and range for F_CLK= 6 MHz)

Bit [3:0]: Capture A/B, Falling/Rising Event

These bits record the occurrence of any rising or falling

edges on the capture GPIO pins. Bits in this register are

cleared by reading the corresponding data register.

LSB

Step

Size

Prescale

2:0

Captured Bits

Range

256 µs

512 µs

1 = A rising or falling event that matches the pin’s rising/fall-

ing condition has occurred.

000

001

010

011

100

Bits 7:0 of free-running timer

Bits 8:1 of free-running timer

Bits 9:2 of free-running timer

1 µs

2 µs

0 = No event that matches the pin’s rising or falling edge

condition.

4 µs 1.024 ms

Because both Capture A events (rising and falling) share

an interrupt, user’s firmware needs to check the status of

both Capture A Falling and Rising Event bits to determine

what caused the interrupt. This is also true for Capture B

events.

Bits 10:3 of free-running timer 8 µs 2.048 ms

Bits 11:4 of free-running timer 16 µs 4.096 ms

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20.0

Processor Status and Control Register

Bit #

7

6

5

4

3

2

1

0

Bit Name

IRQ

Pending

Watchdog

Reset

Bus

Interrupt

Event

LVR/BOR

Reset

Suspend

Interrupt

Enable

Sense

Reserved

Run

Read/Write

Reset

R

0

R/W

1

R/W

0

R/W

1

R/W

0

R

0

-

R/W

1

0

Figure 20-1. Processor Status and Control Register (Address 0xFF)

Bit 7: IRQ Pending

Bit 3: Suspend

When an interrupt is generated, it is registered as a pending

interrupt. The interrupt will remain pending until its interrupt

enable bit is set (Figure 21-1 and Figure 21-2) and inter-

rupts are globally enabled (Bit 2, Processor Status and

Control Register). At that point the internal interrupt han-

dling sequence will clear the IRQ Pending bit until another

interrupt is detected as pending. This bit is only valid if the

Global Interrupt Enable bit is disabled.

Writing a '1' to the Suspend bit will halt the processor and

cause the microcontroller to enter the suspend mode that

significantly reduces power consumption. An interrupt or

USB bus activity will cause the device to come out of sus-

pend. After coming out of suspend, the device will resume

firmware execution at the instruction following the IOWR

which put the part into suspend. When writing the suspend

bit with a resume condition present (such as non-idle USB

activity), the suspend state will still be entered, followed

immediately by the wake-up process (with appropriate de-

lays for the clock start-up). See Section 11.0 for more de-

tails on suspend mode operation.

1 = There are pending interrupts.

0 = No pending interrupts.

Bit 6: Watchdog Reset

1 = Suspend the processor.

The Watchdog Timer Reset (WDR) occurs when the inter-

nal Watchdog timer rolls over. The timer will roll over and

WDR will occur if it is not cleared within t_WATCH(see Section

26.0 for the value of t_WATCH). This bit is cleared by an

LVR/BOR. Note that a Watchdog reset can occur with a

POR/LVR/BOR event, as discussed at the end of this sec-

tion.

0 = Not in suspend mode. Cleared by the hardware when

resuming from suspend.

Bit 2: Interrupt Enable Sense

This bit shows whether interrupts are enabled or disabled.

Firmware has no direct control over this bit as writing a zero

or one to this bit position will have no effect on interrupts.

This bit is further gated with the bit settings of the Global

Interrupt Enable Register (Figure 21-1) and USB Endpoint

Interrupt Enable Register (Figure 21-2). Instructions DI, EI,

and RETI manipulate the state of this bit.

1 = A Watchdog reset occurs.

0 = No Watchdog reset

Bit 5: Bus Interrupt Event

The Bus Reset Status is set whenever the event for the

USB Bus Reset or PS/2 Activity interrupt occurs. The event

type (USB or PS/2) is selected by the state of the USB-PS/2

Interrupt Mode bit in the USB Status and Control Register

(see Figure 13-1). The details on the event conditions that

set this bit are given in Section 21.3. In either mode, this bit

is set as soon as the event has lasted for 128–256 µs, and

the bit will be set even if the interrupt is not enabled. The bit

is only cleared by firmware or LVR/WDR.

1 = Interrupts are enabled.

0 = Interrupts are masked off.

Bit 1: Reserved. Must be written as a 0.

Bit 0: Run

This bit is manipulated by the HALT instruction. When Halt

is executed, the processor clears the run bit and halts at the

end of the current instruction. The processor remains halt-

ed until a reset occurs (low-voltage, brown-out, or Watch-

dog). This bit should normally be written as a ‘1’.

1 = A USB reset occurred or PS/2 Activity is detected, de-

pending on USB-PS/2 Interrupt Select bit.

0 = No event detected since last cleared by firmware or

LVR/WDR.

During power-up, or during a low-voltage reset, the Processor

Status and Control Register is set to 00010001, which

indicates a LVR/BOR (bit 4 set) has occurred and no interrupts

are pending (bit 7 clear). Note that during the t_STARTms partial

suspend at start-up (explained in Section 10.1), a Watchdog

Reset will also occur. When a WDR occurs during the

power-up suspend interval, firmware would read 01010001

from the Status and Control Register after power-up. Normally

the LVR/BOR bit should be cleared so that a subsequent WDR

can be clearly identified. Note that if a USB bus reset (long

SE0) is received before firmware examines this register, the

Bus Interrupt Event bit would also be set.

Bit 4: LVR/BOR Reset

The Low-voltage or Brown-out Reset is set to ‘1’ during a

power-on reset. Firmware can check bits 4 and 6 in the

reset handler to determine whether a reset was caused by

a LVR/BOR condition or a Watchdog timeout. This bit is not

affected by WDR. Note that a LVR/BOR event may be fol-

lowed by a Watchdog reset before firmware begins execut-

ing, as explained at the end of this section.

1 = A POR or LVR has occurred.

0 = No POR nor LVR since this bit last cleared.

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During a Watchdog Reset, the Processor Status and Control

Register is set to 01XX0001, which indicates a Watchdog

Reset (bit 4 set) has occurred and no interrupts are pending

(bit 7 clear).

interrupt can be detected by examining the IRQ Sense bit (Bit

7 in the Processor Status and Control Register).

21.1

Interrupt Vectors

The Interrupt Vectors supported by the device are listed in

Table 21-1. The highest priority interrupt is #1 (USB Bus Reset

/ PS/2 activity), and the lowest priority interrupt is #11

(Wake-up Timer). Although Reset is not an interrupt, the first

instruction executed after a reset is at ROM address 0x0000,

which corresponds to the first entry in the Interrupt Vector

Table. Interrupt vectors occupy two bytes to allow for a

two-byte JMP instruction to the appropriate Interrupt Service

Routine (ISR).

21.0

Interrupts

Interrupts can be generated by the GPIO lines, the internal

free-running timer, the SPI block, the capture timers, on

various USB events, PS/2 activity, or by the wake-up timer. All

interrupts are maskable by the Global Interrupt Enable

Register and the USB End Point Interrupt Enable Register.

Writing a ‘1’ to a bit position enables the interrupt associated

with that bit position. During a reset, the contents of the

interrupt enable registers are cleared, along with the Global

Interrupt enable bit of the CPU, effectively disabling all inter-

rupts.

Table 21-1. Interrupt Vector Assignments

Interrupt Vec-

tor Number

ROM

Address

Function

The interrupt controller contains a separate flip-flop for each

interrupt. See Figure 21-3 for the logic block diagram of the

interrupt controller. When an interrupt is generated it is first

registered as a pending interrupt. It will stay pending until it is

serviced or a reset occurs. A pending interrupt will only

generate an interrupt request if it is enabled by the corre-

sponding bit in the interrupt enable registers. The highest

priority interrupt request will be serviced following the

completion of the currently executing instruction.

not applicable

0x0000 Execution after Reset begins

here

1

0x0002 USB Bus Reset or PS/2 Activity

interrupt

2

3

0x0004 128-µs timer interrupt

0x0006 1.024-ms timer interrupt

0x0008 USB Endpoint 0 interrupt

0x000A USB Endpoint 1 interrupt

0x000C USB Endpoint 2 interrupt

0x000E SPI Interrupt

4

When servicing an interrupt, the hardware will first disable all

interrupts by clearing the Global Interrupt Enable bit in the

CPU (the state of this bit can be read at Bit 2 of the Processor

Status and Control Register). Next, the flip-flop of the current

interrupt is cleared. This is followed by an automatic CALL

instruction to the ROM address associated with the interrupt

being serviced (i.e., the Interrupt Vector, see Section 21.1).

The instruction in the interrupt table is typically a JMP

instruction to the address of the Interrupt Service Routine

(ISR). The user can re-enable interrupts in the interrupt service

routine by executing an EI instruction. Interrupts can be nested

to a level limited only by the available stack space.

5

6

7

8

0x0010 Capture Timer A interrupt

0x0012 Capture Timer B interrupt

0x0014 GPIO interrupt

9

10

11

0x0016 Wake-up Timer interrupt

The Program Counter value as well as the Carry and Zero

flags (CF, ZF) are stored onto the Program Stack by the

automatic CALL instruction generated as part of the interrupt

acknowledge process. The user firmware is responsible for

ensuring that the processor state is preserved and restored

during an interrupt. The PUSH A instruction should typically be

used as the first command in the ISR to save the accumulator

value and the POP A instruction should be used just before the

RETI instruction to restore the accumulator value. The

program counter, CF and ZF are restored and interrupts are

enabled when the RETI instruction is executed.

21.2

Interrupt Latency

Interrupt latency can be calculated from the following

equation:

Interrupt Latency = (Number of clock cycles remaining in the

current instruction)

+

(10 clock cycles for the CALL

instruction)

+ (5 clock cycles for the JMP instruction)

For example, if a 5 clock cycle instruction such as JC is being

executed when an interrupt occurs, the first instruction of the

Interrupt Service Routine will execute a minimum of 16 clocks

(1+10+5) or a maximum of 20 clocks (5+10+5) after the

interrupt is issued. With a 6-MHz external resonator, internal

CPU clock speed is 12 MHz, so 20 clocks take 20/12 MHz =

1.67 µs.

The DI and EI instructions can be used to disable and enable

interrupts, respectively. These instructions affect only the

Global Interrupt Enable bit of the CPU. If desired, EI can be

used to re-enable interrupts while inside an ISR, instead of

waiting for the RETI that exits the ISR. While the global

interrupt enable bit is cleared, the presence of a pending

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21.3

Interrupt Sources

The following sections provide details on the different types of

interrupt sources.

Bit #

7

6

5

4

3

2

1

0

Bit Name

Wake-up

Interrupt

Enable

GPIO

Interrupt

Enable

Capture

Timer B

Intr. Enable Intr. Enable

Capture

Timer A

SPI

Interrupt

Enable

1.024-ms

Interrupt

Enable

128-µs

Interrupt

Enable

USB Bus

Reset /

PS/2 Activity

Intr. Enable

Read/Write

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Figure 21-1. Global Interrupt Enable Register (Address 0x20)

Bit 7: Wake-up Interrupt Enable

edge of the selected GPIO pin(s). For each pin, rising and/or

falling edge capture interrupts can be in selected. Refer to

Section 19.0. These interrupts are independent of the GPIO

interrupt, described in the next section.

The internal wake-up timer is normally used to wake the

part from suspend mode, but it can also provide an interrupt

when the part is awake. The wake-up timer is cleared

whenever the Wake-up Interrupt Enable bit is written to a 0,

and runs whenever that bit is written to a 1. When the inter-

rupt is enabled, the wake-up timer provides periodic inter-

rupts at multiples of period, as described in Section 11.2.

1 = Enable

0 = Disable

Bit 3: SPI Interrupt Enable

1 = Enable wake-up timer for periodic wake-up.

0 = Disable and power-off wake-up timer.

The SPI interrupt occurs at the end of each SPI byte trans-

action, at the final clock edge, as shown in Figure 17-4. After

the interrupt, the received data byte can be read from the SPI

Data Register, and the TCMP control bit will be high

Bit 6: GPIO Interrupt Enable

Each GPIO pin can serve as an interrupt input. During a

reset, GPIO interrupts are disabled by clearing all GPIO

interrupt enable registers. Writing a ‘1’ to a GPIO Interrupt

Enable bit enables GPIO interrupts from the corresponding

input pin. These registers are shown in Figure 21-4 for Port

0 and Figure 21-5 for Port 1. In addition to enabling the

desired individual pins for interrupt, the main GPIO interrupt

must be enabled, as explained in Section 21.0.

1 = Enable

0 = Disable

Bit 2: 1.024-ms Interrupt Enable

The 1.024-ms interrupts are periodic timer interrupts from

the free-running timer (based on the 6-MHz clock). The

user should disable this interrupt before going into the sus-

pend mode to avoid possible conflicts between servicing

the timer interrupts (128-µs interrupt and 1.024-ms inter-

rupt) first or the suspend request first when waking up.

The polarity that triggers an interrupt is controlled indepen-

dently for each GPIO pin by the GPIO Interrupt Polarity

Registers. Setting a Polarity bit to ‘0’ allows an interrupt on

a falling GPIO edge, while setting a Polarity bit to ‘1’ allows

an interrupt on a rising GPIO edge. The Polarity Registers

reset to 0 and are shown in Figure 21-6 for Port 0 and

Figure 21-7 for Port 1.

1 = Enable. Periodic interrupts will be generated approxi-

mately every 1.024 ms.

0 = Disable.

Bit 1: 128-µs Interrupt Enable

All of the GPIO pins share a single interrupt vector, which

means the firmware will need to read the GPIO ports with

enabled interrupts to determine which pin or pins caused

an interrupt.The GPIO interrupt structure is illustrated in

Figure 21-8.

The 128-µs interrupt is another source of timer interrupt

from the free-running timer. The user should disable both

timer interrupts (128-µs and 1.024-ms) before going into

the suspend mode to avoid possible conflicts between ser-

vicing the timer interrupts first or the suspend request first

when waking up.

Note that if one port pin triggered an interrupt, no other port

pins can cause a GPIO interrupt until that port pin has re-

turned to its inactive (non-trigger) state or its corresponding

port interrupt enable bit is cleared. The CY7C637xxC does

not assign interrupt priority to different port pins and the

Port Interrupt Enable Registers are not affected by the in-

terrupt acknowledge process.

1 = Enable. Periodic interrupts will be generated approxi-

mately every 128 µs.

0 = Disable.

Bit 0: USB Bus Reset - PS/2 Interrupt Enable

1 = Enable

0 = Disable

The function of this interrupt is selectable between detec-

tion of either a USB bus reset condition, or PS/2 activity.

The selection is made with the USB-PS/2 Interrupt Mode

bit in the USB Status and Control Register (Figure 13-1). In

either case, the interrupt will occur if the selected condition

exists for 256 µs, and may occur as early as 128 µs.

Bit [5:4]: Capture Timer A and B Interrupts

There are two capture timer interrupts, one for each

associated pin. Each of these interrupts occurs on an enabled

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CY7C63743C

A USB bus reset is indicated by a single ended zero (SE0)

on the USB D+ and D– pins. The USB Bus Reset interrupt

occurs when the SE0 condition ends. PS/2 activity is indi-

cated by a continuous LOW on the SDATA pin. The PS/2

interrupt occurs as soon as the long LOW state is detected.

terrupt is generated regardless of data packet validity

(i.e., good CRC). Firmware must check for data validity.

• The device SIE sends a NAK or STALL handshake pack-

et to the USB host during the host attempts to read data

from the endpoint (INs).

• The device receives an ACK handshake after a success-

ful read transaction (IN) from the host.

• The device SIE sends a NAK or STALL handshake pack-

et to the USB host during the host attempts to write data

(OUTs) to the endpoint FIFO.

During the entire interval of a USB Bus Reset or PS/2 inter-

rupt event, the USB Device Address register is cleared.

The Bus Reset/PS/2 interrupt may occur 128 µs after the

bus condition is removed.

1 = Enable

0 = Disable

1 = Enable

0 = Disable

Refer to Table 22-1 for more information.

Bit #

7 6 5 4 3

Reserved

2

1

0

Bit 0: EP0 Interrupt Enable

Bit Name

EP2

EP1

EP0

If enabled, a control endpoint interrupt is generated when:

• The endpoint 0 mode is set to accept a SETUP token.

• After the SIE sends a 0-byte packet in the status stage

of a control transfer.

• The USB host writes valid data to an endpoint FIFO.

However, if the endpoint is in ACK OUT modes, an in-

terrupt is generated regardless of what data is received.

Firmware must check for data validity.

Interrupt Interrupt Interrupt

Enable

R/W

0

Enable

R/W

0

Enable

R/W

0

Read/Write

Reset

-

0 0 0 0 0

Figure 21-2. Endpoint Interrupt Enable Register

(Address 0x21)

• The device SIE sends a NAK or STALL handshake pack-

et to the USB host during the host attempts to read data

from the endpoint (INs).

Bit [7:3]: Reserved.

Bit [2:1]: EP2,1 Interrupt Enable

• The device SIE sends a NAK or STALL handshake pack-

et to the USB host during the host attempts to write data

(OUTs) to the endpoint FIFO.

There are two non-control endpoint (EP2 and EP1) inter-

rupts. If enabled, a non-control endpoint interrupt is gener-

ated when:

1 = Enable EP0 interrupt

0 = Disable EP0 interrupt

• The USB host writes valid data to an endpoint FIFO.

However, if the endpoint is in ACK OUT modes, an in-

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USB-PS/2 Clear

USB-PS/2 IRQ

Interrupt

Vector

CLR

To CPU

Q

1

D

Enable [0]

(Reg 0x20)

128-µs CLR

128-µs IRQ

USB-

PS/2

Int

IRQ Pending

(Bit 7, Reg 0xFF)

CPU

CLK

1-ms CLR

1-ms IRQ

IRQout

IRQ

EP0 CLR

EP0 IRQ

EP1 CLR

EP1 IRQ

CLR

EP2 CLR

EP2 IRQ

Q

Global

Interrupt

Enable

Bit

1

D

Int Enable

Sense

Enable [2]

(Reg 0x21)

SPI CLR

SPI IRQ

(Bit 2, Reg 0xFF)

EP2

Int

CLK

Capture A CLR

Capture A IRQ

Controlled by DI, EI, and

RETI Instructions

CLR

Capture B CLR

Capture B IRQ

Interrupt

Acknowledge

GPIO CLR

GPIO IRQ

Wake-up CLR

Wake-up IRQ

CLR

Q

1

D

Enable [7]

(Reg 0x20)

Wake-up

Int

CLK

Interrupt

Priority

Encoder

Figure 21-3. Interrupt Controller Logic Block Diagram

0 = Disables GPIO interrupts from the corresponding input

pin.

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

P0 Interrupt Enable

The polarity that triggers an interrupt is controlled indepen-

dently for each GPIO pin by the GPIO Interrupt Polarity

Registers. Figure 21-6 and Figure 21-7 control the interrupt

polarity of each GPIO pin.

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

Figure 21-4. Port 0 Interrupt Enable Register (Address

0x04)

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Bit [7:0]: P0 [7:0] Interrupt Enable

P0 Interrupt Polarity

1 = Enables GPIO interrupts from the corresponding input

pin.

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

0 = Disables GPIO interrupts from the corresponding input

pin.

Figure 21-6. Port 0 Interrupt Polarity Register

(Address 0x06)

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

Bit [7:0]: P0[7:0] Interrupt Polarity

1 = Rising GPIO edge

P1 Interrupt Enable

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

0 = Falling GPIO edge

Bit #

Bit Name

Read/Write

Reset

7

6

5

4

3

2

1

0

P1 Interrupt Polarity

Figure 21-5. Port 1 Interrupt Enable Register

(Address 0x05)

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

Bit [7:0]: P1 [7:0] Interrupt Enable

1 = Enables GPIO interrupts from the corresponding input

pin.

Figure 21-7. Port 1 Interrupt Polarity Register

(Address 0x07)

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Bit [7:0]: P1[7:0] Interrupt Polarity

1 = Rising GPIO edge

0 = Falling GPIO edge

GPIO Interrupt

Flip Flop

Port Bit Interrupt

Polarity Register

OR Gate

(1 input per

GPIO pin)

IRQout

Interrupt

Priority

1

D

Q

M

U

X

Interrupt

Vector

Encoder

GPIO

CLR

Port Bit Interrupt

Enable Register

1 = Enable

0 = Disable

IRA

Global

GPIO Interrupt

Enable

1 = Enable

0 = Disable

(Bit 6, Register 0x20)

Figure 21-8. GPIO Interrupt Diagram

22.0

USB Mode Tables

The following tables give details on mode setting for the USB

Serial Interface Engine (SIE) for both the control endpoint

(EP0) and non-control endpoints (EP1 and EP2).

Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints

Mode

Disable

NAK IN/OUT

Encoding

0000

SETUP

Ignore

Accept

IN

Ignore

NAK

OUT

Comments

Ignore Ignore all USB traffic to this endpoint

NAK

0001

On Control endpoint, after successfully sending an ACK

handshake to a SETUP packet, the SIE forces the

endpoint mode (from modes other than 0000) to 0001.

The mode is also changed by the SIE to 0001 from mode

1011 on issuance of ACK handshake to an OUT.

Status OUT Only

STALL IN/OUT

Ignore IN/OUT

Reserved

Status IN Only

Reserved

0010

0011

0100

0101

0110

0111

1000

Accept

Ignore

STALL

Ignore

Check For Control endpoints

STALL For Control endpoints

Ignore For Control endpoints

Always Reserved

Accept TX 0 Byte STALL For Control Endpoints

Ignore TX Count Ignore Reserved

Ignore

NAK OUT

Ignore

NAK

In mode 1001, after sending an ACK handshake to an

OUT, the SIE changes the mode to 1000

[3]

ACK OUT(STALL =0)

Ignore

ACK

This mode is changed by the SIE to mode 1000 on

1001

[3]

ACK OUT(STALL =1)

STALL issuance of ACK handshake to an OUT

NAK OUT - Status IN

ACK OUT - NAK IN

1010

1011

Accept TX 0 Byte

NAK

ACK

Accept

NAK

This mode is changed by the SIE to mode 0001 on

issuance of ACK handshake to an OUT

NAK IN

ACK IN(STALL =0)

ACK IN(STALL =1)

1100

Ignore

NAK

Ignore An ACK from mode 1101 changes the mode to 1100

[3]

Ignore TX Count Ignore This mode is changed by the SIE to mode 1100 on

Ignore

1101

[3]

STALL

Ignore issuance of ACK handshake to an IN

NAK IN - Status OUT

ACK IN - Status OUT

1110

1111

Accept

NAK

Check An ACK from mode 1111 changes the mode to 1110

Accept TX Count Check This mode is changed by the SIE to mode 1110 on

issuance of ACK handshake to an IN

Note:

3. STALL bit is the bit 7 of the USB Non-Control Device Endpoint Mode registers. Refer to Section 14.3 for more explanation.

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Mode Column:

[3:0] of the Endpoint Count Register (Figure 14-4) in response

to any IN token.

The 'Mode' column contains the mnemonic names given to the

modes of the endpoint. The mode of the endpoint is deter-

mined by the four-bit binaries in the 'Encoding' column as

discussed below. The Status IN and Status OUT modes

represent the status IN or OUT stage of the control transfer.

A 'TX 0 Byte' entry in the IN column means that the SIE will

transmit a zero byte packet in response to any IN sent to the

endpoint. Sending a 0 byte packet is to complete the status

stage of a control transfer.

An 'Ignore' means that the device sends no handshake tokens.

Encoding Column:

An 'Accept' means that the SIE will respond with an ACK to a

valid SETUP transaction.

The contents of the 'Encoding' column represent the Mode Bits

[3:0] of the Endpoint Mode Registers (Figure 14-2 and

Figure 14-3). The endpoint modes determine how the SIE

responds to different tokens that the host sends to the

endpoints. For example, if the Mode Bits [3:0] of the Endpoint

0 Mode Register (Figure 14-2) are set to '0001', which is NAK

IN/OUT mode as shown in Table 22-1 above, the SIE of the

part will send an ACK handshake in response to SETUP

tokens and NAK any IN or OUT tokens. For more information

on the functionality of the Serial Interface Engine (SIE), see

Section 13.0.

Comments Column:

Some Mode Bits are automatically changed by the SIE in

response to many USB transactions. For example, if the Mode

Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode

as shown in Table 22-1, the SIE will change the endpoint Mode

Bits [3:0] to NAK IN-Status OUT mode (1110) after ACKing a

valid status stage OUT token. The firmware needs to update

the mode for the SIE to respond appropriately. See Table 22-1

for more details on what modes will be changed by the SIE.

SETUP, IN, and OUT Columns:

Any SETUP packet to an enabled endpoint with mode set to

accept SETUPs will be changed by the SIE to 0001 (NAKing).

Any mode set to accept a SETUP will send an ACK handshake

to a valid SETUP token.

Depending on the mode specified in the 'Encoding' column,

the 'SETUP', 'IN', and 'OUT' columns contain the device SIE's

responses when the endpoint receives SETUP, IN, and OUT

tokens respectively.

A disabled endpoint will remain disabled until changed by

firmware, and all endpoints reset to the Disabled mode (0000).

Firmware normally enables the endpoint mode after a SetCon-

figuration request.

A 'Check' in the Out column means that upon receiving an

OUT token the SIE checks to see whether the OUT is of zero

length and has a Data Toggle (Data1/0) of 1. If these condi-

tions are true, the SIE responds with an ACK. If any of the

above conditions is not met, the SIE will respond with either a

STALL or Ignore. Table 22-3 gives a detailed analysis of all

possible cases.

The control endpoint has three status bits for identifying the

token type received (SETUP, IN, or OUT), but the endpoint

must be placed in the correct mode to function as such.

Non-control endpoints should not be placed into modes that

accept SETUPs.

A 'TX Count' entry in the IN column means that the SIE will

transmit the number of bytes specified in the Byte Count Bit

Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions”

Endpoint Mode

Encoding

Properties of incoming Changes to the internal register made by the SIE as a result of

Interrupt?

packet

the incoming token

End Point

Mode

3

2

1

0

Token count

buffer

dval

DTOG

DVAL

COUNT

Setup

In

Out

ACK

3

2

1

0

Response Int

SIE’s Response

Bit[3:0], Figure 14-4

Data Valid (Bit 6, Figure 14-4)

Data 0/1 (Bit 7, Figure 14-4)

The validity of the received data

The quality status of the DMA buffer

The number of received bytes

Endpoint Mode changed

by the SIE.

Acknowledgetransactioncompleted

(Bit4,Figure 14-2/3)

Received Token

(SETUP, IN,OUT)

PID Status Bits

(Bit[7:5], Figure 14-2)

Legend:

UC: unchanged

x: don’t care

TX: transmit

RX: receive

TX0: transmit 0-length packet

available for Control endpoint only

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The response of the SIE can be summarized as follows:

6. The SETUP PID status is updated at the beginning of the

Data packet phase.

1. The SIE will only respond to valid transactions, and will ig-

nore non-valid ones.

7. The entire Endpoint 0 mode register and the Count register

are locked to CPU writes at the end of any transaction to

that endpoint in which an ACK is transferred. These

registers are only unlocked by a CPU read of these

registers, and only if that read happens after the transaction

completes. This represents about a 1-µs window in which

the CPU is locked from register writes to these USB

registers. Normally the firmware should perform a register

read at the beginning of the Endpoint ISRs to unlock and

get the mode register information. The interlock on the

Mode and Count registers ensures that the firmware

recognizes the changes that the SIE might have made

during the previous transaction.

2. The SIE will generate an interrupt when a valid transaction

is completed or when the FIFO is corrupted. FIFO

corruption occurs during an OUT or SETUP transaction to

a valid internal address, that ends with a non-valid CRC.

3. An incoming Data packet is valid if the count is < Endpoint

Size + 2 (includes CRC) and passes all error checking;

4. An IN will be ignored by an OUT configured endpoint and

visa versa.

5. The IN and OUT PID status is updated at the end of a

transaction.

Table 22-3. Details of Modes for Differing Traffic Conditions

End Point Mode

PID

Set End Point Mode

Rcved

3

2

1

0

Token

Count Buffer

Dval

DTOG

DVAL

1

COUNT SETUP IN

OUT

ACK

3

2

1

0

Response

Int

SETUP Packet (if accepting)

See22-1

See 22-1

Disabled

SETUP

<= 10 data

valid

x

updates

1

UC

1

0

1

ACK

yes

> 10

x

junk

updates updates

UC

NoChange Ignore

invalid

0

updates

UC

0

x

UC

x

UC

NoChange Ignore

no

NAK IN/OUT

0

1

OUT

IN

x

UC

x

UC

1

UC

NoChange NAK

NoChange Ignore

NoChange NAK

yes

no

> 10

x

UC

x

invalid

x

no

yes

Ignore IN/OUT

0

1

0

OUT

IN

x

UC

x

UC

NoChange Ignore

no

STALL IN/OUT

0

1

OUT

IN

x

UC

x

UC

1

UC

NoChange STALL

NoChange Ignore

NoChange STALL

yes

no

> 10

x

UC

x

invalid

x

no

yes

Control Write

ACK OUT/NAK IN

1

0

1

OUT

IN

<= 10 data

valid

updates

UC

1

updates UC

UC

1

0

1

ACK

yes

> 10

junk

UC

x

updates updates UC

1

UC

NoChange Ignore

NoChange NAK

x

invalid

x

0

updates UC

1

UC

NAK OUT/Status IN

1

0

1

0

OUT

IN

<= 10 UC

valid

UC

1

UC

1

NoChange NAK

yes

no

> 10

UC

x

UC

NoChange Ignore

NoChange TX 0 Byte

x

invalid

x

no

yes

Status IN Only

0

1

0

OUT

IN

<= 10 UC

valid

UC

1

UC

1

0

1

STALL

yes

no

> 10

UC

x

UC

NoChange Ignore

NoChange TX 0 Byte

x

invalid

x

no

yes

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Table 22-3. Details of Modes for Differing Traffic Conditions (continued)

Control Read

ACK IN/Status OUT

1

OUT

IN

2

UC

valid

x

1

updates UC

UC

1

NoChange ACK

yes

2

0

1

UC

1

0

1

STALL

yes

no

!=2

> 10

x

updates

UC

1

UC

NoChange Ignore

invalid

x

UC

no

x

UC

1

0

ACK (back)

yes

NAK IN/Status OUT

1

3

1

2

1

0

OUT

token

OUT

IN

2

UC

valid

dval

valid

x

1

updates UC

UC

1

NoChange ACK

yes

int

2

UC

0

1

UC

ACK

UC

0

3

0

2

0

1

0

1

STALL

count

!=2

> 10

x

buffer

UC

DTOG

updates

UC

DVAL

1

COUNT SETUP IN

updates UC UC

OUT

1

response

STALL

yes

no

UC

1

UC

NoChange Ignore

NoChange NAK

UC

invalid

x

UC

no

x

UC

yes

Status OUT Only

0

1

0

OUT

IN

2

UC

valid

x

1

updates UC

UC

1

NoChange ACK

yes

no

2

0

1

UC

0

1

STALL

!=2

> 10

x

updates

UC

1

UC

NoChange Ignore

invalid

x

UC

no

x

UC

0

1

STALL

yes

OUT Endpoint

ACK OUT, STALL Bit = 0 (Figure 14-3)

1

0

1

OUT

IN

<= 10 data

valid

updates

UC

1

updates UC

UC

1

0

ACK

yes

no

> 10

junk

UC

x

updates updates UC

1

UC

NoChange Ignore

x

invalid

x

0

updates UC

1

UC

ACK OUT, STALL Bit = 1 (Figure 14-3)

1

0

1

OUT

IN

<= 10 UC

valid

UC

1

UC

NoChange STALL

NoChange Ignore

yes

no

> 10

UC

x

UC

x

invalid

x

no

NAK OUT

1

0

OUT

IN

<= 10 UC

valid

UC

1

UC

NoChange NAK

NoChange Ignore

yes

no

> 10

UC

x

UC

x

invalid

x

no

Reserved

0

1

0

1

OUT

IN

x

updates updates

updates

UC

updates updates UC

UC

1

NoChange RX

yes

no

UC

x

UC

NoChange Ignore

IN Endpoint

ACK IN, STALL Bit = 0 (Figure 14-3)

1

0

1

OUT

IN

x

UC

x

UC

1

UC

1

NoChange Ignore

no

1

0

ACK (back)

yes

ACK IN, STALL Bit = 1 (Figure 14-3)

1

0

1

OUT

IN

x

UC

x

UC

1

UC

NoChange Ignore

NoChange STALL

no

yes

NAK IN

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Table 22-3. Details of Modes for Differing Traffic Conditions (continued)

1

0

OUT

IN

x

UC

x

UC

1

UC

NoChange Ignore

NoChange NAK

no

yes

Reserved

0

1

Out

IN

x

UC

x

UC

1

UC

NoChange Ignore

NoChange TX

no

yes

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23.0

Register Summary

Read/Write/

Both/

Default/

Reset

Address

Register Name

Port 0 Data

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00

0x01

0x02

P0

P1

BBBBBBBB

--RR--RR

00000000

Port 1 Data

Port 2 Data

Reserved

D+(SCLK) D- (SDATA)

State State

Reserved

P2.1 (Int Clk VREG Pin

Mode Only

State

0x0A

0x0B

0x0C

0x0D

0x04

0x05

0x06

0x07

GPIO Port 0 Mode 0

GPIO Port 0 Mode 1

GPIO Port 1 Mode 0

GPIO Port 1 Mode 1

Port 0 Interrupt Enable

Port 1 Interrupt Enable

Port 0 Interrupt Polarity

Port 1 Interrupt Polarity

P0[7:0] Mode0

P0[7:0] Mode1

P1[7:0] Mode0

P1[7:0] Mode1

WWWWWWWW 00000000

P0[7:0] Interrupt Enable

P1[7:0] Interrupt Enable

P0[7:0] Interrupt Polarity

P1[7:0] Interrupt Polarity

0xF8

Clock Configuration

Ext. Clock

Resume

Delay

Wake-up Timer Adjust Bit [2:0]

Low-voltage

Reset

Disable

Precision

USB

Clocking

Enable

Internal

Clock

Output

Disable

External

Oscillator

Enable

BBBBBBBB

00000000

0x10

0x12

USB Device Address

Device

Address

Enable

Device Address

BBBBBBBB

00000000

EP0 Mode

SETUP

Received

IN

OUT

ACKed

Mode Bit

BBBBBBBB

B--BBBBB

BB--BBBB

00000000

Received

Transaction

0x14,

0x16

EP1, EP2 Mode Register

EP0,1, and 2 Counter

STALL

Reserved

ACKed

Transaction

Mode Bit

0x11,

0x13,and

0x15

Data 0/1

Toggle

Data Valid

Reserved

Byte Count

0x1F

USB Status and Control

PS/2Pull-up

Enable

VREG

Enable

USB

Reset-PS/2

Activity

Interrupt

Mode

Reserved

USB Bus

Activity

D+/D- Forcing Bit

BBB-BBBB

00000000

0x20

0x21

Global Interrupt Enable

Wake-up

Interrupt

Enable

GPIO

Interrupt

Enable

Capture

SPI

Interrupt

Enable

1.024 ms

Interrupt

Enable

128 µs

Interrupt

Enable

USB Bus

Reset-PS/2

Activity Intr.

Enable

BBBBBBBB

-----BBB

00000000

Timer B Intr. Timer A Intr.

Enable

Endpoint Interrupt Enable

Reserved

EP2

Interrupt

Enable

EP1

Interrupt

Enable

EP0

Interrupt

Enable

0x24

0x25

Timer LSB

Timer Bit [7:0]

RRRRRRRR

----RRRR

00000000

Timer (MSB)

Reserved

Timer Bit [11:8]

0x60

0x61

SPI Data

Data I/O

BBBBBBBB

00000000

SPI Control

TCMP

TBF

Comm Mode [1:0]

CPOL

CPHA

SCK Select

0x40

0x41

0x42

0x43

0x44

Capture Timer A-Rising,

Data Register

Capture A Rising Data

Capture A Falling Data

Capture B Rising Data

Capture B Falling Data

RRRRRRRR

BBBBBBBB

00000000

Capture Timer A-Falling,

Data Register

Capture Timer B-Rising,

Data Register

Capture Timer B-Falling,

Data Register

Capture Timer

Configuration

First Edge

Hold

Prescale Bit [2:0]

Capture B

Falling Intr

Enable

Capture B

Rising Intr

Enable

Capture A

Falling Intr

Enable

Capture A

Rising Intr

Enable

0x45

0xFF

Capture Timer Status

Reserved

Capture B

Falling

Capture B

Capture A

Falling

Capture A

----BBBB

00000000

Rising Event

Event

Process Status & Control

IRQ

Pending

Watch Dog

Reset

Bus

LVR/BOR

Reset

Suspend

Interrupt

Enable

Sense

Reserved

Run

RBBBBR-B

See

Section

20.0

Interrupt

Event

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24.0

Absolute Maximum Ratings

Storage Temperature ..........................................................................................................................................–65°C to +150°C

Ambient Temperature with Power Applied...............................................................................................................–0°C to +70°C

Supply Voltage on V_CCRelative to V_SS..................................................................................................................–0.5V to +7.0V

DC Input Voltage........................................................................................................................................... –0.5V to +V_CC+0.5V

DC Voltage Applied to Outputs in High Z State............................................................................................ –0.5V to + V_CC+0.5V

Maximum Total Sink Output Current into Port 0 and 1 and Pins.......................................................................................... 70 mA

Maximum Total Source Output Current into Port 0 and 1 and Pins ..................................................................................... 30 mA

Maximum On-chip Power Dissipation on any GPIO Pin......................................................................................................50 mW

Power Dissipation ..............................................................................................................................................................300 mW

Static Discharge Voltage .................................................................................................................................................. >2000V

Latch-up Current ........................................................................................................................................................... > 200 mA

25.0

DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70°C

Parameter

General

Conditions

Min.

Max.

Unit

V_CC1

V_CC2

I_CC1

Operating Voltage

Note 4

V_LVR

4.35

5.5

5.25

20

V

Operating Voltage

V_CCOperating Supply Current – Internal

Oscillator Mode

V_CC= 5.5V, no GPIO loading

mA

Typical I_CC1= 16 mA^[5]

V_CC= 5.0V. T = Room Temperature

I_CC2

V_CCOperating Supply Current – External V_CC= 5.5V, no GPIO loading

Oscillator Mode

17

mA

Typical I_CC2= 13 mA^[5]

V_CC= 5.0V. T = Room Temperature

I_SB1

I_SB2

V_PP

Standby Current – No Wake-up Osc

Standby Current – With Wake-up Osc

Programming Voltage (disabled)

Resonator Start-up Interval

Input Leakage Current

Oscillator off, D– > 2.7V

25

75

0.4

256

1

µA

V

Oscillator off, D– > 2.7V

–0.4

T_RSNTR

I_IL

I_SNK

I_SRC

V_CC= 5.0V, ceramic resonator

Any I/O pin

Cumulative across all ports^[6]

µs

µA

mA

Max I_SSGPIO Sink Current

Max I_CCGPIO Source Current

70

30

Low-Voltage and Power-on Reset

Low-Voltage Reset Trip Voltage

V_CCPower-on Slew Time

V_LVR

V_CCbelow V_LVRfor >100 ns^[7]

linear ramp: 0 to 4V^[8]

3.5

4.0

V

t_VCCS

100

ms

USB Interface

VREG Regulator Output Voltage

Capacitance on VREG Pin

Static Output High, driven

[9, 10]

V_REG

C_REG

Load = R_PU+R_PD

3.0

2.8

3.6

300

3.6

V

pF

V

External cap not required

R_PDto Gnd^[4]

V_OHU

Notes:

4. Full functionality is guaranteed in V

range, except USB transmitter specifications and GPIO output currents are guaranteed for V

range.

CC1

CC2

5. Bench measurements taken under nominal operating conditions. Spec cannot be guaranteed at final test.

6. Total current cumulative across all Port pins, limited to minimize Power and Ground-Drop noise effects.

7. LVR is automatically disabled during suspend mode.

8. LVR will re-occur whenever V drops below V

. In suspend or with LVR disabled, BOR occurs whenever V drops below approximately 2.5V.

CC

LVR

CC

9.

V

specified for regulator enabled, idle conditions (i.e., no USB traffic), with load resistors listed. During USB transmits from the internal SIE, the VREG

REG

output is not regulated, and should not be used as a general source of regulated voltage in that case. During receive of USB data, the VREG output drops

when D– is LOW due to internal series resistance of approximately 200Ω at the VREG pin.

10. In suspend mode, V

is only valid if R is connected from D– to VREG pin, and R is connected from D– to ground.

REG

PU PD

Document #: 38-08022 Rev. *C

Page 38 of 49

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DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70°C (continued)

Parameter

Static Output Low

Conditions

With R_PUto VREG pin

Min.

Max.

0.3

Unit

V

V_OLU

V_OHZ

Static Output High, idle or suspend

R_PDconnected D– to Gnd, R_PU

connected D– to VREG pin^[4]

2.7

3.6

V

V_DI

Differential Input Sensitivity

|(D+)–(D–)|

0.2

0.8

V

V_CM

V_SE

C_IN

I_LO

Differential Input Common Mode Range

Single Ended Receiver Threshold

Transceiver Capacitance

2.5

2.0

V

20

pF

µA

kΩ

Hi-Z State Data Line Leakage

External Bus Pull-up resistance (D–)

External Bus Pull-down resistance

0 V < V_in<3.3 V (D+ or D– pins)

–10

10

[11]

R_PU

R_PD

1.3 kΩ ±2% to V_REG

1.274

14.25

1.326

15.75

15 kΩ ±5% to Gnd

PS/2 Interface

Static Output Low

V_OLP

R_PS2

Isink = 5 mA, SDATA or SCLK pins

SDATA, SCLK pins, PS/2 Enabled

0.4

7

V

Internal PS/2 Pull-up Resistance

3

kΩ

General Purpose I/O Interface

Pull-up Resistance

R_UP

V_ICR

V_ICF

V_HC

V_ITTL

8

24

kΩ

V_CC

V

Input Threshold Voltage, CMOS mode

Input Hysteresis Voltage, CMOS mode

Input Threshold Voltage, TTL mode

Output Low Voltage, high drive mode

Low to high edge, Port 0 or 1

High to low edge, Port 0 or 1

Ports 0, 1, and 2

40%

35%

3%

60%

55%

10%

2.0

0.8

V_OL1A

V_OL1B

I_OL1= 50 mA, Ports 0 or 1^[4]

0.8

0.4

V

I_OL1= 25 mA, Ports 0 or 1^[4]

V_OL2

V_OL3

V_OH

Output Low Voltage, medium drive mode

Output Low Voltage, low drive mode

Output High Voltage, strong drive mode

Pull-down resistance, XTALIN pin

I_OL2= 8 mA, Ports 0 or 1^[4]

I_OL3= 2 mA, Ports 0 or 1^[4]

Port 0 or 1, I_OH= 2 mA^[4]

Internal Clock Mode only

0.4

V

V_CC–2

50

V

R_XIN

kΩ

Note:

11. The 200Ω internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately, a 1.5 kΩ,5%pull-up from D– to an external 3.3V supply

can be used.

Document #: 38-08022 Rev. *C

Page 39 of 49

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Switching Characteristics

Parameter

Description

Internal Clock Mode

Internal Clock Frequency

Conditions

Min.

Max.

Unit

F_ICLK

Internal Clock Mode enabled

5.7

6.3

MHz

F_ICLK2

Internal Clock Frequency, USB

mode

Internal Clock Mode enabled, Bit 2 of register

0xF8h is set (Precision USB Clocking)^[12]

5.91

6.09

External Oscillator Mode

T_CYC

Input Clock Cycle Time

USB Operation, with External ±1.5%

Ceramic Resonator or Crystal

164.2

169.2

ns

T_CH

T_CL

Clock HIGH Time

0.45 t_CYC

ns

Clock LOW Time

Reset Timing

t_START

t_WAKE

t_WATCH

Time-out Delay after LVR/BOR

Internal Wake-up Period

WatchDog Timer Period

24

1

60

5

ms

Enabled Wake-up Interrupt^[13]

F_OSC= 6 MHz

10.1

14.6

USB Driver Characteristics

Transition Rise Time

T_R

CLoad = 200 pF (10% to 90%^[4]

CLoad = 600 pF (10% to 90%^[4]

CLoad = 200 pF (10% to 90%^[4]

CLoad = 600 pF (10% to 90%^[4]

t_r/t_f^{[4, 14]}

)

75

ns

%

V

T_R

Transition Rise Time

300

T_F

Transition Fall Time

T_F

Transition Fall Time

300

125

2.0

T_RFM

V_CRS

Rise/Fall Time Matching

80

Output Signal Crossover

Voltage^[18]

CLoad = 200 to 600 pF^[4]

1.3

USB Data Timing

Low Speed Data Rate

T_DRATE

T_DJR1

T_DJR2

T_DEOP

T_EOPR2

T_EOPT

T_UDJ1

T_UDJ2

T_LST

Ave. Bit Rate (1.5 Mb/s ±1.5%)

To Next Transition^[15]

For Paired Transitions^[15]

1.4775

–75

1.5225

75

Mb/s

ns

Receiver Data Jitter Tolerance

–45

45

ns

Differential to EOP transition Skew Note 15

–40

100

ns

EOP Width at Receiver

Source EOP Width

Accepts as EOP^[15]

670

ns

1.25

–95

1.50

95

µs

ns

Differential Driver Jitter

Width of SE0 during Diff. Transition

To next transition, Figure 26-5

To paired transition, Figure 26-5

–150

150

210

ns

Non-USB Mode Driver

Characteristics

Note 16

T_FPS2

SDATA/SCK Transition Fall Time CLoad = 150 pF to 600 pF

50

300

ns

SPI Timing

SPI Master Clock Rate

SPI Slave Clock Rate

See Figures 26-6 to 26-9^[17]

F_CLK/3; see Figure 17-1

T_SMCK

T_SSCK

2

MHz

2.2

Notes:

12. Initially F

= F

until a USB packet is received.

ICLK

ICLK2

13. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)

14. Tested at 200 pF.

15. Measured at cross-over point of differential data signals.

16. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.

17. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).

18. Per the USB 2.0 Specification, Table 7.7, Note 10, the first transition from the Idle state is excluded.

Document #: 38-08022 Rev. *C

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Switching Characteristics (continued)

Parameter

T_SCKH

Description

SPI Clock High Time

SPI Clock Low Time

Conditions

High for CPOL = 0, Low for CPOL = 1

Low for CPOL = 0, High for CPOL = 1

SCK to data valid

Min.

125

–25

100

Max.

Unit

ns

T_SCKL

ns

T_MDO

Master Data Output Time

50

ns

T_MDO1

Master Data Output Time,

First bit with CPHA = 1

Time before leading SCK edge

ns

T_MSU

T_MHD

T_SSU

T_SHD

T_SDO

T_SDO1

Master Input Data Set-up time

Master Input Data Hold time

Slave Input Data Set-up Time

Slave Input Data Hold Time

Slave Data Output Time

50

ns

SCK to data valid

100

Slave Data Output Time,

First bit with CPHA = 1

Time after SS LOW to data valid

T_SSS

T_SSH

Slave Select Set-up Time

Slave Select Hold Time

Before first SCK edge

After last SCK edge

150

ns

T_CYC

T_CH

CLOCK

T_CL

Figure 26-1. Clock Timing

T_F

T_R

D+

V_oh

90%

V_crs

10%

V_ol

10%

D−

Figure 26-2. USB Data Signal Timing

Document #: 38-08022 Rev. *C

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T_PERIOD

Differential

Data Lines

T_JR

T_JR1

T_JR2

Consecutive

Transitions

N * T_PERIOD+ T_JR1

Paired

Transitions

N * T_PERIOD+ T_JR2

Figure 26-3. Receiver Jitter Tolerance

T_PERIOD

Crossover

Point Extended

Crossover

Point

Differential

Data Lines

Diff. Data to

SE0 Skew

N * T_PERIOD+ T_DEOP

Source EOP Width: T_EOPT

Receiver EOP Width: T_EOPR1, T_EOPR2

Figure 26-4. Differential to EOP Transition Skew and EOP Width

T_PERIOD

Crossover

Points

Differential

Data Lines

Consecutive

Transitions

N * T_PERIOD+ T_xJR1

Paired

Transitions

N * T_PERIOD+ T_xJR2

Figure 26-5. Differential Data Jitter

Document #: 38-08022 Rev. *C

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SS

T_SCKL

SCK (CPOL=0)

T_SCKH

SCK (CPOL=1)

MOSI

T_MDO

MSB

LSB

MSB

LSB

MISO

T_MSUT_MHD

Figure 26-6. SPI Master Timing, CPHA = 0

SS

T_SSS

T_SSH

T_SCKL

SCK (CPOL=0)

T_SCKH

SCK (CPOL=1)

MOSI

MSB

LSB

T_SSUT_SHD

MSB

T_SDO

LSB

MISO

Figure 26-7. SPI Slave Timing, CPHA = 0

Document #: 38-08022 Rev. *C

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(SS is under firmware control in SPI Master mode)

SS

T_SCKL

SCK (CPOL=0)

SCK (CPOL=1)

T_SCKH

T_MDO

T_MDO1

MSB

LSB

MOSI

MISO

MSB

LSB

T_MSUT_MHD

Figure 26-8. SPI Master Timing, CPHA = 1

SS

T_SSH

T_SSS

T_SCKL

SCK (CPOL=0)

T_SCKH

SCK (CPOL=1)

MOSI

MSB

LSB

T_SSUT_SHD

T_SDO

T_SDO1

MISO

MSB

LSB

Figure 26-9. SPI Slave Timing, CPHA = 1

Document #: 38-08022 Rev. *C

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Ordering Information

Ordering Code

EPROM

Size

Package

Name

Package Type

Operating

Range

CY7C63723C-PXC

CY7C63723C-SXC

CY7C63743C-PXC

CY7C63743C-SXC

CY7C63743C-QXC

CY7C63722C-XC

8 KB

P3

S3

18-Pin (300-Mil) Lead-free PDIP

18-Pin Small Outline Lead-free Package

24-Pin (300-Mil) Lead-free PDIP

24-Pin Small Outline Lead-free Package

24-lead QSOP Lead-free Package

25-Pad DIE Form

Commercial

P13

S13

Q13

–

28.0

Package Diagrams

18-Lead (300-Mil) Molded DIP P3

51-85010-*A

18 Lead (300 Mil) SOIC - S3

18-Lead (300-Mil) Molded SOIC S3

PIN 1 ID

9

1

MIN.

MAX.

DIMENSIONS IN INCHES[MM]

REFERENCE JEDEC MO-119

0.291[7.391]

0.300[7.620]

*

0.394[10.007]

0.419[10.642]

PART #

10

18

S18.3 STANDARD PKG.

SZ18.3 LEAD FREE PKG.

0.026[0.660]

0.032[0.812]

SEATING PLANE

0.447[11.353]

0.463[11.760]

0.092[2.336]

0.105[2.667]

*

0.004[0.101]

51-85023-A

0.0091[0.231]

0.0125[0.317]

*

0.050[1.270]

TYP.

0.004[0.101]

0.0118[0.299]

0.015[0.381]

0.050[1.270]

0.013[0.330]

0.019[0.482]

51-85023-*B

Document #: 38-08022 Rev. *C

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Package Diagrams (continued)

24-Lead (300-Mil) SOIC S13

PIN 1 ID

12

1

MIN.

DIMENSIONS IN INCHES[MM]

MAX.

*

0.394[10.007]

0.419[10.642]

REFERENCE JEDEC MO-119

PACKAGE WEIGHT 0.65gms

0.291[7.391]

0.300[7.620]

PART #

13

24

0.026[0.660]

0.032[0.812]

S24.3 STANDARD PKG.

SZ24.3 LEAD FREE PKG.

SEATING PLANE

0.597[15.163]

0.615[15.621]

0.092[2.336]

0.105[2.667]

*

0.004[0.101]

0.0091[0.231]

0.0125[0.317]

*

0.050[1.270]

TYP.

0.015[0.381]

0.050[1.270]

0.004[0.101]

0.0118[0.299]

0.013[0.330]

0.019[0.482]

51-85025-*B

24-Lead (300-Mil) PDIP P13

51-85013-*B

Document #: 38-08022 Rev. *C

Page 46 of 49

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Package Diagrams (continued)

24-Lead Quarter Size Outline Q13

51-85055-B

DIE FORM

Cypress Logo

(1907, 3001)

Die Step: 1907 x 3011 microns

Die Size: 1830.8 x 2909 microns

Die Thickness: 14 mils = 355.6 microns

Pad Size: 80 x 80 microns

4

5

6

7

8

9

22

21

20

19

18

Y

10

17

(0,0)

X

Document #: 38-08022 Rev. *C

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Table 28-1 below shows the die pad coordinates for the CY7C63722C-XC. The center location of each bond pad is relative to

the bottom left corner of the die which has coordinate (0,0).

Table 28-1. CY7C63722C-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers)

X

Y

Pad Number

Pin Name

P0.0

P0.1

P0.2

P0.3

P1.0

P1.2

P1.4

P1.6

Vss

(microns)

1

788.95

597.45

406.00

154.95

363.90

531.70

1066.55

1210.75

1449.75

1662.35

1735.35

1752.05

1393.25

1171.80

980.35

2843.15

2687.95

2496.45

2305.05

2113.60

1922.05

1730.90

312.50

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Vss

Vpp

184.85

VREG

XTALIN

XTALOUT

Vcc

184.85

D–

184.85

D+

289.85

P1.7

P1.5

P1.3

P1.1

P0.7

P0.6

P0.5

P0.4

1832.75

2024.30

2215.75

2407.15

2598.65

2843.15

enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document

may be the trademarks of their respective holders.

Document #: 38-08022 Rev. *C

Page 48 of 49

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges

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Document History Page

Document Title: CY7C63722C, CY7C63723C, CY7C63743C enCoRe™ USB Combination Low-Speed USB

and PS/2 Peripheral Controller

Document Number: 38-08022

Orig. of

Change

REV.

ECN NO. Issue Date

Description of Change

**

118643

243308

10/22/02

BON

Converted from Spec 38-00944 to Spec 38-08022.

Added notes 17, 18 to section 26

Removed obsolete parts (63722-PC and 63742)

Added die sale

Added section 23 (Register Summary)

*A

SEE ECN

KKU

Added 24 QSOP package

Added Lead-free packages to section 27

Reformatted to update format

*B

*C

267229

429169

See ECN

ARI

TYJ

Corrected part number in the Ordering Information section

Updated part numbers with ‘C’ part numbers

Changed to ‘Cypress Perform’ logo

Added the 24-QSOP part offering

Document #: 38-08022 Rev. *C

Page 49 of 49

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型号：	CY7C63722C-XC
厂家：	CYPRESS
描述：	enCoRe⑩ USB Combination Low-Speed USB and PS/2 Peripheral Controller enCoRe⑩ USB组合低速USB和PS / 2外围控制器控制器
文件：	总49页 (文件大小：2028K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C63722C-XC [CYPRESS]

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