CY7C64315-16LKXC [CYPRESS]
enCoRe⑩ V Full-Speed USB Controller; 的enCoRe ™V全速USB控制器
| 型号： | CY7C64315-16LKXC |
| 厂家： | 
CYPRESS |
| 描述： | enCoRe⑩ V Full-Speed USB Controller |
| 文件： | 总26页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C6435x
PRELIMINARY
CY7C64345, CY7C6431x
enCoRe™ V Full-Speed USB Controller
❐ Configurable inputs on all GPIO
❐ Low dropout voltage regulator for Port1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the IO pins.
❐ Selectable, regulated digital IO on Port 1
• Configurable Input Threshold for Port 1
• 3.0V, 20 mA Total Port 1 Source Current
• Hot-Swappable
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 3.0V to 5.5V Operating voltage
❐ Temperature range: 0°C to 70°C
❐ 5 mA Strong drive mode on Ports 0 and 1
■ Flexible On-Chip Memory
❐ Up to 32K Flash program storage
50,000 Erase/write cycles
❐ Up to 2048 bytes SRAM data storage
❐ Flexible protection modes
❐ In-System Serial Programming (ISSP)
■ Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator and programmer
❐ Full-speed emulation
■ Additional System Resources
❐ Configurable communication speeds
❐ I2C™ slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ Complex breakpoint structure
❐ 128K Trace memory
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 μA
• Hardware address detection
❐ SPI master and SPI slave
• Configurable between 46.9 kHz - 3 MHz
❐ Three 16-bit timers
❐ 10-bit ADC to use for monitoring battery voltage or other sig-
nals
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6/12/24 MHz main oscillator
❐ Internal low-speed oscillator at 32 kHz for watchdog and
sleep. Thefrequencyrangeis19-50kHzwitha32kHztypical
value.
❐ 0.25% Accuracy for USB with no external components
■ Programmable Pin Configurations
❐ 25 mA Sink current on all GPIO
❐ Pull up, high Z, open drain, CMOS drive modes on all GPIO
enCoRe V
Port 4
Port 3 Port 2 Port 1 Port 0 Prog. LDO
Block Diagram
enCoRe V
CORE
System Bus
SRAM
2048 Bytes
SROM
Flash 32K
CPU Core
(M8C)
Sleep and
Watchdog
Interrupt
Controller
6/12/24 MHz Internal Main Oscillator
POR and LVD
I2C Slave/SPI
Full
Speed
USB
3 16-Bit
Timers
Master-Slave
System Resets
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-12394 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 17, 2007
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■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (power
on reset) circuit eliminates the need for a system supervisor.
Functional Overview
The enCoRe V family of devices are designed to replace multiple
traditional full-speed USB microcontroller system components
with one, low cost single-chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, Flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
■ The 5V maximum input, 1.8/2.5/3V-selectable output,
low-dropout regulator (LDO) provides regulation for IOs. A
register controlled bypass mode allows the user to disable the
LDO.
The architecture for this device family, as illustrated (enCoRe V),
is comprised of three main areas: the CPU core, the system
resources, and the full-speed USB system. Depending on the
enCoRe V package, up to 36 general purpose IO (GPIO) are also
included.
■ Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V family of parts.
Getting Started
The quickest path to understanding the enCoRe V silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the enCoRe V integrated circuit and presents specific pin,
register, and electrical specifications.
This product is an enhanced version of Cypress’ successful
full-speed USB peripheral controllers. Enhancements include
faster CPU at lower voltage operation, lower current
consumption, twice the RAM and Flash, hot-swapable IOs, I2C
hardware address recognition, new very low current sleep mode,
and new package options.
For up-to-date ordering, packaging, and electrical specification
information, reference the latest enCoRe V device data sheets
on the web at http://www.cypress.com.
The enCoRe V Core
The enCoRe V Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click USB (Universal
Serial Bus) to view a current list of available items.
System resources provide additional capability, such as a config-
urable I2C slave/SPI master-slave communication interface and
various system resets supported by the M8C.
Technical Training
Additional System Resources
Free PSoC and USB technical training is available for beginners
and is taught by a marketing or application engineer over the
phone. PSoC training classes cover designing, debugging,
advanced analog, as well as application-specific classes
covering topics such as PSoC, USB and the LIN bus. Go to
http://www.cypress.com, click on Design Support located on the
left side of the web page, and select Technical Training for more
details.
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. Brief statements describing the merits of each system
resource are presented below.
■ Full-speed USB (12 Mbps) with nine configurable endpoints
and512bytesofdedicatedUSBRAM.Noexternalcomponents
are required except two series resistors. It is specified for
commercial temperature USB operation. For reliable USB
operation, ensure the supply voltage is between 4.35V and
5.25V, or around 3.3V.
Consultants
Certified Cypress USB Consultants offer everything from
technical assistance to completed USB designs. To contact or
become
a
Cypress PSoC/USB Consultant go to
http://www.cypress.com, click on Design Support located on
the left side of the web page, and select CYPros Consultants.
■ 10-bit on-chip ADC shared between system performance
manager (used to calculate parameters based on temperature
for flash write operations) and the user.
Technical Support
■ The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a
slower system clock).
Cypress application engineers take pride in fast and accurate
response. You can reach them with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
■ In the case of I2C slave mode, the hardware address recog-
nition feature reduces the already low power consumption by
eliminating the need for CPU intervention until a packet
addressed to the target device has been received.
Many application notes are available to assist you in every
aspect of your design effort. To view the USB application notes,
go to the http://www.cypress.com web site and select Appli-
cation Notes under the Design Resources list located in the
center of the web page. By default, application notes are sorted
by date .
Document Number: 001-12394 Rev. *D
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using the enCoRe V device blocks. Examples of user modules
are timers, 10-bit ADC, SPI/I2C etc.
Development Tools
PSoC Designer is a Microsoft Windows-based, integrated devel-
opment environment for the Programmable System-on-Chip
(PSoC) devices. The PSoC Designer IDE and application runs
on Windows NT 4.0, Windows 2000, Windows Millennium (Me),
or Windows XP. (Reference the PSoC Designer Functional Flow
diagram below.)
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfigu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for selected
enCoRe V block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of enCoRe V block configurations at run
time. PSoC Designer can print out a configuration sheet for a
given project configuration for use during application
programming in conjunction with the Device Data Sheet. Once
the framework is generated, the user can add appli-
cation-specific code to flesh out the framework. It is also possible
to change the selected components and regenerate the
framework.
PSoC Designer helps the customer to select an operating config-
uration for the USB, write application code that uses the USB,
and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 1. PSoC Designer Subsystems
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the merging of
assembly code seamlessly with C code. The link libraries
automatically use absolute addressing or are compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available that
supports the enCoRe V family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the enCoRe V family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the enCoRe V architecture. It comes complete
with embedded libraries providing port and bus operations,
standard keypad and display support, and extended math
functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
Document Number: 001-12394 Rev. *D
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Figure 2. User Module and Source Code Development Flows
Device Editor
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
User
Module
Selection
Source
Code
Generator
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
most Cypress USB and all PSoC devices. Emulation pods for
each device family are available separately. The emulation pod
takes the place of the enCoRe V device in the target board and
performs full-speed (24 MHz) operation.
Generate
Application
Designing with User Modules
Application Editor
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a feature
where the resources of the part are selected as user modules.
For example, the timers, I2C, SPI resources are available as
user modules. User modules make selecting and implementing
peripheral devices simple and easy.
Source
Code
Editor
Project
Manager
Build
Manager
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. User modules also provide tested software to cut
your development time. The user module application
programming interface (API) provides high-level functions to
control and respond to hardware events at run time. The API also
provides optional interrupt service routines that you can adapt as
needed.
Build
All
Debugger
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick and place the user
modules you need for your project. The tool automatically builds
signal chains by connecting user modules to the default IO pins
or as required. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting
values from drop-down menus. When you are ready to test the
hardware configuration or move on to developing code for the
project, you perform the “Generate Application” step. This
causes PSoC Designer to generate source code that automati-
cally configures the device to your specification and provides the
high-level user module API functions.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full-speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document Number: 001-12394 Rev. *D
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Document Conventions
Acronym
Description
POR
power on reset
Acronyms Used
PPOR
PSoC®
SLIMO
SRAM
precision power on reset
Programmable System-on-Chip™
slow IMO
The following table lists the acronyms that are used in this
document.
Acronym
API
Description
application programming interface
central processing unit
general purpose IO
static random access memory
CPU
GPIO
GUI
ICE
ILO
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 5 on page 15 lists all the abbreviations used to
measure the enCoRe V devices.
graphical user interface
in-circuit emulator
Numeric Naming
internal low speed oscillator
internal main oscillator
input/output
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
IMO
IO
LSb
LVD
MSb
least-significant bit
low voltage detect
most-significant bit
Document Number: 001-12394 Rev. *D
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Pin Configuration
The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables.
16-Pin Part Pinout
Figure 3. CY7C64315/CY7C64316 16-Pin enCoRe V Device
P0[4]
P2[3]
P1[7]
P1[5]
P1[1]
12
11
10
9
1
2
3
4
QFN
XRES
(Top View)
P1[4]
P1[0]
Table 1. 16-Pin Part Pinout (QFN)
Pin No.
Type
Digital
IO
Name
Description
1
2
P2[3]
P1[7]
P1[5]
Digital IO, Crystal Input (Xin)
Digital IO, SPI SS, I2C SCL
Digital IO, SPI MISO, I2C SDA
IOHR
IOHR
IOHR
Power
USB line
USB line
Power
IOHR
IOHR
Input
IOH
3
4
P1[1](1)
Digital IO, ISSP CLK, 12C SCL, SPI MOSI
5
Vss
Ground connection
6
D+
USB PHY
7
D–
USB PHY
8
Vdd
Supply
9
P1[0](1)
P1[4]
XRES
P0[4]
P0[7]
P0[3]
P0[1]
P2[5]
Digital IO, ISSP DATA, I2C SDA, SPI CLK
10
11
12
13
14
15
16
Digital IO, optional external clock input (EXTCLK)
Active high external reset with internal pull down
Digital IO
IOH
Digital IO
IOH
Digital IO
IOH
Digital IO
IO
Digital IO, Crystal Output (Xout)
LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output.
Note
1. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR).
Document Number: 001-12394 Rev. *D
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32-Pin Part Pinout
Figure 4. CY7C64345 32-Pin enCoRe V USB Device
P0[1]
1
2
24
23
P0[0]
P2[6]
P2[5]
P2[3]
P2[1]
P1[7]
3
4
5
6
7
8
22
21
20
P2[4]
P2[2]
P2[0]
P3[2]
QFN
( Top View)
P1[5]
P1[3]
P1[1]
19
18
17
P3[0]
XRES
Table 2. 32-Pin Part Pinout (QFN)
Pin No.
1
Type
IOH
IO
Name
P0[1]
Description
Digital IO
2
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1](2)
Vss
Digital IO, Crystal Output (Xout)
Digital IO, Crystal Input (Xin)
Digital IO
3
IO
4
IO
5
IOHR
IOHR
IOHR
IOHR
Power
IO
Digital IO, I2C SCL, SPI SS
Digital IO, I2C SDA, SPI MISO
Digital IO, SPI CLK
6
7
8
Digital IO, ISSP CLK, I2C SCL, SPI MOSI
9
Ground
10
11
12
13
14
15
16
17
18
19
20
21
D+
USB PHY
IO
D–
USB PHY
Power
IOHR
IOHR
IOHR
IOHR
Reset
IO
Vdd
Supply voltage
P1[0](2)
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
Digital IO, ISSP DATA, I2C SDA, SPI CLK
Digital IO
Digital IO, optional external clock input (EXTCLK)
Digital IO
Active high external reset with internal pull down
Digital IO
Digital IO
Digital IO
Digital IO
IO
IO
IO
Note
2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR).
Document Number: 001-12394 Rev. *D
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Table 2. 32-Pin Part Pinout (QFN) (continued)
Pin No.
22
Type
IO
Name
P2[4]
Description
Digital IO
23
IO
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Supply voltage
Digital IO
Digital IO
Digital IO
Ground
24
IOH
25
IOH
26
IOH
27
IOH
28
Power
IOH
29
P0[7]
P0[5]
P0[3]
Vss
30
IOH
31
IOH
32
Power
Power
CP
Vss
Ensure the center pad is connected to ground
LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12394 Rev. *D
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48-Pin Part Pinout
Figure 5. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device
P2[6]
P2[4]
P2[2]
P2[0]
P4[2]
P4[0]
P3[6]
36
35
34
33
32
31
30
NC
P2[7]
P2[5]
1
2
3
4
P2[3]
P2[1]
P4[3]
5
6
QFN
(Top View)
P4[1]
P3[7]
P3[5]
P3[3]
7
P3[4]
P3[2]
P3[0]
XRES
29
28
27
8
9
10
P3[1]
P1[7]
26
25
11
12
P1[6]
Table 3. 48-Pin Part Pinout (QFN)
Pin No.
1
Type
NC
Pin Name
Description
NC
No connection
Digital IO
2
IO
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
3
IO
Digital IO, Crystal Out (Xout)
Digital IO, Crystal In (Xin)
Digital IO
4
IO
5
IO
6
IO
Digital IO
7
IO
Digital IO
8
IO
Digital IO
9
IO
Digital IO
10
11
12
13
14
15
16
17
18
19
20
21
22
IO
Digital IO
IO
Digital IO
IOHR
IOHR
NC
Digital IO, I2C SCL, SPI SS
Digital IO, I2C SDA, SPI MISO
No connection
NC
NC
No connection
IOHR
IOHR
Power
IO
P1[3]
P1[1](3)
Vss
Digital IO, SPI CLK
Digital IO, ISSP CLK, I2C SCL, SPI MOSI
Supply ground
D+
USB
IO
D–
USB
Power
IOHR
Vdd
Supply voltage
P1[0](3)
Digital IO, ISSP DATA, I2C SDA, SPI CLK
Note
3. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR).
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Table 3. 48-Pin Part Pinout (QFN) (continued)
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Type
IOHR
IOHR
IOHR
XRES
IO
Pin Name
P1[2]
Description
Digital IO,
P1[4]
P1[6]
Ext Reset
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Digital IO, optional external clock input (EXTCLK)
Digital IO
Active high external reset with internal pull down
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IO
Digital IO
IOH
IOH
IOH
IOH
Power
NC
Digital IO
Digital IO
Digital IO
Digital IO
Supply voltage
No connection
No connection
Digital IO
NC
NC
NC
IOH
IOH
IOH
Power
IOH
P0[7]
P0[5]
P0[3]
Vss
Digital IO
Digital IO
Supply ground
Digital IO
P0[1]
LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output.
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PRELIMINARY
Register Reference
The section discusses the registers of the enCoRe V device. It
lists all the registers in mapping tables, in address order.
Register Mapping Tables
The enCoRe V device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts: Bank 0 (user space) and Bank 1 (configu-
ration space). The XIO bit in the Flag register (CPU_F) deter-
mines which bank the user is currently in. When the XIO bit is
set, the user is said to be in the “extended” address space or the
“configuration” registers.
Register Conventions
The register conventions specific to this section and the
Register Reference chapter are listed in the following table.
Table 4. Register Conventions
Convention
Description
Read register or bits
R
W
O
L
Write register or bits
Only a read/write register or bits
Logical register or bits
Clearable register or bits
Access is bit specific
C
#
Register Map Bank 0 Table: User Space
Addr
(0,Hex)
Addr
(0,Hex)
Addr
(0,Hex)
Addr
(0,Hex)
Name
Access
Name
Access
Name
Access
Name
Access
PRT0DR
PRT0IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
RW
RW
EP1_CNT0
EP1_CNT1
EP2_CNT0
EP2_CNT1
EP3_CNT0
EP3_CNT1
EP4_CNT0
EP4_CNT1
EP5_CNT0
EP5_CNT1
EP6_CNT0
EP6_CNT1
EP7_CNT0
EP7_CNT1
EP8_CNT0
EP8_CNT1
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
PRT1DR
PRT1IE
RW
RW
PRT2DR
PRT2IE
RW
RW
I2C_XCFG
I2C_XSTAT
I2C_ADDR
I2C_BP
RW
R
RW
R
R
RW
R
RW
RW
RW
PRT3DR
PRT3IE
RW
RW
I2C_CP
CPU_BP
CPU_CP
I2C_BUF
CUR_PP
STK_PP
PRT4DR
PRT4IE
RW
RW
IDX_PP
RW
RW
RW
RW
#
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
PMA0_DR
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
RW
RW
RW
RW
RW
RW
RW
RW
RW
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK2
INT_MSK1
INT_MSK0
RW
RW
RW
RW
RW
RW
RW
RW
INT_SW_E
N
22
62
A2
INT_VC
E2
RC
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev. *D
Page 11 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Addr
Addr
(0,Hex)
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
Addr
Addr
Name
Access
Name
Access
Name
Access
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RES_WDT
INT_MSK3
W
RW
PMA8_DR
PMA9_DR
PMA10_DR
PMA11_DR
PMA12_DR
PMA13_DR
PMA14_DR
PMA15_DR
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SPI_TXR
SPI_RXR
SPI_CR
W
R
#
PT0_CFG
RW
RW
RW
RW
RW
RW
RW
RW
RW
USB_SOF0
USB_SOF1
USB_CR0
USBIO_CR0
USBIO_CR1
EP0_CR
EP0_CNT0
EP0_DR0
EP0_DR1
EP0_DR2
EP0_DR3
EP0_DR4
EP0_DR5
EP0_DR6
EP0_DR7
R
R
RW
#
#
#
PT0_DATA1
PT0_DATA0
PT1_CFG
PT1_DATA1
PT1_DATA0
PT2_CFG
F1
F2
F3
F4
F5
F6
F7
F8
75
76
77
78
#
PT2_DATA1
PT2_DATA0
CPU_F
RL
RW
RW
RW
RW
RW
RW
RW
RW
79
F9
7A
7B
7C
7D
7E
7F
FA
FB
FC
FD
FE
FF
CPU_SCR1
CPU_SCR0
#
#
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev. *D
Page 12 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Register Map Bank 1 Table: Configuration Space
Addr
(1,Hex)
Addr
(1,Hex)
Addr
(1,Hex)
Addr
(1,Hex)
Name
Access
Name
Access
Name
Access
Name
Access
PRT0DM0
PRT0DM1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
RW
RW
PMA4_RA
PMA5_RA
PMA6_RA
PMA7_RA
PMA8_WA
PMA9_WA
PMA10_WA
PMA11_WA
PMA12_WA
PMA13_WA
PMA14_WA
PMA15_WA
PMA8_RA
PMA9_RA
PMA10_RA
PMA11_RA
PMA12_RA
PMA13_RA
PMA14_RA
PMA15_RA
EP1_CR0
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
PRT1DM0
PRT1DM1
RW
RW
PRT2DM0
PRT2DM1
RW
RW
PRT3DM0
PRT3DM1
RW
RW
PRT4DM0
PRT4DM1
RW
RW
EP2_CR0
EP3_CR0
EP4_CR0
EP5_CR0
EP6_CRO
EP7_CR0
EP8_CR0
#
#
#
#
#
#
#
IO_CFG
OUT_P1
RW
RW
OSC_CR0 E0
ECO_CFG E1
OSC_CR2 E2
RW
#
RW
RW
R
VLT_CR
E3
VLT_CMP E4
E5
E6
E7
E8
E9
EA
IMO_TR
ILO_TR
W
W
SPI_CFG
USB_CR1
RW
SLP_CFG EB
SLP_CFG2 EC
SLP_CFG3 ED
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
EE
EF
F0
F1
F2
F3
F4
F5
F6
#
USBIO_CR2
PMA0_WA
PMA1_WA
PMA2_WA
PMA3_WA
PMA4_WA
PMA5_WA
RW
RW
RW
RW
RW
RW
RW
CPU_F
F7
F8
F9
RL
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev. *D
Page 13 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Addr
Addr
(1,Hex)
7A
7B
7C
7D
7E
7F
Addr
Addr
Name
Access
Name
Access
Name
Access
Name
Access
(1,Hex)
(1,Hex)
(1,Hex)
PMA6_WA
PMA7_WA
PMA0_RA
PMA1_RA
PMA2_RA
PMA3_RA
3A
3B
3C
3D
3E
3F
RW
RW
RW
RW
RW
RW
BA
BB
BC
BD
BE
BF
FA
FB
FC
FD
FE
FF
Gray fields are reserved; do not access these fields.
# Access is bit specific.
Document Number: 001-12394 Rev. *D
Page 14 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Electrical Specifications
This chapter presents the DC and AC electrical specifications of
the enCoRe V USB devices. For the most up to date electrical
specifications, verify that you have the most recent data sheet
available by visiting the company web site at
http://www.cypress.com
The following table lists the units of measure that are used in this
chapter.
Table 5. Units of Measure
Symbol
oC
Unit of Measure
degree Celsius
Figure 6. Voltage versus CPU Frequency
dB
decibels
5.5V
fF
femto farad
hertz
Hz
KB
Kbit
kHz
kΩ
1024 bytes
1024 bits
kilohertz
kilohm
3.0V
MHz
MΩ
μA
megahertz
megaohm
microampere
microfarad
μF
μH
μs
μV
microhenry
microsecond
microvolts
750 kHz
3 MHz
CPU Frequency
24 MHz
μVrms
μW
mA
ms
mV
nA
microvolts root-mean-square
microwatts
milli-ampere
milli-second
milli-volts
Figure 7. IMO Frequency Trim Options
5.5V
nanoampere
nanosecond
nanovolts
ns
nV
SLIMO
Mode
= 10
SLIMO SLIMO
Mode
W
ohm
Mode
= 01
= 00
pA
picoampere
picofarad
pF
pp
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
3.0V
ppm
ps
sps
s
V
750 kHz
3 MHz
6 MHz 12 MHz 24 MHz
IMO Frequency
Document Number: 001-12394 Rev. *D
Page 15 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Electrical Characteristics
Absolute Maximum Ratings
Storage Temperature (TSTG)
(4) ............................................. ..............................................................-55oC to 125oC (Typical +25oC)
Supply Voltage Relative to Vss (Vdd).................................... .........................................................................................-0.5V to +6.0V
DC Input Voltage (VIO)........................................................... .........................................................................Vss - 0.5V to Vdd + 0.5V
DC Voltage Applied to Tri-state (VIOZ)................................... .........................................................................Vss - 0.5V to Vdd + 0.5V
Maximum Current into any Port Pin (IMIO)............................. .....................................................................................-25mA to +50mA
Electro Static Discharge Voltage (ESD) (5) ............................ ......................................................................................................2000V
Latch-up Current (LU) (6) ....................................................... .................................................................................................... 200mA
Operating Conditions
Ambient Temperature (TA)..................................................... .............................................................................................0oC to 70oC
Operational Die Temperature (TJ)(7)...................................... .............................................................................................0oC to 85oC
DC Electrical Characteristics
DC Chip-Level Specifications
Table 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 6. DC Chip-Level Specifications
Parameter
Description
Supply Voltage
Conditions
Min
Typ
Max
Units
Vdd
See table titled DC POR and LVD
Specifications on page 18.
3.0
–
5.5
V
IDD24
IDD12
IDD6
Supply Current, IMO = 24 MHz
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Deep Sleep Current
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 24 MHz,
No USB/I2C/SPI.
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 12 MHz,
No USB/I2C/SPI.
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 6 MHz,
No USB/I2C/SPI.
Vdd = 3.0V, TA = 25oC, IO regulator
turned off.
Vdd = 3.0V, TA = 25oC, IO regulator
turned off.
–
–
–
–
–
–
2.15
1.45
1.1
mA
mA
mA
ISB0
ISB1
–
–
0.1
–
–
μA
μA
Standby Current with POR, LVD and
Sleep Timer
1.5
Notes
o
4. Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended duration storage temperatures above 85 C
degrade reliability.
5. Human Body Model ESD.
6. Per JESD78 standard.
7. The temperature rise from ambient to junction is package specific. See “Package Diagram” on page 22 for Thermal Impedances. The user must limit the power
consumption to comply with this requirement.
Document Number: 001-12394 Rev. *D
Page 16 of 26
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CY7C6435x
CY7C64345, CY7C6431x
PRELIMINARY
Table 7. DC Characteristics – USB Interface
Symbol
Rusbi
Rusba
Vohusb
Volusb
Vdi
Description
USB D+ pull up resistance
USB D+ pull up resistance
Static Output High
Conditions
Min
0.900
1.425
2.8
Typ
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
1.575
3.090
3.6
Units
kΩ
kΩ
V
With idle bus
While receiving traffic
Static Output Low
0.3
V
Differential Input Sensitivity
Differential Input Common Mode Range
Single Ended Receiver Threshold
Transceiver Capacitance
Hi-Z State Data Line Leakage
PS/2 Pull-up resistance
0.2
TBD
0.8
V
Vcm
TBD
2.0
50
V
Vse
V
Cin
pF
uA
kΩ
Ω
Iio
On D+ or D- line
TBD
3
TBD
7
Rps2
Rext
External USB Series Resistor
In series with each USB pin
23
25
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and
0°C ≤ TA ≤ 70°C. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 8. 3.0V and 5.5V DC GPIO Specifications
Symbol
RPU
Description
Pull up resistor
Conditions
Min
Typ
5.6
–
Max
8
Units
kΩ
V
4
VOH1
High Output Voltage
Port 0, 2, or 3 Pins
OH < 10 µA, Vdd > 3.0V, maximum of Vdd - 0.2
10 mA source current in all IOs.
–
VOH2
VOH3
VOH4
VOH5
VOH6
VOL
High Output Voltage
Port 0, 2, or 3 Pins
OH = 1mA Vdd > 3.0, maximum of 20 Vdd - 0.9
mA source current in all IOs.
–
–
–
–
V
V
V
V
V
V
High Output Voltage
Port 1 Pins with LDO Regulator Disabled 10 mA source current in all IOs.
OH < 10 µA, Vdd > 3.0V, maximum of Vdd - 0.2
High Output Voltage
Port 1 Pins with LDO Regulator Disabled mA source current in all IOs.
OH = 5mA, Vdd > 3.0V, maximum of 20 Vdd - 0.9
–
–
High Output Voltage
Port 1 Pins with LDO Regulator Enabled IOs all sourcing 5 mA.
OH < 10µA, Vdd > 3.1V, maximum of 4
2.85
2.2
–
3.0
–
3.15
–
High Output Voltage
Port 1 Pins with LDO Regulator Enabled 20 mA source current in all IOs.
OH = 5 mA, Vdd > 3.1V, maximum of
Low Output Voltage
OL = 20mA, Vdd > 3.3V, maximum of
60 mA sink current on even port pins
(for example, P0[2] and P1[4]) and 60
mA sink current on odd port pins (for
example, P0[3] and P1[5]).
–
0.75
VIL
VIH
VH
IIL
Input Low Voltage
Vdd = 3.3 to 5.5.
Vdd = 3.3 to 5.5.
–
–
–
0.8
V
V
Input High Voltage
2.0
50
–
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
60
1
200
25
5
mV
nA
pF
CIN
Package and pin dependent.
Temp = 25oC.
0.5
1.7
COUT
Capacitive Load on Pins as Output
Package and pin dependent.
Temp = 25oC.
0.5
1.7
5
pF
Document Number: 001-12394 Rev. *D
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CY7C64345, CY7C6431x
PRELIMINARY
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Vdd Value for PPOR Trip
PORLEV[1:0] = 10b, HPOR = 1
VPPOR
–
2.82
2.95
V
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
M[2:0] = 010b(8)
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
–
–
2.85
2.95
3.06
–
–
–
2.92
3.02
3.13
–
–
–
2.99
3.09
3.20
–
–
–
V
V
V
–
–
4.62
–
4.73
–
4.83
–
V
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 10.DC Programming Specifications
Symbol
Description
Min
3.0
–
Typ
–
Max
–
Units
V
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
VILP
VIHP
IILP
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
5
25
VIL
–
mA
V
–
–
VIH
–
–
V
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify(9)
–
0.2
mA
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify(10)
–
–
1.5
mA
VOLV
VOHV
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
Vss + 0.75
V
V
Vdd - 1.0
50,000
10
Vdd
–
FlashENPB Flash Write Endurance(11)
–
Cycles
Years
FlashDR
Flash Data Retention(12)
20
–
Notes
8. Always greater than 50 mV above V
9. Driving internal pull down resistor.
10. Driving internal pull down resistor.
11. Erase/write cycles per block.
(PORLEV = 10) for falling supply.
PPOR
12. Following maximum Flash write cycles.
Document Number: 001-12394 Rev. *D
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CY7C64345, CY7C6431x
PRELIMINARY
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 11.AC Chip-Level Specifications
Symbol
FMAX
Description
Maximum Operating Frequency(13)
Min
24
Typ
–
Max
–
Units
MHz
MHz
kHz
MHz
MHz
MHz
%
FCPU
Maximum Processing Frequency(14)
Internal Low Speed Oscillator Frequency
Internal Main Oscillator Stability for 24 MHz ± 5%(15)
Internal Main Oscillator Stability for 12 MHz(16)
Internal Main Oscillator Stability for 6 MHz(17)
Duty Cycle of IMO
24
–
–
F32K1
30.4
22.8
11.4
5.7
40
32
24
12
6.0
50
–
33.6
25.2
12.6
6.3
60
FIMO24
FIMO12
FIMO6
DCIMO
TRAMP
Supply Ramp Time
0
–
μs
Table 12.AC Characteristics – USB Data Timings
Symbol Description
Tdrate Full-speed data rate
Conditions
Average bit rate
Min
12–0.25%
-8
Typ
12
Max
Units
12 + 0.25 MHz
Tdjr1
Tdjr2
Tudj1
Tudj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Receiver data jitter tolerance
Receiver data jitter tolerance
Driver differential jitter
To next transition
To pair transition
To next transition
To pair transition
To SE0 transition
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8
5
ns
ns
ns
ns
ns
ns
ns
ns
-5
-3.5
-4.0
-2
3.5
4.0
5
Driver differential jitter
Source jitter for differntial transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
160
82
175
Width of SE0 interval during differential
transition
14
Table 13.AC Characteristics – USB Driver
Symbol Description
Tr Transition rise time
Conditions
50 pF
Min
4
Typ
TBD
TBD
TBD
TBD
Max
20
Units
ns
Tf
Transition fall time
50 pF
4
20
ns
TR
Vcrs
Rise/fall time matching
Output signal crossover voltage
90.00
1.3
111.11
2.0
%
V
Notes
o
13. Vdd = 3.0V and T = 85 C, digital clocking functions.
14. Vdd = 3.0V and T = 85 C, CPU speed.
J
o
J
15. Trimmed for 3.3V operation using factory trim values.
16. Trimmed for 3.3V operation using factory trim values.
17. Trimmed for 3.3V operation using factory trim values.
Document Number: 001-12394 Rev. *D
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AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14.AC GPIO Specifications
Symbol
Description
Conditions
Min
0
Typ
–
Max
12
Units
MHz
ns
FGPIO
GPIO Operating Frequency
Normal Strong Mode, Port 1
Vdd = 3.3 to 5.5V, 10% - 90%
TRise023 Rise Time, Strong Mode
Ports 0, 2, 3
15
–
80
TRise1
Rise Time, Strong Mode
Port 1
Vdd = 3.3 to 5.5V, 10% - 90%
Vdd = 3.3 to 5.5V, 10% - 90%
7
7
–
–
50
50
ns
ns
TFall
Fall Time, Strong Mode
All Ports
Figure 8. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise023
TRise1
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15.AC External Clock Specifications
Symbol
Description
Min
0.750
20.6
20.6
150
Typ
–
Max
25.2
5300
–
Units
MHz
ns
FOSCEXT Frequency
–
–
–
High Period
–
Low Period
–
ns
Power Up IMO to Switch
–
–
μs
Document Number: 001-12394 Rev. *D
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PRELIMINARY
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 16.AC Programming Specifications
Symbol
TRSCLK
Description
Min
1
Typ
–
Max
20
20
–
Units
ns
Rise Time of SCLK
Fall Time of SCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB
TWRITE
TDSCLK
TDSCLK3
TDSCLK2
Flash Erase Time (Block)
–
–
18
25
45
50
70
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
–
–
–
ns
–
–
ns
AC SPI Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 17.AC SPI Specifications
Symbol
FSPIM
FSPIS
Description
Maximum Input Clock Frequency Selection, Master(18)
Maximum Input Clock Frequency Selection, Slave
Width of SS_ Negated Between Transmissions
Min
–
Typ
–
Max
8.2
4.1
–
Units
MHz
MHz
ns
–
–
TSS
50
–
2
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18.AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Fast Mode
Min Max
Symbol
Description
Units
Min
0
Max
100
–
FSCLI2C
SCL Clock Frequency
0
400
–
kHz
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
4.0
0.6
μs
TLOWI2C
LOW Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100(19)
0.6
1.3
0
–
–
μs
μs
μs
μs
ns
μs
μs
ns
THIGHI2C HIGH Period of the SCL Clock
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
–
–
TSUDATI2C Data Set-up Time
250
4.0
4.7
–
–
TSUSTOI2C Set-up Time for STOP Condition
–
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
–
50
Notes
18. Output clock frequency is half of input clock rate.
19. A Fast mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This is automatically the case if the device does not stretch the
SU;DAT
LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-Mode I2C-bus specification) before the SCL line is released.
+ t
= 1000 + 250 = 1250 ns (according to the
rmax SU;DAT
Document Number: 001-12394 Rev. *D
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PRELIMINARY
Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Package Diagram
This chapter illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the enCoRe V emulation tools and their dimensions, refer to the development kit.
Packaging Dimensions
Figure 10. 16-Lead (3x3 x 0.6 mm) QFN
Document Number: 001-12394 Rev. *D
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Figure 11. 32-Lead (5x5 x 0.6 mm) QFN
001-06335 **
Document Number: 001-12394 Rev. *D
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Figure 12. 48-Lead (7x7 mm) QFN
SOLDERABLE
EXPOSED
PAD
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
001-12919 *A
LF48A
LY48A
STANDARD
LEAD FREE
R
.
Document Number: 001-12394 Rev. *D
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Thermal Impedances
Table 19.Thermal Impedances per Package
Package
16 QFN
Typical θJA
46 oC/W
14.5 oC/W
28 oC/W
*
32 QFN**
48 QFN**
* T = T + Power x θ
JA
J
A
** To achieve the thermal impedance specified for the ** package,
solder the center thermal pad to the PCB ground plane.
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 20.Solder Reflow Peak Temperature
Minimum Peak
Temperature*
Maximum Peak
Temperature
Package
16 QFN
32 QFN
48 QFN
240oC
240oC
240oC
260oC
260oC
260oC
o
o
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Ordering Information
Package
Information
Ordering Code
Flash
SRAM
No. of GPIOs
Target Applications
CY7C64315-16LKXC
16-lead QFN
(3x3x0.6mm)
16K
1K
11
Mid-tier FS USB dongle, RC-host
module
CY7C64316-16LKXC
CY7C64345-32LKXC
CY7C64355-48LFXC
CY7C64356-48LFXC
16-lead QFN
(3x3x0.6mm)
32K
16K
16K
32K
2K
1K
1K
2K
11
25
36
36
Hi-end FS USB dongle, RC-host
module
32-lead QFN
(5x5x0.6mm)
Full-speed USB mouse
Full-speed USB keyboard
Hi-End FS USB keyboard
48-lead QFN
(7x7x1.0mm)
48-lead QFN
(7x7x1.0mm)
Document Number: 001-12394 Rev. *D
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Document History Page
Document Title: CY7C6431X, CY7C64345, CY7C6435X ENCORE TM V FULL-SPEED USB CONTROLLER
Document Number: 001-12394
Orig. of
Change
REV.
ECN.
Description of Change
**
626256
735718
TYJ
New data sheet.
*A
TYJ/ARI Filled in TBDs, added new block diagram, and corrected some values. Part numbers updated as
per new specifications.
*B
1120404
ARI
Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device. Corrected the
description to pin 29 on Table 2, the Typ/Max values for ISB0 on the DC chip-level specifications,
the current value for the latch-up current in the Electrical Characteristics section, and corrected
the 16 QFN package information in the Thermal Impedance table.
Corrected some of the bulleted items on the first page.
Added DC Characteristics–USB Interface table.
Added AC Characteristics–USB Data Timings table.
Added AC Characteristics–USB Driver table.
Corrected Flash Write Endurance minimum value in the DC Programming Specifications table.
Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC
Programming Specifications table.
Implemented new latest template.
Include paramters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2, Tfeopt, Tfst.
Added register map tables.
Corrected a value in the DC Chip-Level Specifications table.
*C
*D
1241024
1639963
TYJ/ARI Corrected Idd values in Table 6 - DC Chip-Level Specifications.
AESA Post to www.cypress.com
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12394 Rev. *D
Revised October 17, 2007
Page 26 of 26
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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