CY7C69356-48LTXC_技术文档

CY7C69356

TrueTouch^®Multi-Touch Gesture

Full Speed USB Controller

TrueTouch^®Multi-Touch Gesture Full Speed USB Controller

❐ Full speed emulation

❐ Complex breakpoint structure

❐ 128-K trace memory

Features

■ Powerful Harvard-architecture processor

❐ M8C processor speeds running up to 24 MHz

❐ Low power at high processing speeds

❐ Interrupt controller

❐ 1.71 V to 5.5 V operating voltage without USB

❐ Commercial temperature range: 0 °C to +70 °C

■ Precision, programmable clocking

❐ Internal ± 5.0 percent 6, 12, or 24 MHz main oscillator

❐ Internal low-speed oscillator at 32 kHz for Watchdog and

Sleep

❐ Optional external 32-kHz crystal

■ TrueTouch™ capacitive touchscreen controller

❐ Supports single-touch and multi-touch applications

❐ Supports up to 33 X/Y sensor inputs

❐ Supports screen sizes 5.6 inch and below (typical)

❐ Fast scan rates: Typical 400 µs per sensor

❐ 0.25 percent accuracy for USB with no external components

■ Programmable pin configurations

❐ 25 mA sink current on all GPIO

❐ Pull up, High Z, open drain CMOS drive modes on all GPIO

❐ CMOS drive mode on ports 0 and 1

❐ Up to 36 analog inputs on GPIO

■ Includes gesture detection library

❐ Configurable inputs on all GPIO

■ Allows development of customized gestures

❐ Selectable, regulated digital I/O on port 1

❐ Configurable input threshold for port 1

❐ 3.0 V, 20 mA total port 1 source current

❐ 5 mA source current mode on ports 0 and 1

❐ Hot-swap capable on all Port1GPIO

■ Low-power TrueTouch block

❐ 2.5 mA average supply current at 8-ms report rate

❐ 1.25 mA average supply current at 16-ms report rate

■ Flexible on-chip memory

❐ Program and data storage options:

• 32-KB flash

❐ 50,000 erase and write cycles

❐ 2048 bytes SRAM data storage

❐ Partial flash updates

■ Versatile analog mux

❐ Common internal analog bus

❐ Simultaneous connection of I/O combinations

❐ High PSRR comparator

❐ Low dropout voltage regulator for the analog array

❐ Flexible protection modes

❐ In-system serial programming (ISSP)

■ Additional system resources

❐ I²C slave

■ Full-speed USB (12 Mbps)

❐ Eight uni-directional endpoints

❐ One bi-directional control endpoint

❐ USB 2.0 compliant

❐ Dedicated 512 byte buffer

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• Implementation requires no clock stretching

• Implementation during sleep modes with less than 100 A

• Hardware address detection

❐ SPI master and SPI slave

• Configurable between 46.9 kHz and 12 MHz

❐ Three 16-bit timers

❐ Watchdog and sleep timers

❐ Internal voltage reference

❐ Integrated supervisory circuit

❐ Internal 3.3-V output regulator

❐ Available on 48-pin QFN packages only

❐ Operating voltage with USB enabled:

• 3.15 V to 3.45 V when supply voltage is around 3.3 V

• 4.35 V to 5.25 V when supply voltage is around 5.0 V

■ Complete development tools

❐ Free development tool (PSoC Designer™)

❐ Full-featured, in-circuit emulator, and programmer

❐ 8- to 10-bit Incremental analog-to-digital converter (ADC)

■ Package options

❐ 48-pin 7 × 7 × 1.0 mm QFN

CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE AGREEMENT (NDA)

Cypress Semiconductor Corporation

Document Number: 001-86334 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 15, 2016

CY7C69356

Logic Block Diagram

1.8/2.5/3V

LDO

PWRSYS

(Regulator)

Port 4 Port 3

Port 2

Port 1

Port 0

PSoC CORE

SYSTEM BUS

Global Analog Interconnect

32K Flash

2K SRAM

Supervisory ROM (SROM)

Nonvolatile Memory

Interrupt

Controller

Sleep and

Watchdog

CPU Core (M8C)

6/12/24 MHz Internal Main Oscillator

(IMO)

Internal Low Speed Oscillator (ILO)

Multiple Clock Sources

TrueTouch™

SYSTEM

Analog

Reference

TrueTouch™

Module

Two

Analog

Mux

Comparators

SYSTEM BUS

Internal

I2C

POR

and

LVD

SPI

Master/

Slave

Three 16-Bit

Programmable

Timers

System

Resets

Digital

Clocks

USB

Voltage

Slave

References

SYSTEM RESOURCES

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CY7C69356

Contents

Functional Overview ........................................................4

The Encore-VI Core ....................................................4

The TrueTouch Analog System ...................................4

Full-Speed USB ...........................................................5

10-bit ADC ...................................................................5

SPI ...............................................................................6

I2C Slave .....................................................................6

Additional System Resources .....................................7

Development Tools ..........................................................8

PSoC Designer Software Subsystems ........................8

Designing with PSoC Designer .......................................9

Select Components .....................................................9

Configure Components ...............................................9

Organize and Connect ................................................9

Generate, Verify, and Debug .......................................9

Pin Information ...............................................................10

Electrical Specifications ................................................11

Absolute Maximum Ratings .......................................11

Operating Temperature .............................................11

DC Chip-Level Specifications ....................................12

DC General Purpose I/O Specifications ....................13

DC Analog Mux Bus Specifications ...........................14

Comparator User Module Electrical Specifications ...14

ADC Electrical Specifications ....................................15

DC Low Power Comparator Specifications ...............15

DC POR and LVD Specifications ..............................16

DC Programming Specifications ...............................17

AC Chip-Level Specifications ....................................18

AC General Purpose I/O Specifications ....................18

AC Comparator Specifications ..................................19

AC External Clock Specifications ..............................20

AC Programming Specifications ................................20

AC SPI Specifications ...............................................21

AC I2C Specifications ................................................24

Packaging Information ...................................................25

Thermal Impedances .................................................26

Capacitance on Crystal Pins .....................................26

Solder Reflow Peak Temperature .............................26

Development Tool Selection .........................................27

Software ....................................................................27

Development Kits ......................................................27

Device Programmers .................................................27

Ordering Information ......................................................28

Ordering Code Definitions .........................................28

Acronyms ........................................................................29

Document Conventions .................................................29

Units of Measure .......................................................29

Numeric Naming ........................................................29

Document History Page .................................................30

Sales, Solutions, and Legal Information ......................31

Worldwide Sales and Design Support .......................31

Products ....................................................................31

PSoC®Solutions .......................................................31

Cypress Developer Community .................................31

Technical Support .....................................................31

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CY7C69356

each GPIO pin. Scanning of enabled TrueTouch capacitive

sensing pins are completed easily across multiple ports.

Functional Overview

The Encore-VI from the Encore family of devices is a single-chip

solution which provides the fastest and most efficient way to

develop and tune a capacitive touchsensing HID application.

These devices are designed to replace multiple traditional

full-speed USB MCU based components with one, low cost

single-chip programmable component. An Encore device

includes configurable analog and digital blocks and

programmable interconnect. This architecture enables the user

to create customized peripheral configurations, to match the

requirements of each individual application. Additionally, a fast

CPU, flash program memory, SRAM data memory, and

configurable I/O are included in a range of convenient pinouts.

Figure 1. Analog System Block Diagram

CS1

IDAC

CS2

CSN

The architecture for this device family, as illustrated in the Logic

Block Diagram on page 2, contains three main areas: the Core,

the TrueTouch Analog System, and the System Resources

(including a full-speed USB port). A common, versatile bus

enables connection between I/O and the analog system. Each

Encore-VI device includes a dedicated TrueTouch block that

provides sensing and scanning control circuitry for capacitive

sensing applications. Encore-VI supports 36 general purpose I/O

(GPIO) out of which 33 GPIOs can be used for capacitive

sensing. The GPIO provides access to the MCU and analog

mux.

Vr

Reference

Buffer

Cinternal

Cexternal (P0[1]

or P0[3])

Comparator

Mux

Refs

Refer to the user module data sheet for performance

requirements and detailed design process explanations.

Counters

The Encore-VI Core

CSCLK

The Encore-VI core encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and internal main

oscillator (IMO) and internal low speed oscillator (ILO). The CPU

core, called the M8C, is a powerful processor with speeds up to

24 MHz. The M8C is a 4-MIPS, 8-bit Harvard architecture

microprocessor.

IMO

Oscillator

Clock Select

The Analog Multiplexer System

System resources provide additional capability, such as

The analog mux bus can connect to every GPIO pin, individually

or in any combination. The bus also connects to the analog

system for analysis with the TrueTouch block comparator.

2

configurable USB and I C slave and SPI master-slave

communication interface, three 16-bit programmable timers, and

various system resets supported by the M8C.

Switch control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

®

The analog system contains the TrueTouch PSoC block and an

internal 1.2-V analog reference, which together support

capacitive sensing of up to 36 inputs.

The TrueTouch Analog System

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

The analog system contains the capacitive sensing hardware

that supports several hardware algorithms. This hardware

performs capacitive sensing and scanning without requiring

external components. Capacitive sensing is configurable on

■ Chip-wide mux that enables analog input from any I/O pin.

■ Crosspoint connection between any I/O pin combinations.

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CY7C69356

■ Identifies Start-of-Frame (SOF) and saves the frame count.

Full-Speed USB

The Encore-VI USB system resource adheres to the USB 2.0

Specification for full speed devices operating at 12 Mb/second

with one upstream port and one USB address. Encore-VI USB

consists of these components:

■ Sends data to or retrieves data from the USB SRAM, by way

of the PSoC Memory Arbiter (PMA).

Firmware is required to handle various parts of the USB

interface. The SIE issues interrupts after key USB events to

direct firmware to appropriate tasks:

■ Serial interface engine (SIE) block.

■ PSoC memory arbiter (PMA) block.

■ 512 bytes of dedicated SRAM.

■ Fill and empty the USB data buffers in USB SRAM.

■ Enable PMA channels appropriately.

■ Coordinate enumeration by decoding USB device requests.

■ Suspend and resume coordination.

■ A full-speed USB Transceiver with internal regulator and two

dedicated USB pins.

Figure 2. USB Transceiver Regulator

■ Verify and select data toggle values.

10-bit ADC

PS2 Pull Up

VOLTAGE

REGULATOR

5V 3.3V

The ADC on Encore-VI device is an independent block with a

state machine interface to control accesses to the block. The

ADC is housed together with the temperature sensor core and

can be connected to this or the Analog mux bus. As a default

operation, the ADC is connected to the temperature sensor

diodes to give digital values of the temperature.

1.5K

5K

TEN

TD

DP

Figure 3. ADC System Performance Block Diagram

V_IN

DM

TRANSMITTER

RECEIVERS

PDN

RD

TEMP SENSOR/ ADC

DPO

RSE0

DMO

TEMP

DIODES

ADC

At the Encore-VI system level, the full-speed USB system

resource interfaces to the rest of the Encore-VI by way of the

M8C’s register access instructions and to the outside world by

way of the two USB pins. The SIE supports nine endpoints

including a bidirectional control endpoint (endpoint 0) and eight

SYSTEM BUS

unidirectional data endpoints (endpoints

1 to 8). The

unidirectional data endpoints are individually configurable as

either IN or OUT.

The USB Serial Interface Engine (SIE) allows the Encore-VI

device to communicate with the USB host at full speed data rates

(12 Mb/s). The SIE simplifies the interface to USB traffic by

automatically handling the following USB processing tasks

without firmware intervention:

INTERFACE BLOCK

COMMAND/ STATUS

■ Translates the encoded received data and formats the data to

be transmitted on the bus.

■ Generates and checks cyclical redundancy checks (CRCs).

Incoming packets failing checksum verification are ignored.

Interface to the M8 C

( Processor) Core

■ Checks addresses. Ignores all transactions not addressed to

the device.

■ Sends appropriate ACK/NAK/Stall handshakes.

The ADC User Module contains an integrator block and one

comparator with positive and negative input set by the MUXes.

■ Identifies token type (SETUP, IN, OUT) and sets the

appropriate token bit once a valid token in received.

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CY7C69356

The input to the integrator stage comes from the analog global

input mux or the temperature sensor with an input voltage range

SPI configuration register (SPI_CFG) sets master/slave

functionality, clock speed, and interrupt select. SPI control

register (SPI_CR) provides four control bits and four status bits

for device interfacing and synchronization.

of 0 V to V

.

REFADC

In the ADC only configuration (the ADC MUX selects the Analog

mux bus, not the default temperature sensor connection), an

external voltage can be connected to the input of the modulator

for voltage conversion. The ADC is run for a number of cycles

set by the timer, depending upon the desired resolution of the

ADC. A counter counts the number of trips by the comparator,

which is proportional to the input voltage. The Temp Sensor block

clock speed is 36 MHz and is divided down to 1 to 12 MHz for

ADC operation.

The SPIM hardware has no support for driving the Slave Select

(SS_) signal. The behavior and use of this signal is dependent

on the application and Encore-VI device and, if required, must

be implemented in firmware.

There is an additional data input in the SPIS, Slave Select (SS_),

which is an active low signal. SS_ must be asserted to enable

the SPIS to receive and transmit. SS_ has two high level

functions:

SPI

■ To allow for the selection of a given slave in a multi-slave

environment.

The serial peripheral interconnect (SPI) 3-wire protocol uses

both edges of the clock to enable synchronous communication

without the need for stringent setup and hold requirements.

■ ToprovideadditionalclockingforTXdataqueuinginSPImodes

0 and 1.

Figure 4. Basic SPI Configuration

2

I C Slave

SPI Master

Data is output by

both the Master

and Slave on

one edge of the

clock.

SPI Slave

2

The I C slave enhanced communications block is

serial-to-parallel processor, designed to interface the Encore-VI

device to a two-wire I C serial communications bus. To eliminate

the need for excessive CPU intervention and overhead, the block

provides I C-specific support for status detection and generation

of framing bits. By default, the I C slave enhanced module is

firmware compatible with the previous generation of I C slave

a

Data is registered at the

input of both devices on the

opposite edge of the clock.

2

SCLK

2

functionality. However, this module provides new features that

are configurable to implement significant flexibility for both

internal and external interfacing. The basic I C features include:

MOSI

MISO

2

■ Slave, transmitter, and receiver operation.

■ Byte processing for low CPU overhead.

■ Interrupt or polling CPU interface.

A device can be a master or slave. A master outputs clock and

data to the slave device and inputs slave data. A slave device

inputs clock and data from the master device and outputs data

for input to the master. Together, the master and slave are

essentially a circular Shift register, where the master generates

the clocking and initiates data transfers.

■ Support for clock rates of up to 400 kHz.

■ 7- or 10-bit addressing (through firmware support).

■ SMBus operation (through firmware support).

A basic data transfer occurs when the master sends eight bits of

data, along with eight clocks. In any transfer, both master and

slave transmit and receive simultaneously. If the master only

sends data, the received data from the slave is ignored. If the

master wishes to receive data from the slave, the master must

send dummy bytes to generate the clocking for the slave to send

data back.

2

Enhanced features of the I C Slave Enhanced Module include:

■ Support for 7-bit hardware address compare.

■ Flexible data buffering schemes.

■ A “no bus stalling” operating mode.

■ A low power bus monitoring mode.

Figure 5. SPI Block Diagram

SPI Block

2

MOSI,

MISO

MOSI,

MISO

The I C block controls the data (SDA) and the clock (SCL) to the

2

external I C interface through direct connections to two

DATA_IN DATA_OUT

2

SCLK

dedicated GPIO pins. When I C is enabled, these GPIO pins are

SCLK

CLK_IN

SYSCLK

SS_

CLK_OUT

INT

not available for general purpose use. The Encore-VI CPU

firmware interacts with the block through I/O register reads and

writes, and firmware synchronization is implemented through

polling and/or interrupts.

In the default operating mode, which is firmware compatible with

2

Registers

previous versions of I C slave modules, the I C bus is stalled

upon every received address or byte, and the CPU is required to

CONFIGURATION[7:0] CONTROL[7:0]

TRANSMIT[7:0] RECEIVE[7:0]

2

read the data or supply data as required before the I C bus

2

continues. However, this I C Slave Enhanced module provides

new data buffering capability as an enhanced feature. In the

2

EZI C buffering mode, the I C slave interface appears as a

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Document Number: 001-86334 Rev. *B

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CY7C69356

2

32-byte RAM buffer to the external I C master. Using a simple

never stalls the bus. In this protocol, the data available in the

RAM (this is managed by the CPU) is valid.

predefined protocol, the master controls the read and write

pointers into the RAM. When this method is enabled, the slave

Figure 6. I²C Block Diagram

I2C Plus

Slave

I2C Core

Buffer Module

CPU Port

SDA_IN

SCL_IN

I2C Basic

Configuration

I2C_BUF

To/From

I2C_CFG

I2C_SCR

I2C_DR

GPIO

Pins

SDA_OUT

SCL_OUT

I2C_EN

32 Byte RAM

HW Addr Cmp

Buffer Ctl

I2C_ADDR

I2C_BP

SYSCLK

I2C_CP

MCU_BP

MCU_CP

Plus Features

I2C_XCFG

STANDBY

I2C_XSTAT

(power on reset) circuit eliminates the need for a system

supervisor.

Additional System Resources

System resources, some of which have been previously listed,

provide additional capability useful to complete systems.

Additional resources include low voltage detection and power on

reset. The following statements describe the merits of each

system resource.

■ The 5 V maximum input, 1.8, 2.5, or 3 V selectable output, LDO

regulator provides regulation for I/Os. A register controlled

bypass mode enables the user to disable the LDO.

■ Standard Cypress PSoC IDE tools are available for debugging

the Encore-VI family of parts.

■ Low voltage detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR

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CY7C69356

time. In essence, this allows you to use more than 100 percent

of PSoC's resources for an application.

Development Tools

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

Code Generation Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and are

linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also allows you to create a trace buffer of registers and memory

locations of interest.

■ In-circuit emulation

■ Built-in support for communication interfaces:

❐ Hardware and software I C slaves and masters

❐ Full-speed USB 2.0

2

❐ Up

to

four

full-duplex

universal

asynchronous

receiver/transmitters (UARTs), SPI master and slave, and

wireless

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an online support Forum

to aid the designer.

PSoC Designer Software Subsystems

Design Entry

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are ADCs, DACs, amplifiers, and filters. Configure

the user modules for your chosen application and connect them

to each other and to the proper pins. Then generate your project.

This prepopulates your project with APIs and libraries that you

can use to program your application.

In-Circuit Emulator

A

low-cost, high-functionality in-circuit emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

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CY7C69356

datasheets explain the internal operation of the User Module and

provide performance specifications. Each datasheet describes

the use of each user module parameter, and other information

you may need to successfully implement your design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Organize and Connect

You build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. You perform the

selection, configuration, and routing so that you have complete

control over all on-chip resources.

The PSoC development process can be summarized in the

following four steps:

Generate, Verify, and Debug

1. Select User Modules

When you are ready to test the hardware configuration or move

on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides application programming interfaces

(APIs) with high-level functions to control and respond to

hardware events at run time and interrupt service routines that

you can adapt as needed.

2. Configure User Modules

3. Organize and Connect

4. Generate, Verify, and Debug

Select Components

PSoC Designer provides a library of pre-built, pre-tested

hardware peripheral components called “user modules.” User

modules make selecting and implementing peripheral devices,

both analog and digital, simple.

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

Configure Components

Each of the User Modules you select establishes the basic

register settings that implement the selected function. They also

provide parameters and properties that allow you to tailor their

precise configuration to your particular application. For example,

a PWM User Module configures one or more

The last step in the development process takes place inside

PSoC Designer's Debugger (access by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging capabil-

ities rival those of systems costing many times more. In addition

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to

correspond to your chosen application. Enter values directly or

by selecting values from drop-down menus. All the user modules

are documented in datasheets that may be viewed directly in

PSoC Designer or on the Cypress website. These user module

to traditional single-step, run-to-breakpoint and watch-variable

features, the debug interface provides a large trace buffer and

allows you to define complex breakpoint events that include

monitoring address and data bus values, memory locations and

external signals.

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CY7C69356

Pin Information

This section describes, lists, and illustrates the CY7C69356 PSoC device pins and pinout configuration.

The CY7C69356 PSoC device is available in a 48-pin QFN package. Every port pin (labeled with a “P”) is capable of digital I/O and

connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of digital I/O.

[1, 2]

Table 1. 48-pin QFN Part Pinout

CY7C69356 48-pin PSoC Device

No.

Name

Description

1

OCDOE

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

CCLK

HCLK

P1[3]

P1[1]

Vss

OCD mode direction pin.

2

I/O

I

OCDO

E

P2[6], AI

P2[4], AI

36

35

34

33

32

31

1

2

3

Crystal output (XOut).

Crystal input (XIn).

A

, P2[7]

I

4

I/O

AI, XOut, P2[5]

3

4

5

6

P2[2], AI

P2[0], AI

P4[2], AI

P4[0], AI

AI, XIn , P2[3]

AI, P2[1]

5

I/O

6

I/O

AI, P4[3]

QFN

(Top View)

7

I/O

AI, P4[1]

AI, P3[7]

30

29

28

27

P3[6], AI

P3[4], AI

7

8

9

10

8

I/O

AI, P3[5]

AI, P3[3]

P3[2], AI

P3[0], AI

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

AI, P3[1]

XRES

26

25

11

12

I/O

AI, I2C SCL, SPI SS, P1[7]

P1[6], AI

I/OHR

I2C SCL, SPI SS.

I2C SDA, SPI MISO.

OCD CPU clock output.

OCD high speed clock output.

SPI CLK.

I/OHR

I

ISSP CLK^[3], I2C SCL, SPI MOSI.

Power

Ground connection.

I/O

D+

D-

Power

Vdd

Supply voltage.

ISSP DATA^[3], I2C SDA, SPI CLK.

I/OHR

I

P1[0]

P1[2]

No.

Name

Description

24

I/OHR

I

P1[4]

Optional external clock input

(EXTCLK).

37

I/OH

I

P0[0]

25

26

P1[6]

38

39

I/OH

I

P0[2]

P0[4]

Input

XRES

Active high external reset with

internal pull down.

27

28

29

30

31

32

33

34

35

36

I/O

I

P3[0]

P3[2]

P3[4]

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

40

41

42

43

44

45

46

47

48

CP

I/OH

I

P0[6]

Vdd

Power

Supply voltage.

OCDO OCD even data I/O.

OCDE OCD odd data output.

I/OH

I

P0[7]

P0[5]

P0[3]

Vss

Integrating input.

Power

I/OH

Power

Ground connection.

I

P0[1]

Vss

Center pad must be connected to ground.

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Notes

1. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.

2. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

must be electrically floated and not connected to any other signal.

3. These are the ISSP pins, which are not High Z at POR.

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CY7C69356

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY7C69356 PSoC devices.

Figure 7. Voltage versus CPU Frequency

5.5 V

1.71 V

5.7 MHz

24 MHz

CPU Frequency

Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings

Symbol

Description

Conditions

Min

Typ

Max

Units

T

Storage temperature

Higher storage temperatures

reduces data retention time.

Recommended Storage

–55

+25

+125

°C

STG

Temperature is +25 °C ± 25 °C.

Extended duration storage

temperatures above 85 °C

degrades reliability.

Vdd

Supply voltage relative to Vss

DC input voltage

–0.5

Vss – 0.5

–25

–

+6.0

Vdd + 0.5

+50

V

IO

IOZ

MIO

DC voltage applied to tristate

V

I

Maximum current into any port

mA

ESD

LU

Electro static discharge voltage Human Body Model ESD.

2000

–

V

Latch-up current

In accordance with JESD78

standard.

200

mA

Operating Temperature

Table 3. Operating Temperature

Symbol

Description

Conditions

Min

Typ

Max

Units

T

Ambient temperature

0

–

+70

°C

A

T

Operational die temperature

The temperature rise from ambient

to junction is package specific. See

Table 23 on page 26. The user must

limit the power consumption to

comply with this requirement.

J

0

–

+85

°C

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CY7C69356

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 4. DC Chip-Level Specifications

Symbol

Description

Supply voltage

Conditions

Min

Typ

Max

Units

[4, 5, 6]

V

Refer the table DC POR and LVD

Specifications on page 16

1.71

–

5.50

V

DD

I

Supply current, IMO = 24 MHz

Supply current, IMO = 12 MHz

Supply current, IMO = 6 MHz

Deep sleep current

Conditions are V = 3.0 V,

–

2.90

1.70

1.20

4.00

2.60

1.80

mA

DD24

DD12

DD6

DD

T = 25 °C, CPU = 24 MHz.

A

No USB/I2C/SPI

Conditions are V = 3.0 V,

DD

T = 25 °C, CPU = 24 MHz.

A

No USB/I2C/SPI

Conditions are V = 3.0 V,

DD

T = 25 °C, CPU = 24 MHz.

A

No USB/I2C/SPI

I

V

=3.0 V, T = 25 °C,

–

0.10

1.1

0.50

1.50

A

SB0

DD

A

I/O regulator turned off

Standby current with POR, LVD

and sleep timer

V

DD

= 3.0 V, T = 25 °C,

SB1

A

I/O regulator turned off

Notes

4. When V remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be

DD

slower than 1 V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SR

parameter.

POWER_UP

5. If powering down in standby sleep mode, to properly detect and recover from a V brown out condition any of the following actions must be taken:

DD

a.Bring the device out of sleep before powering down.

b.Assure that V falls below 100 mV before powering back up.

DD

c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.

d.Increase the buzz rate to assure that the falling edge of V is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.

DD

6. For USB mode, the V supply for bus-powered application should be limited to 4.35 V–5.35 V. For self-powered application, V should be 3.15 V–3.45 V.

DD

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CY7C69356

DC General Purpose I/O Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and

0 °C  T  70 °C, Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.

A

Table 5. 3.0 V to 5.5 V DC GPIO Specifications

Symbol

Description

Pull-up resistor

Conditions

Min

4

Typ

5.6

–

Max

8

Units

k

R

V

PU

High output voltage

Port 2 or 3 pins

I

< 10 A, maximum of 10 mA

OH

source current in all I/Os.

Vdd – 0.2

–

V

OH1

OH2

OH3

V

High output voltage

Port 2 or 3 pins

I

= 1 mA, maximum of 20 mA

Vdd – 0.9

Vdd – 0.2

–

V

OH

source current in all I/Os.

I < 10 A, maximum of 10 mA

OH

source current in all I/Os.

High output voltage

Port 0 or 1 pins with LDO

regulator Disabled for Port 1

V

High output voltage

Port 0 or 1 pins with LDO

regulator Disabled for Port 1

I

= 5 mA, maximum of 20 mA

Vdd – 0.9

2.85

2.20

2.35

1.90

1.60

1.20

–

3.00

–

3.3

–

V

OH4

OH5

OH6

OH7

OH8

OH9

OH10

OL

OH

source current in all I/Os.

I < 10 A, Vdd > 3.1 V, maximum

OH

of 4 I/Os all sourcing 5 mA.

I = 5 mA, Vdd > 3.1 V, maximum

OH

High output voltage

Port 1 pins with LDO regulator

Enabled for 3 V Out

High output voltage

Port 1 pins with LDO regulator

Enabled for 3 V Out

of 20 mA source current in all I/Os.

High output voltage

Port 1 pins with LDO enabled for of 20 mA source current in all I/Os.

2.5 V Out

I

< 10 A, Vdd > 2.7 V, maximum

2.50

–

2.75

–

OH

High output voltage

Port 1 pins with LDO enabled for of 20 mA source current in all I/Os.

2.5 V Out

I

= 2 mA, Vdd > 2.7 V, maximum

OH

High output voltage

Port 1 pins with LDO enabled for of 20 mA source current in all I/Os.

1.8 V Out

I

< 10 A, Vdd > 2.7 V, maximum

1.80

–

2.1

–

OH

High output voltage

Port 1 pins with LDO enabled for of 20 mA source current in all I/Os.

1.8 V Out

I

= 1 mA, Vdd > 2.7 V, maximum

OH

Low output voltage

I

= 25 mA, Vdd > 3.3 V, maximum

–

0.75

OL

of 60 mA sink current on even port

pins (for example, P0[2] and P1[4])

and 60 mA sink current on odd port

pins (for example, P0[3] and P1[5]).

V

I

Input low voltage

–

2.00

–

0.80

V

IL

IH

H

Input high voltage

–

Input hysteresis voltage

Input leakage (absolute value)

Pin capacitance

80

1

mV

n

pF

–

1000

5

IL

C

Package and pin dependent.

Temp = 25 °C.

0.5

1.7

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CY7C69356

Table 6. DC Characteristics – USB Interface

Symbol

Rusbi

Description

USB D+ pull-up resistance

Static output high

Conditions

With idle bus

Min

0.900

1.425

2.8

Typ

–

Max

1.575

3.090

3.6

Units

k

V

Rusba

Vohusb

Volusb

Vdi

While receiving traffic

–

Static output low

–

0.3

V

Differential input sensitivity

0.2

–

V

Vcm

Differential input common mode

range

0.8

–

2.5

V

Vse

Cin

Single ended receiver threshold

Transceiver capacitance

0.8

–

2.0

50

V

pF

A



Iio

Hi-Z state data line leakage

PS/2 pull-up resistance

On D+ or D- line

–10

3000

21.78

–

+10

Rps2

Rext

5000

22.0

7000

22.22

External USB series resistor

In series with each USB pin



DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 7. DC Analog Mux Bus Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

R

Switch resistance to common

analog bus

–

800



SW

Resistance of initialization switch

to Vss

–

800



GND

The maximum pin voltage for measuring R

and R

is 1.8 V with PUMP on.

GND

SW

Comparator User Module Electrical Specifications

The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the

entire device voltage and temperature operating range: –40 °C  TA  85 °C, 3 V  Vdd  5.5 V.

Table 8. Comparator User Module Electrical Specifications

Symbol

Description

Conditions

50 mV overdrive

Min

–

Typ

70

Max

100

30

Units

ns

T

Comparator response time

COMP

Offset

–

2.5

20

mV

µA

Current

Average DC current, 50 mV

overdrive

–

80

Supply voltage >2 V

Supply voltage <2 V

Power supply rejection ratio

–

0

80

40

–

dB

V

PSRR

Input Range

1.5

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CY7C69356

ADC Electrical Specifications

Table 9. ADC User Module Electrical Specifications

Symbol

Input

Description

Conditions

Min

Typ

Max

Units

V

Input voltage range

0

–

V

pF



IN

REFADC

C

R

Input capacitance

Input resistance

5

IIN

IN

Equivalent switched capacitance

1/(500 fF × 1/(400 fF × 1/(300 fF ×

input resistance for 8-, 9-, or 10-bit data clock) data clock) data clock)

resolution

Reference

V

ADC reference voltage

1.14

2.25

–

1.26

6

V

REFADC

Conversion Rate

F

Data clock

Source is chip’s internal main

oscillator. See AC Chip-Level

Specifications on page 18 for

accuracy

MHz

CLK

S8

8-bit sample rate

10-bit sample rate

Data clock set to 6 MHz. Sample

rate = 0.001/ (2^resolution/data

clock)

–

23.43

5.85

–

ksps

S10

Data clock set to 6 MHz. Sample

rate = 0.001/ ((2^resolution/data

clock)

DC Accuracy

RES

Resolution

Can be set to 8-, 9-, or 10-bit

8

–1

–2

0

–

10

+2

bits

LSB

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

INL

–

+2

E

8-bit resolution

3.2

12.8

–

19.2

76.8

+5

Offset

gain

10-bit resolution

For any resolution

0

E

Gain error

–5

%FS

R

Power

I

Operating current

–

2.1

24

30

2.6

–

mA

dB

ADC

PSRR

Power supply rejection ratio

PSRR (Vdd > 3.0 V)

PSRR (Vdd < 3.0 V)

–

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 10. DC Comparator Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V

I

Low power comparator (LPC)

common mode

Maximum voltage limited to Vdd.

0.0

–

1.8

V

LPC

LPC supply current

LPC voltage offset

–

10

40

30

A

LPC

V

2.5

mV

OSLPC

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CY7C69356

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 11. DC POR and LVD Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V

value for PPOR trip

V

must be greater than or equal

DD

to 1.71 V during startup, reset from

the XRES pin, or reset from

watchdog.

V

PORLEV[1:0] = 00b, HPOR = 0

PORLEV[1:0] = 00b, HPOR = 1

PORLEV[1:0] = 01b, HPOR = 1

PORLEV[1:0] = 10b, HPOR = 1

1.61

1.66

2.36

2.60

2.82

1.71

2.41

2.66

2.95

V

PPOR0

–

PPOR1

PPOR2

PPOR3

V

value for LVD trip

DD

[7]

V

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

2.40

2.64

2.85

2.45

2.71

2.92

3.02

3.13

1.90

1.80

4.73

2.51

2.78

2.99

3.09

3.20

2.32

1.84

4.83

V

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

[8]

[9]

2.95

3.06

1.84

[10]

1.75

4.62

Notes

7. Always greater than 50 mV above V

8. Always greater than 50 mV above V

9. Always greater than 50 mV above V

10. Always greater than 50 mV above V

voltage for falling supply.

PPOR1

PPOR2

PPOR3

PPOR0

voltage for falling supply.

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CY7C69356

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 12. DC Programming Specifications

Symbol

Vdd

Description

Conditions

Min

Typ

Max

Units

Supply voltage for flash write

operations

1.71

–

5.25

V

IWRITE

I

Supply current during

programming or verify

–

5

–

25

mA

V

DDP

V

Input low voltage during

programming or verify

See appropriate DC General

Purpose I/O Specifications.

V

IL

ILP

Input high voltage during

programming or verify

See appropriate DC General

Purpose I/O Specifications.

V

–

V

IHP

IH

I

Input current when applying V

to P1[0] or P1[1] during

programming or verify

Driving internal pull down resistor.

–

0.2

1.5

mA

ILP

I

Input current when applying V

to P1[0] or P1[1] during

programming or verify

Driving internal pull down resistor.

–

mA

IHP

V

Output low voltage during

programming or verify

–

Vss + 0.75

Vdd

V

OLP

Output high voltage during

programming or verify

See appropriate DC General

Purpose I/O Specifications.

V

OH

OHP

For Vdd > 3 V use V

on page 13.

in Table 5

OH4

Flash

Flash write endurance

Flash data retention

Erase/write cycles per block.

50,000

20

–

Cycles

Years

ENPB

Following maximum flash write

cycles,

DR

ambient temperature of 55 °C

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CY7C69356

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 13. AC Chip-Level Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

F

Internal main oscillator frequency –

at 24 MHz Setting

22.8

24

25.2

MHz

IMO24

Internal main oscillator frequency –

at 12 MHz setting

11.4

5.7

12

12.6

6.3

MHz

IMO12

IMO6

Internal main oscillator frequency –

at 6 MHz setting

6.0

F

CPU frequency

–

5.7

19

–

25.20

50

MHz

kHz

CPU

Internal low speed oscillator

frequency

32

32K1

F

Internallowspeedoscillator(ILO) –

untrimmed frequency)

13

32

82

kHz

32K_U

DC

Duty cycle of IMO

–

40

50

60

%

IMO

Internal low speed oscillator duty –

cycle

ILO

SR

Power supply slew rate

V

slew rate during power-up

–

1

–

250

–

V/ms

ms

POWER_UP

DD

t

External reset pulse width at

power-up

After supply voltage is valid

XRST

t

External reset pulse width after Applies after part has booted

power-up

10

–

s

XRST2

[11]

AC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 14. AC GPIO Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

F

GPIO operating frequency

Normal strong mode,

Port 1.

0

–

12 MHz for

3 V < Vdd < 5.5 V

MHz

GPIO

TRise23

TRise01

Rise time, strong mode,

Cload = 50 pF, Ports 2 or 3

Vdd = 3.0 to 3.6 V,

10%–90%

15

10

–

80

50

ns

Rise time, strong mode,

Cload = 50 pF, Ports 0 or 1

Vdd = 3.0 to 3.6 V,

10%–90%.

LDO enabled or

disabled.

TFall

Fall time, strong mode,

Cload = 50 pF, All ports

Vdd = 3.0 to 3.6 V,

10%–90%

10

–

50

ns

Note

11. The minimum required XRES pulse length is longer when programming the device (see Table 22 on page 24).

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CY7C69356

Figure 8. GPIO Timing Diagram

90%

GPIO Pin

Output

Voltage

10%

TRise23

TRise01

TRise23L

TRise01L

TFall

TFallL

Table 15. AC Characteristics – USB Data Timings

Symbol

Tdrate

Description

Full speed data rate

Conditions

Average bit rate

Min

12 – 0.25%

–18.5

–9

Typ

12

–

Max

Units

12 + 0.25% MHz

Tdjr1

Receiver data jitter tolerance

Driver differential jitter

To next transition

To pair transition

To next transition

To pair transition

To SE0 transition

18.5

9

ns

Tdjr2

–

Tudj1

Tudj2

Tfdeop

–3.5

–

3.5

4.0

5

–4.0

–

Source jitter for differential

transition

–2

–

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

Receiver SE0 interval of EOP

160

82

–

175

14

ns

Width of SE0 interval during

differential transition

Table 16. AC Characteristics – USB Driver

Symbol Description

Transition rise time

Conditions

Min

4

Typ

–

Max

20

Units

ns

Tr

50 pF

Tf

Transition fall time

4

–

20

ns

TR

Rise/fall time matching

Output signal crossover voltage

90.00

1.3

–

111.1

2.0

%

Vcrs

–

V

AC Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 17. AC Low Power Comparator Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

T

Comparator response time, 50

mV Overdrive

50 mV overdrive does not include

offset voltage.

–

100

ns

LPC

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CY7C69356

AC External Clock Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 18. AC External Clock Specifications

Symbol

Description

Frequency

Conditions

Min

0.75

20.60

150

Typ

–

Max

25.20

5300

–

Units

MHz

ns

F

–

OSCEXT

High period

–

Low period

–

ns

Power up IMO to switch

–

s

Figure 9. AC Waveform

SCLK (P1[1])

T_RSCLK

T_FSCLK

SDATA (P1[0])

T_SSCLK

T_HSCLK

T_DSCLK

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 19. AC Programming Specifications

Symbol

Description

Rise time of SCLK

Conditions

Min

1

Typ

–

Max

20

–

Units

ns

T

RSCLK

Fall time of SCLK

1

–

ns

FSCLK

SSCLK

Data setup time to falling edge of

SCLK

40

–

ns

T

Data hold time from falling edge

of SCLK

40

–

ns

HSCLK

F

T

Frequency of SCLK

0

–

8

MHz

ms

ns

SCLK

Flash erase time (block)

Flash block write time

18

25

60

ERASEB

WRITE

DSCLK

Data out delay from falling edge 3.6  V

of SCLK

DD

T

Data out delay from falling edge 1.71 ≤ V ≤ 3.0

of SCLK

–

130

85

–

ns

s

DSCLK2

DSCLK3

XRST3

DD

Data out delay from falling edge 3.0  V  3.6

DD

of SCLK

External reset pulse width after Required to enter programming

263

power up

mode when coming out of sleep

T

XRES pulse length

300

0.1

–

1

s

XRES

V

stable to wait-and-poll hold

ms

VDDWAIT

DD

off

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Document Number: 001-86334 Rev. *B

Page 20 of 31

CY7C69356

Table 19. AC Programming Specifications (continued)

Symbol

Description

Conditions

Min

Typ

Max

Units

T

V

delay

stable to XRES assertion

14.27

–

ms

VDDXRES

DD

SDATA high pulse time

“Key window” time after a V

0.01

3.20

–

200

ms

POLL

T

19.60

ACQ

DD

ramp acquire event, based on

256 ILO clocks.

T

“Key window” time after an XRES

event, based on 8 ILO clocks

98

–

615

s

XRESINI

AC SPI Specifications

Table 20. SPI Master AC Specifications

Symbol

Description

SCLK clock frequency

SCLK duty cycle

Conditions

Min

–

Typ

Max

6

Units

MHz

%

F

V

3 V

 3 V

SCLK

DD

DC

T

–

50

–

MISO to SCLK setup time

SCLK to MISO hold time

SCLK to MOSI valid time

MOSI high time

60

40

–

ns

SETUP

DD

T

–

ns

HOLD

–

40

–

ns

OUT_VAL

40

–

ns

OUT_HIGH

Figure 10. SPI Master Mode 0 and 2

SPI Master, modes 0 and 2

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_SETUP

T_HOLD

MISO

(input)

LSB

MSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

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CY7C69356

Figure 11. SPI Master Mode 1 and 3

SPI Master, modes 1 and 3

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_SETUP

T_HOLD

MISO

(input)

MSB

LSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

LSB

MSB

Table 21. SPI Slave AC Specifications

Symbol

Description

SCLK clock frequency

SCLK low time

Conditions

Min

Typ

Max

12

–

Units

MHz

ns

F

T

V

 3 V

–

SCLK

DD

42

30

50

–

LOW

SCLK high time

–

ns

HIGH

MOSI to SCLK setup time

SCLK to MOSI hold time

SS high to MISO valid

SCLK to MISO valid

SS high time

–

ns

SETUP

–

ns

HOLD

153

125

–

ns

SS_MISO

SCLK_MISO

SS_HIGH

SS_CLK

CLK_SS

–

ns

50

ns

Time from SS low to first SCLK

Time from last SCLK to SS high

2/SCLK

–

ns

–

ns

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CY7C69356

Figure 12. SPI Slave Mode 0 and 2

SPI Slave, modes 0 and 2

T_{SS_HIGH}

T_{CLK_SS}

T_{SS_CLK}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_{OUT_H}

T_{SS_MISO}

MISO

(output)

T_SETUP

T_HOLD

MOSI

(input)

LSB

MSB

Figure 13. SPI Slave Mode 1 and 3

SPI Slave, modes 1 and 3

T_{SS_CLK}

T_{CLK_SS}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_{OUT_H}

T_{SCLK_MISO}

T_{SS_MISO}

MISO

(output)

MSB

LSB

T_SETUP

T_HOLD

MOSI

(input)

MSB

LSB

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CY7C69356

2

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 22. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Fast Mode

Symbol

Description

Conditions

Units

Min

0

Max

100

–

Min

Max

400

–

f

t

SCL clock frequency

0

kHz

SCLI2C

Hold time (repeated) START

condition. After this period, the

first clock pulse is generated.

4.0

0.6

s

HDSTAI2C

t

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

4.7

–

1.3

0.6

–

s

LOWI2C

HIGHI2C

SUSTAI2C

Setup time for a repeated START

condition

t

Data hold time

0

3.45

0

0.90

s

ns

s

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

[12]

Data setup time

250

4.0

4.7

–

100

–

Setup time for STOP Condition

0.6

1.3

Bus free time between a STOP

and START Condition

t

Pulse width of spikes are

suppressed by the input filter.

–

0

50

ns

SPI2C

Figure 14. Definition for Timing for Fast/Standard Mode on the I²C Bus

Note

12. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t

 250 ns must then be met. This automatically be the case

SU;DAT

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t

+ t

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax

SU;DAT

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Document Number: 001-86334 Rev. *B

Page 24 of 31

CY7C69356

Packaging Information

This section illustrates the packaging specifications for the CY7C69356 PSoC device, along with the thermal impedances for each

package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled

PSoC Emulator Pod Dimensions

at

http://www.cypress.com/design/MR1016

Figure 15. 48-pin QFN (7 × 7 × 1.0 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191

001-13191 *H

Important Note

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

■ Pinned vias for thermal conduction are not required for the low power PSoC device.

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Page 25 of 31

CY7C69356

Thermal Impedances

Table 23. Thermal Impedances per Package

Package

[13]

Typical _JA

[14]

48-pin QFN

18 °C/W

Capacitance on Crystal Pins

Table 24. Typical Package Capacitance on Crystal Pins

Package

Package Capacitance

48-pin QFN

3.3 pF

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 25. Solder Reflow Peak Temperature

[15]

Package

Minimum Peak Temperature

Maximum Peak Temperature

48-pin QFN

240 °C

260 °C

Notes

13. T = T + Power x  .

JA

J

A

14. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.

15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

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Page 26 of 31

CY7C69356

Development Tool Selection

This section presents the development tools available for the CY7C69356 family.

Software

Device Programmers

All device programmers are available for purchase from The

Cypress Store. For programming during development, use:

PSoC Designer

At the core of the PSoC development software suite is PSoC

Designer. Used by thousands of PSoC developers, this robust

software has made designing with PSoC easy for half a decade.

TrueTouch products require a dedicated PSoC Designer

installer. Contact your local sales representative or send your

request to tsbusdev@cypress.com.

■ MiniProg1 Programming Unit (does not support debug

monitor). It is available for purchase through the Cypress online

store as part of kit:CY3210-MiniProg1.

■ MiniProg3 Programming Unit (supports debug monitor). It is

available for purchase through the Cypress online store as part

of kit:CY8CKIT-002.

PSoC Programmer

PSoC Programmer is flexible enough to be used on the bench in

development, yet suitable for factory programming. It works as a

standalone programming application, or it can operate directly

from PSoC Designer. PSoC Programmer software is compatible

with PSoC MiniProg. PSoC programmer is available free of

charge at http://www.cypress.com/psocprogrammer.

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

Development Kits

Under development.

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Document Number: 001-86334 Rev. *B

Page 27 of 31

CY7C69356

Ordering Information

The following table lists the CY7C69356 PSoC devices key package features and ordering codes.

Table 26. PSoC Device Key Features and Ordering Information

Flash SRAM TrueTouch Digital I/O Analog XRES

Package

Ordering Code

USB

(KB) (Bytes)

Blocks

Pins

Inputs

[16]

48-pin (7 × 7 mm) QFN

CY7C69356-48LTXC

32 2048

1

36

Yes

Ordering Code Definitions

CY

48LT

X

7

C

69 356 -

X

C

X = blank or T

blank = Tube; T = Tape and Reel

Temperature Range:

C = Commercial grade

X = Pb-free

Package Type:

48LT = 48-pin QFN

Part Number

Family Code: 69 = Full Speed USB

Technology Code: C = CMOS

Marketing Code: 7 = Cypress Products

Company ID: CY = Cypress

Notes

16. Dual-function Digital I/O pins also connect to the common analog mux.

17. This part may be used for in-circuit debugging. It is NOT available for production.

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Document Number: 001-86334 Rev. *B

Page 28 of 31

CY7C69356

Acronyms

Document Conventions

Table 27. Acronyms used

Acronym

Units of Measure

Description

Table 28. Units of Measure

AC

alternating current

Symbol

°C

Unit of Measure

API

application programming interface

central processing unit

direct current

degree Celsius

decibels

dB

CPU

DC

fF

femto farad

hertz

Hz

GPIO

GUI

ICE

general purpose I/O

graphical user interface

in-circuit emulator

KB

Kbit

kHz

k

MHz

M

A

F

1024 bytes

1024 bits

kilohertz

ILO

internal low speed oscillator

internal main oscillator

input/output

kilohm

IMO

I/O

megahertz

megaohm

LSb

LVD

MSb

POR

PPOR

least-significant bit

microampere

microfarad

low voltage detect

most-significant bit

H

s

microhenry

power on reset

microsecond

microvolts

precision power on reset

Programmable System-on-Chip

slow IMO

V

Vrms

ksps

W

mA

ms

mV

nA

®

PSoC

SLIMO

SRAM

FSR

microvolts root-mean-square

kilo samples per second

microwatts

static random access memory

full scale range

milli-ampere

milli-second

milli-volts

nanoampere

nanosecond

nanovolts

ns

nV

W

ohm

pA

picoampere

picofarad

pF

pp

peak-to-peak

parts per million

picosecond

samples per second

sigma: one standard deviation

volts

ppm

ps

sps

s

V

Numeric Naming

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, 01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are

decimal.

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CY7C69356

Document History Page

Document Title: CY7C69356, TrueTouch^®Multi-Touch Gesture Full Speed USB Controller

Document Number: 001-86334

Origin of Submission

Revision

ECN #

Description of Change

Change

Date

*B

5222044

SKUV

04/15/2016 Changed status from Preliminary to Final.

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Document Number: 001-86334 Rev. *B

Page 30 of 31

CY7C69356

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

ARM Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Lighting & Power Control

Memory

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United

States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

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Document Number: 001-86334 Rev. *B

Revised April 15, 2016

Page 31 of 31

TrueTouch™ and PSoC Designer™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.

2

Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided

2

that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.


型号：	CY7C69356-48LTXC
厂家：	CYPRESS
描述：	USB Bus Controller, CMOS, QFN-48 时钟数据传输外围集成电路
文件：	总31页 (文件大小：2872K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C69356-48LTXC [CYPRESS]

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