CY7S1049GE18 [CYPRESS]
4-Mbit (512K words à 8 bit) Static RAM with PowerSnooze⢠and Error Correcting Code (ECC);
| 型号： | CY7S1049GE18 |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (512K words à 8 bit) Static RAM with PowerSnooze⢠and Error Correcting Code (ECC) |
| 文件： | 总21页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7S1049G
CY7S1049GE
4-Mbit (512K words × 8 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (512K words
× 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
embedded ECC. logic which can detect and correct single-bit
errors in the accessed location.
Features
■ High speed
❐ Access time (tAA) = 10 ns / 15 ns
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
■ Ultra-low power Deep-Sleep (DS) current
❐ IDS = 15 µA
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O7) and address pins (A0
through A18) respectively.
■ Low active and standby currents
❐ Active Current ICC = 38-mA typical
❐ Standby Current ISB2 = 6-mA typical
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O7).
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
The CY7S1049G is available in 44-pin TSOP II, and 36-pin
Molded SOJ (400 Mils).
■ Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)
molded SOJ
Functional Description
The CY7S1049G/CY7S1049GE is
a
high-performance
PowerSnooze™ static RAM organized as 512K words × 8 bits.
This device features fast access times (10 ns) and a unique
ultra-low power Deep-Sleep mode. With Deep-Sleep mode
currents as low as 15 µA, the CY7S1049G/CY7S1049GE
devices combine the best features of fast and low- power SRAMs
in industry-standard package options. The device also features
Product Portfolio
Power Dissipation
Operating ICC
,
Speed
(ns)
Standby, ISB2
Deep-Sleep
current (µA)
Product [1]
Range
VCC Range (V)
(mA)
(mA)
f = fmax
Typ [2] Max Typ [2] Max Typ [2] Max
CY7S1049G(E)18 Industrial
CY7S1049G(E)30
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
15
10
10
–
40
45
45
6
8
–
15
38
38
CY7S1049G(E)
Notes
1. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC
CC
A
Cypress Semiconductor Corporation
Document Number: 001-95414 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 18, 2016
CY7S1049G
CY7S1049GE
Logic Block Diagram – CY7S1049G
DATAIN
DRIVERS
ECC ENCODER
A0
A1
A2
A3
I/O0‐I/O7
512K x 8
RAM ARRAY
A4
A5
A6
A7
A8
A9
COLUMN
DECODER
WE
OE
CE
Power Management
Block
DS
Logic Block Diagram – CY7S1049GE
DATAIN
DRIVERS
ECC ENCODER
A0
A1
A2
A3
I/O0‐I/O7
ERR
512K x 8
RAM ARRAY
A4
A5
A6
A7
A8
A9
COLUMN
DECODER
WE
OE
CE
Power Management
Block
DS
Document Number: 001-95414 Rev. *C
Page 2 of 21
CY7S1049G
CY7S1049GE
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................8
Data Retention Characteristics .......................................9
Data Retention Waveform ................................................9
Deep-Sleep Mode Characteristics .................................10
AC Switching Characteristics .......................................11
Switching Waveforms ....................................................12
Truth Table ......................................................................16
ERR Output – CY7S1049GE ...........................................16
Ordering Information ......................................................17
Ordering Code Definitions .........................................17
Package Diagrams ..........................................................18
Acronyms ........................................................................19
Document Conventions .................................................19
Units of Measure .......................................................19
Document History Page .................................................20
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC® Solutions ......................................................21
Cypress Developer Community .................................21
Technical Support .....................................................21
Document Number: 001-95414 Rev. *C
Page 3 of 21
CY7S1049G
CY7S1049GE
Pin Configurations
Figure 1. 44-pin TSOP II pinout without ERR [3]
NC
NC
A0
1
2
3
4
5
6
7
8
9
44 NC
NC
43
42
41
40
DS
A1
A18
A17
A2
A3
39 A16
38 A15
37 /OE
36 I/O7
35 I/O6
34 VSS
A4
/CE
I/O0
44-pin TSOP II
I/O1 10
VCC 11
VSS
I/O2
I/O3
/WE
VCC
I/O5
I/O4
A14
12
13
14
15
33
32
31
30
A5 16
29 A13
A6
A7
A8
A9
NC
NC
A12
A11
A10
NC
17
18
19
20
21
22
28
27
26
25
24
23
NC
NC
Figure 2. 44-pin TSOP II pinout with ERR [3, 4]
NC
NC
A0
1
2
3
4
5
6
7
8
9
44 NC
NC
43
42
41
40
DS
A1
A18
A17
A2
A3
39 A16
38 A15
37 /OE
36 I/O7
35 I/O6
34 VSS
A4
/CE
I/O0
44-pin TSOP II
I/O1 10
VCC 11
VSS
I/O2
I/O3
/WE
VCC
I/O5
I/O4
A14
12
13
14
15
33
32
31
30
A5 16
29 A13
A6
A7
A8
A9
NC
NC
A12
A11
A10
NC
17
18
19
20
21
22
28
27
26
25
24
23
ERR
NC
Notes
3. NC pins are not connected internally to the die.
4. ERR is an output pin.
Document Number: 001-95414 Rev. *C
Page 4 of 21
CY7S1049G
CY7S1049GE
Pin Configurations (continued)
Figure 3. 36-pin SOJ pinout without ERR [5]
A0
A1
1
2
3
4
5
6
7
8
9
36 DS
35 A18
34 A17
A2
A3
A16
A15
OE
33
32
31
A4
CE
I/O0
I/O1
VCC
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
25 I/O4
GND 10
I/O2 11
I/O3 12
SOJ
WE
A5
A6
A7
A8
A9
A14
A13
A12
A11
A10
NC
13
14
15
16
17
18
24
23
22
21
20
19
Figure 4. 36-pin SOJ pinout with ERR [5, 6]
A0
A1
DS
A18
A17
A16
1
2
3
4
5
6
7
8
9
36
35
34
33
A2
A3
A4
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
CE
I/O0
I/O1
VCC
GND 10
SOJ
I/O2
I/O3
WE
A5
I/O5
I/O4
A14
A13
11
12
13
14
15
16
17
18
26
25
24
23
A6
22 A12
A7
A11
A10
21
20
19
A8
A9
ERR
Notes
5. NC pins are not connected internally to the die.
6. ERR is an output pin.
Document Number: 001-95414 Rev. *C
Page 5 of 21
CY7S1049G
CY7S1049GE
DC input voltage [7] ............................. –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current ....................................................> 140 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage on VCC
Range
Ambient Temperature
VCC
relative to GND [7] ...............................–0.5 V to VCC + 0.5 V
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC voltage applied to outputs
in HI-Z State [7] ...................................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to +85 C
10 ns/ 15 ns
Parameter
Description
Test Conditions
Unit
Min
Typ [8]
Max
VOH
Output HIGH 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
voltage
1.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
38
–
–
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2
–
V
CC = Min, IOH = –4.0 mA
VCC = Min, IOH = –4.0 mA
CC = Min, IOH = –0.1 mA
2.2
–
V
2.4
VCC – 0.5 [9]
–
–
V
VOL
Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
V
V
V
–
–
–
–
–
–
–
–
CC = Min, IOL = 2 mA
CC = Min, IOL = 8 mA
CC = Min, IOL = 8 mA
0.4
V
V
V
–
0.4
–
0.4
[7, 10]
VIH
Input HIGH
voltage
1.4
2
VCC + 0.2
V
V
CC + 0.3
CC + 0.3
2
2.2
–0.2
–0.3
–0.3
–0.5
–1
–1
–
VCC + 0.5
0.4
[7, 10]
VIL
Input LOW
voltage
0.6
0.8
0.8
IIX
Input leakage current
Output leakage current
GND < VIN < VCC
+1
A
A
IOZ
ICC
GND < VOUT < VCC, Output disabled
+1
VCC = Max,
OUT = 0 mA,
CMOS levels
f = 100 MHz
f = 66.7 MHz
45
VCC operating supply current
Standby current – TTL inputs
I
mA
mA
–
40
ISB1
Max VCC, CE > VIH,
IN > VIH or VIN < VIL, f = fMAX
–
–
15
V
Notes
7. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 2 ns.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
9. Guaranteed by design and not tested.
10. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V.
Document Number: 001-95414 Rev. *C
Page 6 of 21
CY7S1049G
CY7S1049GE
DC Electrical Characteristics (continued)
Over the Operating Range of –40 C to +85 C
10 ns/ 15 ns
Parameter
Description
Test Conditions
Unit
Min
Typ [8]
Max
ISB2
Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V,
DS > VCC – 0.2 V,
–
6
8
mA
µA
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
Max VCC, CE> VCC –0.2 V, DS< 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V, f = 0
IDS
Deep-Sleep current
–
–
15
V
Capacitance
Parameter [11]
Description
Input capacitance
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC(typ)
All packages Unit
CIN
10
10
pF
pF
COUT
Thermal Resistance
36-pin SOJ 44-pin TSOP II
Package
Parameter [11]
Description
Test Conditions
Unit
Package
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
59.52
31.48
68.85
15.97
C/W
JC
Thermal resistance
(junction to case)
C/W
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-95414 Rev. *C
Page 7 of 21
CY7S1049G
CY7S1049GE
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [12]
HI-Z Characteristics:
VCC
Output
R1
50
Output
VTH
Z = 50
R2
30 pF*
0
5 pF*
* Including
JIG and
Scope
(a)
(b)
* Capacitive Load Consists
of all Components of the
Test Environment
All Input Pulses
V
HIGH
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Parameters
R1
1.8 V
1667
1538
VCC/2
1.8
3.0 V
317
351
1.5
5.0 V
Unit
317
351
1.5
R2
VTH
V
VHIGH
3.0
3.0
V
Note
12. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization.
Document Number: 001-95414 Rev. *C
Page 8 of 21
CY7S1049G
CY7S1049GE
Data Retention Characteristics
Over the Operating Range of –40C to +85 C
Parameter
VDR
Description
Conditions [13]
Min
Max
Unit
VCC for data retention
–
1.0
–
V
VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V,
ICCDR
Data retention current
–
0
8
–
mA
ns
VIN > VCC – 0.2 V or VIN < 0.2 V
Chip deselect to data retention
time
–
[14]
tCDR
2.2 V < VCC < 5.5 V
VCC < 2.2 V
10
15
–
–
ns
ns
[14, 15]
tR
Operation recovery time
Data Retention Waveform
Figure 6. Data Retention Waveform [15]
DATA RETENTION MODE
VDR = 1.0 V
VCC
VCC(min)
tCDR
VCC(min)
tR
CE
Notes
13. DS signal must be HIGH during Data Retention Mode.
14. These parameters are guaranteed by design.
15. Full-device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s.
Document Number: 001-95414 Rev. *C
Page 9 of 21
CY7S1049G
CY7S1049GE
Deep-Sleep Mode Characteristics
Over the Operating Range of –40 C to +85 C
Parameter
IDS
Description
Conditions
Min
Max
Unit
VCC = VCC (max), DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Deep-Sleep mode current
–
15
µA
Minimum time for DS to be LOW
for part to successfully exit –
Deep-Sleep mode
[16]
tPDS
100
–
–
1
ns
DS assertion to Deep-Sleep
[17]
tDS
–
ms
mode transition time
If tPDS > tPDS(min)
If tPDS < tPDS(min)
If tPDS > tPDS(min)
If tPDS < tPDS(min)
–
–
100
0
s
s
[16]
tDSCD
DS deassertion to chip disable
DS deassertion to chip access
(Active/Standby)
tDSCA
300
–
s
Figure 7. Active, Standby, and Deep-Sleep Operation Modes
Chip
Access
Allowed
Not Allowed
Allowed
ENABLE/
DISABLE
ENABLE/
DISABLE
CE
DS
DON’T CARE
tPDS
DISABLE
tDS
tDSCD
tDSCA
Active/Standby
Mode
Standby
Mode
Active/Standby
Mode
Standby
Mode
Mode
Deep Sleep Mode
Note
16. CE must be pulled HIGH within tDSCD time of DS de-assertion to avoid SRAM data loss.
17. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted
to logic level LOW to keep the device in Deep-Sleep mode.
Document Number: 001-95414 Rev. *C
Page 10 of 21
CY7S1049G
CY7S1049GE
AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
10 ns
15 ns
Unit
Parameter [18]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
10
–
3
–
–
0
–
3
–
0
–
–
10
–
15
–
3
–
–
0
–
3
–
0
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
tACE
10
4.5
–
15
8
tDOE
OE LOW to data valid
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to low impedance [19, 20, 21]
OE HIGH to HI-Z [19, 20, 21]
CE LOW to low impedance [19, 20, 21]
CE HIGH to HI-Z [19, 20, 21]
CE LOW to power-up [21]
CE HIGH to power-down [21]
–
5
8
–
–
5
8
–
–
tPD
10
15
Write Cycle [22, 23]
tWC
tSCE
tAW
Write cycle time
10
7
7
0
0
7
5
0
3
–
–
–
–
–
–
–
–
–
–
5
15
12
12
0
–
–
–
–
–
–
–
–
–
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
12
8
Data setup to write end
tHD
Data hold from write end
WE HIGH to low impedance [19, 20, 21]
WE LOW to HI-Z [19, 20, 21]
0
tLZWE
tHZWE
3
–
Notes
18. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Testconditions fortheread cycleuseoutput loadingshownin part(a)ofFigure5onpage8, unlessspecifiedotherwise.
19. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage.
20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
21. These parameters are guaranteed by design.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
23. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be the sum of tHZWE and tSD
.
Document Number: 001-95414 Rev. *C
Page 11 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY7S1049G (Address Transition Controlled) [24, 25, 26]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 9. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [24, 25, 26]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
DATAOUT VALID
VALID
DATA I/O
ERR
tAA
tOHA
PREVIOUS ERR VALID
ERR VALID
Notes
24. The device is continuously selected. OE = VIL, CE = VIL.
25. WE is HIGH for read cycle.
26. DS is HIGH for chip access.
Document Number: 001-95414 Rev. *C
Page 12 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 10. Read Cycle No. 3 (OE Controlled) [27, 28, 29]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
HIGH
HIGH IMPEDANCE
tLZCE
tPU
DATA I /O
DATA OUT VALID
IMPEDANCE
VCC
SUPPLY
CURRENT
ISB
Notes
27. WE is HIGH for read cycle.
28. Address valid prior to or coincident with CE LOW transition.
29. DS must be HIGH for chip access
Document Number: 001-95414 Rev. *C
Page 13 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 11. Write Cycle No. 1 (CE Controlled) [30, 31, 32]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
OE
tHZOE
tHD
tSD
DATA I/O
DATAIN VALID
Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [30, 31, 32, 33]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
DATA I/O
DATAIN VALID
Notes
30. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
31. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
32. DS must be HIGH for chip access.
33. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD
.
Document Number: 001-95414 Rev. *C
Page 14 of 21
CY7S1049G
CY7S1049GE
Switching Waveforms (continued)
Figure 13. Write Cycle No. 3 (WE Controlled) [34, 35, 36]
tW C
A D D R E S S
tS C E
C E
tA W
tS A
tH A
tP W E
W E
O E
tH Z O E
tH D
tS D
D A T A I/O
D A T A IN V A LID
Note 37
Notes
34. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
35. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL.
36. DS must be HIGH for chip access.
37. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-95414 Rev. *C
Page 15 of 21
CY7S1049G
CY7S1049GE
Truth Table
DS CE OE WE I/O0–I/O7
Mode
Power
Standby (ISB
H
H
H
L
L
L
X
X[38] X[38] HIGH-Z
Standby
)
L
X
H
X
H
L
Data out
Data in
HI-Z
Read all bits
Write all bits
Active (ICC
Active (ICC
Active (ICC
)
)
)
H
H
H
X
Selected, outputs disabled
Deep-Sleep
L[39]
HI-Z
Deep-Sleep Ultra Low Power
(IDS
)
ERR Output – CY7S1049GE
Output [40]
Mode
0
1
Read operation, no single-bit error in the stored data.
Read operation, single-bit error detected and corrected.
Device deselected / outputs disabled / Write operation
High-Z
Notes
38. The input voltage levels on these pins should be either at VIH or VIL.
39. VIL on DS must be < 0.2 V.
40. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-95414 Rev. *C
Page 16 of 21
CY7S1049G
CY7S1049GE
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Operating
Range
Ordering Code
Package Type (All Pb-free)
10 2.2 V–3.6 V CY7S1049G30-10VXI
CY7S1049GE30-10VXI
51-85090 36-pin SOJ
Industrial
36-pin SOJ, With ERR pin
Ordering Code Definitions
CY 7
S
1 04 9
G
XX X X
XX - XX
X
Temperature Range: X = I
I = Industrial
Pb-free
Package Type: XX = V
V = 36-pin SOJ
Speed: XX = 10
10 = 10 ns
Voltage Range: XX = 30
30 = 2.2 V to 3.6 V
X = blank or E; blank= without ERR output, E = with ERR pin
Process Technology: Revision Code “G” = 65 nm Technology
Data width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
S = Deep-Sleep feature
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-95414 Rev. *C
Page 17 of 21
CY7S1049G
CY7S1049GE
Package Diagrams
Figure 14. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85090 *G
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-95414 Rev. *C
Page 18 of 21
CY7S1049G
CY7S1049GE
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
chip enable
Symbol
°C
Unit of Measure
CMOS
ECC
I/O
complementary metal oxide semiconductor
error correcting code
input/output
Degrees Celsius
megahertz
microamperes
microseconds
milliamperes
millimeters
nanoseconds
ohms
MHz
A
s
OE
output enable
mA
mm
ns
SOJ
SRAM
TSOP
TTL
small outline J-lead
static random access memory
thin small outline package
transistor-transistor logic
write enable
%
percent
WE
pF
V
picofarads
volts
W
watts
Document Number: 001-95414 Rev. *C
Page 19 of 21
CY7S1049G
CY7S1049GE
Document History Page
DocumentTitle:CY7S1049G/CY7S1049GE, 4-Mbit(512Kwords ×8bit)StaticRAMwithPowerSnooze™and ErrorCorrecting
Code (ECC)
Document Number: 001-95414
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*B
5025315
VINI
11/24/2015 Changed status from Preliminary to Final.
*C
5090263
NILE
01/18/2016 Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
Document Number: 001-95414 Rev. *C
Page 20 of 21
CY7S1049G
CY7S1049GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Memory
Community | Forums | Blogs | Video | Training
Technical Support
PSoC
cypress.com/go/support
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-95414 Rev. *C
Revised January 18, 2016
Page 21 of 21
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相关型号：
CY7S1049GE30
4-Mbit (512K words à 8 bit) Static RAM with PowerSnooze⢠and Error Correcting Code (ECC)
CYPRESS
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