CY8C20346-24LQXI_技术文档

CY8C20X36/46/66/96

CapSense^®Applications

Features

■ 1.71V to 5.5V Operating Range

■ Versatile Analog Mux

❐ Common Internal Analog Bus

❐ Simultaneous Connection of I/O

❐ High PSRR Comparator

❐ Low Dropout Voltage Regulator for All Analog Resources

■ Low Power CapSense^®Block

❐ Configurable Capacitive Sensing Elements

❐ Supports Combination of CapSense Buttons, Sliders,

Touchpads, Touch Screens, and Proximity Sensor

■ Additional System Resources

❐ I2C Slave:

■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds Running to 24 MHz

❐ Low Power at High Speed

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• No Clock Stretching Required (under most conditions)

❐ Interrupt Controller

• Implementation During Sleep Modes with Less Than

100 µA

• Hardware Address Validation

❐ SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz

❐ Three 16-Bit Timers

❐ Watchdog and Sleep Timers

❐ Internal Voltage Reference

❐ Integrated Supervisory Circuit

❐ 8-bit Delta-Sigma Analog-to-Digital Converter

❐ Temperature Range: -40°C to +85°C

■ Flexible On-Chip Memory

❐ Three Program/Data Storage Size Options:

• CY8C20x36: 8K Flash / 1K SRAM

• CY8C20x46, CY8C20x96: 16K Flash / 2K SRAM

• CY8C20x66: 32K Flash / 2K SRAM

❐ 50,000 Flash Erase/Write Cycles

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ In-System Serial Programming (ISSP)

❐ Two General Purpose High Speed, Low Power Analog

Comparators

■ Complete Development Tools

❐ Free Development Tool (PSoC Designer™)

❐ Full Featured, In-Circuit Emulator and Programmer

❐ Full Speed Emulation

❐ Complex Breakpoint Structure

❐ 128K Trace Memory

■ Full Speed USB

❐ Available on CY8C20646, CY8C20666, CY8C20x96 Only

❐ 12 Mbps USB 2.0 Compliant

❐ Eight Unidirectional Endpoints

❐ One Bidirectional Control Endpoint

❐ Dedicated 512 Byte Buffer

❐ Internally Regulated at 3.3V

■ Package Options

■ Precision, Programmable Clocking

❐ CY8C20x36:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

• 48-Pin SSOP

• 48-Pin 7 x 7 x 1.0 mm QFN

❐ CY8C20x46:

• 16-Pin 3 x 3 x 0.6 mm QFN

• 24-Pin 4 x 4 x 0.6 mm QFN

• 32-Pin 5 x 5 x 0.6 mm QFN

• 48-Pin SSOP

❐ Internal Main Oscillator: 6/12/24 MHz ± 5%

❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and

Sleep Timers

❐ Precision 32 kHz Oscillator for Optional External Crystal

❐ 0.25% Accuracy for USB with No External Components

(CY8C20646, CY8C20666, CY8C20x96 only)

■ Programmable Pin Configurations

❐ Up to 36 GPIO (Depending on Package)

❐ Dual Mode GPIO: All GPIO Support Digital I/O and Analog

Input

❐ 25 mA Sink Current on All GPIO

• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)

❐ CY8C20x96:

• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)

• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)

❐ CY8C20x66:

• 32-Pin 5 x 5 x 0.6 mm QFN

• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)

• 48-Pin SSOP

❐ Pull up, High Z, Open Drain Modes on All GPIO

❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:

• 20 mA (at 3.0V) Total Source Current on Port 0

• 20 mA (at 3.0V) Total Source Current on Port 1

❐ Selectable, Regulated Digital I/O on Port 1

❐ Configurable Input Threshold on Port 1

❐ Hot Swap Capability on all Port 1 GPIO

Cypress Semiconductor Corporation

Document Number: 001-12696 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 09, 2009

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Logic Block Diagram

1.8/2.5/3V

LDO

PWRSYS

(Regulator)

Port 4 Port 3

Port 2

Port 1

Port 0

PSoC CORE

SYSTEM BUS

Global Analog Interconnect

8K/16K/32K Flash

1K/2K

SRAM

Supervisory ROM (SROM)

Nonvolatile Memory

Interrupt

Controller

Sleep and

Watchdog

CPU Core (M8C)

6/12/24 MHz Internal Main Oscillator

(IMO)

Internal Low Speed Oscillator (ILO)

Multiple Clock Sources

CAPSENSE

SYSTEM

Analog

Reference

CapSense

Module

Two

Analog

Mux

Comparators

SYSTEM BUS

Internal

Voltage

References

POR

and

LVD

SPI

Master/

Slave

Three 16-Bit

Programmable

Timers

I2C

Slave

System

Resets

Digital

Clocks

USB

SYSTEM RESOURCES

Document Number: 001-12696 Rev. *F

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®

Figure 1. Analog System Block Diagram

PSoC Functional Overview

The PSoC family consists of on-chip Controller devices. These

devices are designed to replace multiple traditional MCU-based

components with one, low cost single-chip programmable

component. A PSoC device includes configurable analog and

digital blocks, and programmable interconnect. This architecture

allows the user to create customized peripheral configurations,

to match the requirements of each individual application.

Additionally, a fast CPU, Flash program memory, SRAM data

memory, and configurable I/O are included in a range of

convenient pinouts.

IDAC

Vr

The architecture for this device family, as shown in the Logic

Block Diagram on page 2, is comprised of three main areas: the

Core, the CapSense Analog System, and the System Resources

(including a full speed USB port). A common, versatile bus allows

connection between I/O and the analog system. Each

CY8C20x36/46/66/96 PSoC Device includes a dedicated

CapSense block that provides sensing and scanning control

circuitry for capacitive sensing applications. Depending on the

PSoC package, up to 36 general purpose IO (GPIO) are also

included. The GPIO provides access to the MCU and analog

mux.

Reference

Buffer

Cinternal

Comparator

Mux

Refs

PSoC Core

CapSenseCounters

CSCLK

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO

(internal main oscillator) and ILO (internal low speed oscillator).

The CPU core, called the M8C, is a powerful processor with

speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard archi-

tecture microprocessor.

CapSense

ClockSelect

IMO

Oscillator

System Resources provide additional capability, such as

configurable USB and I2C slave/SPI master-slave

communication interface, three 16-bit programmable timers, and

various system resets supported by the M8C.

Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin. Pins are

connected to the bus individually or in any combination. The bus

also connects to the analog system for analysis with the

CapSense block comparator.

The Analog System is composed of the CapSense PSoC block

and an internal 1.2V analog reference, which together support

capacitive sensing of up to 36 inputs.

Switch control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

CapSense Analog System

The Analog System contains the capacitive sensing hardware.

Several hardware algorithms are supported. This hardware

performs capacitive sensing and scanning without requiring

external components. Capacitive sensing is configurable on

each GPIO pin. Scanning of enabled CapSense pins are

completed quickly and easily across multiple ports.

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

■ Chip-wide mux that allows analog input from any I/O pin.

■ Crosspoint connection between any I/O pin combinations.

When designing capacitive sensing applications, refer to the

latest signal-to-noise signal level requirements Application

Notes, which can be found under http://www.cypress.com >

Documentation > Application Notes. In general, and unless

otherwise noted in the relevant Application Notes, the minimum

signal-to-noise ratio (SNR) for CapSense applications is 5:1.

Document Number: 001-12696 Rev. *F

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Additional System Resources

Getting Started

System Resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include low voltage detection and

power on reset. The merits of each system resource are listed

here:

The quickest way to understand PSoC silicon is to read this data

sheet and then use the PSoC Designer Integrated Development

Environment (IDE). This data sheet is an overview of the PSoC

integrated circuit and presents specific pin, register, and

electrical specifications.

■ The I2C slave/SPI master-slave module provides 50/100/400

kHz communication over two wires. SPI communication over

three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower

for a slower system clock).

For in depth information, along with detailed programming

details, see the PSoC^®Programmable System-on-Chip™

Technical Reference Manual for CY8C20x36/46/66/96 PSoC

Devices.

■ The I2C hardware address recognition feature reduces the

already low power consumption by eliminating the need for

CPU intervention until a packet addressed to the target device

is received.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device data sheets on the web

at www.cypress.com/psoc.

Application Notes

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR

(Power-On-Reset) circuit eliminates the need for a system

supervisor.

Application notes are an excellent introduction to the wide variety

of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

■ An internal reference provides an absolute reference for capac-

itive sensing.

Development Kits

■ A register-controlled bypass mode allows the user to disable

the LDO.

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet, Digi-

Key, Farnell, Future Electronics, and Newark.

■ Standard Cypress PSoC IDE tools are available for debugging

the CY8C20x36/46/66/96 family of parts. However, the

additional trace length and a minimal ground plane in the Flex-

Pod can create noise problems that make it difficult to debug

the design. A custom bonded On-Chip Debug (OCD) device is

available in an 48-pin QFN package. The OCD device is

recommended for debugging designs that have high current

and/or high analog accuracy requirements. The QFN package

is compact and is connected to the ICE through a high density

connector.

Training

Free PSoC technical training (on demand, webinars, and

workshops) is available online at www.cypress.com/training. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

CYPros Consultants

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to www.cypress.com/cypros.

Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various

application designs that include firmware and hardware design

files that enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase

articles and forums at www.cypress.com/support. If you cannot

find an answer to your question, call technical support at 1-800-

541-4736.

Document Number: 001-12696 Rev. *F

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Development Tools

PSoC Designer is a Microsoft^®Windows-based, integrated

development environment for the Programmable System-on-

Chip (PSoC) devices. The PSoC Designer IDE and application

runs on Windows XP and Windows Vista.

Code Generation Tools

PSoC Designer supports multiple third-party C compilers and

assemblers. The code generation tools work seamlessly within

the PSoC Designer interface and have been tested with a full

range of debugging tools. The choice is yours.

This system provides design database management by project,

an integrated debugger with In-Circuit Emulator, in-system

programming support, and built-in support for third-party assem-

blers and C compilers.

Assemblers. The assemblers allow assembly code to be

merged seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and linked

with other software modules to get absolute addressing.

PSoC Designer also supports C language compilers developed

specifically for the devices in the PSoC family.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices.

PSoC Designer Software Subsystems

System-Level View

The system-level view is a drag-and-drop visual embedded

system design environment based on PSoC Express. In this

view you solve design problems the same way you might think

about the system. Select input and output devices based upon

system requirements. Add a communication interface and define

the interface to the system (registers). Define when and how an

output device changes state based upon any/all other system

devices. Based upon the design, PSoC Designer automatically

selects one or more PSoC devices that match your system

requirements.

The optimizing C compilers provide all the features of C tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow the designer to read and

program and read and write data memory, read and write I/O

registers, read and write CPU registers, set and clear break-

points, and provide program run, halt, and step control. The

debugger also allows the designer to create a trace buffer of

registers and memory locations of interest.

PSoC Designer generates all embedded code, then compiles

and links it into a programming file for a specific PSoC device.

Chip-Level View

The chip-level view is a more traditional integrated development

environment (IDE) based on PSoC Designer 4.x. You choose a

base device to work with and then select different onboard

analog and digital components called user modules that use the

PSoC blocks. Examples of user modules are ADCs, DACs,

Amplifiers, and Filters. You configure the user modules for your

chosen application and connect them to each other and to the

proper pins. Then you generate your project. This prepopulates

your project with APIs and libraries that you can use to program

your application.

Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

In-Circuit Emulator

A low cost, high functionality In-Circuit Emulator (ICE) is

available for development support. This hardware has the

capability to program single devices.

The tool also supports easy development of multiple configura-

tions and dynamic reconfiguration. Dynamic reconfiguration

allows for changing configurations at run time.

The emulator consists of a base unit that connects to the PC by

way of a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full speed (24

MHz) operation.

Hybrid Designs

You can begin in the system-level view, allow it to choose and

configure your user modules, routing, and generate code, then

switch to the chip-level view to gain complete control over on-

chip resources. All views of the project share common code

editor, builder, and common debug, emulation, and programming

tools.

Document Number: 001-12696 Rev. *F

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Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Organize and Connect

You build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins, or connect system-level

inputs, outputs, and communication interfaces to each other with

valuator functions.

In the system-level view selecting a potentiometer driver to

control a variable speed fan driver and setting up the valuators

to control the fan speed based on input from the pot selects,

places, routes, and configures a programmable gain amplifier

(PGA) to buffer the input from the potentiometer, an analog-to-

digital converter (ADC) to convert the potentiometer’s output to

a digital signal, and a PWM to control the fan.

The PSoC development process can be summarized in the

following four steps:

1. Select Components

2. Configure Components

3. Organize and Connect

4. Generate, Verify, and Debug

In the chip-level view, you perform the selection, configuration,

and routing so that you have complete control over the use of all

on-chip resources.

Select Components

Both the system-level and chip-level views provide a library of

pre-built, pre-tested hardware peripheral components. In the

system-level view these components are called “drivers” and

correspond to inputs (a thermistor, for example), outputs (a

brushless DC fan, for example), communication interfaces (I²C-

bus, for example), and the logic to control how they interact with

one another (called valuators).

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move

on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system.

Both system-level and chip-level designs generate software

based on your design. The chip-level design provides application

programming interfaces (APIs) with high-level functions to

control and respond to hardware events at run time and interrupt

service routines that you can adapt as needed. The system-level

design also generates a C main() program that completely

controls the chosen application and contains placeholders for

custom code at strategic positions allowing you to further refine

the software without disrupting the generated code.

In the chip-level view the components are called “user modules.”

User modules make selecting and implementing peripheral

devices simple, and come in analog, digital, and programmable

system-on-chip varieties.

Configure Components

Each of the components you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a Pulse

Width Modulator (PWM) User Module configures one or more

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to corre-

spond to your chosen application. Enter values directly or by

selecting values from drop-down menus.

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

The last step in the development process takes place inside

PSoC Designer’s Debugger (access by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging capabil-

ities rival those of systems costing many times more. In addition

to traditional single-step, run-to-breakpoint and watch-variable

features, the debug interface provides a large trace buffer and

allows you to define complex breakpoint events that include

monitoring address and data bus values, memory locations and

external signals.

Both the system-level drivers and chip-level user modules are

documented in data sheets that are viewed directly in PSoC

Designer. These data sheets explain the internal operation of the

component and provide performance specifications. Each data

sheet describes the use of each user module parameter or driver

property, and other information you may need to successfully

implement your design.

Document Number: 001-12696 Rev. *F

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Document Conventions

Acronyms Used

Units of Measure

The following table lists the acronyms that are used in this

document.

A units of measure table is located in the Electrical Specifications

section. Table 11 on page 17 lists all the abbreviations used to

measure the PSoC devices.

Table 1. Acronyms

Numeric Naming

Acronym

AC

Description

alternating current

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, 01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are

decimal.

API

application programming interface

central processing unit

direct current

CPU

DC

FSR

GPIO

GUI

full scale range

general purpose I/O

graphical user interface

in-circuit emulator

ICE

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

I/O

LSb

least-significant bit

LVD

low voltage detect

MSb

POR

PPOR

PSoC®

SLIMO

SRAM

most-significant bit

power on reset

precision power on reset

Programmable System-on-Chip™

slow IMO

static random access memory

Document Number: 001-12696 Rev. *F

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Pinouts

The CY8C20x36/46/66/96 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.

Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES

are not capable of Digital I/O.

16-Pin QFN (No E-Pad)

Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device ^[2]

Type

Figure 2. CY8C20236, CY8C20246 PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

I/O

I

P2[5] Crystal output (XOut)

P2[3] Crystal input (XIn)

P1[7] I2C SCL, SPI SS

P1[5] I2C SDA, SPI MISO

P1[3] SPI CLK

I/O

AI, XOut, P2[5]

AI, XIn, P2[3]

1

2

P0[4], AI

IOHR

12

11

10

QFN

(Top View)

XRES

P1[4], EXTCLK, AI

P1[2], AI

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI MISO, P1[5]

3

4

9

P1[1] ISSP CLK^[1], I2C SCL, SPI

MOSI

7

8

Power

Vss Ground connection

P1[0] ISSP DATA^[1], I2C SDA, SPI

CLK

IOHR

I

9

IOHR

I

P1[2]

10

P1[4] Optional external clock

(EXTCLK)

11

Input

XRES Active high external reset with

internal pull down

12

13

14

15

16

IOH

Power

I

P0[4]

Vdd Supply voltage

P0[7]

IOH

I

P0[3] Integrating input

P0[1] Integrating input

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

1. These are the ISSP pins, which are not High Z at POR (Power On Reset).

2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.

Document Number: 001-12696 Rev. *F

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24-Pin QFN

[2, 3]

Table 3. Pin Definitions - CY8C20336, CY8C20346

Type

Figure 3. CY8C20336, CY8C20346 PSoC Device

Name

Description

No.

Digital Analog

1

2

3

4

5

6

7

I/O

I

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

Crystal output (XOut)

Crystal input (XIn)

18

17

16

15

AI, XOut, P2[5]

AI, XIn, P2[3]

1

2

3

4

5

6

P0[4], AI

P0[2], AI

P0[0], AI

P2[0], AI

XRES

I/O

IOHR

I2C SCL, SPI SS

I2C SDA, SPI MISO

SPI CLK

ISSP CLK^[1], I2C SCL, SPI

MOSI

AI, P2[1]

QFN

(Top View)

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI MISO, P1[5]

AI, SPI CLK, P1[3]

14

13

P1[6], AI

8

NC

No connection

9

Power

Vss

P1[0]

Ground connection

ISSP DATA^[1], I2C SDA, SPI

CLK

10

IOHR

I

11

12

IOHR

I

P1[2]

P1[4]

Optional external clock input

(EXTCLK)

13

14

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull down

15

16

17

18

19

20

21

22

23

24

CP

I/O

I

P2[0]

P0[0]

P0[2]

P0[4]

P0[6]

IOH

Power

Vdd

Supply voltage

IOH

I

P0[7]

P0[5]

P0[3]

P0[1]

Vss

Integrating input

Center pad must be connected

to ground

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Note

3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

must be electrically floated and not connected to any other signal.

Document Number: 001-12696 Rev. *F

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24-Pin QFN with USB

[2, 3]

Table 4. Pin Definitions - CY8C20396 PSoC Device

Type

Pin No.

Name

Description

Figure 4. CY8C20396 PSoC Device

Digital Analog

1

2

I/O

I

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

VSS

D+

3

I/O

4

IOHR

I2C SCL, SPI SS

18

17

16

15

14

13

P2[5]

P2[3]

1

2

P0[2]

5

I2C SDA, SPI MISO

SPI CLK

P0[0]

6

XRES

P2[1]

3

4

5

6

QFN

( Top View)

I2 C SCL, SPI SS, P1[7]

I2 C SDA, SPI MISO, P1[5]

SPI CLK, P1[3]

P1[6]

7

ISSP CLK, I2C SCL, SPI MOSI

Ground

P1[4] , EXTCLK

P1[2]

8

Power

9

I/O

I

USB D+

10

11

12

13

14

D-

USB D-

Power

VDD

P1[0]

P1[2]

P1[4]

Supply

IOHR

I

ISSP DATA, I2C SDA

Optional external clock input

(EXTCLK)

15

16

IOHR

I

P1[6]

RESET INPUT

XRES

Active high external reset with

internal pull down

17

18

19

20

21

22

23

24

CP

IOH

I

P0[0]

P0[2]

P0[4]

P0[6]

P0[7]

P0[5]

P0[3]

P0[1]

VSS

Integrating input

Power

Thermal pad must be

connected to Ground

LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output

Document Number: 001-12696 Rev. *F

Page 10 of 39

[+] Feedback

CY8C20X36/46/66/96

32-Pin QFN

Table 5. Pin Definitions - CY8C20436, CY8C20446,

CY8C20466 PSoC Device ^{[2, 3]}

Type

Figure 5. CY8C20436, CY8C20446, CY8C20466 PSoC Device

Name

Description

No.

Digital Analog

1

IOH

I/O

I

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

P3[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

Integrating input

2

3

I/O

Crystal output (XOut)

Crystal input (XIn)

AI, P0[1]

AI, P2[7]

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0[0], AI

P2[6], AI

P2[4], AI

P2[2], AI

P2[0], AI

P3[2], AI

P3[0], AI

XRES

4

I/O

AI, XOut, P2[5]

AI, XIn, P2[3]

AI, P2[1]

5

I/O

QFN

(Top View)

6

I/O

7

I/O

AI, P3[3]

AI, P3[1]

AI, I2C SCL, SPI SS, P1[7]

8

IOHR

I2C SCL, SPI SS

9

I2C SDA, SPI MISO

10

11

12

13

14

15

SPI CLK.

ISSP CLK^[1], I2C SCL, SPI MOSI.

Power

Ground connection.

ISSP DATA^[1], I2C SDA., SPI CLK

IOHR

I

P1[0]

P1[2]

P1[4]

Optional external clock input

(EXTCLK)

16

17

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull down

18

I/O

I

P3[0]

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CP

I/O

I

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I/O

IOH

Power

Vdd

Supply voltage

IOH

I

P0[7]

P0[5]

P0[3]

Vss

Integrating input

Power

Ground connection

Vss

Center pad must be connected to

ground

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Document Number: 001-12696 Rev. *F

Page 11 of 39

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CY8C20X36/46/66/96

32-Pin QFN (with USB)

[2, 3]

Table 6. Pin Definitions - CY8C20496 PSoC Device

Type

Figure 5. CY8C20496 PSoC Device

Name

Description

No.

Digital Analog

1

IOH

I/O

I

P0[1]

P2[5]

P2[3]

P2[1]

P1[7]

P1[5]

P1[3]

P1[1]

V_SS

2

XTAL Out

XTAL In

3

I/O

AI , P0[1]

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0[0] , AI

P2[6] , AI

P2[4] , AI

P2[2] , AI

P2[0] , AI

P3[2] , AI

P3[0] , AI

XRES

2

XTAL OUT, P [5]

4

I/O

XTAL IN P2 3

,

[ ]

5

IOHR

I2C SCL, SPI SS

I2C SDA, SPI MISO

SPI CLK

AI P2 1

,

[ ]

QFN

( Top View)

6

P

I2C SCL, SPI SS

7]

1[

,

I2C SDA, SPI MISO P

5

1[ ]

,

7

SPI CLK P1

]

[3

,

8

TC CLK, I2C SCL, SPI MOSI

Ground Pin

TC CLK, I2C SCL, SPI MOSI,P1 1

[ ]

9

Power

10

11

12

13

14

15

16

17

I

D+

USB PHY

D-

USB PHY

Power

Vdd

Power pin

IOHR

I

P1[0]

P1[2]

P1[4]

P1[6]

TC DATA*, I2C SDA, SPI CLKI

EXTCLK

Input

XRES Active high external reset with

internal pull down

18

I/O

I

P3[0]

19

20

21

22

23

24

25

26

27

28

29

30

31

32

I/O

I

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I/O

IOH

Power

Vdd

Power Pin

IOH

I

P0[7]

P0[5]

P0[3]

Vss

Ground Pin

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Document Number: 001-12696 Rev. *F

Page 12 of 39

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CY8C20X36/46/66/96

48-Pin SSOP

Table 7. Pin Definitions - CY8C20536, CY8C20546,

[2]

and CY8C20566 PSoC Device

Figure 6. CY8C20536, CY8C20546, and CY8C20566 PSoC Device

Name

Description

AI, P0[7]

AI, P0[5]

AI, P0[3]

AI P0[1]

AI, P2[7]

1

2

3

4

5

6

VDD

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

P0[6], AI

P0[4], AI

P0[2], AI

P0[0], AI

P2[6], AI

P2[4], AI

P2[2], AI

P2[0], AI

P3[6], AI

P3[4], AI

P3[2], AI

P3[0], AI

XRES

1

IOH

I/O

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

2

3

XTALOUT, P2[5]

XTALIN, P2[3]

7

8

9

4

AI, P2[1]

NC

5

NC

10

6

I/O

XTAL Out

XTAL In

AI, P4[3]

AI, P4[1]

NC

11

12

13

14

7

I/O

SSOP

8

I/O

AI, P3[7]

9

No connection

AI, P3[5] 15

AI, P3[3] 16

AI, P3[1] 17

NC

10

NC

11 I/O

12 I/O

13

I

P4[3]

P4[1]

NC

18

19

20

NC

P1[6], AI

I2C SCL, SPI SS, P1[7]

No connection

I2C SDA, SPI MISO, P1[5] 21

SPI CLK, P1[3]

TC CLK, I2C SCL, SPI MOSI, P1[1] 23

22

P1[4], EXT CLK

P1[2], AI

14 I/O

15 I/O

16 I/O

17 I/O

18

I

P3[7]

P3[5]

P3[3]

P3[1]

NC

VSS 24

P1[0], TC DATA, I2C SDA, SPI CLK

No connection

19

NC

No connection

20 IOHR

21 IOHR

22 IOHR

23 IOHR

24

I

P1[7]

P1[5]

P1[3]

P1[1]

VSS

P1[0]

P1[2]

P1[4]

P1[6]

NC

I2C SCL, SPI SS

I2C SDA, SPI MISO

SPI CLK

TC CLK^[1], I2C SCL, SPI MOSI

Ground Pin

TC DATA^[1], I2C SDA, SPI CLK

25 IOHR

26 IOHR

27 IOHR

28 IOHR

29

I

EXT CLK

No connection

30

NC

31

NC

32

NC

Name

Description

33

34

35

NC

No connection

41

42

I/O

I

P2[2]

P2[4]

P2[6]

XRES Active high external reset with internal 43

pull down

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

I

P3[0]

P3[2]

P3[4]

P3[6]

P2[0]

44

45

46

47

48

IOH

I

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Power

Power Pin

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Document Number: 001-12696 Rev. *F

Page 13 of 39

[+] Feedback

CY8C20X36/46/66/96

48-Pin QFN

[2, 3]

Table 8. Pin Definitions - CY8C20636 PSoC Device

Figure 7. CY8C20636 PSoC Device

No.

Name

Description

1

NC

No connection

2

I/O

I

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

NC

AI ,P2[7]

P2[6] ,AI

P2[4] ,AI

36

35

34

33

32

31

1

2

3

Crystal output (XOut)

Crystal input (XIn)

AI, XOut,P2[5]

3

4

5

6

P2[2] ,AI

P2[0] ,AI

P4[2] ,AI

P4[0] ,AI

4

I/O

AI, XIn ,P2[3]

AI ,P2[1]

AI ,P4[3]

AI ,P4[1]

AI ,P3[7]

AI,P3[5]

AI,P3[3]

5

I/O

QFN

( Top View)

6

I/O

30

29

28

27

P3[6] ,AI

P3[4] , AI

7

8

9

10

7

I/O

P3[2] ,AI

8

I/O

] , AI

P3[0

XRES

P1[6], AI

9

I/O

AI P

3[1]

26

25

11

12

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O

AI,I2 C SCL, SPI SS,P1[7]

I/O

IOHR

I2C SCL, SPI SS

I2C SDA, SPI MISO

No connection

SPI CLK

NC

IOHR

I

P1[3]

P1[1]

Vss

ISSP CLK^[1], I2C SCL, SPI MOSI

Power

Ground connection

DNU

Vdd

Power

IOHR

Supply voltage

ISSP DATA^[1], I2C SDA, SPI CLK

I

P1[0]

P1[2]

P1[4]

IOHR

Optional external clock input

(EXTCLK)

25

26

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull down

27

28

29

I/O

I

P3[0]

P3[2]

P3[4]

No.

Name

Description

30

31

32

33

34

35

36

37

38

39

I/O

I

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

40

41

42

43

44

45

46

47

48

CP

IOH

I

P0[6]

Vdd

Power

Supply voltage

No connection

I/O

NC

I/O

NC

I/O

IOH

I

P0[7]

P0[5]

P0[3]

Vss

I/O

IOH

I/O

Integrating input

IOH

Power

Ground connection

IOH

I

P0[1]

Vss

Power

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Document Number: 001-12696 Rev. *F

Page 14 of 39

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CY8C20X36/46/66/96

48-Pin QFN with USB

[2, 3]

Table 9. Pin Definitions - CY8C20646, CY8C20666 PSoC Device

Figure 8. CY8C20646, CY8C20666 PSoC Device

No.

Name

Description

1

NC

No connection

NC

AI, P2[7]

P2[6],AI

P2[4],AI

36

35

34

33

32

31

1

2

I/O

I

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

NC

3

Crystal output (XOut)

Crystal input (XIn)

AI, XOut, P2[5]

3

4

5

6

P2[2],AI

P2[0],AI

P4[2],AI

P4[0],AI

4

I/O

AI, XIn , P2[3]

AI, P2[1]

5

I/O

AI, P4[3]

QFN

(Top View)

6

I/O

AI, P4[1]

AI, P3[7]

30

29

28

27

P3[6],AI

P3[4], AI

7

8

9

10

7

I/O

AI, P3[5]

AI, P3[3]

AI, P3[1]

P3[2],AI

8

I/O

], AI

P3[0

9

I/O

XRES

26

25

11

12

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O

AI, I2C SCL, SPI SS, P1[7]

P1[6], AI

I/O

IOHR

I2C SCL, SPI SS

I2C SDA, SPI MISO

No connection

NC

No connection

IOHR

I

P1[3]

P1[1]

Vss

SPI CLK

ISSP CLK^[1], I2C SCL, SPI MOSI

Ground connection

USB D+

Power

I/O

D+

D-

USB D-

Power

Vdd

Supply voltage

ISSP DATA^[1], I2C SDA, SPI CLK

IOHR

I

P1[0]

P1[2]

P1[4]

Optional external clock input

(EXTCLK)

25

26

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull down

27

28

29

I/O

I

P3[0]

P3[2]

P3[4]

No.

Name

Description

30

31

32

33

34

35

36

37

38

39

I/O

I

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

40

41

42

43

44

45

46

47

48

CP

IOH

I

P0[6]

Vdd

Power

Supply voltage

I/O

NC

No connection

I/O

NC

I/O

IOH

I

P0[7]

P0[5]

P0[3]

Vss

I/O

IOH

I/O

Integrating input

IOH

Power

Ground connection

IOH

I

P0[1]

Vss

Power

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Document Number: 001-12696 Rev. *F

Page 15 of 39

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CY8C20X36/46/66/96

48-Pin QFN OCD

The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit

[4]

debugging.

[2, 3]

Table 10. Pin Definitions - CY8C20066 PSoC Device

Figure 9. CY8C20066 PSoC Device

No.

Name

Description

1

OCDOE

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

CCLK

HCLK

P1[3]

P1[1]

Vss

OCD mode direction pin

OCDO

2

I/O

I

P2[6], AI

P2[4], AI

36

35

34

33

32

31

1

2

E

A

I

, P2[7]

3

Crystal output (XOut)

Crystal input (XIn)

AI, XOut, P2[5]

3

4

5

6

P2[2], AI

P2[0], AI

P4[2], AI

P4[0], AI

4

I/O

AI, XIn , P2[3]

AI, P2[1]

5

I/O

6

I/O

AI, P4[3]

QFN

(Top View)

AI, P4[1]

AI, P3[7]

30

29

28

27

P3[6], AI

P3[4], AI

7

8

9

10

7

I/O

8

I/O

AI, P3[5]

AI, P3[3]

P3[2], AI

P3[0], AI

9

I/O

AI, P3[1]

XRES

26

25

11

12

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

AI, I2C SCL, SPI SS, P1[7]

P1[6], AI

I/O

IOHR

I2C SCL, SPI SS

I2C SDA, SPI MISO

OCD CPU clock output

OCD high speed clock output

SPI CLK.

ISSP CLK^[1], I2C SCL, SPI MOSI

Ground connection

USB D+

IOHR

I

Power

I/O

D+

D-

USB D-

Power

Vdd

Supply voltage

ISSP DATA⁽¹⁾, I2C SDA, SPI CLK

IOHR

I

P1[0]

P1[2]

No.

Name

Description

24

IOHR

I

P1[4]

Optional external clock input

(EXTCLK)

37

IOH

I

P0[0]

25

26

P1[6]

38

39

IOH

I

P0[2]

P0[4]

Input

XRES

Active high external reset with

internal pull down

27

28

29

30

31

32

33

34

35

36

I/O

I

P3[0]

P3[2]

P3[4]

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

40

41

42

43

44

45

46

47

48

CP

IOH

I

P0[6]

Vdd

Power

Supply voltage

OCDO OCD even data I/O

OCDE OCD odd data output

IOH

I

P0[7]

P0[5]

P0[3]

Vss

Integrating input

Power

IOH

Power

Ground connection

I

P0[1]

Vss

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Note

4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.

Document Number: 001-12696 Rev. *F

Page 16 of 39

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CY8C20X36/46/66/96

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C20x36/46/66/96 PSoC devices. For the latest electrical

specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.

Figure 10. Voltage versus CPU Frequency

Figure 11. IMO Frequency Trim Options

5.5V

SLIMO SLIMO SLIMO

Mode

= 01

Mode

= 00

Mode

= 10

1.71V

750 kHz

3 MHz

750 kHz

3 MHz

6 MHz 12 MHz 24 MHz

24 MHz

IMO Frequency

CPU Frequency

The following table lists the units of measure that are used in this section.

Table 11. Units of Measure

Symbol

Unit of Measure

degree Celsius

Symbol

Unit of Measure

°C

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

dB

decibels

fF

femto farad

hertz

Hz

nanoampere

nanosecond

nanovolts

KB

Kbit

kHz

ksps

kΩ

1024 bytes

1024 bits

nV

Ω

kilohertz

ohm

kilo samples per second

kilohm

pA

pF

pp

ppm

ps

picoampere

picofarad

MHz

MΩ

μA

megahertz

megaohm

microampere

microfarad

microhenry

microsecond

microwatts

peak-to-peak

parts per million

picosecond

μF

sps

s

samples per second

μH

μs

sigma: one standard deviation

volts

V

μW

Document Number: 001-12696 Rev. *F

Page 17 of 39

[+] Feedback

CY8C20X36/46/66/96

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 12. Absolute Maximum Ratings

Symbol

Description

Conditions

Min

Typ

Max

Units

T

Storage Temperature

Higher storage temperatures reduces data

retention time. Recommended Storage

Temperature is +25°C ± 25°C. Extended

–55

+25

+125

°C

STG

o

duration storage temperatures above 85 C

degrades reliability.

Vdd

Supply Voltage Relative to Vss

DC Input Voltage

–0.5

Vss – 0.5

Vss –0.5

–25

–

+6.0

Vdd + 0.5

+50

V

IO

IOZ

MIO

DC Voltage Applied to Tri-state

Maximum Current into any Port Pin

Electro Static Discharge Voltage

Latch up Current

V

I

mA

V

ESD

LU

Human Body Model ESD

2000

–

In accordance with JESD78 standard

–

200

mA

Operating Temperature

Table 13. Operating Temperature

Symbol

Description

Ambient Temperature

Conditions

Min

Typ

Max

Units

T

–40

–

+85

°C

A

T

Operational Die Temperature

The temperature risefrom ambient tojunction

is package specific. Refer the table Thermal

Impedances per Package on page 34. The

user must limit the power consumption to

comply with this requirement.

J

–40

–

+100

°C

Document Number: 001-12696 Rev. *F

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DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 14. DC Chip-Level Specifications

Symbol

Description

Supply Voltage

Conditions

Min

Typ

Max

Units

[5]

Vdd

Refer the table DC POR and LVD

Specifications on page 24

1.71

–

5.5

V

I

Supply Current, IMO = 24 MHz

Supply Current, IMO = 12 MHz

Supply Current, IMO = 6 MHz

Deep Sleep Current

Conditions are Vdd <= 3.0V, T = 25°C,

–

2.88

1.71

1.16

4.0

2.6

1.8

mA

DD24

DD12

DD6

A

CPU = 24 MHz. CapSense running at 12

MHz, no I/O sourcing current

Conditions are Vdd <= 3.0V, T = 25°C,

A

CPU = 12 MHz. CapSense running at 12

MHz, no I/O sourcing current

Conditions are Vdd <= 3.0V, T = 25°C,

A

CPU = 6 MHz. CapSense running at 6 MHz,

no I/O sourcing current

I

Vdd <= 3.0V, T = 25°C, I/O regulator turned

–

0.1

–

μA

SB0

A

off

Standby Current with POR, LVD and Vdd <= 3.0V, T = 25°C, I/O regulator turned

Sleep Timer

1.07

1.5

SB1

A

off

DC General Purpose IO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and

–40°C ≤ T ≤ 85°C, 2.4V to 3.0V and –40°C ≤ T ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ T ≤ 85°C, respectively. Typical parameters

A

apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 15. 3.0V to 5.5V DC GPIO Specifications

Symbol

Description

Pull up Resistor

Conditions

Min

Typ

5.6

–

Max

8

Units

kΩ

R

4

PU

V

High Output Voltage

Port 2 or 3 Pins

IOH < 10 μA, maximum of 10 mA source Vdd - 0.2

current in all IOs

–

V

OH1

High Output Voltage

Port 2 or 3 Pins

IOH = 1 mA, maximum of 20 mA source

current in all IOs

Vdd - 0.9

–

V

OH2

OH3

High Output Voltage

Port 0 or 1 Pins with LDO Regulator current in all IOs

Disabled for Port 1

IOH < 10 μA, maximum of 10 mA source Vdd - 0.2

V

High Output Voltage

Port 0 or 1 Pins with LDO Regulator current in all IOs

Disabled for Port 1

IOH = 5 mA, maximum of 20 mA source

Vdd - 0.9

2.85

–

3.00

–

3.3

–

V

OH4

OH5

OH6

OH7

OH8

High Output Voltage

Port 1 Pins with LDO Regulator

Enabled for 3V Out

IOH < 10 μA, Vdd > 3.1V, maximum of

4 IOs all sourcing 5 mA

High Output Voltage

Port 1 Pins with LDO Regulator

Enabled for 3V Out

IOH = 5 mA, Vdd > 3.1V, maximum of

20 mA source current in all IOs

2.20

High Output Voltage

Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs

Out

IOH < 10 μA, Vdd > 2.7V, maximum of

2.35

2.50

–

2.75

–

High Output Voltage

Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs

Out

IOH = 2 mA, Vdd > 2.7V, maximum of

1.90

Note

5. When Vdd remains in the range from 1.71V to 1.9V for more than 50 usec, the slew rate when moving from the 1.71V to 1.9V range to greater than 2V must be

slower than 1V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the T

parameter.

RAMP

Document Number: 001-12696 Rev. *F

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Table 15. 3.0V to 5.5V DC GPIO Specifications (continued)

Symbol Description

High Output Voltage

Conditions

Min

Typ

Max

Units

V

IOH < 10 μA, Vdd > 2.7V, maximum of

1.60

1.80

2.1

V

OH9

OH10

OL

Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs

Out

V

High Output Voltage

Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs

Out

IOH = 1 mA, Vdd > 2.7V, maximum of

1.20

–

V

Low Output Voltage

IOL = 25 mA, Vdd > 3.3V, maximum of

60 mA sink current on even port pins (for

example, P0[2] and P1[4]) and 60 mA sink

current on odd port pins (for example, P0[3]

and P1[5])

0.75

V

I

Input Low Voltage

–

2.00

–

0.80

V

IL

IH

H

Input High Voltage

Input Hysteresis Voltage

Input Leakage (Absolute Value)

Pin Capacitance

80

–

1

5

mV

μA

pF

–

0.001

1.7

IL

C

Package and pin dependent

0.5

Temp = 25°C

Document Number: 001-12696 Rev. *F

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Table 16. 2.4V to 3.0V DC GPIO Specifications

Symbol Description

Pull up Resistor

Conditions

Min

4

Typ

5.6

–

Max

8

Units

kΩ

R

PU

V

High Output Voltage

Port 2 or 3 Pins

IOH < 10 μA, maximum of 10 mA

source current in all IOs

Vdd - 0.2

–

V

OH1

High Output Voltage

Port 2 or 3 Pins

IOH = 0.2 mA, maximum of 10 mA

source current in all IOs

Vdd - 0.4

Vdd - 0.2

–

V

OH2

OH3

High Output Voltage

Port 0 or 1 Pins with LDO Regulator

IOH < 10 μA, maximum of 10 mA

source current in all IOs

Disabled for Port 1

V

High Output Voltage

Port 0 or 1 Pins with LDO Regulator

Disabled for Port 1

IOH = 2 mA, maximum of 10 mA source Vdd - 0.5

current in all IOs

–

1.80

–

2.1

–

V

OH4

OH5A

OH6A

OL

High Output Voltage

Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs

Out

IOH < 10 μA, Vdd > 2.4V, maximum of

1.50

1.20

–

High Output Voltage

Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs

Out

IOH = 1 mA, Vdd > 2.4V, maximum of

Low Output Voltage

IOL = 10 mA, maximum of 30 mA sink

current on even port pins (for example,

P0[2] and P1[4]) and 30 mA sink

current on odd port pins (for example,

P0[3] and P1[5])

–

0.75

V

I

Input Low Voltage

–

1.4

–

0.72

V

IL

IH

H

Input High Voltage

Input Hysteresis Voltage

Input Leakage (Absolute Value)

Capacitive Load on Pins

80

–

1

5

mV

μA

pF

–

0.001

1.7

IL

C

Package and pin dependent

Temp = 25 C

0.5

o

Table 17. 1.71V to 2.4V DC GPIO Specifications

Symbol Description

Pull up Resistor

Conditions

Min

4

Typ

5.6

–

Max

8

Units

kΩ

R

PU

V

High Output Voltage

Port 2 or 3 Pins

IOH = 10 μA, maximum of 10 mA

source current in all I/Os

Vdd - 0.2

–

V

OH1

High Output Voltage

Port 2 or 3 Pins

IOH = 0.5 mA, maximum of 10 mA

source current in all I/Os

Vdd - 0.5

Vdd - 0.2

–

V

OH2

OH3

High Output Voltage

Port 0 or 1 Pins with LDO Regulator

Disabled for Port 1

IOH = 100 μA, maximum of 10 mA

source current in all I/Os

V

High Output Voltage

Port 0 or 1 Pins with LDO Regulator

Disabled for Port 1

IOH=2mA, maximumof10mAsource Vdd - 0.5

current in all I/Os

–

V

OH4

OL

V

Low Output Voltage

IOL = 5 mA, maximum of 20 mA sink

current on even port pins (for example,

P0[2] and P1[4]) and 30 mA sink

current on odd port pins (for example,

P0[3] and P1[5])

–

0.4

V

Input Low Voltage

Input High Voltage

–

0.3 x Vdd

V

IL

0.65 x Vdd

IH

Document Number: 001-12696 Rev. *F

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Table 17. 1.71V to 2.4V DC GPIO Specifications (continued)

Symbol

Description

Input Hysteresis Voltage

Input Leakage (Absolute Value)

Capacitive Load on Pins

Conditions

Min

–

Typ

80

Max

Units

mV

μA

V

–

1

5

H

I

–

0.001

1.7

IL

C

Package and pin dependent

Temp = 25 C

0.5

pF

o

Table 18.DC Characteristics – USB Interface

Symbol

Rusbi

Rusba

Vohusb

Volusb

Vdi

Description

USB D+ Pull Up Resistance

Static Output High

Conditions

With idle bus

Min

0.900

1.425

2.8

Typ

Max

1.575

3.090

3.6

Units

kΩ

V

-

While receiving traffic

Static Output Low

0.3

V

Differential Input Sensitivity

0.2

0.8

V

Vcm

Differential Input Common Mode

Range

2.5

V

Vse

Cin

Single Ended Receiver Threshold

Transceiver Capacitance

0.8

-

2.0

50

V

-

pF

μA

kΩ

Ω

Iio

Hi-Z State Data Line Leakage

PS/2 Pull Up Resistance

On D+ or D- line

-10

3

+10

7

Rps2

Rext

5

External USB Series Resistor

In series with each USB pin

21.78

22.0

22.22

DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 19. DC Analog Mux Bus Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

R

Switch Resistance to Common Analog

Bus

–

800

Ω

SW

R

Resistance of Initialization Switch to

Vss

–

800

Ω

GND

The maximum pin voltage for measuring R

and R

is 1.8V

GND

SW

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 20. DC Comparator Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V

Low Power Comparator (LPC)

common mode

Maximum voltage limited to Vdd

0.0

–

1.8

V

LPC

I

LPC supply current

LPC voltage offset

–

10

40

30

μA

LPC

V

2.5

mV

OSLPC

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Comparator User Module Electrical Specifications

The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the

entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.

Table 21. Comparator User Module Electrical Specifications

Symbol

Description

Conditions

50 mV overdrive

Min

Typ

70

Max

100

30

Units

ns

T

Comparator Response Time

COMP

Offset

2.5

20

mV

µA

Current

PSRR

Average DC current, 50 mV

overdrive

80

Supply voltage >2V

Supply voltage <2V

Power Supply Rejection Ratio

80

40

dB

V

Input

0

1.5

Range

ADC Electrical Specifications

Table 22. ADC User Module Electrical Specifications

Symbol

Input

Description

Conditions

Min

Typ

Max

Units

V

Input Voltage Range

This gives 72% of maximum

code

Vss

1.3

V

IN

C

Input Capacitance

Resolution

5

pF

IN

RES

S8

Settings 8, 9, or 10

8

10

Bits

ksps

8-Bit Sample Rate

Data Clock set to 6 MHz.

Sample Rate = 0.001/

(2^Resolution/Data clock)

23.4375

5.859

S10

10-Bit Sample Rate

Data Clock set to 6 MHz.

Sample Rate = 0.001/

ksps

(2^Resolution/Data clock)

DC Accuracy

[6]

DNL

INL

Differential Nonlinearity

For any configuration

-1

-2

0

+2

LSB

mV

Integral Nonlinearity

Offset Error

Eoffset

15

90

I

Operating Current

Data Clock

275

350

12

μA

ADC

F

Source is chip’s internal main

oscillator. See device data

sheet for accuracy.

2.25

MHz

CLK

PSRR Power Supply Rejection Ration

PSRR (Vdd>3.0V)

24

30

12

0

dB

PSRR (2.2 < Vdd < 3.0)

PSRR (2.0 < Vdd < 2.2)

PSRR (Vdd < 2.0)

dB

Egain Gain Error

For any resolution

1

5

%FSR

R

Input Resistance

Equivalent switched cap input

resistance for 8-, 9-, or 10-bit

resolution.

1/(500fF*

1/(400fF*

1/(300fF*

Ω

IN

Data-Clock) Data-Clock) Data-Clock)

Note

6. Monotonicity is not guaranteed.

Document Number: 001-12696 Rev. *F

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DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 23. DC POR and LVD Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

Vdd Value for PPOR Trip

Vdd must be greater than or equal to

V

PORLEV[1:0] = 00b, HPOR = 0 1.71Vduringstartup, resetfromtheXRES

PORLEV[1:0] = 00b, HPOR = 1 pin, or reset from watchdog.

PORLEV[1:0] = 01b, HPOR = 1

1.61

–

1.66

2.36

2.60

2.82

1.71

2.41

2.66

2.95

V

PPOR0

PPOR1

PPOR2

PPOR3

V

PORLEV[1:0] = 10b, HPOR = 1

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

[7]

V

2.40

2.64

2.85

2.45

2.71

2.92

3.02

3.13

1.90

1.80

4.73

2.51

2.78

2.99

3.09

3.20

2.32

1.84

4.83

V

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

[8]

[9]

2.95

3.06

1.84

[10]

1.75

4.62

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 24. DC Programming Specifications

Symbol

Vdd

Description

Conditions

Min

Typ

Max

Units

Supply Voltage for Flash Write

Operations

1.71

–

5.25

V

IWRITE

I

Supply Current During

Programming or Verify

–

5

–

25

mA

V

DDP

V

Input Low Voltage During

Programming or Verify

See the appropriate DC General Purpose

IO Specifications on page 19

V

IL

ILP

Input High Voltage During

Programming or Verify

See appropriate DC General Purpose IO

Specifications on page 19 table on pages

15 or 16

V

–

V

IHP

IH

I

Input Current when Applying Vilp Driving internal pull down resistor

to P1[0] or P1[1] During

Programming or Verify

–

0.2

1.5

mA

ILP

Input Current when Applying Vihp Driving internal pull down resistor

to P1[0] or P1[1] During

–

IHP

Programming or Verify

V

Output Low Voltage During

Programming or Verify

–

Vss + 0.75

Vdd

V

OLP

Output High Voltage During

Programming or Verify

See appropriate DC General Purpose IO

Specifications on page 19 table on page

V

OH

OHP

16. For Vdd > 3V use V

in Table 13 on

OH4

page 18.

Flash

Flash Write Endurance

Flash Data Retention

Erase/write cycles per block

50,000

10

–

-

ENPB

Following maximum Flash write cycles;

ambient temperature of 55°C

20

Years

DR

Notes

7. Always greater than 50 mV above V

8. Always greater than 50 mV above V

9. Always greater than 50 mV above V

10. Always greater than 50 mV above V

voltage for falling supply.

PPOR1

PPOR2

PPOR3

PPOR0

voltage for falling supply.

Document Number: 001-12696 Rev. *F

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AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 25. AC Chip-Level Specifications

Symbol

Description

CPU Frequency

Conditions

Min

5.7

Typ

–

Max

25.2

50

Units

MHz

kHz

F

CPU

Internal Low Speed Oscillator Frequency

19

32

24

32K1

Internal Main Oscillator Frequency at 24

MHz Setting

22.8

25.2

MHz

IMO24

F

Internal Main Oscillator Frequency at 12

MHz Setting

11.4

5.7

12

12.6

6.3

MHz

IMO12

IMO6

Internal Main Oscillator Frequency at 6

MHz Setting

6.0

DC

T

Duty Cycle of IMO

Supply Ramp Time

40

20

1

50

–

60

–

%

μs

ms

μs

IMO

RAMP

XRST

XRST2

T

External Reset Pulse Width at Power Up After supply voltage is valid

External Reset Pulse Width after Power Applies after part has booted

10

[11]

Up

Note

11. The minimum required XRES pulse length is longer when programming the device (see Table 32 on page 28).

Document Number: 001-12696 Rev. *F

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AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 26. AC GPIO Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

F

GPIO Operating Frequency

Normal Strong Mode Port 0, 1

0

–

6 MHz for

1.71V<Vdd<2.4V

MHz

GPIO

0

–

12 MHz for

2.4V<Vdd<5.5V

TRise23

Rise Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%

Ports 2 or 3

15

10

80

50

80

50

70

ns

TRise23L Rise Time, Strong Mode Low Supply,

Cload = 50 pF, Ports 2 or 3

Vdd = 1.71 to 3.0V, 10% – 90%

TRise01

Rise Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%

Ports 0 or 1

LDO enabled or disabled

TRise01L Rise Time, Strong Mode Low Supply,

Cload = 50 pF, Ports 0 or 1

Vdd = 1.71 to 3.0V, 10% – 90%

LDO enabled or disabled

TFall

Fall Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%

All Ports

TFallL

Fall Time, Strong Mode Low Supply,

Cload = 50 pF, All Ports

Vdd = 1.71 to 3.0V, 10% – 90%

Figure 12. GPIO Timing Diagram

90%

GPIO Pin

Output

Voltage

10%

TRise23

TRise01

TRise23L

TRise01L

TFall

TFallL

Document Number: 001-12696 Rev. *F

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Table 27.AC Characteristics – USB Data Timings

Symbol

Tdrate

Description

Full speed data rate

Conditions

Average bit rate

Min

12–0.25%

-18.5

-9

Typ

12

–

Max

Units

12 + 0.25% MHz

Tdjr1

Receiver data jitter tolerance

Driver differential jitter

To next transition

To pair transition

To next transition

To pair transition

To SE0 transition

18.5

9

ns

Tdjr2

–

Tudj1

Tudj2

Tfdeop

-3.5

–

3.5

4.0

5

-4.0

–

Source jitter for differential

transition

-2

–

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

Receiver SE0 interval of EOP

160

82

–

175

14

ns

Width of SE0 interval during

differential transition

Table 28.AC Characteristics – USB Driver

Symbol Description

Transition rise time

Conditions

Min

4

Typ

–

Max

20

Units

ns

Tr

Tf

50 pF

Transition fall time

4

–

20

ns

TR

Rise/fall time matching

Output signal crossover voltage

90.00

1.3

–

111.1

2.0

%

Vcrs

–

V

AC Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 29. AC Low Power Comparator Specifications

Symbol

Description

Comparator Response Time, 50 50 mV overdrive does not include

mV Overdrive offset voltage.

Conditions

Min

Typ

Max

Units

T

100

ns

LPC

AC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 30. AC Analog Mux Bus Specifications

Symbol

Description

Switch Rate

Conditions

Min

Typ

Max

Units

F

Maximumpinvoltagewhenmeasuring

switch rate is 1.8Vp-p

–

6.3

MHz

SW

AC External Clock Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 31. AC External Clock Specifications

Symbol

Description

Conditions

Min

0.750

20.6

150

Typ

–

Max

25.2

5300

–

Units

MHz

ns

F

Frequency

High Period

Low Period

OSCEXT

–

ns

Power Up IMO to Switch

–

μs

Document Number: 001-12696 Rev. *F

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AC Programming Specifications

Figure 13. AC Waveform

SCLK (P1[1])

T_RSCLK

T_FSCLK

SDATA (P1[0])

T_SSCLK

T_HSCLK

T_DSCLK

The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 32. AC Programming Specifications

Symbol

Description

Rise Time of SCLK

Conditions

Min

1

Typ

–

Max

20

–

Units

ns

T

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

T

F

T

Fall Time of SCLK

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

Flash Erase Time (Block)

–

18

25

60

85

130

–

ERASEB

WRITE

DSCLK

DSCLK3

DSCLK2

XRST3

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK 3.6 < Vdd

Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6

Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0

External Reset Pulse Width after Power Up Required to enter programming mode

when coming out of sleep

–

ns

–

ns

263

–

μs

Document Number: 001-12696 Rev. *F

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AC I2C Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 33. AC Characteristics of the I2C SDA and SCL Pins

Standard

Mode

Fast Mode

Symbol

Description

Units

Min

Max

100

–

Min

0

Max

F

T

SCL Clock Frequency

0

400 kHz

SCLI2C

Hold Time (repeated) START Condition. After this period, the first clock pulse is 4.0

generated.

0.6

–

μs

HDSTAI2C

T

LOW Period of the SCL Clock

4.7

4.0

4.7

0

–

1.3

0.6

0

–

μs

ns

μs

ns

LOWI2C

HIGH Period of the SCL Clock

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

Setup Time for a Repeated START Condition

Data Hold Time

–

[12]

Data Setup Time

250

4.0

4.7

–

100

–

Setup Time for STOP Condition

0.6

1.3

0

–

Bus Free Time Between a STOP and START Condition

Pulse Width of spikes are suppressed by the input filter.

–

[13]

50

SPI2C

Figure 14. Definition for Timing for Fast/Standard Mode on the I²C Bus

SDA

SCL

T_SPI2C

T

LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

Notes

12. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t

≥ 250 ns must then be met. This automatically be the case

SU;DAT

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax

SU;DAT

13. In I2C sleep mode, wherein the part can wake up from sleep when the address matches its own slave address, there is no glitch/spike filtering on SCL and SDA lines

on the 7-bit address + R/W bit. Once, the part wakes up there is glitch/spike filtering on SCL and SDA lines.

Document Number: 001-12696 Rev. *F

Page 29 of 39

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CY8C20X36/46/66/96

Table 34. SPI Master AC Specifications

Symbol Description

SCLK clock frequency

Conditions

Min

Typ

Max

Units

F

V

≥ 2.4V

DD

6

3

MHz

SCLK

< 2.4V

DD

DC

T

SCLK duty cycle

50

%

MISO to SCLK setup time

V

≥ 2.4V

< 2.4V

60

100

ns

SETUP

DD

T

SCLK to MISO hold time

SCLK to MOSI valid time

MOSI high time

40

ns

HOLD

40

OUT_VAL

OUT_HIGH

40

Table 35. SPI Slave AC Specifications

Symbol

Description

SCLK clock frequency

Conditions

Min

Typ

Max

Units

F

V

≥ 2.4V

< 2.4V

12

6

MHz

SCLK

DD

T

SCLK low time

41.67

30

ns

LOW

SCLK high time

HIGH

MOSI to SCLK setup time

SCLK to MOSI hold time

SS high to MISO valid

SCLK to MISO valid

SS high time

SETUP

50

HOLD

153

125

50

SS_MISO

SCLK_MISO

SS_HIGH

SS_CLK

CLK_SS

Time from SS low to first SCLK

Time from last SCLK to SS high

2/SCLK

Document Number: 001-12696 Rev. *F

Page 30 of 39

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CY8C20X36/46/66/96

Packaging Information

This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances

for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 15. 16-pin QFN No E-pad 3x3mm Package Outline (Sawn)

001-09116 *D

Figure 16. 24-Pin (4x4 x 0.6 mm) QFN

001-13937 *B

Document Number: 001-12696 Rev. *F

Page 31 of 39

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CY8C20X36/46/66/96

Figure 17. 32-Pin (5x5 x 0.6 mm) QFN

001-42168 *C

Figure 18. 48-Pin (300 MIL) SSOP

.020

1

24

0.395

0.420

0.292

0.299

DIMENSIONS IN INCHES MIN.

MAX.

25

48

0.620

0.630

0.005

0.010

SEATING PLANE

.010

0.088

0.092

0.095

0.110

GAUGE PLANE

0.004

0.024

0.040

0.025

BSC

0°-8°

0.008

0.016

0.008

51-85061 *C

0.0135

Document Number: 001-12696 Rev. *F

Page 32 of 39

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CY8C20X36/46/66/96

Figure 19. 48-Pin (7x7 mm) QFN

001-13191 *D

Important Notes

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

■ Pinned vias for thermal conduction are not required for the low power PSoC device.

Document Number: 001-12696 Rev. *F

Page 33 of 39

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CY8C20X36/46/66/96

Thermal Impedances

Table 36. Thermal Impedances per Package

[14]

Package

Typical θ_JA

o

32.69 C/W

16 QFN

o

[15]

20.90 C/W

24 QFN

o

[15]

19.51 C/W

32 QFN

o

69 C/W

48 SSOP

o

[15]

17.68 C/W

48 QFN

Solder Reflow Peak Temperature

This table lists the minimum solder reflow peak temperature to achieve good solderability.

Table 37. Solder Reflow Peak Temperature

[16]

Package

16 QFN

24 QFN

32 QFN

48 SSOP

48 QFN

Maximum Peak Temperature

Minimum Peak Temperature

o

240 C

260 C

o

240 C

260 C

o

240 C

260 C

o

220 C

260 C

o

240 C

260 C

Capacitance on Crystal Pins

Table 38. Typical Package Capacitance on Crystal Pins

Package

32 QFN

48 QFN

Package Capacitance

3.2 pF

3.3 pF

Notes

14. T = T + Power x θ .

JA

J

A

15. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.

o

16. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications.

Document Number: 001-12696 Rev. *F

Page 34 of 39

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CY8C20X36/46/66/96

Development Tool Selection

Software

Evaluation Tools

All evaluation tools are sold at the Cypress Online Store.

CY3210-MiniProg1

PSoC Designer™

The CY3210-MiniProg1 kit enables the user to program PSoC

devices via the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

via a provided USB 2.0 cable. The kit includes:

At the core of the PSoC development software suite is PSoC

Designer, used to generate PSoC firmware applications. PSoC

Designer is available free of charge at

http://www.cypress.com/psocdesigner and includes a free C

compiler.

■ MiniProg Programming Unit

PSoC Programmer

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

PSoC Programmer is flexible enough and is used on the bench

in development and is also suitable for factory programming.

PSoC Programmer works either as a standalone programming

application or operates directly from PSoC Designer or PSoC

Express. PSoC Programmer software is compatible with both

PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC

programmer is available free of cost at

■ Getting Started Guide

■ USB 2.0 Cable

http://www.cypress.com/psocprogrammer.

CY3210-PSoCEval1

Development Kits

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

All development kits are sold at the Cypress Online Store.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface enables users to run, halt, and single step the

processor and view the content of specific memory locations.

PSoC Designer supports the advance emulation features also.

The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ USB 2.0 Cable

CY3214-PSoCEvalUSB

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

The CY3214-PSoCEvalUSB evaluation kit features

a

development board for the CY8C24794-24LFXI PSoC device.

Special features of the board include both USB and capacitive

sensing development and debugging support. This evaluation

board also includes an LCD module, potentiometer, LEDs, an

enunciator and plenty of bread boarding space to meet all of your

evaluation needs. The kit includes:

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

Document Number: 001-12696 Rev. *F

Page 35 of 39

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CY8C20X36/46/66/96

CY3207ISSP In-System Serial Programmer (ISSP)

Device Programmers

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production programming environment.

Note that CY3207ISSP needs special software and is not

compatible with PSoC Programmer. The kit includes:

All device programmers are purchased from the Cypress Online

Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular

programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

■ Modular Programmer Base

■ Three Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Table 39. Emulation and Programming Accessories

[17]

[18]

[19]

Part Number

CY8C20236-24LKXI

CY8C20246-24LKXI

CY8C20336-24LQXI

CY8C20346-24LQXI

CY8C20396-24LQXI

CY8C20436-24LQXI

CY8C20446-24LQXI

CY8C20466-24LQXI

CY8C20496-24LQXI

CY8C20536-24PVXI

CY8C20546-24PVXI

CY8C20566-24PVXI

CY8C20636-24LTXI

CY8C20646-24LTXI

CY8C20666-24LTXI

Pin Package

16 QFN

Flex-Pod Kit

Foot Kit

Adapter

CY3250-20266QFN

CY3250-20366QFN

CY3250-16QFN-RK

CY3250-16QFN-FK

CY3250-24QFN-FK

Not Available

See note 15

See note 19

See note 15

See note 19

16 QFN

24 QFN

32 QFN

48 SSOP

48 QFN

CY3250-20466QFN

CY3250-32QFN-RK

CY3250-32QFN-FK

Not Available

See note 15

See note 19

CY3250-20566

CY3250-48SSOP-FK

CY3250-48QFN-FK

See note 19

CY3250-20566

CY3250-20666QFN

Third-Party Tools

Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and

production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC

device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/?rID2748.

Notes

17. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

18. Foot kit includes surface mount feet that can be soldered to the target PCB.

19. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Document Number: 001-12696 Rev. *F

Page 36 of 39

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CY8C20X36/46/66/96

Ordering Information

The following table lists the CY8C20x36/46/66/96 PSoC devices' key package features and ordering codes.

Table 40. PSoC Device Key Features and Ordering Information

Analog

Flash

SRAM

CapSense

Blocks

Digital I/O

Pins

XRES

Inputs^[20]

Package

Ordering Code

USB

(Bytes) (Bytes)

16-Pin (3x3x0.6mm) QFN

CY8C20236-24LKXI

CY8C20236-24LKXIT

8K

1K

1

13

Yes

No

16-Pin (3x3x0.6mm) QFN

(Tape and Reel)

16 Pin (3x3 x 0.6 mm) QFN

CY8C20246-24LKXI

CY8C20246-24LKXIT

16K

2K

1

13

Yes

No

13

16 Pin (3x3 x 0.6 mm) QFN

(Tape and Reel)

24-Pin (4x4x0.6mm) QFN

CY8C20336-24LQXI

CY8C20336-24LQXIT

8K

1K

1

20

Yes

No

24-Pin (4x4x0.6mm) QFN

(Tape and Reel)

24 Pin (4x4 x 0.6 mm) QFN

CY8C20346-24LQXI

CY8C20346-24LQXIT

16K

2K

1

20

Yes

No

20

24 Pin (4x4 x 0.6 mm) QFN

(Tape and Reel)

24-Pin (4x4x0.6mm) QFN

CY8C20396-24LQXI

CY8C20396-24LQXIT

16K

2K

1

19

Yes

24-Pin (4x4x0.6mm) QFN

(Tape and Reel)

32-Pin (5x5x0.6mm) QFN

CY8C20436-24LQXI

CY8C20436-24LQXIT

8K

1K

1

28

Yes

No

32-Pin (5x5x0.6mm) QFN

(Tape and Reel)

32 Pin (5x5 x 0.6 mm) QFN

CY8C20446-24LQXI

CY8C20446-24LQXIT

16K

2K

1

28

Yes

No

28

32 Pin (5x5 x 0.6 mm) QFN

(Tape and Reel)

32 Pin (5x5 x 0.6 mm) QFN

CY8C20466-24LQXI

CY8C20466-24LQXIT

32K

2K

1

28

Yes

No

28

32 Pin (5x5 x 0.6 mm) QFN

(Tape and Reel)

32 Pin (5x5 x 0.6 mm) QFN

CY8C20496-24LQXI

CY8C20496-24LQXIT

16K

2K

1

25

Yes

25

32 Pin (5x5 x 0.6 mm) QFN

(Tape and Reel)

48-Pin SSOP

CY8C20536-24PVXI

CY8C20536-24PVXIT

8K

1K

1

34

Yes

No

34

48-Pin SSOP

(Tape and Reel)

48-Pin SSOP

CY8C20546-24PVXI

CY8C20546-24PVXIT

16K

2K

1

34

Yes

No

34

48-Pin SSOP

(Tape and Reel)

48-Pin SSOP

CY8C20566-24PVXI

CY8C20566-24PVXIT

32K

2K

1

34

Yes

No

34

48-Pin SSOP

(Tape and Reel)

48 Pin (7x7 mm) QFN

CY8C20636-24LTXI

CY8C20636-24LTXIT

8K

1K

1

36

Yes

No

36

48 Pin (7x7 mm) QFN

(Tape and Reel)

48 Pin (7x7 mm) QFN

CY8C20646-24LTXI

CY8C20646-24LTXIT

16K

2K

1

36

Yes

36

48 Pin (7x7 mm) QFN

(Tape and Reel)

48 Pin (7x7 mm) QFN

CY8C20666-24LTXI

CY8C20666-24LTXIT

32K

2K

1

36

Yes

36

48 Pin (7x7 mm) QFN

(Tape and Reel)

48 Pin (7x7 mm) QFN (OCD)^[4]

CY8C20066-24LTXI

32K

2K

1

36

Yes

36

Notes

20. Dual-function Digital I/O Pins also connect to the common analog mux.

Document Number: 001-12696 Rev. *F

Page 37 of 39

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CY8C20X36/46/66/96

Document History Page

Document Title: CY8C20x36/46/66/96 CapSense^®Applications

Document Number: 001-12696

Revision

**

ECN

Origin of Change Submission Date

Description of Change

766857

HMT

See ECN

New silicon and document (Revision **).

*A

*B

1242866 HMT

Add features. Update all applicable sections. Update specs.

Fix 24-pin QFN pinout moving pins inside. Update package

revisions. Update and add to Emulation and Programming

Accessories table.

2174006 AESA

See ECN

Added 48-Pin SSOP Part Pinout

Modified symbol R

Specification

to R

in Table DC Analog Mux Bus

VDD

GND

Added footnote in Table DC Analog Mux Bus Specification

Added 16K FLASH Parts. Updated Notes, Package Diagrams

and Ordering Information table. Updated Thermal Impedance

and Solder Reflow tables

*C

2587518 TOF/JASM/MNU/ 10/13/08

HMT

Converted from Preliminary to Final

Fixed broken links. Updated data sheet template.

Added operating voltage ranges with USB

ADC resolution changed from 10-bit to 8-bit

Included ADC specifications table

Included Comparator specification table

Included Voh7, Voh8, Voh9, Voh10 specs

Flash data retention – condition added to Note

Input leakage spec changed to 1 μA max

GPIO rise time for ports 0,1 and ports 2,3 made common

AC Programming specifications updated

Included AC Programming cycle timing diagram

AC SPI specification updated

The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0

Added USB specification

Added SPI CLK to P1[0]

Updated package diagrams

Updated thermal impedances for QFN packages

Updated F

Updated voltage ranges for F

parameter in Table 23

GPIO

and F

in Table 30

SPIM

SPIS

Update Development Tools, add Designing with PSoC

Designer. Edit, fix links, notes and table format. Update R

IN

formula, fix TRise parameter names in GPIO figure, fix Switch

Rate note. Update maximum data in Table 20. DC POR and

LVD Specifications.

*D

*E

2649637 SNV/AESA

2700196 SNV/PYRS

03/17/2009

04/30/2009

Changed title to “CY8C20x36/46/66, CY8C20396

CapSense™ Applications”. Updated data sheet Features, pin

information, and ordering information sections. Updated

package diagram 001-42168 to *C.

Added part numbers CY8C20496, CY8C20536, CY8C20546,

CY8C20636, CY8C20646. Updated Features on page 1

Added 48-PinQFN withoutUSB pinDiagram and Pin Definition

table. Added 32-Pin QFN (with USB) package

Added SPI Master and Slave AC Specifications

Updated Emulations and Programming Accessories Table on

page 33. Updated Ordering Information on page 37

Removed reference to Hi-Tech C Compiler in Development

Tool Selection on page 35

*F

2761504 MATT/AESA

09/09/2009

Added Note 5 and 13. Updated Table 14, 38, 39, and Ordering

Information table. Updated Figure 19.

Document Number: 001-12696 Rev. *F

Page 38 of 39

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CY8C20X36/46/66/96

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com

clocks.cypress.com

wireless.cypress.com

memory.cypress.com

image.cypress.com

psoc.cypress.com/solutions

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use

as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support

systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-12696 Rev. *F

Revised September 09, 2009

Page 39 of 39

PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are

property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these

components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the

trademarks of their respective holders.

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型号：	CY8C20346-24LQXI
厂家：	CYPRESS
描述：	CapSense Applications CapSense应用时钟
文件：	总39页 (文件大小：1045K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C20346-24LQXI [CYPRESS]

相关型号：

CY8C20346-24LQXIT

CY8C20346A-24LQXI

CY8C20346A-24LQXIT

CY8C20346AS-24LQXI

CY8C20346AS-24LQXIT

CY8C20347-24LQXI

CY8C20347-24LQXIT

CY8C20347S-24LQXI

CY8C20347S-24LQXIT

CY8C20366-24LQXI

CY8C20366-24LQXIT

CY8C20396-24LQXI