CY8C21434-24PVXI [CYPRESS]
Microcontroller, 8-Bit, FLASH, M8C CPU, 24MHz, CMOS, PDSO28,;
| 型号： | CY8C21434-24PVXI |
| 厂家： | 
CYPRESS |
| 描述： | Microcontroller, 8-Bit, FLASH, M8C CPU, 24MHz, CMOS, PDSO28, 微控制器 光电二极管 |
| 文件： | 总34页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PSoC™ Mixed-Signal Array
Preliminary Data Sheet
CY8C21234,
CY8C21334, and CY8C21434
Features
■ Powerful Harvard Architecture Processor
■ M8C Processor Speeds to 24 MHz
■ Low Power at High Speed
■ Flexible On-Chip Memory
■ Programmable Pin Configurations
■ 25 mA Drive on All GPIO
■ 8 Kbytes Flash Program Storage 50,000
Erase/Write Cycles
■ Pull Up, Pull Down, High Z, Strong, or Open
■ 512 Bytes SRAM Data Storage
■ In-System Serial Programming (ISSP™)
■ Partial Flash Updates
Drain Drive Modes on All GPIO
■ 2.4V to 5.25V Operating Voltage
■ Up to 8 Analog Inputs on GPIO
■ Configurable Interrupt on All GPIO
■ Versatile Analog Mux
■ Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pump (SMP)
■ Industrial Temperature Range: -40°C to +85°C
■ Flexible Protection Modes
■ EEPROM Emulation in Flash
■ Common Internal Analog Bus
■ Advanced Peripherals (PSoC Blocks)
■ 4 Analog Type “E” PSoC Blocks Provide:
■ Simultaneous Connection of IO Combinations
■ Capacitive Sensing Application Capability
■ Additional System Resources
■ Complete Development Tools
■ Free Development Software
- 2 Comparators with DAC Refs
- Dual 8-Bit 8:1 ADC
■ 4 Digital PSoC Blocks Provide:
(PSoC™ Designer)
■ Full-Featured, In-Circuit Emulator and
■ I2C™ Master, Slave and MultiMaster to
Programmer
400 kHz
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
■ Full Speed Emulation
■ Watchdog and Sleep Timers
■ Complex Breakpoint Structure
■ 128 Kbytes Trace Memory
■ User-Configurable Low Voltage Detection
■ Integrated Supervisory Circuit
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
■ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
■ Internal ±2.5% 24/48 MHz Oscillator
■ Internal Oscillator for Watchdog and Sleep
■ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Port 3 Port 2 Port 1 Port 0
PSoC
CORE
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
System Bus
Global Digital Interconnect
Global Analog Interconnect
Flash
CPU Core
SROM
SRAM
Sleep and
Watchdog
Interrupt
Controller
(M8C)
Clock Sources
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digi-
tal blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
(Includes IMO and ILO)
ANALOG SYSTEM
DIGITAL SYSTEM
Digital
Analog
Ref
Analog
PSoC
Block
Array
PSoC
Block Array
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Analog
Mux
I2C
SYSTEM RESOURCES
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12025 Rev. *A
1
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architec-
ture microprocessor.
Port 3
Port 2
Port 1
Port 0
To System Bus
Digital Clocks
From Core
To Analog
System
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal
arrays, I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3V to a number of PSoC subsystems, a
switch mode pump (SMP) that generates normal operating volt-
ages off a single battery cell, and various system resets sup-
ported by the M8C.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBB00
DBB01
DCB02 DCB03
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digital blocks can be connected to the GPIO
through a series of global buses that can route any signal to any
pin. Freeing designs form the constraints of a fixed peripheral
controller.
4
8
8
8
8
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
8 bits in precision.
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
The Digital System
Digital System Block Diagram
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configura-
tions include those listed below.
The Analog System
The Analog System is composed of 4 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are listed below.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ Analog-to-digital converters (up to 2, with 8-bit resolution
■ Pin-to-pin comparators (1)
■ UART 8 bit with selectable parity (up to 4)
■ SPI master, slave and multi-master
■ I2C slave and master (1 available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 4)
■ Single-ended comparators (up to 2) with absolute (1.3V) ref-
erence or 8-bit DAC reference
■ 1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns
of three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column con-
tains one CT block and one SC block.
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
June 24, 2004
Document No. 38-12025 Rev. *A
2
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a switch mode pump, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
Array Input
Configuration
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
ACI0[1:0]
ACI1[1:0]
All IO
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
X
X
ACOL1MUX
Analog MUX Bus
X
X
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
X
Array
ACE00
ASE10
ACE01
ASE11
■ An internal 1.3 voltage reference provides an absolute refer-
ence for the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Analog System Block Diagram, CY8C21x34
Depending on your PSoC device characteristics, the digital and
analog systems can have 4 digital blocks and up to 4 analog
blocks. The following table lists the resources available for
specific PSoC device groups.The PSoC device covered by this
data sheet is shown in the next to the last row of the table.
The Analog Multiplexer System
The common analog bus connects to every GPIO pin. Pins can
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with com-
parators and analog-to-digital conversion.
PSoC Device Characteristics
Switch control logic enables selected pins to precharged contin-
uously under hardware control. This enables capacitive mea-
surement for applications such as touch sensing:
PSoC Part
Number
■ Track pad, finger sensing
up to
64
CY8C29x66
CY8C27x66
CY8C27x43
CY8C24x23
CY8C22x13
CY8C21x34
CY8C21x23
4
2
2
1
1
1
1
16
8
12
12
12
12
8
4
4
4
2
1
0
0
4
4
4
2
1
2
2
12
12
12
6
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
up to
24
up to
44
8
up to
24
4
up to
16
4
3
up to
28
4a
4a
4
8
up to
16
4
4, 8
a. Limited functionality, Type ACE and ASE, compared to other device groups.
June 24, 2004
Document No. 38-12025 Rev. *A
3
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
Getting Started
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows 98, Windows
NT 4.0, Windows 2000, Windows Millennium (Me), or Windows
XP. (Reference the PSoC Designer Functional Flow diagram
below.)
The quickest path to understanding the PSoC silicon is by read-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC develop-
ment. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Context
Sensitive
Help
Graphical Designer
PSoCTM
Interface
Tele-Training
Designer
Free PSoC "Tele-Training" is available for beginners and taught
by a live marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes cover-
ing topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Importable
Design
Database
PSoC
Configuration
Sheet
Device
Database
PSoCTM
Designer
Core
Consultants
Application
Database
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Manufacturing
Information
File
Engine
Project
Database
User
Modules
Library
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
PSoC Designer Subsystems
June 24, 2004
Document No. 38-12025 Rev. *A
4
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
Debugger
PSoC Designer Software Subsystems
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfig-
uration allows for changing configurations at run time.
Online Help System
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
PSoC Development Tool Kit
June 24, 2004
Document No. 38-12025 Rev. *A
5
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
the device to your specification and provides the high-level user
module API functions.
User Modules and the PSoC
Development Process
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the hard-
ware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
Device Editor
Placement
User
Module
Selection
Source
Code
Generator
and
Parameter
-ization
Generate
Application
Application Editor
Source
Code
Editor
Project
Manager
Build
Manager
To speed the development process, the PSoC Designer Inte-
grated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library con-
tains over 50 common peripherals such as ADCs, DACs Tim-
ers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Build
All
Debugger
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Mod-
ule configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high-
level functions to control and respond to hardware events at run
time. The API also provides optional interrupt service routines
that you can adapt as needed.
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all gener-
ated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a profes-
sional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as nec-
essary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a ROM file image suitable for programming.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the set-
ting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a pictorial environment (GUI) for
configuring the hardware. You pick the user modules you need
for your project and map them onto the PSoC blocks with point-
and-click simplicity. Next, you build signal chains by intercon-
necting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger down-
loads the ROM image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
June 24, 2004
Document No. 38-12025 Rev. *A
6
CY8C21x34 Preliminary Data Sheet
PSoC™ Overview
Document Conventions
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Refer-
ence Manual on http://www.cypress.com. This document
encompasses and is organized into the following chapters and
sections.
Acronyms Used
The following table lists the acronyms that are used in this doc-
ument.
Acronym
AC
Description
1.
Pin Information ............................................................. 8
alternating current
1.1 Pinouts ................................................................... 8
1.1.1 16-Pin Part Pinout ..................................... 8
1.1.2 20-Pin Part Pinout ..................................... 9
1.1.3 28-Pin Part Pinout ................................... 10
1.1.4 32-Pin Part Pinout .................................. 11
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
2.
3.
Register Reference ..................................................... 12
EEPROM
FSR
GPIO
IO
electrically erasable programmable read-only memory
full scale range
2.1 Register Conventions ........................................... 12
2.2 Register Mapping Tables ..................................... 12
general purpose IO
Electrical Specifications ............................................ 15
input/output
3.1 Absolute Maximum Ratings ................................ 16
3.2 Operating Temperature ....................................... 16
3.3 DC Electrical Characteristics ................................ 16
3.3.1 DC Chip-Level Specifications ................... 16
3.3.2 DC General Purpose IO Specifications .... 17
3.3.3 DC Amplifier Specifications ..................... 18
3.3.4 DC Switch Mode Pump Specifications ..... 19
3.3.5 DC Analog Reference Specifications ....... 20
3.3.6 DC Analog PSoC Block Specifications ..... 20
3.3.7 DC Multiplexer Specifications ................... 20
3.3.8 DC POR and LVD Specifications ............. 21
3.3.9 DC Programming Specifications ............... 22
3.4 AC Electrical Characteristics ................................ 23
3.4.1 AC Chip-Level Specifications ................... 23
3.4.2 AC General Purpose IO Specifications .... 24
3.4.3 AC Amplifier Specifications ...................... 25
3.4.4 AC Multiplexer Specifications ................... 25
3.4.5 AC Digital Block Specifications ................. 26
3.4.6 AC External Clock Specifications ............. 27
3.4.7 AC Programming Specifications ............... 28
3.4.8 AC I2C Specifications ............................... 28
IPOR
LSb
imprecise power on reset
least-significant bit
LVD
low voltage detect
MSb
PC
most-significant bit
program counter
POR
PPOR
PSoC™
PWM
RAM
ROM
SC
power on reset
precision power on reset
Programmable System-on-Chip
pulse width modulator
random access memory
read only memory
switched capacitor
SMP
switch mode pump
Units of Measure
A units of measure table is located in the Electrical Specifica-
tions section. Table 3-1 on page 15 lists all the abbreviations
used to measure the PSoC devices.
4.
Packaging Information ............................................... 30
4.1 Packaging Dimensions ......................................... 30
4.2 Thermal Impedances .......................................... 32
Numeric Naming
Hexidecimal numbers are represented with all letters in upper-
case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
5.
6.
Ordering Information .................................................. 33
5.1 Ordering Code Definitions ................................... 33
Sales and Service Information .................................. 34
6.1 Revision History .................................................. 34
6.2 Copyrights ............................................................ 34
June 24, 2004
Document No. 38-12025 Rev. *A
7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C21x34 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1
16-Pin Part Pinout
Table 1-1. 16-Pin Part Pinout (SOIC)
Type
Pin
CY8C21234 16-Pin PSoC Device
Name
Description
No.
Digital Analog
1
2
3
4
5
IO
IO
IO
IO
I
I
I
I
P0[7] Analog column mux input.
P0[5] Analog column mux input.
P0[3] Analog column mux input.
P0[1] Analog column mux input.
AI, P0[7]
AI, P0[5]
AI, P0[3]
AI, P0[1]
SMP
Vdd
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P1[4], EXTCLK
P1[2]
SOIC
Power
Power
SMP
Switch Mode Pump (SMP) connection to
required external components.
Vss
I2C SCL, P1[1]
Vss
6
Vss
Ground connection.
P1[0], I2C SDA
7
IO
P1[1] I2C Serial Clock (SCL).
Vss Ground connection.
8
Power
9
IO
IO
IO
IO
IO
IO
IO
P1[0] I2C Serial Data (SDA).
P1[2]
10
11
12
13
14
15
16
P1[4] Optional External Clock Input (EXTCLK).
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input.
P0[6] Analog column mux input.
I
I
I
I
Power
Vdd
Supply voltage.
LEGEND A = Analog, I = Input, and O = Output.
June 2004
Document No. 38-12025 Rev. *A
8
CY8C21x34 Preliminary Data Sheet
1. Pin Information
1.1.2
20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (SSOP)
Type
Pin
CY8C21334 20-Pin PSoC Device
Name
Description
No.
Digital Analog
1
2
IO
IO
IO
IO
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Ground connection.
AI, P0[7]
AI, P0[5]
Vdd
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
3
AI, P0[3]
4
AI, P0[1]
Vss
5
Power
Power
SSOP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
6
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P1[6]
7
P1[4], EXTCLK
P1[2]
8
I2C SCL, P1[1]
Vss
9
I2C Serial Clock (SCL).
Ground connection.
P1[0], I2C SDA
10
10
11
12
13
IO
IO
IO
P1[0]
P1[2]
P1[4]
I2C Serial Data (SDA).
Optional External Clock Input (EXT-
CLK).
14
15
IO
P1[6]
Input
XRES
Active high pin reset with internal pull
down.
16
17
18
19
20
IO
IO
IO
IO
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Power
LEGEND A = Analog, I = Input, and O = Output.
June 24, 2004
Document No. 38-12025 Rev. *A
9
CY8C21x34 Preliminary Data Sheet
1. Pin Information
1.1.3
28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (SSOP)
Type
Pin
CY8C21434 28-Pin PSoC Device
Name
Description
No.
Digital Analog
1
2
IO
IO
I
I
P0[7]
P0[5]
Analog column mux input.
AI, P0[7]
AI, P0[5]
AI, P0[3]
AI, P0[1]
P2[7]
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Analog column mux input and column
output.
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6]
3
IO
I
I
P0[3]
Analog column mux input and column
output.
4
5
6
7
8
9
IO
IO
IO
IO
IO
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
Analog column mux input.
P2[5]
AI, P2[3]
AI, P2[1]
SMP
P2[4]
SSOP
P2[2], AI
P2[0], AI
XRES
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
P1[6]
Power
Switch Mode Pump (SMP) connection to
required external components.
P1[4], EXTCLK
P1[2]
I2C SCL, P1[1]
Vss
10
11
12
13
14
15
16
17
18
19
IO
IO
IO
IO
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
P1[0], I2C SDA
I2C Serial Clock (SCL)
Ground connection.
I2C Serial Data (SDA)
Power
Input
IO
IO
IO
IO
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Optional External Clock Input (EXTCLK)
Active high pin reset with internal pull
down.
20
21
22
23
24
25
26
27
28
IO
IO
IO
IO
IO
IO
IO
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Direct switched capacitor block input.
Direct switched capacitor block input.
I
I
I
I
Analog column mux input.
Analog column mux input.
Analog column mux input
Analog column mux input.
Supply voltage.
Power
LEGEND A: Analog, I: Input, O: Output.
June 24, 2004
Document No. 38-12025 Rev. *A
10
CY8C21x34 Preliminary Data Sheet
1. Pin Information
1.1.4
32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Type
Pin
CY8C21434 32-Pin PSoC Device
Name
Description
No.
Digital Analog
1
2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
Analog column mux input.
3
4
AI, P0[1]
P2[7]
1
2
3
4
5
6
7
8
P0[0], AI
P2[6]
24
23
22
21
20
19
18
5
6
P2[5]
P2[3]
P2[1]
P3[3]
P2[4]
P2[2]
P2[0]
P3[2]
P3[0]
7
MLF
(Top View)
8
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
9
10
11
12
13
14
15
P3[1]
I2C Serial Clock (SCL)
Ground connection.
I2C Serial Data (SDA)
I2C SCL, P1[7]
17 XRES
Power
IO
IO
IO
P1[0]
P1[2]
P1[4]
Optional External Clock Input
(EXTCLK)
16
17
IO
P1[6]
Input
XRES
Active high pin reset with internal
pull down.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
I
I
Analog column mux input.
Analog column mux input.
Analog column mux input
Analog column mux input.
Supply voltage.
Power
Power
IO
IO
IO
I
I
I
P0[7]
P0[5]
P0[3]
Vss
Analog column mux input.
Analog column mux input.
Analog column mux input.
Ground connection.
LEGEND A = Analog, I = Input, and O = Output.
* Note The MLF package has a center pad that must be connected
to the same ground as the Vss pin.
June 24, 2004
Document No. 38-12025 Rev. *A
11
2. Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device by way of mapping tables, in offset order. For detailed register infor-
mation, reference the PSoC™ Mixed Signal Array Technical Reference Manual.
2.1
Register Conventions
2.2
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as IO space and is
broken into two parts. The XOI bit in the Flag register deter-
mines which bank the user is currently in. When the XOI bit is
set, the user is said to be in the “extended” address space or
the “configuration” registers.
Convention
Description
Read and write register or bit(s)
Read register or bit(s)
RW
R
W
L
Write register or bit(s)
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
June 2004
Document No. 38-12025 Rev. *A
12
CY8C21x34 Preliminary Data Sheet
2. Register Reference
Register Map 0 Table: User Space
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC10CR0
ASD11CR0
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
PRT3GS
PRT3DM2
CUR_PP
STK_PP
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
IDX_PP
RW
RW
RW
RW
#
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
AMUXCFG
PWM_CR
RW
RW
RW
W
RW
#
RES_WDT
#
CMP_CR0
CMP_CR1
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
#
#
ADC0_CR
ADC1_CR
W
RW
#
#
TMP0_DR
TMP1_DR
TMP2_DR
TMP3_DR
RW
RW
RW
RW
W
RW
#
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDIOLT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
ACB00CR1
ACB00CR2
RW
RW
ACB01CR1
ACB01CR2
RW
RW
CPU_F
RL
DAC_D
CPU_SCR1
CPU_SCR0
RW
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
June 24, 2004
Document No. 38-12025 Rev. *A
13
CY8C21x34 Preliminary Data Sheet
2. Register Reference
Register Map 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
ASC10CR0
ASD11CR0
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
OSC_GO_EN DD
RW
RW
RW
RW
RW
RW
RW
R
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
ADC0_TR
ADC1_TR
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
CMP_GO_EN 64
65
RW
RW
AMD_CR1
ALT_CR0
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
W
W
CLK_CR2
RW
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
MUX_CR6
MUX_CR7
RW
W
RW
RW
RW
RW
CLK_CR3
TMP0_DR
TMP1_DR
TMP2_DR
TMP3_DR
RW
RW
RW
RW
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDIOLT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
ACB00CR1
ACB00CR2
ACB01CR1
ACB01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
DAC_CR
CPU_SCR1
CPU_SCR0
RW
#
#
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
June 24, 2004
Document No. 38-12025 Rev. *A
14
3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 85oC and T ≤ 100oC as specified, except where noted.
A
J
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO
Mode=0
3.00
2.40
SLIMO SLIMO
Mode=1 Mode=1
93 kHz 3 MHz
CPU Frequency
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
Figure 3-1a. Voltage versus CPU Frequency
Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
oC
Unit of Measure
Symbol
µW
mA
ms
mV
nA
Unit of Measure
degree Celsius
decibels
micro watts
milli-ampere
milli-second
milli-volts
dB
fF
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nano ampere
nanosecond
nanovolts
Kbit
kHz
kΩ
ns
kilohertz
nV
kilohm
Ω
ohm
MHz
MΩ
µA
megahertz
megaohm
micro ampere
micro farad
micro henry
microsecond
micro volts
pA
pico ampere
pico farad
pF
pp
peak-to-peak
parts per million
picosecond
µF
ppm
ps
µH
µs
sps
σ
samples per second
sigma: one standard deviation
volts
µV
µVrms
micro volts root-mean-square
V
June 2004
Document No. 38-12025 Rev. *A
15
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.1
Absolute Maximum Ratings
Table 3-2. Absolute Maximum Ratings
Symbol
Description
Min
-55
Typ
Max
+100
Units
oC
Notes
TSTG
Storage Temperature
–
Higher storage temperatures will reduce data
retention time.
oC
V
TA
Vdd
VIO
–
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
–
–
–
–
–
–
–
+85
-0.5
+6.0
Vss - 0.5
Vss - 0.5
-25
Vdd + 0.5
Vdd + 0.5
+50
V
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Static Discharge Voltage
V
IMIO
–
mA
V
2000
–
–
–
Latch-up Current
200
mA
3.2
Operating Temperature
Table 3-3. Operating Temperature
Symbol
TA
Description
Min
-40
Typ
Max
+85
Units
Notes
oC
oC
Ambient Temperature
Junction Temperature
–
–
TJ
-40
+100
The temperature rise from ambient to junction is
package specific. See “Thermal Impedances”
on page 32. The user must limit the power con-
sumption to comply with this requirement.
3.3
DC Electrical Characteristics
3.3.1
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-4. DC Chip-Level Specifications
Symbol
Vdd
Description
Min
2.40
Typ
Max
5.25
Units
Notes
Supply Voltage
–
2
V
Conditions are Vdd = 5.0V, 25oC, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
IDD
Supply Current, IMO = 24 MHz
Supply Current, IMO = 6 MHz
Supply Current, IMO = 6 MHz
–
–
–
4
mA
mA
mA
Conditions are Vdd = 3.3V, 25oC, CPU = 3 MHz,
clock doubler disabled. VC1 = 375 kHz, VC2 =
23.4 kHz, VC3 = 23.4 kHz.
IDD3
1
2
Conditions are Vdd = 2.55V, 25oC, CPU = 3
MHz, clock doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 23.4 kHz.
IDD27
0.8
1.5
Vdd = 2.55V, 0oC to 40oC.
ISB27
ISB
VREF
VREF27
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active. Mid temperature range.
–
0.95
2.5
2
µA
µA
V
Vdd = 3.3V, -40oC ≤ TA ≤ 85oC.
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and internal slow oscillator active.
–
5
Reference Voltage (Bandgap)
1.28
1.235
1.30
1.30
1.32
1.330
Trimmed for appropriate Vdd. Vdd = 3.0V to
5.25V.
Reference Voltage (Bandgap)
V
Trimmed for appropriate Vdd. Vdd = 2.4V to
3.0V.
June 24, 2004
Document No. 38-12025 Rev. *A
16
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-5. DC GPIO Specifications for Vdd >= 3.0V
Symbol
RPU
Description
Min
Typ
5.6
Max
Units
kΩ
Notes
Pull up Resistor
4
4
8
8
–
RPD
Pull down Resistor
High Output Level
5.6
–
kΩ
VOH
Vdd - 1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 IO switch-
ing, 4 per side)
VOL
Low Output Level
–
–
0.75
0.8
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 IO switch-
ing, 4 per side)
VIL
Input Low Level
Input High Level
Input Hysteresis
–
–
V
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
VIH
VH
2.1
–
–
V
60
1
–
mV
nA
pF
pF
IIL
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
–
Gross tested to 1 µA.
Package and pin dependent. Temp = 25oC.
Package and pin dependent. Temp = 25oC.
CIN
COUT
–
3.5
3.5
10
10
–
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and
-40°C ≤ TA ≤ 85°C. Typical parameters apply to 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-6. DC GPIO Specifications for 2.4V to 3.0V
Symbol
RPU
Description
Min
Typ
5.6
Max
Units
kΩ
Notes
Pull up Resistor
4
4
8
8
–
RPD
Pull down Resistor
High Output Level
5.6
–
kΩ
VOH
Vdd - 0.4
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 IO switch-
ing, 4 per side)
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 IO switch-
ing, 4 per side)
VIL
Input Low Level
Input High Level
Input Hysteresis
–
–
0.8
–
V
Vdd = 3.0 to 5.5
Vdd = 3.0 to 5.5
VIH
VH
2.0
–
–
V
60
1
–
mV
nA
pF
pF
IIL
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
–
Gross tested to 1 µA.
Package and pin dependent. Temp = 25oC.
Package and pin dependent. Temp = 25oC.
CIN
COUT
–
3.5
3.5
10
10
–
June 24, 2004
Document No. 38-12025 Rev. *A
17
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.3
DC Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-7. 5V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
Min
Typ
2.5
Max
Units
mV
Notes
–
–
–
–
15
–
µV/oC
pA
TCVOSOA
IEBOA
10
200
4.5
–
–
Gross tested to 1 µA.
Package and pin dependent. Temp = 25oC.
CINOA
9.5
pF
VCMOA
0.0
Vdd - 1
V
GOLOA
ISOA
Open Loop Gain
80
–
–
–
dB
Amplifier Supply Current
10
30
µA
Table 3-8. 3.3V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
Open Loop Gain
Min
Typ
2.5
Max
Units
Notes
–
15
mV
µV/oC
pA
TCVOSOA
IEBOA
–
10
200
4.5
–
–
–
–
Gross tested to 1 µA.
Package and pin dependent. Temp = 25oC.
CINOA
VCMOA
GOLOA
ISOA
–
9.5
pF
0
Vdd - 1
–
V
80
–
–
dB
Amplifier Supply Current
10
30
µA
Table 3-9. 2.7V DC Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range
Open Loop Gain
Min
Typ
Max
Units
mV
µV/oC
pA
Notes
–
2.5
10
200
4.5
–
15
TCVOSOA
IEBOA
–
–
–
–
Gross tested to 1 µA.
Package and pin dependent. Temp = 25oC.
CINOA
VCMOA
GOLOA
ISOA
–
9.5
pF
0
Vdd - 1
–
V
80
–
–
dB
Amplifier Supply Current
10
30
µA
June 24, 2004
Document No. 38-12025 Rev. *A
18
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.4
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-10. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
5V Output Voltage from Pump
3.3V Output Voltage from Pump
2.6V Output Voltage from Pump
Min
4.75
Typ
5.0
Max
5.25
Units
Notes
Average, neglecting ripple
Average, neglecting ripple
Average, neglecting ripple
VPUMP 5V
V
V
V
V
V
PUMP 3V
PUMP 2V
3.00
2.45
3.25
2.55
3.60
2.70
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.8V, VPUMP = 5.0V
For implementation, which includes 2 uH induc-
tor, 1 uF cap, and Schottky diode.
8
5
5
–
–
–
–
–
–
mA
mA
mA
V
BAT = 1.3V, VPUMP = 2.55V
VBAT 5V
Input Voltage Range from Battery
Input Voltage Range from Battery
Input Voltage Range from Battery
Minimum Input Voltage from Battery to Start Pump
Line Regulation (over Vi range)
Load Regulation
1.8
1.0
1.0
1.2
–
–
5.0
3.3
3.0
–
V
V
V
BAT3V
BAT 2V
–
V
–
V
VBATSTART
–
V
∆VPUMP_Line
∆VPUMP_Load
5
–
%VO
%VO
mVpp
–
5
–
∆VPUMP_Ripple Output Voltage Ripple (depends on cap/load)
–
25
–
For I load = 5mA, VPUMP = 3.25V, 2 uH induc-
tor, 1 uF capacitor, and Schottky diode.
E3
Efficiency
Efficiency
35
35
50
80
–
–
%
%
For I load = 5mA, VPUMP = 3.25V, 2 uH induc-
tor, 1 uF capacitor, and Schottky diode.
E255
For I load = 1mA, VPUMP = 2.55V, VBAT = 1.3V,
10 uH inductor, 1 uF capacitor, and Schottky
diode.
FPUMP
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
DCPUMP
D1
Vdd
VPUMP
L1
SMP
+
C1
VBAT
TM
Battery
PSoC
Vss
Figure 3-2. Basic Switch Mode Pump Circuit
June 24, 2004
Document No. 38-12025 Rev. *A
19
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.5
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks.
Table 3-11. DC Analog Reference Specifications
Symbol
Description
Min
VREF - 0.003
Typ
Max
Units
–
AGND = BandGap
VREF
VREF + 0.003
V
3.3.6
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-12. DC Analog PSoC Block Specifications
Symbol
FLP1
Description
Min
Typ
Max
Units
kHz
kHz
Notes
Low-Pass Filter Frequency for ADC, Slow Setting
Low-Pass Filter Frequency for ADC, Fast Setting
–
–
4
–
–
FLP2
40
3.3.7
DC Multiplexer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-13. DC Multiplexer Specifications
Symbol
RSW
Description
Min
Typ
Max
400
800
Units
Notes
Switch Resistance to Common Analog Bus
–
–
–
–
Ω
Ω
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
RVCC
Resistance of Initialization Switch to Vcc
TBD
Ω
June 24, 2004
Document No. 38-12025 Rev. *A
20
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.8
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-14. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
VPPOR0R
VPPOR1R
VPPOR2R
2.36
2.399
V
V
V
PORLEV[1:0] = 01b
–
–
2.82
4.55
2.950
4.700
PORLEV[1:0] = 10b
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
VPPOR0
VPPOR1
VPPOR2
2.36
2.82
4.55
V
V
V
PORLEV[1:0] = 01b
–
PORLEV[1:0] = 10b
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.505a
2.990b
3.090
3.200
4.550
4.750
4.830
4.950
V
V
V
V
V
V
V
V
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.400
2.850
2.950
3.060
4.370
4.500
4.620
4.710
2.45
2.921
3.023
3.133
4.483
4.643
4.727
4.814
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.620c
3.090
3.160
3.320d
4.740
4.830
4.920
5.120
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
2.495
2.960
3.030
3.180
4.540
4.620
4.710
4.890
2.55
V
V
V
V
V
V
V
V
3.023
3.095
3.250
4.643
4.727
4.815
5.000
a. Always greater than 50 mV above V
(PORLEV = 00) for falling supply.
PPOR
b. Always greater than 50 mV above V
(PORLEV = 01) for falling supply.
PPOR
c. Always greater than 50 mV above VLVD0
d. Always greater than 50 mV above VLVD3
.
.
June 24, 2004
Document No. 38-12025 Rev. *A
21
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.3.9
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-15. DC Programming Specifications
Symbol
VddIWRITE
IDDP
Description
Min
2.70
Typ
Max
Units
Notes
Minimum Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
–
5
–
–
–
–
V
–
25
0.8
–
mA
V
VILP
–
VIHP
2.2
–
V
IILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
0.2
mA
Driving internal pull-down resistor.
Driving internal pull-down resistor.
IIHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
VOLV
VOHV
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
Vss + 0.75
Vdd
V
V
Vdd - 1.0
FlashENPB
FlashENT
FlashDR
Flash Endurance (per block)
Flash Endurance (total)a
Flash Data Retention
50,000
1,800,000
10
–
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
–
Years
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
The PSoC devices use an adaptive algorithm to enhance endurance over the industrial temperature range (-40°C to +85°C ambient). Any temperature range within a 50°C
span between 0°C and 85°C is considered constant with respect to endurance enhancements. For instance, if room temperature (25°C) is the nominal operating tempera-
ture, then the range from 0°C to 50°C can be approximated by the constant value 25 and a temperature sensor is not needed.
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
June 24, 2004
Document No. 38-12025 Rev. *A
22
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-16. 5V and 3.3V AC Chip-Level Specifications
Symbol
FIMO24
Description
Min
23.4
Typ
Max
Units
MHz
Notes
24.6a,b,c
Internal Main Oscillator Frequency for 24 MHz
24
6
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 15.
6.15a,b,c
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.85
MHz
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 15.
a,b
FCPU1
FCPU2
FBLK5
CPU Frequency (5V Nominal)
0.93
0.93
0
24
12
48
MHz
MHz
MHz
24.6
12.3b,c
CPU Frequency (3.3V Nominal)
a,b,d
Digital PSoC Block Frequency0(5V Nominal)
49.2
Refer to the AC Digital Block Specifica-
tions below.
b,d
FBLK33
Digital PSoC Block Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
32 kHz Period Jitter
0
24
32
MHz
kHz
ns
24.6
F32K1
15
–
64
Jitter32k
TXRST
100
–
External Reset Pulse Width
10
40
–
–
µs
DC24M
Step24M
Fout48M
Jitter24M1
FMAX
24 MHz Duty Cycle
50
50
48.0
600
–
60
%
24 MHz Trim Step Size
–
kHz
MHz
ps
49.2a,c
48 MHz Output Frequency
46.8
–
Trimmed. Utilizing factory trim values.
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
12
–
MHz
µs
TRAMP
0
–
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V.
d. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
Table 3-17. 2.7V AC Chip-Level Specifications
Symbol
FIMO12
Description
Min
10.80
Typ
120
Max
Units
MHz
Notes
12.5a,b,c
Internal Main Oscillator Frequency for 12 MHz
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
6.25a,b,c
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
MHz
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
3.15a,b
FCPU1
CPU Frequency (2.7V Nominal)
0.93
0
3
MHz
MHz
12.5a,b,c
FBLK27
Digital PSoC Block Frequency (2.7V Nominal)
12
Refer to the AC Digital Block Specifica-
tions below.
F32K1
Internal Low Speed Oscillator Frequency
8
32
96
kHz
Jitter32k
TXRST
32 kHz Period Jitter
–
150
–
ns
External Reset Pulse Width
24 MHz Duty Cycle
10
40
–
–
µs
DC24M
Step24M
Jitter24M1
FMAX
50
50
800
–
60
–
%
24 MHz Trim Step Size
kHz
ps
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
–
12
–
MHz
µs
TRAMP
0
–
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
June 24, 2004
Document No. 38-12025 Rev. *A
23
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
Jitter24M1
F24M
Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram
3.4.2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-18. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
Description
GPIO Operating Frequency
Min
Typ
Max
Units
MHz
Notes
0
–
12
18
18
–
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
2
–
10
10
27
22
–
Table 3-19. 2.7V AC GPIO Specifications
Symbol
FGPIO
Description
GPIO Operating Frequency
Min
Typ
Max
Units
Notes
Normal Strong Mode
0
–
3
MHz
ns
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
6
–
50
50
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
6
–
ns
18
18
40
40
120
120
ns
ns
90%
10%
GPIO
Pin
TRiseF
TRiseS
TFallF
TFallS
Figure 3-5. GPIO Timing Diagram
June 24, 2004
Document No. 38-12025 Rev. *A
24
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.4.3
AC Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-20. AC Amplifier Specifications
Symbol
TCOMP
Description
Min
Typ
Max
100
200
Units
ns
ns
Notes
Comparator Mode Response Time, 50 mV Overdrive
Vcc ≥ 3.0V.
2.4V < Vcc < 3.0V.
3.4.4
AC Multiplexer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-21. AC Multiplexer Specifications
Symbol
FSW
Description
Min
Typ
Max
Units
MHz
Notes
Switch Rate
–
–
3
June 24, 2004
Document No. 38-12025 Rev. *A
25
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.4.5
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-22. AC Digital Block Specifications, Vcc ≥ 3.0V
Function
Description
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
Min
Typ
Maxa
48
Units
MHz
Notes
4.75V < Vdd < 5.25V.
All
Functions
Timer
24
–
MHz
ns
3.0V < Vdd < 4.75V.
50b
–
–
–
–
–
–
Maximum Frequency, No Capture
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
48
24
–
MHz
MHz
ns
4.75V < Vdd < 5.25V.
–
50b
–
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
48
24
MHz
MHz
4.75V < Vdd < 5.25V.
–
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
50b
50b
–
–
–
–
–
–
–
ns
Synchronous Restart Mode
Disable Mode
–
ns
–
ns
Maximum Frequency
48
48
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
CRCPRS
Maximum Input Clock Frequency
–
(PRS Mode)
CRCPRS
Maximum Input Clock Frequency
–
–
24
MHz
(CRC Mode)
SPIM
SPIS
Maximum Input Clock Frequency
–
–
–
–
–
8
MHz
MHz
ns
Maximum Input Clock Frequency
–
4
50b
–
Width of SS_ Negated Between Transmissions
–
Transmitter Maximum Input Clock Frequency
Receiver Maximum Input Clock Frequency
16
MHz
–
16
8
48
24
MHz
MHz
4.75V < Vdd < 5.25V.
3.0V < Vdd < 4.75V.
a. Maximum frequencies refer to typical oscillator settings and do not include oscillator tolerance. Refer to 5V and 3.3V AC Chip-Level Specifications, on page 23 for actual lim-
its.
b. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Table 3-23. 2.7V AC Digital Block Specifications
Function
All
Description
Min
Typ
Maxa
12
Units
MHz
Notes
Maximum Block Clocking Frequency
2.4V < Vdd < 3.0V.
Functions
100b
Timer
Capture Pulse Width
–
–
–
–
–
–
ns
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
12
–
MHz
ns
100b
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
48
24
MHz
MHz
4.75V < Vdd < 5.25V.
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
–
–
–
–
–
–
ns
100b
100b
–
Synchronous Restart Mode
Disable Mode
–
ns
–
ns
Maximum Frequency
12
12
MHz
MHz
CRCPRS
Maximum Input Clock Frequency
–
(PRS Mode)
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
12
6
MHz
MHz
SPIM
June 24, 2004
Document No. 38-12025 Rev. *A
26
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
Table 3-23. 2.7V AC Digital Block Specifications (continued)
SPIS
Maximum Input Clock Frequency
–
–
–
–
–
4
ns
100b
Width of SS_ Negated Between Transmissions
–
ns
Transmitter Maximum Input Clock Frequency
Receiver Maximum Input Clock Frequency
–
–
12
12
MHz
MHz
a. Maximum frequencies refer to typical oscillator settings and do not include oscillator tolerance. Refer to 2.7V AC Chip-Level Specifications, on page 23 for actual limits.
b. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
3.4.6
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
and are for design guidance only or unless otherwise specified.
Table 3-24. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
24.24
Units
MHz
Notes
FOSCEXT
Frequency
High Period
Low Period
0
–
–
–
–
–
–
–
20.6
20.6
150
–
–
–
ns
ns
µs
Power Up IMO to Switch
Table 3-25. 3.3V AC External Clock Specifications
Symbol
Description
Frequency with CPU Clock divide by 1a
Frequency with CPU Clock divide by 2 or greaterb
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
Min
Typ
Max
Units
Notes
12.120
FOSCEXT
0
–
–
–
–
–
MHz
MHz
ns
24.240
FOSCEXT
0
–
–
–
41.7
41.7
150
–
–
–
ns
µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
Table 3-26. 2.7V AC External Clock Specifications
Symbol
Description
Frequency with CPU Clock divide by 1a
Frequency with CPU Clock divide by 2 or greaterb
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
Min
Typ
Max
Units
MHz
Notes
12.120
FOSCEXT
0
0
–
–
–
–
–
24.240
FOSCEXT
MHz
ns
–
–
–
41.7
41.7
150
–
–
–
ns
µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
June 24, 2004
Document No. 38-12025 Rev. *A
27
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
3.4.7
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
and are for design guidance only or unless otherwise specified.
Table 3-27. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Min
Typ
Max
Units
ns
Notes
Rise Time of SCLK
Fall Time of SCLK
1
–
20
20
–
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB Flash Erase Time (Block)
–
15
30
–
–
TWRITE
TDSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
2
3.4.8
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only or unless otherwise specified.
Table 3-28. AC Characteristics of the I2C SDA and SCL Pins for Vcc ≥ 3.0V
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
Description
SCL Clock Frequency
Units
kHz
Notes
FSCLI2C
0
0
400
–
THDSTAI2C Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
µs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
µs
µs
µs
µs
ns
µs
µs
ns
–
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
–
–
100a
0.6
1.3
0
TSUDATI2C Data Set-up Time
250
4.0
–
TSUSTOI2C Set-up Time for STOP Condition
–
TBUFI2C
TSPI2C
Bus Free Time Between a STOP and START Condition 4.7
–
Pulse Width of spikes are suppressed by the input fil-
ter.
–
50
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This will automatically be
SU;DAT
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax SU;DAT
Table 3-29. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
Description
SCL Clock Frequency
Units
kHz
Notes
FSCLI2C
0
–
–
–
–
THDSTAI2C Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0
–
µs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
–
–
–
–
µs
µs
µs
µs
TSUSTAI2C Set-up Time for a Repeated START Condition
THDDATI2C Data Hold Time
June 24, 2004
Document No. 38-12025 Rev. *A
28
CY8C21x34 Preliminary Data Sheet
3. Electrical Specifications
Table 3-29. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued)
Standard Mode
Min Max
250
4.0
Bus Free Time Between a STOP and START Condition 4.7
Fast Mode
Min Max
Symbol
Description
Units
ns
Notes
TSUDATI2C Data Set-up Time
–
–
–
–
–
–
–
–
–
–
–
–
TSUSTOI2C Set-up Time for STOP Condition
TBUFI2C
TSPI2C
µs
µs
ns
Pulse Width of spikes are suppressed by the input fil-
ter.
–
SDA
SCL
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Figure 3-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
June 24, 2004
Document No. 38-12025 Rev. *A
29
4. Packaging Information
4.1
Packaging Dimensions
This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
PIN 1 ID
8
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
REFERENCE JEDEC MO-119
*
0.291[7.391]
0.299[7.594]
*
0.394[10.007]
0.419[10.642]
PART #
9
16
S16.3 STANDARD PKG.
SZ16.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.397[10.083]
0.413[10.490]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
0.0091[0.231]
0.0125[0.317]
*
0.050[1.270]
TYP.
0.004[0.101]
0.0118[0.299]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
51-85022 *B
Figure 4-1. 16-Lead (150-Mil) SOIC
June 2004
Document No. 38-12025 Rev. *A
30
CY8C21x34 Preliminary Data Sheet
4. Packaging Information
51-85077 *C
Figure 4-2. 20-Lead (210-MIL) SSOP
51-85079 - *C
Figure 4-3. 28-Lead (210-Mil) SSOP
June 24, 2004
Document No. 38-12025 Rev. *A
31
CY8C21x34 Preliminary Data Sheet
4. Packaging Information
51-85188 **
Figure 4-4. 32-Lead (5x5 mm) MLF
4.2
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
16 SOIC
20 SSOP
Typical θJA
96 oC/W
95 oC/W
TBD
28 SSOP
32 MLF
TBD
TJ = TA + Power x θJA
June 24, 2004
Document No. 38-12025 Rev. *A
32
5. Ordering Information
The following table lists the CY8C21x34 PSoC Device family’s key package features and ordering codes.
CY8C21x34 PSoC Device Key Features and Ordering Information
a
a
a
a
a
a
a
a
16 Pin (150-Mil) SOIC
CY8C21234-24SXI
CY8C21234-24SXIT
CY8C21334-24PVXI
CY8C21334-24PVXIT
CY8C21434-24PVXI
CY8C21434-24PVXIT
CY8C21434-24LFXI
CY8C21434-24LFXIT
8
8
8
8
8
8
8
8
512
512
512
512
512
512
512
512
Yes -40°C to +85°C
Yes -40°C to +85°C
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
12
12
16
16
16
16
28
28
0
0
0
0
0
0
0
0
No
No
8
8
8
8
8
8
8
8
16 Pin (150-Mil) SOIC
(Tape and Reel)
20 Pin (300-Mil) SSOP
No
No
No
No
No
No
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Yes
Yes
Yes
Yes
Yes
Yes
20 Pin (300-Mil) SSOP
(Tape and Reel)
28 Pin (210-Mil) SSOP
28 Pin (210-Mil) SSOP
(Tape and Reel)
32 Pin (5x5) MLF
32 Pin (5x5) MLF
(Tape and Reel)
a. All Digital IO Pins also connect to the common analog mux.
5.1
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
PX = PDIP Pb Free
SX = SOIC Pb Free
Thermal Rating:
C = Commercial
I = Industrial
PVX = SSOP Pb Free
LFX = MLF Pb Free
AX = TQFP Pb Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
June 24, 2004
Document No. 38-12025 Rev. *A
33
6. Sales and Service Information
To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone:
Facsimile:
800.669.0557
425.787.4641
Web Sites: Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
6.1
Revision History
Document Title:
CY8C21x34 PSoC Mixed Signal Array Preliminary Data Sheet
Document Number: 38-12025
Revision
**
ECN #
Issue Date
Origin of Change
HMT
Description of Change
New silicon and document (Revision **).
05/19/2004
227340
Updated Overview and Electrical Spec. chapters, along with revisions to the
24-pin pinout part. Revised the register mapping tables. Added a 28-pin
pinout part.
*A
235992
See ECN
SFV
Distribution: External/Public
Posting: None
6.2
Copyrights
© Cypress MicroSystems, Inc. 2004. All rights reserved. PSoC™ (Programmable System-on-Chip™) are trademarks of Cypress MicroSystems, Inc. All other trademarks
or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Micro-
Systems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applications, unless pursuant to an express written agreement with Cypress MicroSystems.
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12025 Rev. *A
34
相关型号：
CY8C21434B-24LCXI
Multifunction Peripheral, CMOS, 5 X 5 MM 0.40 MM HEIGHT, LEAD FREE, MO-220, QFN-32
CYPRESS
CY8C21434B-24LCXIT
Multifunction Peripheral, CMOS, 5 X 5 MM 0.40 MM HEIGHT, LEAD FREE, MO-220, QFN-32
CYPRESS
©2020 ICPDF网 联系我们和版权申明