CY8C22213-24PVXIT [CYPRESS]
Multifunction Peripheral, CMOS, PDSO20, 0.210 INCH, SSOP-20;
| 型号： | CY8C22213-24PVXIT |
| 厂家： | 
CYPRESS |
| 描述： | Multifunction Peripheral, CMOS, PDSO20, 0.210 INCH, SSOP-20 光电二极管 |
| 文件： | 总24页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C21323
PRELIMINARY
Automotive PSoC® Programmable
System-on-Chip™
Features
Logic Block Diagram
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ Low Power at High Speed
❐ 4.75V to 5.25V Operating Voltage
❐ Automotive Temperature Range: -40°C to +125°C
■ Advanced Peripherals (PSoC® Blocks)
❐ 4 Analog Type “E” PSoC Blocks Provide:
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
❐ 4 Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 4K Flash Program Storage 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 Bytes Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±4% 24 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to eight Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Additional System Resources
❐ I2C™ Master, Slave and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
Cypress Semiconductor Corporation
Document Number:001-06161 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 21, 2009
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Figure 1. Digital System Block Diagram
PSoC Functional Overview
Port 1
The PSoC family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
Port 0
To System Bus
Digital Clocks
FromCore
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
4
The PSoC architecture, as illustrated in the “Logic Block
Diagram” on page 1, is comprised of four main areas: the Core,
the System Resources, the Digital System, and the Analog
System. Configurable global bus resources enable all the device
resources to be combined into a complete custom system. Each
PSoC device includes four digital blocks. Depending on the
PSoC package, up to two analog comparators and up to 16
general purpose IO (GPIO) are also included. The GPIO provide
access to the global digital and analog interconnects.
DBB00
DBB01
DCB02
DCB03
8
8
8
8
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
GIE[7:0]
GIO[7:0]
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a two MIPS 8-bit Harvard
architecture microprocessor.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references. Digital
peripheral configurations include the following:
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal arrays,
I2C functionality for implementing an I2C master, slave,
Multi-Master, an internal voltage reference that provides an
absolute value of 1.3V to a number of PSoC subsystems, and
various system resets supported by the M8C.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digital blocks can be connected to the GPIO
through a series of global busses that can route any signal to any
pin, freeing designs from the constraints of a fixed peripheral
controller.
■ UART 8 bit with selectable parity (up to 4)
■ SPI master and slave
■ I2C slave, master, multi-master (1 available as a System
Resource)
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA (up to 4)
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global busses that can route any signal to any pin. The
busses also enable signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device
Characteristics” on page 3.
Document Number:001-06161 Rev. *A
Page 2 of 24
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The Analog System
Additional System Resources
The Analog System is composed of four configurable blocks to
allow creation of complex analog signal flows. Analog periph-
erals are very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The following statements describe the merits of each
system resource:
■ Analog-to-digital converters (single or dual, with up to 10-bit
resolution)
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ Pin-to-pin comparators (1)
■ Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■ 1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
The number of blocks is on the device family which is detailed in
the table titled “PSoC Device Characteristics” on page 3.
PSoC Device Characteristics
Figure 2. Analog System Block Diagram, CY8C21323
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The PSoC device covered by
this data sheet is highlighted here.
Array Input
Configuration
Table 1. PSoC Device Characteristics
PSoC Part
Number
ACI0[1:0]
ACI1[1:0]
CY8C29x66
CY8C27x43
up to
64
4
2
16
8
12
12
4
4
4
4
12
12
2K
32K
16K
up to
44
256
Bytes
AC O L 1MU X
CY8C24x94
49
1
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
Array
CY8C24x23A
up to
24
256
Bytes
[1]
ACE00
ASE10
ACE01
ASE11
CY8C21x34
CY8C21x23
up to
28
1
1
4
4
28
8
0
0
2
2
4
512
8K
4K
Bytes
[1]
16
4
256
Bytes
Note
1. Limited analog functionality.
Document Number:001-06161 Rev. *A
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PSoC Consultant go to http://www.cypress.com, click on Support
located at the top of the web page, and select CYPros
Consultants.
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the PSoC
Programmable System-on-Chip Technical Reference Manual,
which can be found on http://www.cypress.com/psoc.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/.
Application Notes
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at http://www.cypress.com.
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to
http://www.cypress.com and select Application Notes under
Documentation list located in the center of the web page.
Development Kits
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
Order >> Buy Kits at http://www.cypress.com/shop, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. (Reference the PSoC Designer
Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Technical Training
Free On-Demand PSoC Training modules are available for new
users to PSoC. Training modules cover designing, debugging,
advanced
analog,
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
Document Number:001-06161 Rev. *A
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Online Help System
PSoC Designer Software Subsystems
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
Hardware Tools
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration r changing configurations at run time.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
PSoC Designer sets up power-on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. Once the framework is
generated, the user can add application-specific code to flesh
out the framework. It’s also possible to change the selected
components and regenerate the framework.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (12 MHz) operation
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, busses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and the software. This substantially lowers the risk of
having to select a different part to meet the final design require-
ments.
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse
a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Assembler The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode, and linked with other software modules to get
absolute addressing.
C Language Compiler A C language compiler is available that
supports PSoC family devices. Even if you have never worked in
the C language before, the product quickly allows you to create
complete C programs for the PSoC family devices.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run time. The API also provides optional interrupt service
routines that you can adapt as needed.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
Document Number:001-06161 Rev. *A
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the use of each user module parameter and documents the
setting of each register controlled by the user module.
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and enter
parameter values directly or by selecting values from drop-down
menus. When you are ready to test the hardware configuration
or move on to developing code for the project, you perform the
“Generate Application” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the high-level user module API
functions.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
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Units of Measure
Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 3-1 on page 12 lists all the abbreviations used to
measure the PSoC devices.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Numeric Naming
Acronym
AC
Description
alternating current
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
EEPROM
electrically erasable programmable read-only
memory
FSR
GPIO
IO
full scale range
general purpose IO
input/output
IPOR
LSb
imprecise power on reset
least-significant bit
low voltage detect
LVD
MSb
PC
most-significant bit
program counter
POR
PPOR
PSoC®
PWM
ROM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
read only memory
switched capacitor
static random access memory
SRAM
Document Number:001-06161 Rev. *A
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Pinouts
The CY8C21323 PSoC device is available in one package, which is listed and illustrated in the following table. Every port pin (labeled
with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
20-Pin Part Pinout
Table 2. 20-Pin Part Pinout (SSOP)
Type
Figure 3. CY8C21323 20-Pin PSoC Device
Pin
No.
Name
Description
Digital Analog
1
2
IO
IO
IO
IO
I
I
I
I
P0[7] Analog column mux input.
P0[5] Analog column mux input.
P0[3] Analog column mux input.
P0[1] Analog column mux input.
A, I,P0[7]
A,I, P0[5]
A,I, P0[3]
A,I, P0[1]
Vss
Vdd
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
P0[6], A,I
P0[4], A,I
P0[2], A,I
P0[0], A,I
XRES
3
4
SSOP
5
Power
Power
Vss
Ground connection.
I2C SCL,P1[7]
I2C SDA,P1[5]
P1[3]
P1[6]
6
IO
IO
IO
IO
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
P1[4],EXTCLK
P1[2]
P1[0],I2C SDA
7
I2C SCL,P1[1]
Vss
8
10
[2]
9
P1[1] I2C Serial Clock (SCL), ISSP-SCLK .
10
11
12
13
Vss
Ground connection.
[2]
IO
IO
IO
P1[0] I2C Serial Data (SDA), ISSP-SDATA
P1[2]
.
P1[4] Optional External Clock Input
(EXTCLK).
14
15
IO
P1[6]
Input
XRES Active high external reset with internal
pull down.
16
17
18
19
20
IO
IO
IO
IO
I
I
I
I
P0[0] Analog column mux input.
P0[2] Analog column mux input.
P0[4] Analog column mux input.
P0[6] Analog column mux input.
Power
Vdd
Supply voltage.
LEGEND A = Analog, I = Input, and O = Output.s.
Notes
2. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number:001-06161 Rev. *A
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Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Convention
Description
Read register or bit(s)
R
W
L
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
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Table 3. Register Map Bank 0 Table: User Space
Addr
Addr
Addr
Addr
Name
PRT0DR
Access
RW
Name
Access
Name
Access
RW
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
(0,Hex)
00
40
41
42
43
44
45
46
47
48
49
ASE10CR0
80
C0
PRT0IE
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
ASE11CR0
RW
PRT1GS
PRT1DM2
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
I2C_CFG
I2C_SCR
I2C_DR
RW
#
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
RW
RW
#
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
PWM_CR
CMP_CR0
CMP_CR1
RES_WDT
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
ADC0_CR
ADC1_CR
#
#
W
RW
#
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
W
RW
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number:001-06161 Rev. *A
Page 10 of 24
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PRELIMINARY
CY8C21323
Addr
Addr
Addr
Addr
Name
Access
Name
Access
Name
RDI0RI
Access
RW
Name
Access
(0,Hex)
(0,Hex)
(0,Hex)
(0,Hex)
30
70
71
72
73
74
75
76
77
78
79
B0
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RDI0SYN
RDI0IS
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
7A
7B
7C
7D
7E
7F
FB
FC
FD
FE
FF
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 4. Register Map Bank 1 Table: Configuration Space
Addr
Addr
Addr
Name
Addr
(1,Hex)
Name
Access
RW
Name
Access
Access
Name
Access
(1,Hex)
(1,Hex)
(1,Hex)
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
00
40
41
42
43
44
45
46
47
48
49
4A
4B
ASE10CR0
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
RW
C0
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
ASE11CR0
RW
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number:001-06161 Rev. *A
Page 11 of 24
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PRELIMINARY
CY8C21323
Addr
(1,Hex)
Addr
(1,Hex)
Addr
(1,Hex)
Addr
Name
Access
Name
Access
Name
Access
Name
Access
(1,Hex)
1D
5D
9D
OSC_GO_EN DD
RW
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
5E
5F
60
61
62
63
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
DE
RW
RW
RW
RW
RW
RW
R
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
DBB00FN
DBB00IN
DBB00OU
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
CMP_GO_EN 64
65
VLT_CMP
ADC0_TR
ADC1_TR
RW
RW
AMD_CR1
ALT_CR0
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
CLK_CR3
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RW
RDI0SYN
RDI0IS
RW
RW
RW
RW
RW
RW
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number:001-06161 Rev. *A
Page 12 of 24
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PRELIMINARY
CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 125oC and T ≤ 135oC, except where noted.
A
J
Figure 4. Voltage versus CPU Frequency
5.25
4.75
3.00
2.40
93 kHz 3 MHz
12 MHz
24 MHz
CPUFrequency
The following table lists the units of measure that are used in this chapter.
Table 5. Units of Measure
Symbol
oC
Unit of Measure
degree Celsius
Symbol
μW
mA
ms
mV
nA
Unit of Measure
microwatts
dB
decibels
milli-ampere
milli-second
milli-volts
fF
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
ns
kilohertz
nV
kilohm
W
ohm
MHz
MΩ
μA
megahertz
megaohm
pA
picoampere
picofarad
pF
microampere
microfarad
microhenry
microsecond
microvolts
pp
peak-to-peak
parts per million
picosecond
μF
ppm
ps
μH
μs
sps
s
samples per second
sigma: one standard deviation
volts
μV
μVrms
microvolts root-mean-square
V
Document Number:001-06161 Rev. *A
Page 13 of 24
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PRELIMINARY
CY8C21323
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Symbol
TSTG
Description
Min
-55
Typ.
Max
+125
Units
oC
Notes
Storage Temperature
+25
Higher storage temperatures
reduce data retention time.
Recommended storage temper-
ature is +25°C +/- 25°C. Storage
temperatures above 65oC
degrade reliability. Maximum
combined storage and opera-
tional time at +125°C is 7000
hours.
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
–
–
–
+125
+6.0
oC
V
Vdd
VIO
-0.5
Vss -
0.5
Vdd +
0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss -
0.5
–
Vdd +
0.5
V
IMIO
ESD
LU
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
-25
2000
–
–
–
–
+25
–
mA
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 7. Operating Temperature
Symbol
Description
Min
-40
Typ.
Max
+125
+135
Units
Notes
TA
TJ
Ambient Temperature
Junction Temperature
–
–
oC
oC
-40
The temperature rise from
ambient to junction is package
specific. See “Thermal Imped-
ances” on page 22. The user
mustlimitthepowerconsumption
to comply with this requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 8. DC Chip-Level Specifications
Symbol
Vdd
Description
Min
4.75
Typ.
Max
5.25
Units
Notes
Supply Voltage
–
3
V
See DC POR and LVD
specifications, Table 11 on
page 16.
Conditions are Vdd = 5.0V, 25oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 =
93.75 kHz, VC3 = 0.366 kHz.
IDD
Supply Current, IMO = 24 MHz
–
4
mA
Document Number:001-06161 Rev. *A
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PRELIMINARY
CY8C21323
Table 8. DC Chip-Level Specifications (continued)
Symbol
ISB
Description
Min
Typ.
Max
12
Units
μA
Notes
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
–
–
5
5
Vdd = 5.25V, -40oC ≤ TA ≤ 55oC.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
100
μA
V
Vdd = 5.25V, 55oC ≤ TA ≤ 125oC.
VREF
AGND
Reference Voltage (Bandgap)
1.28
1.30
1.32
Trimmed for appropriate Vdd.
Vdd = 4.75V to 5.25V.
Analog Ground
VREF
VREF
VREF
V
- 0.003
+ 0.003
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 9. DC GPIO Specifications
Symbol
RPU
Description
Min
Typ.
5.6
Max
Units
kΩ
Notes
Pull up Resistor
4
4
8
8
–
RPD
VOH
Pull down Resistor
High Output Level
5.6
–
kΩ
3.5
V
IOH = 10 mA, Vdd = 4.75 to
5.25V (8 total loads, 4 on even
port pins (for example, P0[2],
P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
0.8
V
IOL = 25 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5])). 150 mA maximum
combined IOL budget.
VIL
VIH
VH
IIL
Input Low Level
–
–
V
Vdd = 4.75 to 5.25.
Vdd = 4.75 to 5.25.
Input High Level
2.1
–
–
V
Input Hysteresis
60
1
–
mV
nA
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
Gross tested to 1 μA.
CIN
–
3.5
10
Package and pin dependent.
Temp = 25oC.
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25oC.
DC Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10. DC Amplifier Specifications
Symbol
VOSOA
Description
Min
Typ.
2.5
Max
15
Units
mV
μV/oC
Notes
Input Offset Voltage (absolute value)
–
–
–
–
TCVOSOA Average Input Offset Voltage Drift
10
–
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
200
4.5
–
pA
Gross tested to 1 μA.
9.5
pF
Package and pin dependent.
Temp = 25oC.
Document Number:001-06161 Rev. *A
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PRELIMINARY
CY8C21323
Table 10. DC Amplifier Specifications (continued)
Symbol
VCMOA
Description
Min
0.0
Typ.
Max
Units
Notes
Common Mode Voltage Range
–
Vdd - 1 V
GOLOA
ISOA
Open Loop Gain
–
–
80
10
–
dB
Amplifier Supply Current
100
μA
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 11. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
PORLEV[1:0] = 10b
Min
Typ.
4.55
Max
4.70
Units
Notes
Vdd must be greater than or
equal to 2.5V during startup,
reset from the XRES pin, or reset
from Watchdog.
VPPOR2
V
Vdd Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
VLVD6
VLVD7
4.62
4.71
4.73
4.81
4.83
4.95
V
V
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 12. DC Programming Specifications
Symbol
Description
Min
4.75
Typ.
Max
Units
Notes
VddIWRITE Supply Voltage for Flash Write Operations
–
5
–
–
V
IDDP
VILP
Supply Current During Programming or Verify
–
–
25
mA
V
Input Low Voltage During Programming or
Verify
0.8
VIHP
IILP
Input High Voltage During Programming or
Verify
2.2
–
–
–
–
–
–
–
V
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
0.2
1.5
mA
mA
V
Driving internal pull down
resistor.
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
Driving internal pull down
resistor.
VOLV
VOHV
Output Low Voltage During Programming or
Verify
–
Vss +
0.75
Output High Voltage During Programming or
Verify
3.5
Vdd
V
Flash Endurance (per block)[3]
FlashENPB
FlashENT
FlashDR
100
64000
15
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.0
0
0
0
Flash Endurance (total)[3], [4]
Flash Data Retention[5]
–
–
–
Years
Notes
3. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information
4. A maximum of 36 x 100 block endurance cycles is allowed.
5. Flash data retention based on the use condition of ≤ 7000 hours at T ≤ 125°C and the remaining time at T ≤ 65°C.
A
A
Document Number:001-06161 Rev. *A
Page 16 of 24
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PRELIMINARY
CY8C21323
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only..
Table 13. AC Chip-Level Specifications
Symbol
FIMO24
FCPU1
FBLK5
Description
Min
Typ.
24
Max
24.6
Units
MHz
Notes
Internal Main Oscillator Frequency for 24 MHz 23.4
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency0(5V Nominal)
0.09
0
12
24
12.48 MHz
24.96 MHz
Refer to the AC Digital Block
Specifications below.
F32K1
Internal Low Speed Oscillator Frequency
32 kHz RMS Period Jitter
15
–
32
100
250
–
64
600
–
kHz
ns
Jitter32k
Jitter32k
TXRST
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
–
ns
10
40
–
–
μs
DC24M
Step24M
50
50
600
–
60
–
%
24 MHz Trim Step Size
kHz
ps
Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO)
–
FMAX
Maximum frequency of signal on row input or
row output.
–
12.48 MHz
TRAMP
Supply Ramp Time
0
–
– μs
Figure 5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 6. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Document Number:001-06161 Rev. *A
Page 17 of 24
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PRELIMINARY
CY8C21323
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 14. AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ.
Max
12.48
22
Units
MHz
ns
Notes
GPIO Operating Frequency
0
–
–
–
Normal Strong Mode
TRiseF
TFallF
Rise Time, Normal Strong Mode, Cload = 50 pF 2
Fall Time, Normal Strong Mode, Cload = 50 pF 2
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
22
ns
TRiseS
TFallS
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
7
7
27
22
–
ns
–
ns
Figure 7. GPIO Timing Diagram
90%
10%
GPIO
Pin
TRiseF
TRiseS
TFallF
TFallS
AC Amplifier Specifications
The following table list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 15. AC Amplifier Specifications
Symbol
Description
Min
Typ.
Max
150
Units
ns
Notes
TCOMP1
Comparator Mode Response Time, 50 mVpp
Signal Centered on Ref
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 16. AC Digital Block Specifications
Function
Description
Min
Typ.
Max
Units
Notes
All
Maximum Block Clocking Frequency (> 4.75V)
24.96 MHz
4.75V < Vdd < 5.25V.
Functions
Timer
Capture Pulse Width
50[6]
–
–
–
–
–
–
–
ns
Maximum Frequency, No Capture
Maximum Frequency, With or Without Capture
–
24.96 MHz
24.96 MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
–
Counter Enable Pulse Width
Maximum Frequency, No Enable Input
50
–
–
ns
24.96 MHz
24.96 MHz
Maximum Frequency, Enable Input
–
Document Number:001-06161 Rev. *A
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PRELIMINARY
CY8C21323
Table 16. AC Digital Block Specifications (continued)
Function
Description
Min
20
Typ.
Max
Units
ns
Notes
Dead
Band
Kill Pulse Width:
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
–
–
–
–
–
–
–
–
50
50
–
ns
ns
Maximum Frequency
24.96 MHz
24.96 MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
–
4.75V < Vdd < 5.25V.
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
–
24.96 MHz
SPIM
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
4.1
MHz
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
SPIS
–
–
–
2.05
–
MHz
ns
Width of SS_ Negated Between Transmissions 50
Trans-
mitter
Maximum Input Clock Frequency
–
8.2
MHz
Maximum data rate at 3.08 MHz due to 8
x over clocking.
Receiver Maximum Input Clock Frequency
–
–
24.96 MHz
Maximum data rate at 3.08 MHz due to 8
x over clocking.
AC External Clock Specifications
The following table list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 17. AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
Typ.
Max
24.24
5300
–
Units
MHz
Notes
FOSCEXT Frequency
–
–
–
–
–
–
–
High Period
Low Period
ns
ns
μs
20.6
Power Up IMO to Switch
150
–
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 18. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Rise Time of SCLK
Min
Typ.
Max
20
Units
ns
Notes
1
1
–
–
–
–
–
Fall Time of SCLK
20
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
ns
–
ns
8
MHz
ms
ms
ns
TERASEB Flash Erase Time (Block)
–
15
30
–
–
TWRITE
TDSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
50
Note
6. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number:001-06161 Rev. *A
Page 19 of 24
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PRELIMINARY
CY8C21323
2
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 19. AC Characteristics of the I2C SDA and SCL Pins for Vcc ≥ 4.75V
Standard Mode
Min Max
100
Fast Mode
Min Max
Symbol
Description
Units
kHz
Notes
FSCLI2C SCL Clock Frequency
THDSTAI2 Hold Time (repeated) START Condition. After 4.0
this period, the first clock pulse is generated.
0
0
400
–
–
0.6
μs
C
TLOWI2C LOW Period of the SCL Clock
THIGHI2C HIGH Period of the SCL Clock
4.7
4.0
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
TSUSTAI2 Set up Time for a Repeated START Condition 4.7
C
THDDATI2 Data Hold Time
C
TSUDATI2 Data Set up Time0
C
0
–
0
–
μs
ns0
μs
μs
ns
2500
4.0
0
0
–
100[7]
0.6
–
TSUSTOI2 Set up Time for STOP Condition
C
–
–
TBUFI2C Bus Free Time Between a STOP and START 4.7
Condition
–
–
1.3
0
–
TSPI2C
Pulse Width of spikes are suppressed by the –
input filter.
50
Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
Note
7. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number:001-06161 Rev. *A
Page 20 of 24
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PRELIMINARY
CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21323 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 9. 20-Pin (210-MIL) SSOP
51-85077 *C
Document Number:001-06161 Rev. *A
Page 21 of 24
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PRELIMINARY
CY8C21323
Thermal Impedances
Table 20. Thermal Impedances per Package
[8]
Package
Typical θJA
117 oC/W
20 SSOP
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 21. Solder Reflow Peak Temperature
Minimum Peak Temperature[9] Maximum Peak Temperature
Package
20 SSOP
240oC
260oC
Notes
8. TJ = TA + POWER x θJA
9. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number:001-06161 Rev. *A
Page 22 of 24
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PRELIMINARY
CY8C21323
Ordering Information
The following table lists the CY8C21323 PSoC device’s key package features and ordering codes.
Table 22. PSoC Device Key Features and Ordering Information
20 Pin (210-Mil) SSOP
CY8C21334-12PVXE
8K
512
512
-40°C to +125°C
-40°C to +125°C
4
4
4
4
16
16
16
16
0
0
Yes
Yes
20 Pin (210-Mil) SSOP
(Tape and Reel)
CY8C21334-12PVXET 8K
8 Pin (300 Mil) DIP
8 Pin (150 Mil) SOIC
CY8C22113-24PI
CY8C22113-24SI
CY8C22113-24SIT
2
2
2
256
256
256
No -40°C to +85°C
No -40°C to +85°C
4
4
4
3
3
3
6
6
6
4
4
4
1
1
1
No
No
No
8 Pin (150 Mil) SOIC
(Tape and Reel)
No
-40°C to +85°C
20 Pin (300 Mil) DIP
CY8C22213-24PI
CY8C22213-24PVI
CY8C22213-24PVIT
2
2
2
256
256
256
No -40°C to +85°C
No -40°C to +85°C
4
4
4
3
3
3
16
16
16
10
10
10
1
1
1
Yes
Yes
Yes
20 Pin (210 Mil) SSOP
20 Pin (210 Mil) SSOP
(Tape and Reel)
No
-40°C to +85°C
32 Pin (5x5 mm) MLF
CY8C22213-24LFI
2
256
No -40°C to +85°C
4
3
16
10
1
Yes
Note For Die sales information, contact a local Cypress sales office, or a Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 21 xxx-12xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number:001-06161 Rev. *A
Page 23 of 24
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PRELIMINARY
CY8C21323
Document History Page
Document Title: CY8C21323 Automotive PSoC® Programmable System-on-Chip™
Document Number:001-06161
Orig. of
Change
Submission
Date
Revision
**
*A
ECN
Description of Change
New silicon and document (Revision **).
414127
HMT
02/05/06
2641945 OGNE/PYRS 01/21/09
Changed 25 mA Drive on All GPIO under Programmable Pin Configurations to
25 mA Sink, 10 mA Drive on All GPIO
Changed Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution) to Analog-to-digital converters (single or dual, with up to 10-bit
resolution)
Updated template.
Added Note in Ordering Information section.
Changed title from PSoC Mixed-Signal Array to PSoC
Programmable System-on-Chip
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number:001-06161 Rev. *A
Revised January 21, 2009
Page 24 of 24
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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