CY8C24423A-24PVXAT [CYPRESS]
Automotive PSoC Programmable System-on-Chip; 汽车的PSoC可编程系统级芯片
| 型号： | CY8C24423A-24PVXAT |
| 厂家： | 
CYPRESS |
| 描述： | Automotive PSoC Programmable System-on-Chip |
| 文件： | 总36页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C24423A
Automotive PSoC®
Programmable System-on-Chip
■
Additional System Resources
Features
❐
❐
❐
❐
❐
I2C™ Slave, Master, or Multi-Master operation up to 400 kHz
Watchdog and Sleep Timers
■
AEC Qualified
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
■
Powerful Harvard Architecture Processor
❐
❐
❐
❐
❐
M8C Processor Speeds up to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0V to 5.25V Operating Voltage
Automotive Temperature Range: -40°C to +85°C
■
Complete Development Tools
❐
❐
❐
❐
❐
Free Development Software (PSoC Designer™)
Full Featured, In-Circuit Emulator and Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
■
Advanced Peripherals (PSoC® Blocks)
❐
Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
Four Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Logic Block Diagram
Analog
Drivers
❐
Port 2 Port 1 Port 0
PSoC CORE
• Full- or Half-Duplex UART
System Bus
• SPI Master or Slave
• Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Global Digital Interconnect
Global Analog Interconnect
Flash 4K
❐
SRAM
SROM
■
Precision, Programmable Clocking
256 Bytes
❐
❐
❐
❐
Internal ±5% 24/48 MHz Oscillator
High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
Optional External Oscillator, up to 24 MHz
Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
■
Flexible On-Chip Memory
DIGITAL SYSTEM
ANALOG SYSTEM
❐
❐
❐
❐
❐
❐
4K Bytes Flash Program Storage, 1000 Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Analog
Ref
Digital
Block
Array
Analog
Block
Array
Analog
Input
Muxing
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
■
Programmable Pin Configurations
❐
25 mA Sink, 10 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
Up to 12 Analog Inputs on GPIO[1]
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on All GPIO
POR and LVD
System Resets
Internal
Voltage
Ref.
❐
❐
❐
Digital
Clocks
Multiply
Accum.
Decimator
I2C
SYSTEM RESOURCES
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See
the PSoC Technical Reference Manual for more details.
Cypress Semiconductor Corporation
Document Number: 001-52469 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 22, 2009
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CY8C24423A
Digital System
PSoC Functional Overview
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user modules.
The PSoC family consists of many programmable
system-on-chips with on-chip Controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, and programmable interconnects. This architecture
enables the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts and packages.
Figure 1. Digital System Block Diagram
Port 1
Port 2
Port 0
To System Bus
Digital Clocks
From Core
To Analog
System
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. Each CY8C24x23A PSoC device
includes four digital blocks and six analog blocks. Depending on
the PSoC package, up to 24 general purpose I/O (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
8
4
8
8
8
DBB00
DBB01
DCB02
DCB03
4
PSoC Core
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with
multiple vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included Sleep Timer and Watchdog Timer (WDT).
Digital peripheral configurations include:
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead Band (8 to 24 bit)
Counters (8 to 32 bit)
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
Timers (8 to 32 bit)
Full or Half-Duplex 8-bit UART with selectable parity
SPI master and slave
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±5% over temperature and voltage. A low power 32 kHz ILO
(internal low speed oscillator) is provided for the Sleep Timer and
WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate 24
MHz system clock using a PLL. The clocks, together with
programmable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into the
PSoC device.
I2C master, slave, or multi-master
Cyclical Redundancy Checker/Generator (16 bit)
IrDA
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
Document Number: 001-52469 Rev. *C
Page 2 of 36
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CY8C24423A
Figure 2. Analog System Block Diagram
Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are:
P0[7]
P0[5]
P0[6]
P0[4]
P0[3]
P0[1]
P0[2]
P0[0]
■
Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta-Sigma, and SAR)
P2[6]
P2[4]
■
■
■
■
■
■
■
■
■
■
■
■
■
Filters (two and four pole band-pass, low-pass, and notch)
Amplifiers (up to two, with selectable gain up to 48x)
Instrumentation amplifiers (one with selectable gain up to 93x)
Comparators (up to two, with 16 selectable thresholds)
DACs (up to two, with 6 to 9-bit resolution)
Multiplying DACs (up to two, with 6 to 9-bit resolution)
High current output drivers (two with 30 mA drive)
1.3V reference (as a System Resource)
DTMF Dialer
P2[3]
P2[1]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Modulators
Correlators
Peak Detectors
Block Array
ACB00 ACB01
Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.
ASC10
ASD20
ASD11
ASC22
Analog Reference
Interface to
Digital System
Reference
Generators
RefHi
RefLo
AGND
AGNDIn
RefIn
BandGap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-52469 Rev. *C
Page 3 of 36
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CY8C24423A
Additional System Resources
Getting Started
System Resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource follow:
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C24x23A PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
■
■
■
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
Application Notes
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Training
■
An internal 1.3V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
PSoC Device Characteristics
training covers a wide variety of topics and skill levels to assist
you in your designs.
Depending on your PSoC device characteristics, the digital and
analog systems can have a varying number of digital and analog
blocks. The following table lists the resources available for
specific PSoC device groups. The PSoC device covered by this
data sheet is highlighted in Table 1.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Table 1. PSoC Device Characteristics
Solutions Library
PSoC Part
Number
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
[2]
CY8C29x66
CY8C27x43
up to
64
4
2
16
8
12
12
4
4
4
4
12
12
2K
32K
16K
up to
44
256
Bytes
Technical Support
CY8C24x94
64
1
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
[2]
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
CY8C24x23A
up to
24
256
Bytes
CY8C23x33
up to
1
1
1
0
4
4
4
0
12
28
8
2
0
0
0
2
2
2
0
4
256
Bytes
8K
8K
4K
8K
[2]
[3]
CY8C21x34
CY8C21x23
CY8C20x34
up to
28
4
4
3
512
Bytes
[3]
16
256
Bytes
[3, 4]
up to
28
28
512
Bytes
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense™ block.
Document Number: 001-52469 Rev. *C
Page 4 of 36
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CY8C24423A
Code Generation Tools
Development Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
PSoC Designer Software Subsystems
System-Level View
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
Hybrid Designs
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-52469 Rev. *C
Page 5 of 36
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CY8C24423A
Organize and Connect
Designing with PSoC Designer
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
Select Components
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-52469 Rev. *C
Page 6 of 36
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CY8C24423A
Units of Measure
Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 12 lists all the abbreviations used to
measure the PSoC devices.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Numeric Naming
Table 2. Acronyms
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are
decimal.
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR
GPIO
GUI
full scale range
general purpose I/O
graphical user interface
human body model
in-circuit emulator
internal low speed oscillator
internal main oscillator
input/output
HBM
ICE
ILO
IMO
I/O
IPOR
LSb
imprecise power on reset
least-significant bit
low voltage detect
most-significant bit
program counter
LVD
MSb
PC
PLL
phase-locked loop
power on reset
POR
PPOR
precision power on reset
PSoC
PWM
SC
Programmable System-on-Chip
pulse width modulator
switched capacitor
SRAM
static random access memory
Document Number: 001-52469 Rev. *C
Page 7 of 36
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CY8C24423A
Pinouts
The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Type
Figure 3. CY8C24423A 28-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
I/O
I/O
I
P0[7] Analog column mux input
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
P0[6], AI
P0[4], AI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I/O
P0[5] Analog column mux input and column
output
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
3
I/O
I/O
I
P0[3] Analog column mux input and column
output
P2[7]
P2[5]
4
5
I/O
I/O
I/O
I/O
I/O
P0[1] Analog column mux input
AI, P2[3]
AI, P2[1]
SSOP
P2[7]
Vss
P2[0], AI
XRES
P1[6]
6
P2[5]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
7
I
I
P2[3] Direct switched capacitor block input
P2[1] Direct switched capacitor block input
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
8
I2C SCL, XTALin, P1[1]
Vss
9
Power
Vss
Ground connection
10
11
12
13
I/O
I/O
I/O
I/O
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK[5]
14
15
Power
Input
Vss
Ground connection
I/O
P1[0] CrystalOutput(XTALout),I2CSerialData
(SDA), ISSP-SDATA[5]
16
17
18
19
I/O
I/O
I/O
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active high external reset with internal
pull down
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
P2[0] Direct switched capacitor block input
P2[2] Direct switched capacitor block input
P2[4] External Analog Ground (AGND)
P2[6] External Voltage Reference (VRef)
P0[0] Analog column mux input
I
I
I
I
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Power
Vdd
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Note
5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 001-52469 Rev. *C
Page 8 of 36
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CY8C24423A
Registers
Register Conventions
Register Mapping Tables
This section lists the registers of the automotive CY8C24x23A
PSoC device. For detailed register information, reference the
PSoC Technical Reference Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
The register conventions specific to this section are listed in the
following table.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 4. Abbreviations
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 001-52469 Rev. *C
Page 9 of 36
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CY8C24423A
Table 5. Register Map Bank 0 Table: User Space
Name Addr (0,Hex) Access Name
PRT0DR
Addr (0,Hex) Access
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
#
RW
#
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
W
RW
#
AMX_IN
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
#
#
W
RW
#
RW
#
W
RW
#
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
#
W
RW
#
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 001-52469 Rev. *C
Page 10 of 36
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CY8C24423A
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 001-52469 Rev. *C
Page 11 of 36
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CY8C24423A
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC devices. For the latest electrical
specifications, visit http://www.cypress.com/psoc.
Specifications are valid for -40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted.
A
J
Refer to Table 22 on page 22 for the electrical specifications on the IMO using SLIMO mode.
Figure 4. Voltage versus CPU Frequency
Figure 5. IMO Frequency Trim Options
5.25
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
O
e
V
a
a
p
4.75
l
e
R
i
d
r
g
t
i
i
n
o
g
n
3.6
3.0
SLIMO
Mode=1
SLIMO
Mode=0
3.0
0
0
93 kHz
12 MHz
24 MHz
6 MHz
12 MHz
IMO Frequency
24 MHz
CPU Frequency
(nominal setting)
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
Unit of Measure
degree Celsius
Symbol
μVrms
μW
mA
ms
mV
nA
Unit of Measure
microvolts root-mean-square
microwatts
dB
decibels
fF
femto farad
hertz
milli-ampere
milli-second
Hz
KB
1024 bytes
1024 bits
milli-volts
Kbit
kHz
kΩ
nanoampere
nanosecond
nanovolts
kilohertz
ns
kilohm
nV
Mbaud
Mbps
MHz
MΩ
μA
μF
μH
μs
μV
megabaud
megabits per second
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
Ω
pA
ohm
picoampere
pF
picofarad
pp
peak-to-peak
parts per million
picosecond
ppm
ps
sps
σ
V
samples per second
sigma: one standard deviation
volts
Document Number: 001-52469 Rev. *C
Page 12 of 36
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CY8C24423A
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 8. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
Notes
TSTG
-55
25
+100
°C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25°C ± 25°C.
Extended duration storage
temperatures above 65°C
degrades reliability.
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
+85
°C
V
Vdd
VIO
+6.0
Vss - 0.5
Vdd +
0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd +
0.5
V
IMIO
ESD
LU
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch Up Current
-25
2000
–
–
–
–
+50
–
mA
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 9. Operating Temperature
Symbol
Description
Min
-40
-40
Typ
–
Max
+85
Units
Notes
TA
TJ
Ambient Temperature
Junction Temperature
°C
–
+100
°C The temperature rise from ambient
to junction is package specific. See
Table 34 on page 32. The user must
limit the power consumption to
comply with this requirement.
Document Number: 001-52469 Rev. *C
Page 13 of 36
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CY8C24423A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 10. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
Supply Current
3.0
–
5.25
V
See DC POR and LVD specifications,
Table 20 on page 20.
IDD
–
5
8
mA Conditions are Vdd = 5.0V, CPU = 3
MHz, 48 MHz disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75
kHz, Analog power = off. SLIMO mode
= 0. IMO = 24 MHz.
IDD3
Supply Current
–
3.3
6.0
mA Conditions are Vdd = 3.3V, CPU = 3
MHz, 48 MHz disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75
kHz, Analog power = off. SLIMO mode
= 0. IMO = 24 MHz.
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[6]
–
–
–
3
4
4
6.5
25
μA Conditions are with internal low speed
oscillator active, Vdd = 3.3V, -40°C ≤
TA ≤ 55°C, Analog power = off.
μA Conditions are with internal low speed
oscillator active, Vdd = 3.3V, 55°C < TA
≤ 85°C, Analog power = off.
μA Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3V, -40°C ≤ TA ≤ 55°C, Analog
power = off.
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at High Temperature.[6]
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and External Crystal.[6]
7.5
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and External Crystal at High
Temperature.[6]
–
5
26
μA Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3 V, 55°C < TA ≤ 85°C, Analog
power = off.
VREF
Reference Voltage (Bandgap)
1.28
1.30
1.32
V
Trimmed for appropriate Vdd.
Vdd ≥ 3.0V
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-52469 Rev. *C
Page 14 of 36
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CY8C24423A
DC General Purpose I/O Specifications
Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 11. 5V and 3.3V DC GPIO Specifications
Symbol
RPU
Description
Min
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
Pull Up Resistor
4
4
8
8
–
RPD
Pull Down Resistor
High Output Level
VOH
Vdd - 1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
maximum 40 mA on odd port pins
(for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
VOL
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port
pins (for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 150
mA maximum combined IOL
budget.
VIL
VIH
VH
IIL
Input Low Level
–
2.1
–
–
–
0.8
V
V
Input High Level
Input Hysterisis
60
1
–
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
nA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
CIN
–
3.5
10
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
Document Number: 001-52469 Rev. *C
Page 15 of 36
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CY8C24423A
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor
(SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time (CT) PSoC block.
Table 12. 5V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
TCVOSOA Average Input Offset Voltage Drift
7.0
20
35.0
–
μV/°C
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
pA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
4.5
9.5
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or
high opamp bias)
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
Specification is applicable at high
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
–
–
–
–
–
–
dB power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = High
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRROA Supply Voltage Rejection Ratio
64
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Document Number: 001-52469 Rev. *C
Page 16 of 36
[+] Feedback
CY8C24423A
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VOSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5V Only
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA Average Input Offset Voltage Drift
–
–
–
7.0
20
35.0
–
μV/°C
IEBOA
CINOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
pA Gross tested to 1 μA
4.5
9.5
pF Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open Loop Gain
Specification is applicable at high
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
60
60
80
–
–
–
–
–
–
dB power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
Power = Medium, Opamp Bias = Low
Power = High is 5V only
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
ISOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
150
300
600
1200
2400
200
400
800
1600
3200
μA
μA
μA
μA
μA
Not allowed
PSRROA Supply Voltage Rejection Ratio
64
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd
DC Low Power Comparator Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC Low power comparator (LPC) reference
voltage range
0.2
–
Vdd - 1
V
ISLPC
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
VOSLPC
2.5
Document Number: 001-52469 Rev. *C
Page 17 of 36
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CY8C24423A
DC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 15. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
VOSOB
Input Offset Voltage (Absolute Value)
TCVOSOB Average Input Offset Voltage Drift
–
+6
–
–
μV/°C
V
VCMOB
Common-Mode Input Voltage Range
0.5
Vdd - 1.0
ROUTOB
Output Resistance
Power = Low
Power = High
–
–
1
1
–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 32Ω to
Vdd/2)
0.5 x Vdd + 1.1
0.5 x Vdd + 1.1
–
–
–
–
V
V
Power = Low
Power = High
VOLOWOB Low Output Voltage Swing (Load = 32Ω to
Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRROB Supply Voltage Rejection Ratio
52
64
–
dB
VOUT > (Vdd - 1.25).
Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
VOSOB
Input Offset Voltage (Absolute Value)
TCVOSOB Average Input Offset Voltage Drift
–
+6
-
–
μV/°C
V
VCMOB
Common-Mode Input Voltage Range
0.5
Vdd - 1.0
ROUTOB
Output Resistance
Power = Low
Power = High
–
–
1
1
–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
Power = High
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
VOLOWOB Low Output Voltage Swing (Load = 1 kΩ to
Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
0.8
2.0
2.0
4.3
mA
mA
–
PSRROB Supply Voltage Rejection Ratio
52
64
–
dB
VOUT > (Vdd - 1.25)
Document Number: 001-52469 Rev. *C
Page 18 of 36
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CY8C24423A
DC Analog Reference Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 17. 5V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2[7]
AGND = 2 x BandGap[7]
AGND = P2[4] (P2[4] = Vdd/2)[7]
AGND = BandGap[7]
Min
1.28
Typ
1.30
Max
1.32
Units
BG
–
V
V
V
V
V
V
V
Vdd/2 - 0.04
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
Vdd/2 - 0.01
2 x BG - 0.030
P2[4]
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
–
–
–
BG + 0.008
1.6 x BG - 0.010
0.000
–
AGND = 1.6 x BandGap[7]
–
AGND Block to Block Variation
(AGND = Vdd/2)[7]
–
–
–
–
–
RefHi = Vdd/2 + BandGap[8]
RefHi = 3 x BandGap[8]
Vdd/2 + BG - 0.10
3 x BG - 0.06
Vdd/2 + BG
3 x BG
Vdd/2 + BG + 0.10
3 x BG + 0.06
V
V
V
V
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)[8] 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[8]
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6] + 0.100
P2[6] = 1.3V)[8]
–
–
–
–
–
–
RefHi = 3.2 x BandGap[8]
RefLo = Vdd/2 - BandGap[8]
RefLo = BandGap[8]
3.2 x BG - 0.112
Vdd/2 - BG - 0.04
BG - 0.06
3.2 x BG
Vdd/2 - BG 0.024
BG
3.2 x BG + 0.076
Vdd/2 - BG + 0.04
BG + 0.06
V
V
V
V
V
V
+
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)[8] 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[8]
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
RefLo = P2[4] - P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)[8]
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
Table 18. 3.3V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2[7]
Min
1.28
Typ
1.30
Max
1.33
Units
BG
–
V
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
–
AGND = 2 x BandGap[7]
AGND = P2[4] (P2[4] = Vdd/2)[7]
AGND = BandGap[7]
Not Allowed
–
P2[4] - 0.008
BG - 0.009
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
–
–
AGND = 1.6 x BandGap[7]
1.6 x BG - 0.027
-0.034
V
–
AGND Column to Column Variation
mV
(AGND = Vdd/2)[7]
–
RefHi = Vdd/2 + BandGap[8]
Not Allowed
Notes
7. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block.
8. This specification is only valid when Ref Control Power = High.
Document Number: 001-52469 Rev. *C
Page 19 of 36
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CY8C24423A
Table 18. 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
RefHi = 3 x BandGap[8]
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)[8]
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[8]
Min
Typ
Max
Units
–
–
–
–
Not Allowed
Not Allowed
Not Allowed
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057
V
P2[6] = 0.5V)[8]
–
–
–
–
–
–
RefHi = 3.2 x BandGap[8]
RefLo = Vdd/2 - BandGap[8]
RefLo = BandGap[8]
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)[8]
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[8]
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefLo = P2[4] - P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)[8]
P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092
V
DC Analog PSoC Block Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 19. DC Analog PSoC Block Specifications
Symbol
RCT
Description
Min
–
Typ
12.2
80
Max
–
Units
kΩ
fF
Notes
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
CSC
–
–
DC POR and LVD Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 20. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip
Vdd must be greater than or
equal to 2.5V during startup,
reset from the XRES pin, or
reset from Watchdog.
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
–
Vdd Value for LVD Trip
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[9]
2.99[10]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
9. Always greater than 50 mV above V
10. Always greater than 50 mV above V
(PORLEV=00) for falling supply.
(PORLEV=01) for falling supply.
PPOR
PPOR
Document Number: 001-52469 Rev. *C
Page 20 of 36
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CY8C24423A
DC Programming Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 21. DC Programming Specifications
Symbol
Description
Min
3.0
–
Typ
–
Max
–
Units
V
Notes
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
VILP
VIHP
IILP
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
5
25
0.8
–
mA
V
–
–
2.1
–
–
V
Input Current when Applying VILP to P1[0] or P1[1]
During Programming or Verify
–
0.2
mA Drivinginternalpulldown
resistor.
IIHP
InputCurrentwhenApplyingVIHP toP1[0]orP1[1]
During Programming or Verify
–
–
1.5
mA Drivinginternalpulldown
resistor.
VOLV
VOHV
Output Low Voltage During Programming or Verify
–
–
–
0.75
Vdd
V
V
Output High Voltage During Programming or
Verify
Vdd - 1.0
FlashENPB Flash Endurance (per block)
1,000
–
–
–
Erase/write cycles per
block
FlashENT
FlashDR
Flash Endurance (total)[11]
Flash Data Retention
36,000
10
–
–
–
–
–
Erase/write cycles
Years
Note
11. A maximum of 36 x 1,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 1,000 maximum cycles each, 36x2 blocks
of 500 maximum cycles each, or 36x4 blocks of 250 maximum cycles each (to limit the total number of cycles to 36x1,000 and that no single block ever sees more
than 1,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-52469 Rev. *C
Page 21 of 36
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CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 22. 5V and 3.3V AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal Main Oscillator
Frequency for 24 MHz
Min
Typ
24
Max
Units
Notes
22.8[13]
25.2[12,13]
MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 5 on
page 12. SLIMO mode = 0.
MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 5 on
page 12. SLIMO mode = 1.
FIMO6
Internal Main Oscillator
Frequency for 6 MHz
5.5[13]
6
6.5[12,13]
FCPU1
FCPU2
F48M
CPU Frequency (5V Vdd
Nominal)
CPU Frequency (3.3V Vdd
Nominal)
0.089[13]
0.089[13]
0
24
12
48
25.2[12,13]
12.6[13]
MHz Minimum CPU frequency is 0.022 MHz
when SLIMO mode = 1
MHz Minimum CPU frequency is 0.022 MHz
when SLIMO mode = 1
Digital PSoC Block Frequency
50.4[12,13,14] MHz Refer to the AC Digital Block
Specifications.
25.2[13,14]
64
F24M
F32K1
Digital PSoC Block Frequency
Internal Low Speed Oscillator
Frequency
0
15
24
32
MHz
kHz This specification applies when the ILO
has been trimmed. During power up,
the ILO is untrimmed and has a
minimum frequency of 5 kHz.
F32K2
External Crystal Oscillator
–
32.768
–
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
FPLL
Jitter24M2
TPLLSLEW
PLL Frequency
24 MHz Period Jitter (PLL)
PLL Lock Time
–
–
0.5
0.5
23.986
–
600
10
MHz Is a multiple (x732) of crystal frequency.
ps Refer to Figure 9 on page 23.
ms Refer to Figure 6 on page 23.
ms Refer to Figure 7 on page 23.
–
–
–
TPLLSLEWSLOW PLL Lock Time for Low Gain
Setting
50
TOS
External Crystal Oscillator
Startup to 1%
External Crystal Oscillator
Startup to 100 ppm
–
–
1700
2800
2620
3800
ms Refer to Figure 8 on page 23.
TOSACC
ms The crystal oscillator frequency is
within 100 ppm of its final value by the
end of the TOSACC period. Correct
operation assumes a properly loaded 1
µW maximum drive level 32.768 kHz
crystal. 3.0V ≤ Vdd ≤ 5.25V, -40 oC ≤ TA
≤ 85 oC.
Jitter32k
TXRST
DC24M
Step24M
Fout48M
Jitter24M1P
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
24 MHz Period Jitter (IMO)
Peak-to-Peak
–
10
40
–
45.6[13]
–
100
–
50
50
48.0
300
–
–
60
–
ns Refer to Figure 10 on page 23.
μs
%
kHz
50.4[12, 13] MHz Trimmed. Using factory trim values.
–
ps Refer to Figure 9 on page 23.
Jitter24M1R
FMAX
24 MHz Period Jitter (IMO) Root
Mean Squared
Maximum Frequency of signal
on row input or row output.
–
–
–
–
–
600
ps
MHz
μs
12.6[13]
–
TRAMP
Supply Ramp Time
20
Notes
12. 4.75V ≤ Vdd ≤ 5.25V.
13. Accuracy derived from Internal Main Oscillator (IMO) with appropriate trim for Vdd range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 001-52469 Rev. *C
Page 22 of 36
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CY8C24423A
Figure 6. PLL Lock Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEW
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1P
Jitter24M2
F24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F32K2
Document Number: 001-52469 Rev. *C
Page 23 of 36
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CY8C24423A
AC General Purpose I/O Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 23. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
Units
Notes
GPIO Operating Frequency
12.6[13] MHz Normal Strong Mode
TRiseF
TFallF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
18
18
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
2
–
TRiseS
TFallS
10
10
27
22
–
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Document Number: 001-52469 Rev. *C
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CY8C24423A
AC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 24. 5V AC Operational Amplifier Specifications
Symbol
TROA
Description
Min
Typ
Max
Units
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
TSOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SRROA
SRFOA
BWOA
ENOA
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Table 25. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
Description
Min
Typ
Max
Units
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
3.92
0.72
μs
μs
TSOA
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
5.41
0.72
μs
μs
SRROA
SRFOA
BWOA
ENOA
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.31
2.7
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.24
1.8
–
–
–
–
V/μs
V/μs
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.67
2.8
–
–
–
–
MHz
MHz
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
Document Number: 001-52469 Rev. *C
Page 25 of 36
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CY8C24423A
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 kΩ resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Document Number: 001-52469 Rev. *C
Page 26 of 36
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CY8C24423A
AC Low Power Comparator Specifications
Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 26. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
Typ
Max
Units
Notes
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within VREFLPC
AC Digital Block Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 27. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Description
Capture Pulse Width
Min
50[15]
Typ
–
Max
Units
Notes
–
ns
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
50.4[13] MHz 4.75V ≤ Vdd ≤ 5.25V.
25.2[13] MHz
–
50[15]
–
–
Counter
–
–
ns
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
–
50.4[13] MHz 4.75V ≤ Vdd ≤ 5.25V.
25.2[13] MHz
–
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
50[15]
50[15]
–
–
–
–
–
–
–
–
–
ns
ns
ns
Maximum Frequency
50.4[13] MHz 4.75V ≤ Vdd ≤ 5.25V.
50.4[13] MHz 4.75V ≤ Vdd ≤ 5.25V.
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
25.2[13] MHz
SPIM
SPIS
8.4[13]
MHz Maximum data rate is 4.2 Mbps
due to 2 x over clocking.
–
–
–
4.2[13]
–
MHz
ns
Width of SS_ Negated Between Transmissions 50[15]
Transmitter
Maximum Input Clock Frequency
–
–
–
–
25.2[13] MHz Maximum baud rate is 3.15
Mbaud due to 8 x over clocking.
50.4[13] MHz Maximum baud rate is 6.3
Mbaud due to 8 x over clocking.
25.2[13] MHz Maximum baud rate is 3.15
Mbaud due to 8 x over clocking.
50.4[13] MHz Maximum baud rate is 6.3
Mbaud due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
–
Receiver
Maximum Input Clock Frequency
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-52469 Rev. *C
Page 27 of 36
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CY8C24423A
AC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 28. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.5
2.5
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.2
2.2
μs
μs
SRROB
SRFOB
BWOB
BWOB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.65
0.65
–
–
–
–
V/μs
V/μs
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
0.8
0.8
–
–
–
–
MHz
MHz
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
Table 29. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
TROB
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
3.8
3.8
μs
μs
TSOB
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
2.6
2.6
μs
μs
SRROB
SRFOB
BWOB
BWOB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
Small Signal Bandwidth, 20 mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
0.7
0.7
–
–
–
–
MHz
MHz
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
Document Number: 001-52469 Rev. *C
Page 28 of 36
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CY8C24423A
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.
Table 30. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
FOSCEXT Frequency
–
–
–
High Period
–
Low Period
–
ns
Power Up IMO to Switch
–
–
μs
Table 31. 3.3V AC External Clock Specifications
Symbol Description
FOSCEXT Frequency with CPU Clock divide by 1[16]
Min
0.093
0.186
41.7
41.7
150
Typ
–
Max
12.3
24.6
5300
–
Units
MHz
MHz
ns
FOSCEXT Frequency with CPU Clock divide by 2 or greater[17]
–
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
–
–
ns
–
–
μs
AC Programming Specifications
Table 32 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 32. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
Fall Time of SCLK
1
–
ns
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB Flash Erase Time (Block)
–
20
20
–
–
TWRITE
TDSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
50
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK
–
–
ns
Notes
16. Maximum CPU frequency is 12 MHz nominal at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
17. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-52469 Rev. *C
Page 29 of 36
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CY8C24423A
AC I2C Specifications
Table 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
0
Max
100[18]
–
Min
Max
400[18]
–
FSCLI2C
0
kHz
THDSTAI2C Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0
0.6
μs
TLOWI2C
THIGHI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
1.3
0.6
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
0.6
0
TSUDATI2C Data Setup Time
250
4.0
4.7
100[19]
TSUSTOI2C Setup Time for STOP Condition
0.6
TBUFI2C
Bus Free Time Between a STOP and START
Condition
1.3
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Notes
18. F
is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
specification adjusts accordingly.
SCLI2C
SCLI2C
F
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement T
≥ 250 ns must then be met. This is automatically the
SUDATI2C
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t + T = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SUDATI2C
Document Number: 001-52469 Rev. *C
Page 30 of 36
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CY8C24423A
Packaging Information
This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances
for the package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 15. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 001-52469 Rev. *C
Page 31 of 36
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CY8C24423A
Thermal Impedances
Table 34. Thermal Impedances per Package
[20]
Package
Typical θJA
101°C/W
28 SSOP
Capacitance on Crystal Pins
Table 35. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
2.8 pF
28 SSOP
Solder Reflow Peak Temperature
The following table lists the minimum solder reflow peak temperatures to achieve good solderability.
Table 36. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[21] Maximum Peak Temperature
240°C 260°C
28 SSOP
Notes
20. T = T + POWER x θ
J
A
JA
o
o
21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-52469 Rev. *C
Page 32 of 36
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CY8C24423A
Development Tool Selection
This section presents the development tools available for the CY8C24x23A family.
Software
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store. The online store (www.cypress.com/shop) also has the
most up to date information on kit contents, descriptions, and
availability.
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for years. PSoC
Designer is available free of charge at http://www.cypress.com.
PSoC Designer comes with a free C compiler.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
■
■
■
■
■
■
Evaluation Board with LCD Module
MiniProg Programming Unit
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
PSoC Designer Software CD
Getting Started Guide
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store (www.cypress.com/shop) also has the
most up to date information on kit contents, descriptions, and
availability.
USB 2.0 Cable
CY3210-24X23 Evaluation Pod (EvalPod)
PSoC EvalPods are pods that connect to the ICE In-Circuit
Emulator (CY3215-DK kit) to allow debugging capability. They
can also function as a standalone device without debugging
capability. The EvalPod has a 28-pin DIP footprint on the bottom
for easy connection to development kits or other hardware. The
top of the EvalPod has prototyping headers for easy connection
to the device's pins. CY3210-24X23 provides evaluation of the
CY8C24x23A PSoC device family.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
■
■
■
■
■
■
■
■
■
■
■
■
ICE-Cube Unit
28-Pin PDIP Emulation Pod for CY8C29466-24PXI
28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two)
PSoC Designer Software CD
ISSP Cable
MiniEval Socket Programming and Evaluation board
Backward Compatibility Cable (for connecting to legacy Pods)
Universal 110/220 Power Supply (12V)
European Plug Adapter
USB 2.0 Cable
Getting Started Guide
Development Kit Registration form
Document Number: 001-52469 Rev. *C
Page 33 of 36
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CY8C24423A
CY3207ISSP In-System Serial Programmer (ISSP)
Device Programmers
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
All device programmers can be purchased from the Cypress
Online Store.
CY3210-MiniProg1
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. This software is free and
can be downloaded from http://www.cypress.com. The kit
includes:
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
■
■
■
CY3207 Programmer Unit
PSoC ISSP Software CD
■
■
■
■
■
■
MiniProg Programming Unit
MiniEval Socket Programming and Evaluation Board
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
PSoC Designer Software CD
110 ~ 240V Power Supply, Euro-Plug Adapter
USB 2.0 Cable
Getting Started Guide
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 37. Emulation and Programming Accessories
Part Number
Pin Package
Pod Kit[22]
Foot Kit[23]
Adapter[24]
CY8C24423A-24PVXA
28 SSOP
CY3250-24X23A
CY3250-28SSOP-FK
Adapters can be found at
http://www.emulation.com.
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and production. Specific details for each of these tools
can be found at http://www.cypress.com under Design
Resources > Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at http://www.cypress.com.
Notes
22. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
23. Foot kit includes surface mount feet that can be soldered to the target PCB.
24. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-52469 Rev. *C
Page 34 of 36
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CY8C24423A
Ordering Information
The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes.
Table 38. CY8C24423A Automotive PSoC Device Key Features and Ordering Information
28 Pin (210 Mil) SSOP
CY8C24423A-24PVXA 4K
CY8C24423A-24PVXAT 4K
256 -40°C to +85°C
256 -40°C to +85°C
4
4
6
6
24
24
12
12
2
2
Yes
Yes
28 Pin (210 Mil) SSOP
(Tape and Reel)
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
C = Commercial
I = Industrial
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Automotive Extended -40
°
C to +125°C
A = Automotive -40 C to +85°C
°
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-52469 Rev. *C
Page 35 of 36
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CY8C24423A
Document History Page
Document Title: CY8C24423A Automotive PSoC® Programmable System-on-Chip
Document Number: 001-52469
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
New data sheet for Automotive A-Grade
Minor ECN to correct the spec number in Document History.
**
2678061 VIVG/PYRS
03/24/09
04/08/09
*A
*B
*C
2685606
2702925
SHEA
BTK
05/06/2009 Post to external web
2742354 BTK/PYRS
07/22/09 Changed title. Updated Features section. Updated text of PSoC Functional
Overview section. Updated Getting Started section. Made corrections and minor text
edits to Pinouts section. Changed the name of the Register Reference section to
"Registers". Added clarifying comments to some electrical specifications. Updated
some figures. Changed TRAMP specification per MASJ input. Fixed all AC specifi-
cations to conform to a ±5% IMO accuracy. Made other miscellaneous minor text
edits. Deleted some non-applicable or redundant information. Added a footnote to
clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block
connections. Updated Development Tool Selection section.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
Products
PSoC
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
Clocks & Buffers
Wireless
Memories
Image Sensors
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52469 Rev. *C
Revised July 22, 2009
Page 36 of 36
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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