CY8C27243-12PVXE中文资料_数据手册_规格书

PSoC® Mixed-Signal Array

Final Data Sheet

Automotive:

CY8C27243, CY8C27443, and CY8C27643

Features

■

Powerful Harvard Architecture Processor

■

Precision, Programmable Clocking

■

Additional System Resources

2

❐

M8C Processor Speeds to 12 MHz

8x8 Multiply, 32-Bit Accumulate

Low Power at High Speed

4.75V to 5.25V Operating Voltage

Extended Temp. Range: -40°C to +105°C

❐

Internal ±4% 24 MHz Oscillator

❐

I C™ Slave, Master, and Multi-Master to

400 kHz

24 MHz with Optional 32.768 kHz Crystal

Optional External Oscillator, up to 24 MHz

Internal Oscillator for Watchdog and Sleep

❐

Watchdog and Sleep Timers

User-Configurable Low Voltage Detection

Integrated Supervisory Circuit

On-Chip Precision Voltage Reference

Flexible On-Chip Memory

Advanced Peripherals (PSoC Blocks)

❐

16K Bytes Flash Program Storage

256 Bytes SRAM Data Storage

In-System Serial Programming (ISSP)

Partial Flash Updates

❐

12 Rail-to-Rail Analog PSoC Blocks Provide:

■

Complete Development Tools

❐

Free Development Software

(PSoC™ Designer)

- Up to 14-Bit ADCs

- Up to 9-Bit DACs

Flexible Protection Modes

❐

Full-Featured, In-Circuit Emulator and

Programmer

- Programmable Gain Amplifiers

- Programmable Filters and Comparators

8 Digital PSoC Blocks Provide:

■

Programmable Pin Configurations

❐

Full Speed Emulation

Complex Breakpoint Structure

128K Bytes Trace Memory

❐

25 mA Sink on All GPIO

- 8- to 32-Bit Timers, Counters, and PWMs

- CRC and PRS Modules

- Up to 2 Full-Duplex UARTs

- Multiple SPI™ Masters or Slaves

- Connectable to all GPIO Pins

Pull Up, Pull Down, High Z, Strong, or Open

Drain Drive Modes on all GPIO

Up to 12 Analog Inputs on GPIO

Four 30 mA Analog Outputs on GPIO

Configurable Interrupt on All GPIO

❐

Complex Peripherals by Combining Blocks

PSoC® Functional Overview

Analog

Drivers

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

PSoC

CORE

The PSoC® family consists of many Mixed-Signal Array with

On-Chip Controller devices. These devices are designed to

replace multiple traditional MCU-based system components

with one, low cost single-chip programmable device. PSoC

devices include configurable blocks of analog and digital logic,

as well as programmable interconnects. This architecture

allows the user to create customized peripheral configurations

that match the requirements of each individual application.

Additionally, a fast CPU, Flash program memory, SRAM data

memory, and configurable IO are included in a range of conve-

nient pinouts and packages.

System Bus

Global Digital Interconnect

SRAM

Global Analog Interconnect

SROM

Flash 16K

256 Bytes

Sleep and

Watchdog

CPUCore(M8C)

Interrupt

Controller

Multiple Clock Sources

The PSoC architecture, as illustrated on the left, is comprised of

four main areas: PSoC Core, Digital System, Analog System,

and System Resources. Configurable global busing allows all

device resources to be combined into a complete custom sys-

tem. The CY8C27x43 automotive family can have up to five IO

ports that connect to the global digital and analog interconnects,

providing access to 8 digital blocks and 12 analog blocks.

(IncludesIMO,ILO, PLL, andECO)

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref.

Analog

Block

Array

Digital

Block Array

Analog

Input

Muxing

The PSoC Core

The PSoC Core is a powerful engine that supports a rich fea-

ture set. The core includes a CPU, memory, clocks, and config-

urable GPIO (General Purpose IO).

POR and LVD

System Resets

Internal

Voltage

Ref.

Digital

Clocks

Multiply

Accum.

2

Decimator

I C

The M8C CPU core is a powerful processor with speeds up to

12 MHz, providing a two MIPS 8-bit Harvard architecture micro-

SYSTEM RESOURCES

November 9, 2006

1

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

processor. The CPU utilizes an interrupt controller with 17 vec-

tors, to simplify programming of real time embedded events.

Program execution is timed and protected using the included

Sleep and Watch Dog Timers (WDT).

Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead Band (8 to 32 bit)

■ Counters (8 to 32 bit)

Memory includes 16 KB of Flash for program storage and 256

bytes of SRAM for data storage. Program Flash utilizes four

protection levels on blocks of 64 bytes, allowing customized

software IP protection.

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 2)

■ SPI Master and Slave (up to 2)

■ I2C Slave and Multi-master (1 available as a System

The PSoC device incorporates flexible internal clock genera-

tors, including a 24 MHz IMO (internal main oscillator) accurate

to 4% over temperature and voltage. A low power 32 kHz ILO

(internal low speed oscillator) is provided for the Sleep timer

and WDT. If crystal accuracy is desired, the ECO (32.768 kHz

external crystal oscillator) is available for use as a Real Time

Clock (RTC) and can optionally generate a crystal-accurate 24

MHz system clock using a PLL. The clocks, together with pro-

grammable clock dividers (as a System Resource), provide the

flexibility to integrate almost any timing requirement into the

PSoC device.

Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 2)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a

series of global buses that can route any signal to any pin. The

buses also allow for signal multiplexing and for performing logic

operations. This configurability frees your designs from the con-

straints of a fixed peripheral controller.

PSoC GPIOs provide connection to the CPU, digital and analog

resources of the device. Each pin’s drive mode may be selected

from eight options, allowing great flexibility in external interfac-

ing. Every pin also has the capability to generate a system inter-

rupt on high level, low level, and change from last read.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows you the opti-

mum choice of system resources for your application. Family

resources are shown in the table titled “PSoC Device Charac-

teristics” on page 3.

The Digital System

The Analog System

The Digital System is composed of 8 digital PSoC blocks. Each

block is an 8-bit resource that can be used alone or combined

with other blocks to form 8, 16, 24, and 32-bit peripherals, which

are called user module references.

The Analog System is composed of 12 configurable blocks,

each comprised of an opamp circuit allowing the creation of

complex analog signal flows. Analog peripherals are very flexi-

ble and can be customized to support specific application

requirements. Some of the more common PSoC analog func-

tions (most available as user modules) are listed below.

Port 5

Port 3

Port 1

Port 4

Port 2

Port 0

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-

tion, selectable as Incremental, Delta Sigma, and SAR)

To SystemBus

DigitalClocks

FromCore

ToAnalog

System

■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to

DIGITAL SYSTEM

93x)

DigitalPSoCBlockArray

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

Row 0

4

DBB00

DBB10

DBB01

DCB02

DCB12

DCB03

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 40 mA drive as a PSoC

8

Core resource)

8

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

Row 1

4

DBB11

DCB13

■ Modulators

■ Correlators

■ Peak Detectors

GIE[7:0]

GIO[7:0]

■ Many other topologies possible

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Digital System Block Diagram

November 9, 2006

Document No. 38-12023 Rev. *D

2

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

Analog blocks are provided in columns of three, which include

one CT (Continuous Time) and two SC (Switched Capacitor)

blocks, as shown in the figure below.

Additional System Resources

System Resources, some of which have been previously listed,

provide additional capability useful to complete systems. Addi-

tional resources include a multiplier, decimator, switch mode

pump, low voltage detection, and power on reset. Brief state-

ments describing the merits of each system resource are pre-

sented below.

P0[7]

P0[5]

P0[6]

P0[4]

■ Digital clock dividers provide three customizable clock fre-

quencies for use in applications. The clocks can be routed to

both the digital and analog systems. Additional clocks can be

generated using digital PSoC blocks as clock dividers.

P0[3]

P0[1]

P0[2]

P0[0]

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate to assist in both general math as well

as digital filters.

P2[6]

P2[4]

P2[3]

P2[1]

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta

Sigma ADCs.

P2[2]

P2[0]

■ The I2C module provides 100 and 400 kHz communication

over two wires. Slave, master, and multi-master modes are

all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system

supervisor.

Array Input Configuration

ACI0[1:0]

ACI1[1:0]

ACI2[1:0]

ACI3[1:0]

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

PSoC Device Characteristics

Block Array

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. The following table lists the resources

available for specific PSoC device groups.The PSoC device

covered by this data sheet is highlighted below.

ACB00

ASC10

ASD20

ACB01

ASD11

ASC21

ACB02

ASC12

ASD22

ACB03

ASD13

ASC23

PSoC Device Characteristics

Analog Reference

PSoC Part

Number

Interface to

Digital System

Re ference

Generators

Ref Hi

Ref Lo

AGND

AGNDIn

Ref In

Bandgap

up to

64

CY8C29x66

4

16

12

4

12

2K

32K

up to

44

256

Bytes

CY8C27x43

CY8C24x94

CY8C24x23A

2

1

8

4

12

48

12

4

2

4

2

12

6

16K

4K

56

1K

M8C Interface (Address Bus, Data Bus, Etc.)

up to

24

256

Bytes

6

Analog System Block Diagram

up to

28

512

Bytes

a

CY8C21x34

CY8C21x23

CY8C20x34

1

0

4

0

28

8

0

2

0

8K

4K

8K

4

256

Bytes

a

16

4

up to

28

512

Bytes

b

28

3

a. Limited analog functionality.

b. Two analog blocks and one CapSense.

November 9, 2006

Document No. 38-12023 Rev. *D

3

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

Getting Started

Development Tools

PSoC Designer is a Microsoft^®Windows-based, integrated

development environment for the Programmable System-on-

Chip (PSoC) devices. The PSoC Designer IDE and application

runs on Windows NT 4.0, Windows 2000, Windows Millennium

(Me), or Windows XP. (Reference the PSoC Designer Func-

tional Flow diagram below.)

The quickest path to understanding the PSoC silicon is by read-

ing this data sheet and using the PSoC Designer Integrated

Development Environment (IDE). This data sheet is an over-

view of the PSoC integrated circuit and presents specific pin,

register, and electrical specifications. For in-depth information,

along with detailed programming information, reference the

PSoC Mixed-Signal Array Technical Reference Manual.

PSoC Designer helps the customer to select an operating con-

figuration for the PSoC, write application code that uses the

PSoC, and debug the application. This system provides design

database management by project, an integrated debugger with

In-Circuit Emulator, in-system programming support, and the

macro assembler for the CPUs.

For up-to-date Ordering, Packaging, and Electrical Specification

information, reference the latest PSoC device data sheets on

the web at http://www.cypress.com/psoc.

Development Kits

PSoC Designer also supports a high-level C language compiler

developed specifically for the devices in the family.

Development Kits are available from the following distributors:

Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store

contains development kits, C compilers, and all accessories for

PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program-

mable System-on-Chip) to view a current list of available items.

Context

Graphical Designer

PSoC

Sensitive

Interface

Help

Designer

Technical Training Modules

Free PSoC technical training modules are available for users

new to PSoC. Training modules cover designing, debugging,

Importable

Design

advanced

analog

and

CapSense.

Go

to

http://

www.cypress.com/techtrain.

Database

PSoC

Configuration

Sheet

Device

Database

Consultants

PSoC

Designer

Core

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to http://www.cypress.com, click on Design

Support located on the left side of the web page, and select

CYPros Consultants.

Application

Database

Manufacturing

Information

File

Engine

Project

Database

User

Modules

Technical Support

Library

PSoC application engineers take pride in fast and accurate

response. They can be reached with a 4-hour guaranteed

response at http://www.cypress.com/support/login.cfm.

Application Notes

Emulation

Pod

In-Circuit

Emulator

Device

Programmer

A long list of application notes will assist you in every aspect of

your design effort. To view the PSoC application notes, go to

the http://www.cypress.com web site and select Application

Notes under the Design Resources list located in the center of

the web page. Application notes are listed by date by default.

PSoC Designer Subsystems

November 9, 2006

Document No. 38-12023 Rev. *D

4

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

Debugger

PSoC Designer Software Subsystems

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing the designer to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow the designer to read and

program and read and write data memory, read and write IO

registers, read and write CPU registers, set and clear break-

points, and provide program run, halt, and step control. The

debugger also allows the designer to create a trace buffer of

registers and memory locations of interest.

Device Editor

The Device Editor subsystem allows the user to select different

onboard analog and digital components called user modules

using the PSoC blocks. Examples of user modules are ADCs,

DACs, Amplifiers, and Filters.

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic configu-

ration allows for changing configurations at run time.

Online Help System

PSoC Designer sets up power-on initialization tables for

selected PSoC block configurations and creates source code

for an application framework. The framework contains software

to operate the selected components and, if the project uses

more than one operating configuration, contains routines to

switch between different sets of PSoC block configurations at

run time. PSoC Designer can print out a configuration sheet for

given project configuration for use during application program-

ming in conjunction with the Device Data Sheet. Once the

framework is generated, the user can add application-specific

code to flesh out the framework. It’s also possible to change the

selected components and regenerate the framework.

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is avail-

able for development support. This hardware has the capability

to program single devices.

Design Browser

The Design Browser allows users to select and import precon-

figured designs into the user’s project. Users can easily browse

a catalog of preconfigured designs to facilitate time-to-design.

Examples provided in the tools include a 300-baud modem, LIN

Bus master and slave, fan controller, and magnetic card reader.

The emulator consists of a base unit that connects to the PC by

way of the parallel or USB port. The base unit is universal and

will operate with all PSoC devices. Emulation pods for each

device family are available separately. The emulation pod takes

the place of the PSoC device in the target board and performs

full speed (24 MHz) operation.

Application Editor

In the Application Editor you can edit your C language and

Assembly language source code. You can also assemble, com-

pile, link, and build.

Assembler. The macro assembler allows the assembly code

to be merged seamlessly with C code. The link libraries auto-

matically use absolute addressing or can be compiled in relative

mode, and linked with other software modules to get absolute

addressing.

C Language Compiler. A C language compiler is available

that supports Cypress MicroSystems’ PSoC family devices.

Even if you have never worked in the C language before, the

product quickly allows you to create complete C programs for

the PSoC family devices.

The embedded, optimizing C compiler provides all the features

of C tailored to the PSoC architecture. It comes complete with

embedded libraries providing port and bus operations, standard

keypad and display support, and extended math functionality.

November 9, 2006

Document No. 38-12023 Rev. *D

5

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

Designing with User Modules

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture

a unique flexibility that pays dividends in managing specification

change during development and later by lowering inventory

costs. These configurable resources, called PSoC Blocks, have

the ability to implement a wide variety of user-selectable func-

tions. Each block has several registers that determine its func-

tion and connectivity to other blocks, multiplexers, buses and to

the IO pins. Iterative development cycles permit you to adapt

the hardware as well as the software. This substantially lowers

the risk that you will have to select a different part to meet the

final design requirements.

Device Editor

Placement

and

Parameter

-ization

User

Module

Selection

Source

Code

Generator

Generate

Application

Application Editor

Source

Code

Editor

To speed the development process, the PSoC Designer Inte-

grated Development Environment (IDE) provides a library of

pre-built, pre-tested hardware peripheral functions, called “User

Modules.” User modules make selecting and implementing

peripheral devices simple, and come in analog, digital, and

mixed signal varieties. The standard User Module library con-

tains over 50 common peripherals such as ADCs, DACs Tim-

ers, Counters, UARTs, and other not-so common peripherals

such as DTMF Generators and Bi-Quad analog filter sections.

Project

Manager

Build

Manager

Build

All

Debugger

Each user module establishes the basic register settings that

implement the selected function. It also provides parameters

that allow you to tailor its precise configuration to your particular

application. For example, a Pulse Width Modulator User Mod-

ule configures one or more digital PSoC blocks, one for each 8

bits of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also

provide tested software to cut your development time. The user

module application programming interface (API) provides high-

level functions to control and respond to hardware events at

run-time. The API also provides optional interrupt service rou-

tines that you can adapt as needed.

Event &

Breakpoint

Manager

Interface

to ICE

Storage

Inspector

User Module and Source Code Development Flows

The next step is to write your main program, and any sub-rou-

tines using PSoC Designer’s Application Editor subsystem.

The Application Editor includes a Project Manager that allows

you to open the project source code files (including all gener-

ated code files) from a hierarchal view. The source code editor

provides syntax coloring and advanced edit features for both C

and assembly language. File search capabilities include simple

string searches and recursive “grep-style” patterns. A single

mouse click invokes the Build Manager. It employs a profes-

sional-strength “makefile” system to automatically analyze all

file dependencies and run the compiler and assembler as nec-

essary. Project-level options control optimization strategies

used by the compiler and linker. Syntax errors are displayed in

a console window. Double clicking the error message takes you

directly to the offending line of source code. When all is correct,

the linker builds a HEX file image suitable for programming.

The API functions are documented in user module data sheets

that are viewed directly in the PSoC Designer IDE. These data

sheets explain the internal operation of the user module and

provide performance specifications. Each data sheet describes

the use of each user module parameter and documents the set-

ting of each register controlled by the user module.

The development process starts when you open a new project

and bring up the Device Editor, a graphical user interface (GUI)

for configuring the hardware. You pick the user modules you

need for your project and map them onto the PSoC blocks with

point-and-click simplicity. Next, you build signal chains by inter-

connecting user modules to each other and the IO pins. At this

stage, you also configure the clock source connections and

enter parameter values directly or by selecting values from

drop-down menus. When you are ready to test the hardware

configuration or move on to developing code for the project, you

perform the “Generate Application” step. This causes PSoC

Designer to generate source code that automatically configures

the device to your specification and provides the high-level user

module API functions.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger down-

loads the HEX image to the In-Circuit Emulator (ICE) where it

runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

November 9, 2006

Document No. 38-12023 Rev. *D

6

[+] Feedback

CY8C27x43 Automotive Data Sheet

PSoC® Overview

Document Conventions

Table of Contents

For an in depth discussion and more information on your PSoC

device, obtain the PSoC Mixed-Signal Array Technical Refer-

ence Manual. This document encompasses and is organized

into the following chapters and sections.

Acronyms Used

The following table lists the acronyms that are used in this doc-

ument.

1.

Pin Information ............................................................. 8

Acronym

AC

Description

alternating current

1.1 Pinouts ................................................................... 8

1.1.1 20-Pin Part Pinout ...............................................8

1.1.2 28-Pin Part Pinout ...............................................9

1.1.3 48-Pin Part Pinout .............................................10

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

CT

2.

3.

Register Reference ..................................................... 11

DAC

DC

digital-to-analog converter

direct current

2.1 Register Conventions ........................................... 11

2.2 Register Mapping Tables ..................................... 11

ECO

EEPROM

FSR

GPIO

GUI

external crystal oscillator

electrically erasable programmable read-only memory

full scale range

Electrical Specifications ............................................ 14

3.1 Absolute Maximum Ratings ................................ 15

3.2 Operating Temperature ....................................... 15

3.3 DC Electrical Characteristics ................................ 16

3.3.1 DC Chip-Level Specifications .............................16

3.3.2 DC General Purpose IO Specifications ..............16

3.3.3 DC Operational Amplifier Specifications ............17

3.3.4 DC Low Power Comparator Specifications ........17

3.3.5 DC Analog Output Buffer Specifications ............18

3.3.6 DC Analog Reference Specifications .................19

3.3.7 DC Analog PSoC Block Specifications ...............20

3.3.8 DC POR and LVD Specifications .......................20

3.3.9 DC Programming Specifications ........................21

3.4 AC Electrical Characteristics ................................ 22

3.4.1 AC Chip-Level Specifications .............................22

3.4.2 AC General Purpose IO Specifications ..............24

3.4.3 AC Operational Amplifier Specifications .............25

3.4.4 AC Low Power Comparator Specifications ........27

3.4.5 AC Digital Block Specifications ..........................27

3.4.6 AC Analog Output Buffer Specifications .............28

3.4.7 AC External Clock Specifications .......................28

3.4.8 AC Programming Specifications .........................29

3.4.9 AC I2C Specifications .........................................29

general purpose IO

graphical user interface

human body model

HBM

ICE

in-circuit emulator

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

IO

IPOR

LSb

imprecise power on reset

least-significant bit

LVD

low voltage detect

MSb

PC

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC®

PWM

SC

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

switched capacitor

4.

Packaging Information ............................................... 30

SRAM

static random access memory

4.1 Packaging Dimensions ......................................... 30

4.2 Thermal Impedances .......................................... 32

4.3 Capacitance on Crystal Pins ............................... 32

4.4 Solder Reflow Peak Temperature ........................ 32

Units of Measure

A units of measure table is located in the Electrical Specifica-

tions section. Table 3-1 on page 14 lists all the abbreviations

used to measure the PSoC devices.

5.

6.

Ordering Information .................................................. 33

5.1 Ordering Code Definitions ................................... 33

Sales and Service Information .................................. 34

6.1 Revision History ................................................... 34

6.2 Copyrights and Flash Code Protection ................ 34

Numeric Naming

Hexidecimal numbers are represented with all letters in upper-

case with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’ or ‘b’ are decimal.

November 9, 2006

Document No. 38-12023 Rev. *D

7

[+] Feedback

1. Pin Information

This chapter describes, lists, and illustrates the CY8C27x43 automotive PSoC device pins and pinout configurations.

1.1

Pinouts

The CY8C27x43 automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.

Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.

1.1.1

20-Pin Part Pinout

Table 1-1. 20-Pin Part Pinout (SSOP)

Type

CY8C27243 20-Pin PSoC Device

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

8

9

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

Vss

Analog column mux input.

A, I,P0[7]

A,IO, P0[5]

A,IO, P0[3]

A,I, P0[1]

Vdd

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

IO

I

Analog column mux input and column output.

Analog column mux input.

P0[6], A,I

P0[4], A,IO

P0[2], A,IO

P0[0], A,I

XRES

Vss

Power

Ground connection.

SSOP

I2CSCL,P1[7]

I2CSDA, P1[5]

P1[3]

IO

P1[7]

P1[5]

P1[3]

P1[1]

I2C Serial Clock (SCL).

P1[6]

I2C Serial Data (SDA).

P1[4],EXTCLK

P1[2]

P1[0],XTALout,I2CSDA

I2CSCL,XTALin, P1[1]

Vss

Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*.

10

11

Vss

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA*.

12

P1[2]

13

14

15

IO

P1[4]

P1[6]

XRES

Optional External Clock Input (EXTCLK).

Input

Active high external reset with internal pull

down.

16

17

18

19

20

IO

I

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Analog column mux input.

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.

November 9, 2006

Document No. 38-12023 Rev. *D

8

[+] Feedback

CY8C27x43 Automotive Data Sheet

1. Pin Information

1.1.2

28-Pin Part Pinout

Table 1-2. 28-Pin Part Pinout (SSOP)

Type

CY8C27443 28-Pin PSoC Device

No.

Name

Description

Digital Analog

1

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Vss

Analog column mux input.

A, I,P0[7]

A,IO, P0[5]

A,IO, P0[3]

A,I, P0[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Vdd

P0[6], A, I

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

IO

I

Analog column mux input and column output.

Analog column mux input.

3

P0[4], A,IO

P0[2], A,IO

P0[0], A, I

P2[6],Ex ternalVRef

P2[4],Ex ternalAGND

P2[2], A, I

4

P2[7]

P2[5]

5

6

A,I, P2[3]

A, I,P2[1]

SSOP

7

I

Direct switched capacitor block input.

Ground connection.

8

Vss

P2[0], A, I

XRES

P1[6]

9

Power

Input

I2CSCL,P1[7]

I2CSDA,P1[5]

P1[3]

10

11

12

13

IO

P1[7]

P1[5]

P1[3]

P1[1]

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

P1[4],EXTCLK

P1[2]

P1[0],XTALout,I2CSDA

I2CSCL,XTALin,P1[1]

Vss

Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*.

14

15

Vss

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA*.

16

17

18

19

IO

P1[2]

P1[4]

P1[6]

XRES

Optional External Clock Input (EXTCLK).

Active high external reset with internal pull

down.

20

21

22

23

24

25

26

27

28

IO

I

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Direct switched capacitor block input.

External Analog Ground (AGND).

External Voltage Reference (VRef).

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See

the PSoC Mixed-Signal Array Technical Reference Manual for details.

November 9, 2006

Document No. 38-12023 Rev. *D

9

[+] Feedback

CY8C27x43 Automotive Data Sheet

1. Pin Information

1.1.3

48-Pin Part Pinout

Table 1-3. 48-Pin Part Pinout (SSOP)

Type

CY8C27643 48-Pin PSoC Device

No.

Name

Description

Digital Analog

1

IO

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P4[7]

P4[5]

P4[3]

P4[1]

Vss

Analog column mux input.

A, I,P0[7]

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

Vdd

P0[6], A,I

P0[4],A,IO

P0[2],A,IO

P0[0], A,I

2

IO

I

Analog column mux input and column output.

Analog column mux input.

A,IO,P0[5]

A,IO,P0[3]

A, I,P0[1]

P2[7]

3

4

5

6

4

5

P2[6],ExternalVRef

P2[5]

6

A, I,P2[3]

A, I,P2[1]

P4[7]

7

8

9

P2[4],ExternalAGND

P2[2], A,I

P2[0], A,I

P4[6]

P4[4]

P4[2]

7

I

Direct switched capacitor block input.

8

9

P4[5] 10

P4[3]

P4[1]

Vss

10

11

12

13

14

15

16

17

18

19

20

21

22

23

11

12

13

14

SSOP

P4[0]

XRES

P3[7]

Power

Input

Ground connection.

P3[5] 15

P3[6]

IO

P3[7]

P3[5]

P3[3]

P3[1]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

P3[3]

P3[1]

16

17

P3[4]

P3[2]

P5[3] 18

P5[1] 19

I2CSCL,P1[7]

P3[0]

P5[2]

P5[0]

P1[6]

20

21

I2CSDA,P1[5]

P1[3]

I2CSCL,XTALin,P1[1]

Vss

22

23

P1[4],EXTCLK

P1[2]

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

24

P1[0],XTALout,I2CSDA

Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*.

24

25

Vss

Ground connection.

IO

P1[0]

Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA*.

26

27

28

29

30

31

32

33

34

35

IO

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P3[0]

P3[2]

P3[4]

P3[6]

XRES

Optional External Clock Input (EXTCLK).

Active high external reset with internal pull

down.

36

37

38

39

40

41

42

43

44

45

46

47

48

IO

P4[0]

P4[2]

P4[4]

P4[6]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I

Direct switched capacitor block input.

External Analog Ground (AGND).

External Voltage Reference (VRef).

Analog column mux input.

I

IO

I

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.

November 9, 2006

Document No. 38-12023 Rev. *D

10

[+] Feedback

2. Register Reference

This chapter lists the registers of the CY8C27x43 automotive PSoC devices. For detailed register information, reference the

PSoC Mixed-Signal Array Technical Reference Manual.

2.1

Register Conventions

2.2

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The PSoC device has a total register address space of 512

bytes. The register space is referred to as IO space and is

divided into two banks. The XOI bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XOI

bit is set the user is in Bank 1.

Convention

Description

Read register or bit(s)

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

Note In the following register mapping tables, blank fields are

Reserved and should not be accessed.

C

#

November 9, 2006

Document No. 38-12023 Rev. *D

11

[+] Feedback

CY8C27x43 Automotive Data Sheet

2. Register Reference

Register Map Bank 0 Table: User Space

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

PRT5GS

PRT5DM2

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

RW

#

RW

#

RW

INT_CLR3

INT_MSK3

RW

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

DBB10DR0

DBB10DR1

DBB10DR2

DBB10CR0

DBB11DR0

DBB11DR1

DBB11DR2

DBB11CR0

DCB12DR0

DCB12DR1

DCB12DR2

DCB12CR0

DCB13DR0

DCB13DR1

DCB13DR2

DCB13CR0

#

AMX_IN

RW

INT_MSK0

INT_MSK1

INT_VC

RES_WDT

DEC_DH

DEC_DL

DEC_CR0

DEC_CR1

MUL_X

RW

RC

W

RC

RW

W

R

RW

W

RW

#

ARF_CR

CMP_CR0

ASY_CR

CMP_CR1

RW

#

W

RW

#

RW

#

W

RW

#

MUL_Y

MUL_DH

MUL_DL

ACC_DR1

ACC_DR0

ACC_DR3

ACC_DR2

#

W

RW

#

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RW

W

RW

#

W

RW

#

CPU_F

RL

#

RDI1RI

RDI1SYN

RDI1IS

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RW

W

RW

#

W

RW

#

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

November 9, 2006

Document No. 38-12023 Rev. *D

12

[+] Feedback

CY8C27x43 Automotive Data Sheet

2. Register Reference

Register Map Bank 1 Table: Configuration Space

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

OSC_GO_EN DD

RW

R

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

DBB00FN

DBB00IN

DBB00OU

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

RW

DBB01FN

DBB01IN

DBB01OU

RW

VLT_CMP

AMD_CR1

ALT_CR0

ALT_CR1

CLK_CR2

RW

DCB02FN

DCB02IN

DCB02OU

RW

IMO_TR

ILO_TR

BDG_TR

ECO_TR

W

RW

W

DCB03FN

DCB03IN

DCB03OU

RW

DBB10FN

DBB10IN

DBB10OU

RW

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RW

DBB11FN

DBB11IN

DBB11OU

RW

CPU_F

RL

DCB12FN

DCB12IN

DCB12OU

RW

RDI1RI

RDI1SYN

RDI1IS

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RW

DCB13FN

DCB13IN

DCB13OU

RW

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

November 9, 2006

Document No. 38-12023 Rev. *D

13

[+] Feedback

3. Electrical Specifications

This chapter presents the DC and AC electrical specifications of the CY8C27x43 automotive PSoC device. For the most up to date

electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40^oC ≤ T ≤ 105^oC and T ≤ 125^oC, except where noted.

A

J

5.25

4.75

Valid

Operating

Region

3.00

93 kHz

12 MHz

24 MHz

CPUFrequency

Figure 3-1. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 3-1: Units of Measure

Symbol

Unit of Measure

Symbol

Unit of Measure

o

degree Celsius

µW

microwatts

C

dB

fF

decibels

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

femto farad

hertz

Hz

KB

1024 bytes

1024 bits

kilohertz

nanoampere

nanosecond

nanovolts

Kbit

kHz

kΩ

nV

Ω

kilohm

ohm

MHz

MΩ

µA

megahertz

megaohm

microampere

microfarad

microhenry

microsecond

microvolts

pA

pF

pp

ppm

ps

picoampere

picofarad

peak-to-peak

parts per million

picosecond

µF

µH

µs

sps

σ

samples per second

sigma: one standard deviation

volts

µV

µVrms

microvolts root-mean-square

V

November 9, 2006

Document No. 38-12023 Rev. *D

14

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.1

Absolute Maximum Ratings

Table 3-2: Absolute Maximum Ratings

Symbol

Description

Min

-55

Typ

+25

Max

+105

Units

Notes

o

T

Storage Temperature

Higher storage temperatures will reduce data

retention time. Recommended storage temper-

ature is +25°C ± 25°C. Storage temperatures

STG

C

o

above 65 C will degrade reliability. Maximum

combined storage and operational time at

+105°C is 7000 hours.

T

Ambient Temperature with Power Applied

-40

–

+105

A

C

Vdd

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-0.5

–

+5.5

V

Vss - 0.5

Vdd + 0.5

IO

V

DC Voltage Applied to Tri-state

Vss - 0.5

-25

–

Vdd + 0.5

+25

V

IOZ

I

Maximum Current into any Port Pin

mA

MIO

MAIO

Maximum Current into any Port Pin Configured as Analog

Driver

-50

+50

ESD

LU

Static Discharge Voltage

Latch-up Current

2000

–

V

Human Body Model ESD.

200

mA

3.2

Operating Temperature

Table 3-3: Operating Temperature

Symbol

Description

Min

Typ

Max

Units

Notes

o

T

Ambient Temperature

Junction Temperature

-40

–

+105

A

C

T

-40

+125

The temperature rise from ambient to junction is

package specific. See “Thermal Impedances

per Package” on page 32. The user must limit

the power consumption to comply with this

requirement.

J

November 9, 2006

Document No. 38-12023 Rev. *D

15

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3

DC Electrical Characteristics

3.3.1

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-4: DC Chip-Level Specifications

Symbol

Description

Min

4.75

Typ

Max

5.25

Units

Notes

Vdd

Supply Voltage

Supply Current

–

5

V

o

I

–

8

mA

DD

Conditions are Vdd = 5.25V, -40 C ≤ T ≤

A

o

105 C, CPU = 3 MHz, SYSCLK doubler dis-

abled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 =

93.75 kHz, analog power = off.

I

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

–

5

7

14

µA

Conditions are with internal slow speed oscilla-

SB

a

o

WDT.

tor, Vdd = 5.25V, -40 C ≤ T ≤ 55 C. Analog

A

power = off.

I

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

100

16

Conditions are with internal slow speed oscilla-

SBH

a

o

WDT.

tor, Vdd = 5.25V, 55 C < T ≤ 105 C. Analog

A

power = off.

I

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

Conditions are with properly loaded, 1 µW max,

SBXTL

a

o

WDT.

32.768 kHz crystal. Vdd = 5.25V, -40 C ≤ T

≤

A

o

55 C. Analog power = off.

I

Sleep (Mode) Current with POR, LVD, Sleep Timer, and

–

7

100

µA

Conditions are with properly loaded, 1µW max,

SBXTLH

a

o

WDT.

32.768 kHz crystal. Vdd = 5.25V, 55 C < T

≤

A

o

105 C. Analog power = off.

V

Reference Voltage (Bandgap)

1.25

1.3

1.35

V

Trimmed for appropriate Vdd.

REF

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions

enabled.

3.3.2

DC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-5: DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

Max

Units

kΩ

Notes

R

Pull up Resistor

4

8

–

PU

PD

OH

R

Pull down Resistor

High Output Level

5.6

–

kΩ

V

3.5

V

IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

Low Output Level

–

0.75

0.8

V

IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]),

4 on odd port pins (for example, P0[3], P1[5])).

OL

V

I

Input Low Level

Input High Level

Input Hysterisis

–

V

Vdd = 4.75 to 5.25.

IL

IH

H

2.2

–

V

110

1

–

mV

nA

pF

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

Capacitive Load on Pins as Output

–

Gross tested to 1 µA.

IL

o

C

–

3.5

10

IN

Package and pin dependent. Temp = 25 C.

o

–

OUT

Package and pin dependent. Temp = 25 C.

November 9, 2006

Document No. 38-12023 Rev. *D

16

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3.3

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC

blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 3-6: DC Operational Amplifier Specifications

Symbol

Description

Min

Typ

1.6

Max

Units

mV

Notes

V

Input Offset Voltage (absolute value) Low Power

Input Offset Voltage (absolute value) Mid Power

Input Offset Voltage (absolute value) High Power

Input Offset Voltage Drift

–

11

9

OSOA

1.3

1.2

7.0

mV

9

o

TCV

35.0

200

10

OSOA

µV/ C

I

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Common Mode Voltage Range

–

10

pA

EBOA

o

C

4.5

pF

V

INOA

Package and pin dependent. Temp = 25 C.

V

0.0

0.5

–

Vdd

The common-mode input voltage range is mea-

sured through an analog output buffer. The

specification includes the limitations imposed

by the characteristics of the analog output

buffer.

CMOA

Common Mode Voltage Range (high power or high

opamp bias)

Vdd - 0.5

G

Open Loop Gain

–

dB

Specification is applicable at high power. For all

other bias modes (except high power, high

opamp bias), minimum is 60 dB.

OLOA

OHIGHOA

OLOWOA

SOA

Power=Low

80

Power=Medium

Power=High

V

High Output Voltage Swing (worst case internal load)

Power=Low

Vdd - 0.2

Vdd - 0.5

–

V

Power=Medium

Power=High

Low Output Voltage Swing (worst case internal load)

Power=Low

–

0.2

0.5

V

Power=Medium

Power=High

I

Supply Current (including associated AGND buffer)

Power=Low

–

150

300

600

1200

2400

4600

80

200

400

800

1600

3200

6400

–

µA

dB

Power=Low, Opamp Bias=High

Power=Medium

Power=Medium, Opamp Bias=High

Power=High

Power=High, Opamp Bias=High

Supply Voltage Rejection Ratio

PSRR

Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN

≤ Vdd.

OA

3.3.4

DC Low Power Comparator Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-7. DC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V

I

Low power comparator (LPC) reference voltage range

0.2

–

Vdd - 1

V

REFLPC

LPC supply current

LPC voltage offset

10

40

30

µA

SLPC

V

–

2.5

mV

OSLPC

November 9, 2006

Document No. 38-12023 Rev. *D

17

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3.5

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-8: DC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

mV

Notes

V

Input Offset Voltage (Absolute Value)

–

3

18

–

OSOB

TCV

Input Offset Voltage Drift

–

+6

–

µV/°C

OSOB

CMOB

V

Common-Mode Input Voltage Range

Output Resistance

.5

–

Vdd - 1.0

V

Ω

V

R

1

–

OUTOB

V

High Output Voltage Swing (Load = 32 ohms to Vdd/2)

.5 x Vdd + 1.3

–

OHIGHOB

OLOWOB

SOB

Low Output Voltage Swing (Load = 32 ohms to Vdd/2)

–

.5 x Vdd - 1.3

V

I

Supply Current Including Bias Cell (No Load)

Power = Low

–

1.1

2.6

64

5.1

8.8

–

mA

dB

Power = High

PSRR

Supply Voltage Rejection Ratio

OB

November 9, 2006

Document No. 38-12023 Rev. *D

18

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3.6

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control

register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Table 3-9: DC Analog Reference Specifications

Symbol

Description

Bandgap Voltage Reference 5V

Min

Typ

Max

Units

V

1.25

1.30

Vdd/2

2.60

P2[4]

1.3

1.35

V

BG5

a

–

AGND = Vdd/2

Vdd/2 - 0.02

2.4

Vdd/2 + 0.02

2.8

CT Block Power = High

a

AGND = 2 x BandGap

CT Block Power = High

a

AGND = P2[4] (P2[4] = Vdd/2)

CT Block Power = High

P2[4] - 0.02

1.23

P2[4] + 0.02

1.37

a

AGND = BandGap

CT Block Power = High

a

AGND = 1.6 x BandGap

1.98

2.08

0.000

2.14

CT Block Power = High

a

AGND Column to Column Variation (AGND=Vdd/2)

CT Block Power = High

- 0.035

0.035

–

RefHi = Vdd/2 + BandGap

Ref Control Power = High

V

Vdd/2 + 1.15

3.65

Vdd/2 + 1.30

3.9

Vdd/2 + 1.45

4.15

RefHi = 3 x BandGap

Ref Control Power = High

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

Ref Control Power = High

P2[6] + 2.4

P2[4] + 1.24

P2[4] + P2[6] - 0.1

2.4

P2[6] + 2.6

P2[4] + 1.30

P2[4] + P2[6]

2.60

P2[6] + 2.8

P2[4] + 1.36

P2[4] + P2[6] + 0.1

2.8

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

Ref Control Power = High

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

Ref Control Power = High

RefHi = 2 x BandGap

Ref Control Power = High

RefHi = 3.2 x BandGap

Ref Control Power = High

3.9

4.16

4.42

RefLo = Vdd/2 – BandGap

Ref Control Power = High

Vdd/2 - 1.45

1.15

Vdd/2 - 1.3

1.30

Vdd/2 - 1.15

1.45

RefLo = BandGap

Ref Control Power = High

V

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

Ref Control Power = High

2.4 - P2[6]

P2[4] - 1.45

P2[4] - P2[6] - 0.1

2.6 - P2[6]

P2[4] - 1.3

P2[4] - P26

2.8 + P2[6]

P2[4] - 1.15

P2[4] - P2[6] + 0.1

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

Ref Control Power = High

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

Ref Control Power = High

a. AGND tolerance includes the offsets of the local buffer in the PSoC block. BG = Bandgap voltage is 1.3V ± 0.05V.

November 9, 2006

Document No. 38-12023 Rev. *D

19

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3.7

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-10: DC Analog PSoC Block Specifications

Symbol

Description

Min

Typ

12.24

80

Max

Units

kΩ

fF

Notes

R

C

Resistor Unit Value (Continuous Time)

–

CT

SC

Capacitor Unit Value (Switched Capacitor)

3.3.8

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-11: DC POR and LVD Specifications

Symbol

Description

Vdd Value for PPOR Trip (positive ramp)

PORLEV[1:0] = 01b

Min

Typ

Max

Units

Notes

V

–

4.40

–

V

PPOR1R

PORLEV[1:0] = 10b

4.60

PPOR2R

Vdd Value for PPOR Trip (negative ramp)

PORLEV[1:0] = 01b

V

PPOR1

4.40

4.60

V

PPOR2

PORLEV[1:0] = 10b

PPOR Hysteresis

V

PORLEV[1:0] = 01b

–

0

–

mV

PH1

PORLEV[1:0] = 10b

PH2

Vdd Value for LVD Trip

VM[2:0] = 110b

V

4.54

4.63

4.80

4.90

4.92

5.01

V

LVD6

VM[2:0] = 111b

LVD7

November 9, 2006

Document No. 38-12023 Rev. *D

20

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.3.9

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-12: DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

mA

Notes

I

Supply Current During Programming or Verify

–

15

–

25

0.8

–

DDP

V

Input Low Voltage During Programming or Verify

Input High Voltage During Programming or Verify

–

V

ILP

2.2

–

V

IHP

I

Input Current when Applying Vilp to P1[0] or P1[1] During

Programming or Verify

–

0.2

mA

Driving internal pull-down resistor.

ILP

I

Input Current when Applying Vihp to P1[0] or P1[1] During

Programming or Verify

–

1.5

mA

IHP

V

Output Low Voltage During Programming or Verify

Output High Voltage During Programming or Verify

–

Vss + 0.75

V

OLV

3.5

100

Vdd

–

V

OHV

a

Flash

–

Erase/write cycles per block.

Erase/write cycles.

ENPB

ENT

DR

Flash Endurance (per block)

a,b

25,600

15

–

Flash Endurance (total)

c

–

Years

Flash Data Retention

a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer

to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

b. A maximum of 256 x 100 block endurance cycles is allowed.

c. Flash data retention based on the use condition of ≤ 7000 hours at T_A≤ 105°C and the remaining time at T_A≤ 65°C.

November 9, 2006

Document No. 38-12023 Rev. *D

21

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4

AC Electrical Characteristics

3.4.1

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-13: AC Chip-Level Specifications

Symbol

IMO24

CPU1

48M

Description

Min

22.95

Typ

Max

24.96

Units

MHz

Notes

F

Internal Main Oscillator Frequency for 24 MHz

24

12

–

Trimmed. Utilizing factory trim values.

CPU Frequency (5V Nominal)

Digital PSoC Block Frequency

Internal Low Speed Oscillator Frequency

External Crystal Oscillator

0.90

–

12.48

–

MHz

kHz

Not allowed.

a

0

24

32

24M

24.96

64

15

–

32K1

32.768

23.986

–

kHz

Accuracy is capacitor and crystal dependent.

Is a multiple (x732) of crystal frequency.

32K2

PLL Frequency

–

MHz

PLL

Jitter24M2

24 MHz Period Jitter (PLL)

PLL Lock Time

–

800

10

ps

T

0.5

ms

PLLSLEW

T

PLL Lock Time for Low Gain Setting

0.5

–

50

ms

PLLSLEWS-

LOW

T

External Crystal Oscillator Startup to 1%

–

1700

2800

ms

OS

2620

3800

External Crystal Oscillator Startup to 200 ppm

OSACC

Jitter32k

32 kHz Period Jitter

–

100

–

ns

T

External Reset Pulse Width

10

–

µs

XRST

DC24M

24 MHz Duty Cycle

40

–

50

300

–

60

–

%

Step24M

24 MHz Trim Step Size

kHz

ps

Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak

–

Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared

–

600

ps

F

T

Maximum frequency of signal on row input or row output.

Supply Ramp Time

–

12.48

MHz

MAX

0

–

µs

RAMP

a. See the individual user module data sheets for information on maximum frequencies for user modules.

PLL

Enable

T

24 MHz

PLLSLEW

F_PLL

PLL

Gain

0

Figure 3-2. PLL Lock Timing Diagram

November 9, 2006

Document No. 38-12023 Rev. *D

22

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

PLL

Enable

T

24 MHz

PLLSLEWLOW

F_PLL

PLL

Gain

1

Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram

32K

Select

32 kHz

T

OS

F_32K2

Figure 3-4. External Crystal Oscillator Startup Timing Diagram

Jitter24M1

F_24M

Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter32k

F_32K2

Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram

November 9, 2006

Document No. 38-12023 Rev. *D

23

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4.2

AC General Purpose IO Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-14: AC GPIO Specifications

Symbol

Description

GPIO Operating Frequency

Min

Typ

Max

12.48

Units

MHz

Notes

Normal Strong Mode

F

0

–

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

3

2

9

–

22

–

ns

Vdd = 4.75 to 5.25V, 10% - 90%

–

27

22

–

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

Figure 3-7. GPIO Timing Diagram

November 9, 2006

Document No. 38-12023 Rev. *D

24

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4.3

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Table 3-15: AC Operational Amplifier Specifications

Symbol

SR

Description

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low

Min

Typ

Max

Units

Notes

ROA

0.15

–

V/µs

Power = Low, Opamp Bias = High

Power = Medium

0.15

1.7

V/µs

Power = Medium, Opamp Bias = High

Power = High

1.7

Power = High, Opamp Bias = High

Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low

6.5

SR

FOA

0.01

0.5

–

V/µs

Power = Low, Opamp Bias = High

Power = Medium

Power = Medium, Opamp Bias = High

Power = High

0.5

Power = High, Opamp Bias = High

Gain Bandwidth Product

4.0

BW

OA

Power = Low

0.75

3.1

–

MHz

Power = Low, Opamp Bias = High

Power = Medium

Power = Medium, Opamp Bias = High

Power = High

3.1

Power = High, Opamp Bias = High

5.4

November 9, 2006

Document No. 38-12023 Rev. *D

25

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

dBV/rtHz

10000

0

0.01

0.1

1.0

10

1000

100

0.001

0.01

0.1 Freq (kHz)

1

10

100

Figure 3-8. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequen-

cies, increased power level reduces the noise spectrum level.

nV/rtHz

10000

PH_BH

PH_BL

PM_BL

PL_BL

1000

100

10

0.001

0.01

0.1

1

10

100

Freq (kHz)

Figure 3-9. Typical Opamp Noise

November 9, 2006

Document No. 38-12023 Rev. *D

26

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4.4

AC Low Power Comparator Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-16. AC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

µs

Notes

T

LPC response time

–

50

≥ 50 mV overdrive comparator reference set

RLPC

within V

.

REFLPC

3.4.5

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-17: AC Digital Block Specifications

Function

Description

Min

Typ

Max

24.96

Units

Notes

4.75V < Vdd < 5.25V.

All

Maximum Block Clocking Frequency (> 4.75V)

Functions

Timer

a

Capture Pulse Width

–

ns

50

–

Maximum Frequency, No Capture

Maximum Frequency, With Capture

Enable Pulse Width

–

24.96

–

MHz

ns

4.75V < Vdd < 5.25V.

–

a

Counter

50

–

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

–

24.96

MHz

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

20

50

–

ns

a

Synchronous Restart Mode

Disable Mode

–

ns

50

–

Maximum Frequency

–

24.96

MHz

4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency

–

(PRS Mode)

CRCPRS

(CRC Mode)

Maximum Input Clock Frequency

–

24.96

4

MHz

SPIM

SPIS

Maximum data rate at 4.1 MHz due to 2 x over

clocking.

Maximum Input Clock Frequency

–

2

–

MHz

ns

a

Width of SS_ Negated Between Transmissions

50

–

Transmitter Maximum Input Clock Frequency

–

8

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

Receiver

Maximum Input Clock Frequency

–

16

24.96

MHz

Maximum data rate at 3.08 MHz due to 8 x over

clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

November 9, 2006

Document No. 38-12023 Rev. *D

27

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4.6

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-18: AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T

Rising Settling Time to 0.1%, 1V Step, 100pF Load

ROB

Power = Low

–

3

µs

Power = High

µs

T

Falling Settling Time to 0.1%, 1V Step, 100pF Load

SOB

Power = Low

–

3

µs

Power = High

SR

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load

ROB

FOB

Power = Low

0.6

–

V/µs

Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load

Power = Low

Power = High

0.6

–

V/µs

BW

Small Signal Bandwidth, 20mV , 3dB BW, 100pF Load

pp

OB

0.8

–

MHz

Power = Low

Power = High

Large Signal Bandwidth, 1V , 3dB BW, 100pF Load

pp

300

–

kHz

Power = Low

Power = High

3.4.7

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-19: AC External Clock Specifications

Symbol

Description

Min

Typ

Max

24.24

Units

MHz

Notes

F

Frequency

0

–

OSCEXT

–

High Period

Low Period

20.6

150

–

ns

µs

Power Up IMO to Switch

November 9, 2006

Document No. 38-12023 Rev. *D

28

[+] Feedback

CY8C27x43 Automotive Data Sheet

3. Electrical Specifications

3.4.8

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-20: AC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

ns

Notes

T

Rise Time of SCLK

Fall Time of SCLK

1

–

20

–

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

T

F

T

1

–

ns

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

Flash Erase Time (Block)

–

15

30

–

ERASEB

WRITE

DSCLK

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

–

45

2

3.4.9

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 3-21: AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Min Max

100

Fast Mode

Min Max

Symbol

SCLI2C

Description

SCL Clock Frequency

Units

kHz

Notes

F

T

0

400

–

Hold Time (repeated) START Condition. After this

period, the first clock pulse is generated.

4.0

–

0.6

µs

HDSTAI2C

T

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

Set-up Time for a Repeated START Condition

Data Hold Time

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

ns

µs

ns

LOWI2C

–

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

–

a

Data Set-up Time

250

4.0

–

100

0.6

Set-up Time for STOP Condition

–

Bus Free Time Between a STOP and START Condition 4.7

1.3

0

–

Pulse Width of spikes are suppressed by the input fil-

ter.

–

50

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data

bit to the SDA line t_rmax+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SDA

T_SPI2C

T

LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

SCL

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

Figure 3-10. Definition for Timing for Fast/Standard Mode on the I²C Bus

November 9, 2006

Document No. 38-12023 Rev. *D

29

[+] Feedback

4. Packaging Information

This chapter illustrates the packaging specifications for the CY8C27x43 automotive PSoC device, along with the thermal imped-

ances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

4.1

Packaging Dimensions

51-85077 *C

Figure 4-1. 20-Lead (210-Mil) SSOP

November 9, 2006

Document No. 38-12023 Rev. *D

30

[+] Feedback

CY8C27x43 Automotive Data Sheet

4. Packaging Information

51-85079 *C

Figure 4-2. 28-Lead (210-Mil) SSOP

51-85061 *C

51-85061-C

Figure 4-3. 48-Lead (300-Mil) SSOP

November 9, 2006

Document No. 38-12023 Rev. *D

31

[+] Feedback

CY8C27x43 Automotive Data Sheet

4. Packaging Information

4.2

Thermal Impedances

Table 4-1. Thermal Impedances per Package

Package

20 SSOP

28 SSOP

48 SSOP

Typical θ_JA

*

o

95 C/W

o

95 C/W

o

69 C/W

* T = T + POWER x θ_JA

J

A

4.3

Capacitance on Crystal Pins

Table 4-2: Typical Package Capacitance on Crystal Pins

Package

20 SSOP

28 SSOP

48 SSOP

Package Capacitance

2.6 pF

2.8 pF

3.3 pF

4.4

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 4-3. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature*

Maximum Peak Temperature

o

20 SSOP

240 C

260 C

o

28 SSOP

48 SSOP

240 C

260 C

o

240 C

260 C

o

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C

o

with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

November 9, 2006

Document No. 38-12023 Rev. *D

32

[+] Feedback

5. Ordering Information

The following table lists the CY8C27x43 automotive PSoC device’s key package features and ordering codes.

Table 5-1. CY8C27x43 Automotive PSoC Key Features and Ordering Information

20 Pin (210 Mil) SSOP

CY8C27243-12PVXE

CY8C27243-12PVXET

CY8C27443-12PVXE

CY8C27443-12PVXET

CY8C27643-12PVXE

CY8C27643-12PVXET

16K

256

No

-40C to +105C

8

12

16

24

44

8

4

Yes

20 Pin (210 Mil) SSOP

(Tape and Reel)

8

28 Pin (210 Mil) SSOP

12

28 Pin (210 Mil) SSOP

(Tape and Reel)

48 Pin (300 Mil) SSOP

(Tape and Reel)

5.1

Ordering Code Definitions

CY 8 C 27 xxx-SPxx

Package Type:

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb-Free

SX = SOIC Pb-Free

PVX = SSOP Pb-Free

LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free

E = Extended

Speed: 12 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

November 9, 2006

Document No. 38-12023 Rev. *D

33

[+] Feedback

6. Sales and Service Information

To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134

408.943.2600

Web Links:

Company Information – http://www.cypress.com

Sales – http://www.cypress.com/aboutus/sales_locations.cfm

Technical Support – http://www.cypress.com/support/login.cfm

6.1

Revision History

Table 6-1. CY8C27x43 Automotive Data Sheet Revision History

Document Title:

CY8C27243, CY8C27443, and CY8C27643 Automotive PSoC Mixed-Signal Array Final Data Sheet

38-12023

Issue Date

Document Number:

Revision

**

ECN #

Origin of Change

Description of Change

211622

225728

271469

286034

563653

03/30/2004 SFV

06/01/2004 SFV

First release of the CY8C27x43 automotive PSoC device data sheet.

*A

*B

*C

*D

Changes made to the Electrical Specifications chapter and Overview. Also changed title.

Update per SFV memo. Input MWR changes, including removing SMP. Change to Final.

Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table.

See ECN

HMT

Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC

Device Characteristics table. Update Technical Training Modules paragraph. Add ISSP note to

pinout tables. Update typical and recommended Storage Temperature per extended temp. specs.

Update CY branding and QFN convention. Update copyright and trademarks. Swap 48-pin SSOP

pins 45 and 46. Update links to new CY.com Portal.

Distribution: External Public

Posting: None

6.2

Copyrights and Flash Code Protection

Copyrights

a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.

The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry

embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products

for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of

Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress

Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety

applications, unless pursuant to an express written agreement with Cypress Semiconductor.

Flash Code Protection

Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.

Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its family of products is one of the

most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the

code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor

manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress

Semiconductor are committed to continuously improving the code protection features of our products.

November 9, 2006

34

[+] Feedback

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	0.210 INCH, LEAD FREE, SSOP-20
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.71	地址总线宽度：
位大小：	8	边界扫描：	NO
CPU系列：	M8C	最大时钟频率：	24.96 MHz
外部数据总线宽度：		JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3	长度：	7.2 mm
湿度敏感等级：	3	I/O 线路数量：	16
端子数量：	20	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP20,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	RAM（字节）：	256
RAM（字数）：	256	ROM（单词）：	16384
ROM可编程性：	FLASH	座面最大高度：	2 mm
速度：	12 MHz	子类别：	Microcontrollers
最大压摆率：	8 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	20
宽度：	5.3 mm	Base Number Matches：	1

型号	制造商	描述	替代类型	文档
CY8C24223A-12PVXE	CYPRESS	PSoC㈢ Mixed-Signal Array	类似代替
CY8C24223A-12PVXET	CYPRESS	PSoC㈢ Mixed-Signal Array	类似代替

型号	制造商	描述	价格	文档
CY8C27243-12PVXET	CYPRESS	PSoC㈢ Mixed-Signal Array	获取价格
CY8C27243-24PVI	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24PVIT	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24PVXI	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24PVXI	INFINEON	CY8C27x43	获取价格
CY8C27243-24PVXIT	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24SI	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24SIT	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24SXI	CYPRESS	PSoC Mixed Signal Array	获取价格
CY8C27243-24SXIT	CYPRESS	PSoC Mixed Signal Array	获取价格

CY8C27243-12PVXE

CY8C27243-12PVXE 概述

CY8C27243-12PVXE 规格参数

CY8C27243-12PVXE 数据手册

CY8C27243-12PVXE 替代型号

CY8C27243-12PVXE 相关器件

CY8C27243-12PVXE 相关文章

热门型号