CY8C28413-12PVXQ_技术文档

CY8C28243, CY8C28403, CY8C28413

CY8C28433, CY8C28445, CY8C28452

CY8C28513, CY8C28533, CY8C28545

Extended Industrial PSoC^®

Programmable System-on-Chip

❐

30 mA Analog Outputs on GPIO

Configurable Interrupt on All GPIO

Features

■

Varied Resource Options Within One PSoC Device Group

■

Additional System Resources

Up to 2 Hardware I²C Resources

• Each Resource Implements Slave, Master, or Multi-Master

Modes

• Operation Between 0 and 400 kHz

Watchdog and Sleep Timers

User-Configurable Low Voltage Detection

Flexible Internal Voltage References

Integrated Supervisory Circuit

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds up to 12 MHz

8x8 Multiply, 32-Bit Accumulate

Low Power at High Speed

4.75V to 5.25V Operating Voltage

Extended Temperature Range: -40°C to +105°C

❐

■

Advanced Reconfigurable Peripherals (PSoC Blocks)

❐

Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

On-Chip Precision Voltage Reference

■

Complete Development Tools

• Up to 9-Bit DACs

❐

Free Development Software (PSoC Designer™)

Full Featured In-Circuit Emulator, and Programmer

Full Speed Emulation

Flexible and Functional Breakpoint Structure

128K Trace Memory

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

• Multiple ADC configurations

• Dedicated SAR ADC, up to 192 ksps with Sample and Hold

• Up to 4 Synchronized or Independent Delta-Sigma ADCs

for Advanced Applications

Up to 4 Limited Type E Analog Blocks Provide:

• Dual Channel Capacitive Sensing Capability

• Comparators with Programmable DAC Reference

• Up to 10-bit Single-Slope ADCs

System Block Diagram

❐

Analog

Drivers

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

PSoC

CORE

Up to 12 Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• Shift Register, CRC, and PRS Modules

• Up to 3 Full-Duplex UARTs

System Bus

Global Digital Interconnect

SRAM

Global Analog Interconnect

• Up to 6 Half-Duplex UARTs

• Multiple Variable Data Length SPI™ Masters or Slaves

• Connectable to All GPIO

SROM

Flash 16K

1K

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

❐

Complex Peripherals by Combining Blocks

■

Precision, Programmable Clocking

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

❐

Internal ±4% 24 MHz Main Oscillator

Optional 32.768 kHz Crystal for Precise On-Chip Clocks

Optional External Oscillator, up to 24 MHz

Internal Low Speed, Low Power Oscillator for Watchdog and

Sleep Functionality

DIGITAL SYSTEM

ANALOG SYSTEM

Analog

Ref.

Analog

Block

Array

Digital

Block

Array

■

Flexible On-Chip Memory

❐

16K Bytes Flash Program Storage 100 Erase/Write Cycles

1K Bytes SRAM Data Storage

In-System Serial Programming (ISSP™)

Partial Flash Updates

Flexible Protection Modes

EEPROM Emulation in Flash

Analog

Input

Muxing

POR and LVD Internal Switch

Voltage Mode

Digital

2

4 Type 2

2 I²C

■

Programmable Pin Configurations

Clocks MACs Decimators Blocks

System Resets

Ref.

Pump

❐

25 mA Sink, 10 mA Drive on all GPIO

❐

Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on All GPIO

SYSTEM RESOURCES

❐

Analog Input on All GPIO

Cypress Semiconductor Corporation

Document Number: 001-46339 Rev. *F

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Revised November 10, 2009

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CY8C28xxx

Contents

Features ...............................................................................1

System Block Diagram .......................................................1

Contents ..............................................................................2

DC Operational Amplifier Specifications .....................30

DC Type-E Operational Amplifier Specifications .........31

DC Low Power Comparator Specifications .................33

DC Analog Output Buffer Specifications .....................33

DC Analog Reference Specifications ..........................34

DC Analog PSoC Block Specifications ........................35

DC Analog Mux Bus Specifications .............................36

DC SAR10 ADC Specifications ...................................36

DC POR and LVD Specifications ................................37

DC Programming Specifications .................................37

PSoC Functional Overview ................................................3

The PSoC Core .............................................................3

The Digital System ........................................................3

The Analog System .......................................................4

System Resources ........................................................7

PSoC Device Characteristics ........................................7

Getting Started ....................................................................8

Application Notes ..........................................................8

Development Kits ..........................................................8

Training .........................................................................8

CYPros Consultants ......................................................8

Solutions Library ............................................................8

Technical Support .........................................................8

AC Electrical Characteristics ..........................................38

AC Chip Level Specifications ......................................38

AC General Purpose I/O Specifications ......................40

AC Operational Amplifier Specifications ......................40

AC Type-E Operational Amplifier Specifications .........42

AC Low Power Comparator Specifications .................42

AC Analog Mux Bus Specifications .............................42

AC Digital Block Specifications ...................................42

AC Analog Output Buffer Specifications ......................43

AC SAR10 ADC Specifications ...................................43

AC External Clock Specifications ................................44

AC Programming Specifications ..................................44

AC I2C Specifications ..................................................44

Development Tools ............................................................8

PSoC Designer Software Subsystems ..........................8

In-Circuit Emulator .........................................................9

Designing with PSoC Designer .........................................9

Select Components .......................................................9

Configure Components .................................................9

Organize and Connect ..................................................9

Generate, Verify, and Debug .........................................9

Packaging Information .....................................................46

Packaging Dimensions ................................................46

Document Conventions ...................................................10

Acronyms Used ...........................................................10

Units of Measure .........................................................10

Numeric Naming ..........................................................10

Thermal Impedances .......................................................48

Capacitance on Crystal Pins ..........................................48

Solder Reflow Peak Temperature ...................................48

Development Tool Selection ...........................................49

Software ......................................................................49

Development Kits ........................................................49

Evaluation Tools ..........................................................49

Device Programmers ...................................................50

Accessories (Emulation and Programming) ................50

Pinouts ..............................................................................11

20-Pin Part Pinout ......................................................11

28-Pin Part Pinout .......................................................12

44-Pin Part Pinout ......................................................13

Register Reference ...........................................................14

Register Conventions ......................................................14

Register Mapping Tables .................................................14

Electrical Specifications ..................................................27

Absolute Maximum Ratings ...........................................28

Operating Temperature ...................................................28

Ordering Information ........................................................51

Ordering Code Definitions ...........................................52

Document History Page ...................................................53

Sales, Solutions, and Legal Information ........................53

Worldwide Sales and Design Support .........................53

Products ......................................................................53

DC Electrical Characteristics ..........................................29

DC Chip Level Specifications ......................................29

DC General Purpose I/O Specifications ......................30

Document Number: 001-46339 Rev. *F

Page 2 of 53

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CY8C28xxx

32-bit peripherals, which are called user modules. The digital

blocks can be connected to any GPIO through a series of global

buses that can route any signal to any pin.

PSoC Functional Overview

The PSoC family consists of many devices with On-Chip

Controllers. These devices are designed to replace multiple

traditional MCU based system components with one low cost

single chip programmable component. A PSoC device includes

configurable analog blocks, digital blocks, and interconnections.

This architecture enables the user to create customized

peripheral configurations to match the requirements of each

individual application. In addition, a fast CPU, Flash program

memory, SRAM data memory, and configurable I/O are included

in a range of convenient pinouts and packages.

Figure 1. Digital System Block Diagram^[1]

Port 5

Port 3

Port 1

Port 0

Port 4

Port 2

Digital Clocks

From Core

To Analog

System

To System Bus

DIGITAL SYSTEM

Digital PSoC Block Array

The CY8C28xxx group of PSoC devices described in this data

sheet have multiple resource configuration options available.

Therefore, not every resource mentioned in this data sheet is

available for each CY8C28xxx subgroup. The CY8C28x45

subgroup has a full feature set of all resources described. There

are six more segmented subgroups that allow designers to use

a device with only the resources and functionality necessary for

a specific application. See Table 2 on page 7 to determine the

resources available for each CY8C28xxx subgroup. The same

information is also presented in more detail in the Ordering Infor-

mation section.

Row 0

4

DBC00

DBC01 DCC02 DCC03

4

8

Row 1

4

DBC10

DBC11 DCC12 DCC13

4

The architecture for this specific PSoC device family, as shown

in the System Block Diagram on page 1, consists of four main

areas: PSoC Core, Digital System, Analog System, and System

Resources. The configurable global bus system allows all the

device resources to be combined into a complete custom

system. PSoC CY8C28xxx family devices have up to six I/O

ports that connect to the global digital and analog interconnects,

providing access to up to 12 digital blocks and up to 16 analog

blocks.

Row 2

4

DBC20

DBC21 DCC22 DCC23

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature

set. The core includes a CPU, memory, clocks, and configurable

general Purpose I/O (GPIO). The M8C CPU core is a powerful

processor with speeds up to 24 MHz, providing a four MIPS 8-bit

Harvard architecture microcontroller.

Digital peripheral configurations include:

■

PWMs (8 to 16 bit, One-shot and Multi-shot capability)

PWMs with Dead band/Kill (8 to 16 bit)

Counters (8 to 32 bit)

Memory encompasses 16K bytes of Flash for program storage,

1K bytes of SRAM for data storage. The PSoC device incorpo-

rates flexible internal clock generators, including a 24 MHz

internal main oscillator (IMO) accurate to 2.5% over temperature

and voltage. A low power 32 kHz internal low speed oscillator

(ILO) is provided for the sleep timer and watch dog timer (WDT).

The 32.768 kHz external crystal oscillator (ECO) is available for

use as a real time clock (RTC) and can optionally generate a

crystal-accurate 24 MHz system clock using a PLL.

Timers (8 to 32 bit)

Full-duplex 8-bit UARTs (up to 3) with selectable parity

Half-duplex 8-bit UARTs (up to 6) with selectable parity

Variable length SPI slave and master

❐

Up to 6 total slaves and masters (8-bit)

Supports 8 to 16 bit operation

❐

PSoC GPIOs provide connections to the CPU, and digital and

analog resources. Each pin’s drive mode may be selected from

8 options, which allows great flexibility in external interfacing.

Every pin also has the capability to generate a system interrupt

on high level, low level, and change from last read.

■

I²C slave, master, or multi-master (up to 2 available as System

Resources)

■

IrDA (up to 3)

Pseudo Random Sequence Generators (8 to 32 bit)

Cyclical Redundancy Checker/Generator (16 bit)

Shift Register (2 to 32 bit)

The Digital System

The Digital System is composed of up to 12 configurable digital

PSoC blocks. Each block is an 8-bit resource that can be used

alone or combined with other blocks to create 8, 16, 24, and

Note

1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.

Document Number: 001-46339 Rev. *F

Page 3 of 53

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CY8C28xxx

Figure 2. Analog System Block Diagram for CY8C28x45 and

CY8C28x52 Devices

The Analog System

The Analog System is composed of up to 16 configurable analog

blocks, each containing an opamp circuit that allows the creation

of complex analog signal flows. Some devices in this PSoC

family have an analog multiplex bus that can connect to every

GPIO pin. This bus can also connect to the analog system for

analysis with comparators and analog-to-digital converters. It

can be split into two sections for simultaneous dual-channel

processing.

All GPIO

P0[7]

P0[5]

P0[6]

P0[4]

P0[3]

P0[1]

P0[2]

P0[0]

Some of the more common PSoC analog functions (most

available as user modules) are:

P2[6]

P2[4]

P2[3]

P2[1]

■

Analog-to-digital converters (6 to 14-bit resolution, up to 4,

selectable as Incremental or Delta Sigma)

P2[2]

P2[0]

■

Dedicated 10-bit SAR ADC with sample rates up to 192 ksps

Synchronized, simultaneous Delta Sigma ADCs (up to 4)

Filters (2 to 8 pole band-pass, low-pass, and notch)

Amplifiers (up to 4, with selectable gain to 48x)

Instrumentation amplifiers (up to 2, with selectable gain to 93x)

Comparators (up to 6, with 16 selectable thresholds)

DACs (up to 4, with 6 to 9-bit resolution)

Multiplying DACs (up to 4, with 6 to 9-bit resolution)

High current output drivers (up to 4 with 30 mA drive)

1.3V reference (as a System Resource)

DTMF Dialer

Array Input Configuration

ACI0[1:0]

ACI1[1:0]

ACI2[1:0]

ACI3[1:0]

ACI4[1:0]

ACI5[1:0]

Block Array

ACC00

ASC10

ASD20

ACC01

ASD11

ASC21

ACC02

ASC12

ASD22

ACC03

ASD13

ASC23

ACE00

ASE10

ACE01

ASE11

Modulators

Analog Reference

Correlators

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGNDIn

RefIn

Bandgap

AGND

Peak detectors

Many other topologies possible

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-46339 Rev. *F

Page 4 of 53

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CY8C28xxx

Figure 3. Analog System Block Diagram for CY8C28x43

Devices

Figure 4. Analog System Block Diagram for CY8C28x33

Devices

All GPIO

P0[7]

P0[5]

P0[6]

P0[4]

P0[7]

P0[5]

P0[6]

P0[3]

P0[1]

P0[2]

P0[0]

P0[3]

P0[4]

P0[1]

P2[6]

P2[4]

P0[2]

P0[0]

P2[3]

P2[1]

P2[3]

P2[1]

P2[6]

P2[4]

P2[2]

P2[0]

Array Input Configuration

ACI0[1:0]

ACI1[1:0]

ACI4[1:0]

ACI5[1:0]

ACI0[1:0]

ACI1[1:0]

ACI2[1:0]

ACI3[1:0]

Block Array

ACC00

ACC01

ASD11

ASC21

Block Array

ACE00

ASE10

ACE01

ASE11

ACC00

ASC10

ASD20

ACC01

ASD11

ASC21

ACC02

ASC12

ASD22

ACC03

ASD13

ASC23

ASC10

ASD20

Analog Reference

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-46339 Rev. *F

Page 5 of 53

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CY8C28xxx

Figure 5. Analog System Block Diagram for CY8C28x23

Devices

Figure 6. Analog System Block Diagram for CY8C28x13

Devices

P0[7]

All GPIO

P0[5]

P0[6]

P0[7]

P0[5]

P0[6]

P0[4]

P0[3]

P0[4]

P0[1]

P0[2]

P0[0]

P2[3]

P2[1]

P0[3]

P0[1]

P0[2]

P0[0]

P2[6]

P2[4]

Array Input

Configuration

ACI0[1:0]

ACI1[1:0]

Array Input

Configuration

ACI0[1:0]

ACI1[1:0]

Block Array

ACE00

ACE01

ASE10

ASE11

Block Array

ACC00

ACC01

ASD11

ASC21

Analog Reference

ASC10

ASD20

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

Analog Reference

M8C Interface (Address Bus, Data Bus, Etc.)

Interface to

Digital System

Reference

Generators

RefHi

RefLo

AGND

AGNDIn

RefIn

Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-46339 Rev. *F

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CY8C28xxx

System Resources

Table 1. PSoC Device Characteristics

System Resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include a multiplier, multiple

decimators, switch mode pump, low voltage detection, and

power on reset. Statements describing the merits of each system

resource follow:

PSoC Part

Number

CY8C29x66 up to

64

4

16

12

4

12

2K

1K

32K

16K

CY8C28xxx

up to upto up to upto up to up to up to

[2]

44

3

12

44

4

6

12/4

■

Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

CY8C27x43 up to

44

2

8

12

4

12

256

Bytes

CY8C24x94 64

1

4

48

12

2

6

1K

16K

4K

CY8C24x23 up to

A

256

Bytes

■

Multiply accumulate (MAC) provides fast 8-bit multiplier with

32-bit accumulate, to assist in general math and digital filters.

24

CY8C23x33 up to

1

0

4

0

12

28

8

2

0

2

0

4

256

Bytes

8K

4K

8K

Uptofourdecimatorsprovidecustomhardwarefiltersfordigital

signal processing applications such as Delta-Sigma ADCs and

CapSense capacitive sensor measurement.

[3]

4

CY8C21x34 up to

28

512

Bytes

[3]

4

CY8C21x23 16

256

Bytes

■

Up to two I²C resources provide 0 to 400 kHz communication

over two wires. Slave, master, and multi-master modes are all

supported. I²C resources have hardware address detection

capability.

[4]

3

CY8C20x34 up to

28

512

Bytes

The devices covered by this data sheet all have the same archi-

tecture, specifications, and ratings. However, the amount of

some hardware resources varies from device to device within the

group. The following table lists resources available for the

specific device subgroups covered by this data sheet.

■

Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR (Power

On Reset) circuit eliminates the need for a system supervisor.

An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

Table 2. CY8C28xxx Device Characteristics

PSoC Device Characteristics

There are other PSoC device groups in addition to the one

described in this data sheet. These other PSoC device groups

offer even more resource options. The following table lists the

resources available for specific PSoC device groups. The PSoC

device group covered by this data sheet is highlighted.

PSoC Part

Number

CY8C28x03

CY8C28x13

CY8C28x23

CY8C28x33

CY8C28x43

CY8C28x45

CY8C28x52

N

Y

N

Y

N

Y

12

0

6

0

4

0

4

0

4

2

1

2

1

2

1

0

2

4

up to up to

24

0

2

4

8

up to up to

40 40

up to up to

44 10

up to up to

40 40

12 12

up to up to

44 44

up to up to

44 44

8

12

up to up to

24 24

Notes

2. Has 12 regular analog blocks and four limited Type-E analog blocks.

3. Limited analog functionality

.

4. Two analog blocks and one CapSense.

Document Number: 001-46339 Rev. *F

Page 7 of 53

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CY8C28xxx

PSoC Designer also supports C language compilers developed

specifically for the devices in the PSoC family.

Getting Started

The quickest way to understand PSoC silicon is to read this data

sheet and then use the PSoC Designer Integrated Development

Environment (IDE). This data sheet is an overview of the PSoC

integrated circuit and presents specific pin, register, and

electrical specifications.

PSoC Designer Software Subsystems

System-Level View

A drag-and-drop visual embedded system design environment

based on PSoC Express. In the system level view you create a

model of your system inputs, outputs, and communication inter-

faces. You define when and how an output device changes state

based upon any or all other system devices. Based upon the

design, PSoC Designer automatically selects one or more PSoC

On-Chip Controllers that match your system requirements.

For in depth information, along with detailed programming

details, see the PSoC® Programmable System-on-Chip

Technical Reference Manual for CY8C28xxx PSoC devices.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device data sheets on the web

at www.cypress.com/psoc.

PSoC Designer generates all embedded code, then compiles

and links it into a programming file for a specific PSoC device.

Application Notes

Chip-Level View

Application notes are an excellent introduction to the wide variety

of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

The chip-level view is a more traditional integrated development

environment (IDE) based on PSoC Designer 4.4. Choose a base

device to work with and then select different onboard analog and

digital components called user modules that use the PSoC

blocks. Examples of user modules are ADCs, DACs, Amplifiers,

and Filters. Configure the user modules for your chosen

application and connect them to each other and to the proper

pins. Then generate your project. This prepopulates your project

with APIs and libraries that you can use to program your

application.

Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet,

Digi-Key, Farnell, Future Electronics, and Newark.

Training

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

configuration allows for changing configurations at run time.

Free PSoC technical training (on demand, webinars, and

workshops) is available online at www.cypress.com/training. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

Hybrid Designs

You can begin in the system-level view, allow it to choose and

configure your user modules, routing, and generate code, then

switch to the chip-level view to gain complete control over

on-chip resources. All views of the project share a common code

editor, builder, and common debug, emulation, and programming

tools.

CYPros Consultants

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC Consultant go to www.cypress.com/cypros.

Solutions Library

Code Generation Tools

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various appli-

cation designs that include firmware and hardware design files

that enable you to complete your designs quickly.

PSoC Designer supports multiple third party C compilers and

assemblers. The code generation tools work seamlessly within

the PSoC Designer interface and have been tested with a full

range of debugging tools. The choice is yours.

Technical Support

Assemblers. The assemblers allow assembly code to merge

seamlessly with C code. Link libraries automatically use absolute

addressing or are compiled in relative mode, and linked with

other software modules to get absolute addressing.

For assistance with technical issues, search KnowledgeBase

articles and forums at www.cypress.com/support. If you cannot

find an answer to your question, call technical support at

1-800-541-4736.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices.

Development Tools

PSoC Designer is a Microsoft^®Windows-based, integrated

development

environment

for

the

Programmable

The optimizing C compilers provide all the features of C tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

System-on-Chip (PSoC) devices. The PSoC Designer IDE runs

on Windows XP or Windows Vista.

This system provides design database management by project,

an integrated debugger with In-Circuit Emulator, in-system

programming support, and built-in support for third-party

assemblers and C compilers.

Debugger

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing you to test the program in a physical

system while providing an internal view of the PSoC device.

Document Number: 001-46339 Rev. *F

Page 8 of 53

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CY8C28xxx

Debugger commands allow the designer to read and program

and read and write data memory, read and write I/O registers,

read and write CPU registers, set and clear breakpoints, and

provide program run, halt, and step control. The debugger also

allows the designer to create a trace buffer of registers and

memory locations of interest.

Width Modulator (PWM) User Module configures one or more

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to

correspond to your chosen application. Enter values directly or

by selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are

documented in data sheets that are viewed directly in the PSoC

Designer. These data sheets explain the internal operation of the

component and provide performance specifications. Each data

sheet describes the use of each user module parameter or driver

property, and other information you may need to successfully

implement your design.

Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

In-Circuit Emulator

Organize and Connect

A low cost, high functionality ICE (In-Circuit Emulator) is

available for development support. This hardware has the

capability to program single devices.

You can build signal chains at the chip level by interconnecting

user modules to each other and the I/O pins, or connect system

level inputs, outputs, and communication interfaces to each

other with valuator functions.

The emulator consists of a base unit that connects to the PC by

way of a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full speed (24

MHz) operation.

In the system-level view, selecting a potentiometer driver to

control a variable speed fan driver and setting up the valuators

to control the fan speed based on input from the pot selects,

places, routes, and configures a programmable gain amplifier

(PGA) to buffer the input from the potentiometer, an analog to

digital converter (ADC) to convert the potentiometer’s output to

a digital signal, and a PWM to control the fan.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

In the chip-level view, perform the selection, configuration, and

routing so that you have complete control over the use of all

on-chip resources.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Application” step. This causes PSoC Designer to generate

source code that automatically configures the device to your

specification and provides the software for the system.

The PSoC development process can be summarized in the

following four steps:

1. Select components

Both system-level and chip-level designs generate software

based on your design. The chip-level design provides application

programming interfaces (APIs) with high level functions to

control and respond to hardware events at run-time and interrupt

service routines that you can adapt as needed. The system-level

design also generates a C main() program that completely

controls the chosen application and contains placeholders for

custom code at strategic positions allowing you to further refine

the software without disrupting the generated code.

2. Configure components

3. Organize and Connect

4. Generate, Verify, and Debug

Select Components

Both the system-level and chip-level views provide a library of

prebuilt, pretested hardware peripheral components. In the

system-level view, these components are called “drivers” and

correspond to inputs (a thermistor, for example), outputs (a

brushless DC fan, for example), communication interfaces

(I²C-bus, for example), and the logic to control how they interact

with one another (called valuators).

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger

downloads the HEX image to the In-Circuit Emulator (ICE) where

it runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

In the chip-level view, the components are called “user modules”.

User modules make selecting and implementing peripheral

devices simple, and come in analog, digital, and mixed signal

varieties.

Configure Components

Each of the components you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a Pulse

Document Number: 001-46339 Rev. *F

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CY8C28xxx

Document Conventions

Acronyms Used

Units of Measure

The following table lists the acronyms that are used in this

document.

A units of measure table is located in the Electrical Specifications

section. Table 18 on page 27 lists all the abbreviations used to

measure the PSoC devices.

Acronym

AC

Description

alternating current

Numeric Naming

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, 01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

CT

DAC

DC

digital-to-analog converter

direct current

ECO

EEPROM

external crystal oscillator

electrically erasable programmable read-only

memory

FSR

GPIO

GUI

full scale range

general purpose I/O

graphical user interface

human body model

in-circuit emulator

HBM

ICE

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

I/O

IPOR

LSb

imprecise power on reset

least-significant bit

LVD

low voltage detect

MSb

PC

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC®

PWM

SAR

SC

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

successive approximation register

switched capacitor

SLIMO

SMP

SRAM

slow IMO

switch mode pump

static random access memory

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CY8C28xxx

Pinouts

This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations.

The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every

port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.

20-Pin Part Pinout

Table 3. 20-Pin Part Pinout (SSOP)

Type

CY8C28243 20-Pin PSoC Device

No.

Name

Description

Digital Analog

S, AI, M, P0[7]

S, AIO, M, P0[5]

S, AIO, M, P0[3]

S, AI, M, P0[1]

SMP

I2C0 SCL, M, P1[7]

I2C0 SDA, M, P1[5]

M, P1[3]

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

I/O

I, M, S P0[7] Analog column mux and SAR ADC

input.^[5]

1

2

3

4

5

6

7

8

9

Vdd

P0[6], M, AI, S

P0[4], M, AIO, S

P0[2], M, AIO, S

P0[0], M, AI, S

XRES

P1[6], M, I2C1 SCL

P1[4], M, EXTCLK

P1[2], M, I2C1 SDA

P1[0], M, XTALout, I2C0 SDA

I/O, M, S P0[5] Analog column mux and SAR ADC

input. Analog column output.^{[5, 6]}

SSOP

I/O, M, S P0[3] Analog column mux and SAR ADC

input. Analog column output.^{[5, 6]}

I, M, S P0[1] Analog column mux and SAR ADC

input.^[5]

I2C0 SCL, XTALin, M, P1[1]

Vss

Output

SMP Switch Mode Pump (SMP)

connection to external components.

10

6

7

8

9

I/O

M

P1[7] I2C0 Serial Clock (SCL).

P1[5] I2C0 Serial Data (SDA).

P1[3]

P1[1] Crystal Input (XTALin), I2C0 Serial

Clock (SCL), ISSP-SCLK^[4]

.

10

11

Power

Vss Ground connection.

I/O

M

P1[0] Crystal Output (XTALout), I2C0

Serial Data (SDA), ISSP-SDATA^[4]

.

12

13

I/O

M

P1[2] I2C1 Serial Data (SDA).^[7]

P1[4] Optional External Clock Input

(EXTCLK).

14

15

I/O

M

P1[6] I2C1 Serial Clock (SCL).^[7]

Input

XRES Active high external reset with

internal pull down.

16

17

18

19

20

I/O

I, M, S P0[0] Analog column mux and SAR ADC

input.^[5]

I/O, M, S P0[2] Analog column mux and SAR ADC

input. Analog column output.^{[5, 8]}

I/O, M, S P0[4] Analog column mux and SAR ADC

input. Analog column output.^{[5, 8]}

I, M, S P0[6] Analog column mux and SAR ADC

input.^[5]

Power

Vdd Supply voltage.

LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.

Notes

4. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx

PSoC devices for details.

5. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices.

6. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices.

Document Number: 001-46339 Rev. *F

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CY8C28xxx

28-Pin Part Pinout

Table 4. 28-Pin Part Pinout (SSOP)

Type

Description

CY8C28413, CY8C28433, CY8C28445, and CY8C28452

28-Pin PSoC Devices

No.

Name

Digital

Analog

1

2

I/O

I, M, S

P0[7] Analog column mux and SAR ADC input.^[5]

S, AI, M, P0[7]

S, AIO, M, P0[5]

S, AIO, M, P0[3]

S, AI, M, P0[1]

M, P2[7]

I/O, M, S P0[5] Analog column mux and SAR ADC input.

Analog column output.^{[5, 6]}

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Vdd

P0[6], M, AI, S

28

27

26

25

24

23

22

21

20

19

18

17

16

15

P0[4], M, AIO, S

P0[2], M, AIO, S

P0[0], M, AI, S

P2[6], M, External VRef

P2[4], M, External AGND

P2[2], M, AI

3

I/O

I/O, M, S P0[3] Analog column mux and SAR ADC input.

Analog column output.^{[5, 6]}

P0[1] Analog column mux and SAR ADC input.^[5]

4

5

6

7

8

9

I/O

I, M, S

M

M, P2[5]

P2[7]

AI, M, P2[3]

AI, M, P2[1]

M

P2[5]

SSOP

I, M

P2[3] Direct switched capacitor block input.^[9]

P2[1] Direct switched capacitor block input.^[9]

SMP

P2[0], M, AI

XRES

P1[6], M, I2C1 SCL

P1[4], M, EXTCLK

P1[2], M, I2C1 SDA

P1[0], M, XTALout, I2C0 SDA

I2C0 SCL, M, P1[7]

I2C0 SDA, M, P1[5]

M, P1[3]

Output

SMP Switch Mode Pump (SMP) connection to

external components.

10

11

12

13

I/O

M

P1[7] I2C0 Serial Clock (SCL).

P1[5] I2C0 Serial Data (SDA).

P1[3]

I2C0 SCL, XTALin, M, P1[1]

Vss

P1[1] Crystal Input (XTALin), I2C0 Serial Clock

(SCL), ISSP-SCLK^[4]

Ground connection.

.

14

15

Power

Vss

I/O

M

P1[0] Crystal Output (XTALout), I2C0 Serial Data

(SDA), ISSP-SDATA^[4]

.

16

17

18

19

I/O

M

P1[2] I2C1 Serial Data (SDA).^[7]

P1[4] Optional External Clock Input (EXTCLK).

P1[6] I2C1 Serial Clock (SCL).^[7]

Input

XRES Active high external reset with internal pull

down.

20

21

22

23

24

25

I/O

I, M

M

P2[0] Direct switched capacitor block input.^[10]

P2[2] Direct switched capacitor block input.^[10]

P2[4] External Analog Ground (AGND).

M

P2[6] External Voltage Reference (VRef).

P0[0] Analog column mux and SAR ADC input.^[5]

I, M, S

I/O, M, S P0[2] Analog column mux and SAR ADC input.

Analog column output.^{[5, 8]}

26

I/O

I/O, M, S P0[4] Analog column mux and SAR ADC input.

Analog column output.^{[5, 8]}

27

28

I, M, S

Power

P0[6] Analog column mux and SAR ADC input.^[5]

Vdd Supply voltage.

LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input

Notes

7. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices.

8. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog

column output for these devices.

9. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.

10. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices.

Document Number: 001-46339 Rev. *F

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CY8C28xxx

44-Pin Part Pinout

Table 5. 44-Pin Part Pinout (TQFP)

Type

CY8C28513, CY8C28533, and CY8C28545

44-Pin PSoC Devices

No.

Name

Description

Digital Analog

1

2

3

4

5

6

7

8

I/O

M

I, M

M

P2[5]

P2[3] Direct switched capacitor block input.^[9]

P2[1] Direct switched capacitor block input.^[9]

P4[7]

P4[5]

P4[3]

P4[1]

M

Output

SMP Switch Mode Pump (SMP) connection to

external components.

M, P2[5]

AI, M, P2[3]

AI, M, P2[1]

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

SMP

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

26

25

24

23

P2[4], M, External AGND

P2[2], M, AI

P2[0], M, AI

P4[6], M

P4[4], M

P4[2], M

P4[0], M

XRES

P3[6], M

P3[4], M

9

I/O

M

P3[7]

10

11

12

13

14

15

16

P3[5]

P3[3]

P3[1]

P1[7] I2C0 Serial Clock (SCL).

P1[5] I2C0 Serial Data (SDA).

P1[3]

TQFP

M, P3[7]

M, P3[5]

M, P3[3]

9

10

11

P1[1] Crystal Input (XTALin), I2C0 Serial Clock

(SCL), ISSP-SCLK^[4]

Ground connection.

.

P3[2], M, I2C1 SCL

17

18

Output

Vss

I/O

M

P1[0] Crystal Output (XTALout), I2C0 Serial Data

(SDA), ISSP-SDATA^[4]

.

19

20

21

22

23

24

25

26

I/O

M

P1[2] I2C1 Serial Data (SDA).^[7]

P1[4] Optional External Clock Input (EXTCLK).

P1[6] I2C1 Serial Clock (SCL).^[7]

P3[0] I2C1 Serial Data (SDA).^[7]

P3[2] I2C1 Serial Clock (SCL).^[7]

P3[4]

P3[6]

Input

XRES Active high external reset with internal pull

down.

27

28

29

30

31

32

33

34

35

36

I/O

M

P4[0]

P4[2]

M

P4[4]

M

P4[6]

I, M

M

P2[0] Direct switched capacitor block input.^[10]

P2[2] Direct switched capacitor block input.^[10]

P2[4] External Analog Ground (AGND).

P2[6] External Voltage Reference (VRef).

P0[0] Analog column mux and SAR ADC input.^[5]

M

I, M, S

I/O, M, S P0[2] Analog column mux and SAR ADC input.

Analog column output.^{[5, 8]}

37

I/O

I/O, M, S P0[4] Analog column mux and SAR ADC input.

Analog column output.^{[5, 8]}

38

39

40

41

I, M, S

Power

I, M, S

P0[6] Analog column mux and SAR ADC input.^[5]

Vdd Supply voltage.

P0[7] Analog column mux and SAR ADC input.^[5]

I/O

I/O, M, S P0[5] Analog column mux and SAR ADC input.

Analog column output.^{[5, 6]}

42

I/O

I/O, M, S P0[3] Analog column mux and SAR ADC input.

Analog column output.^{[5, 6]}

43

44

I/O

I, M, S

P0[1] Analog column mux and SAR ADC input.^[5]

P2[7]

LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.

Document Number: 001-46339 Rev. *F

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CY8C28xxx

Register Reference

This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the

PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices.

Register Conventions

Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

CY8C28xxx PSoC devices have a total register address space

of 512 bytes. The register space is referred to as I/O space and

is divided into two banks. The XIO bit in the Flag register

(CPU_F) determines which bank of registers CPU instructions

access. When the XIO bit is set the registers in Bank 1 are

accessed by CPU instructions. When the XIO bit is cleared the

registers in Bank 0 are accessed by CPU instructions.

Convention

Description

Read register or bit(s)

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

Note In the following register mapping tables, blank fields are

reserved and should not be accessed.

C

#

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CY8C28xxx

Table 6. CY8C28x03 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

RDI2RI

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

DBC20DR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

W

RW

#

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

RW

PRT0IE

DBC20DR1

DBC20DR2

DBC20CR0

DBC21DR0

DBC21DR1

DBC21DR2

DBC21CR0

DCC22DR0

DCC22DR1

DCC22DR2

DCC22CR0

DCC23DR0

DCC23DR1

DCC23DR2

DCC23CR0

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

RDI2SYN

RDI2IS

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

#

W

RW

#

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

#

W

RW

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

#

W

RW

#

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CUR_PP

STK_PP

RW

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

RES_WDT

I2C1_SCR

I2C1_MSCR

#

W

RW

#

I2C1_DR

RW

#

MUL1_X

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

W

MUL0_X

W

RW

#

MUL1_Y

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

W

MUL0_Y

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

F1

F2

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

F3

#

F4

W

RW

#

F5

F6

CPU_F

F7

RL

#

F8

W

RW

#

RDI1SYN

RDI1IS

F9

FA

FB

FC

FD

FE

FF

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

#

W

RW

#

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

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CY8C28xxx

Table 7. CY8C28x03 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

DBC20FN

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

RDI2RI

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

DBC20IN

SADC_TSCMPL

SADC_TSCMPH

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RDI2SYN

RDI2IS

DBC20OU

DBC20CR1

DBC21FN

DBC21IN

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

DBC21OU

DBC21CR1

DCC22FN

DCC22IN

DCC22OU

DCC22CR1

DCC23FN

DCC23IN

DCC23OU

DCC23CR1

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

DBC00FN

DBC00IN

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

VLT_CMP

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3

SADC_CR4

I2C0_ADDR

I2C1_ADDR

AMUX_CLK

RDI0RI

IMO_TR

ILO_TR

RW

BDG_TR

ECO_TR

I2C1_CFG

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

SADC_TSCR0

SADC_TSCR1

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

CPU_F

RL

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 16 of 53

[+] Feedback

CY8C28xxx

Table 8. CY8C28x13 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

RDI2RI

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

DBC20DR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

W

RW

#

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

RW

PRT0IE

DBC20DR1

DBC20DR2

DBC20CR0

DBC21DR0

DBC21DR1

DBC21DR2

DBC21CR0

DCC22DR0

DCC22DR1

DCC22DR2

DCC22CR0

DCC23DR0

DCC23DR1

DCC23DR2

DCC23CR0

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

RDI2SYN

RDI2IS

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

#

W

RW

#

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

#

W

RW

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

#

W

RW

#

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CUR_PP

STK_PP

RW

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

DEC0_DH

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RC

AMUX_CFG

RW

DEC0_DL

DEC1_DH

DEC1_DL

RES_WDT

#

W

RW

#

DEC_CR0*

DEC_CR1*

MUL0_X

RW

W

#

MUL1_X

MUL1_Y

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

W

RW

#

W

MUL0_Y

W

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

F1

F2

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

F3

#

F4

W

RW

#

F5

F6

CPU_F

F7

RL

#

F8

W

RW

#

RDI1SYN

RDI1IS

F9

FA

FB

FC

FD

FE

FF

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

#

DAC1_D

RW

#

W

RW

#

DAC0_D

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 17 of 53

[+] Feedback

CY8C28xxx

Table 9. CY8C28x13 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

DBC20FN

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

RDI2RI

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

DBC20IN

SADC_TSCMPL

SADC_TSCMPH

ACE_AMD_CR1

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RDI2SYN

RDI2IS

DBC20OU

DBC20CR1

DBC21FN

DBC21IN

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

ACE_PWM_CR

ACE_ADC0_CR

ACE_ADC1_CR

RW

DBC21OU

DBC21CR1

DCC22FN

DCC22IN

ACE_CLK_CR0

ACE_CLK_CR1

ACE_CLK_CR3

RW

DCC22OU

DCC22CR1

DCC23FN

DCC23IN

ACE01CR1

ACE01CR2

ASE11CR0

DCC23OU

DCC23CR1

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

DEC0_CR

DEC1_CR

RW

DEC0_CR0

DEC_CR3

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

DEC1_CR0

DEC_CR5

RW

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

IDAC_CR1

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

DBC00FN

DBC00IN

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

VLT_CMP

ADC0_TR

ADC1_TR

IDAC_CR2

IMO_TR

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3

SADC_CR4

I2C0_ADDR

ILO_TR

AMUX_CFG1

RW

BDG_TR

ECO_TR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

MUX_CR4

MUX_CR5

AMUX_CLK

RDI0RI

RW

SADC_TSCR0

SADC_TSCR1

ACE_AMD_CR0

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

ACE_AMX_IN

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

ACE_CMP_CR0

ACE_CMP_CR1

CPU_F

RL

ACE_CMP_GI_EN

ACE_ALT_CR0

ACE_ABF_CR0

RW

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

ACE0_CR1

ACE0_CR2

ACE0_CR3

RW

IDAC_CR0

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 18 of 53

[+] Feedback

CY8C28xxx

Table 10. CY8C28x33 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

RDI2RI

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

DBC20DR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

W

RW

#

ASC10CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

RW

PRT0IE

DBC20DR1

DBC20DR2

DBC20CR0

DBC21DR0

DBC21DR1

DBC21DR2

DBC21CR0

DCC22DR0

DCC22DR1

DCC22DR2

DCC22CR0

DCC23DR0

DCC23DR1

DCC23DR2

DCC23CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

RDI2SYN

RDI2IS

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

#

W

RW

#

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

#

W

RW

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

#

W

RW

#

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

RW

CUR_PP

STK_PP

RW

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

AMX_IN

RW

#

DEC0_DH

DEC0_DL

DEC1_DH

DEC1_DL

DEC2_DH

DEC2_DL

DEC3_DH

DEC3_DL

MUL1_X

RC

W

AMUX_CFG

CLK_CR3

ARF_CR

RES_WDT

#

CMP_CR0

ASY_CR

W

RW

#

CMP_CR1

RW

DEC_CR0*

DEC_CR1*

MUL0_X

RW

W

#

W

RW

#

MUL1_Y

W

MUL0_Y

W

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RW

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

F1

F2

RDI0LT0

F3

#

RDI0LT1

F4

W

RW

#

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

F5

F6

CPU_F

F7

RL

#

F8

W

RW

#

RDI1SYN

RDI1IS

F9

FA

FB

FC

FD

FE

FF

RDI1LT0

#

RDI1LT1

DAC1_D

RW

#

W

RW

#

RDI1RO0

RDI1RO1

RDI1DSM

DAC0_D

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 19 of 53

[+] Feedback

CY8C28xxx

Table 11. CY8C28x33 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

DBC20FN

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

RDI2RI

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

DBC20IN

SADC_TSCMPL

SADC_TSCMPH

ACE_AMD_CR1

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RDI2SYN

RDI2IS

DBC20OU

DBC20CR1

DBC21FN

DBC21IN

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

ACE_PWM_CR

ACE_ADC0_CR

ACE_ADC1_CR

RW

DBC21OU

DBC21CR1

DCC22FN

DCC22IN

ACE_CLK_CR0

ACE_CLK_CR1

ACE_CLK_CR3

DCC22OU

DCC22CR1

DCC23FN

DCC23IN

ACE01CR1

ACE01CR2

ASE11CR0

RW

DCC23OU

DCC23CR1

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

DEC0_CR

DEC1_CR

DEC2_CR

DEC3_CR

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

IDAC_CR1

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

DEC0_CR0

DEC_CR3

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

DEC1_CR0

DEC_CR4

RW

DEC2_CR0

DEC_CR5

RW

DEC3_CR0

RW

DBC00FN

DBC00IN

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

VLT_CMP

ADC0_TR

ADC1_TR

IDAC_CR2

IMO_TR

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

AMD_CR1

ALT_CR0

RW

RTC_S

RTC_CR

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3

SADC_CR4

I2C0_ADDR

CLK_CR2

RW

ILO_TR

AMUX_CFG1

BDG_TR

ECO_TR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

MUX_CR4

MUX_CR5

AMUX_CLK

RDI0RI

RW

SADC_TSCR0

SADC_TSCR1

ACE_AMD_CR0

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

ACE_AMX_IN

RW

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

ACE_CMP_CR0

ACE_CMP_CR1

CPU_F

RL

ACE_CMP_GI_EN

ACE_ALT_CR0

ACE_ABF_CR0

RW

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

ACE0_CR1

ACE0_CR2

ACE0_CR3

RW

IDAC_CR0

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 20 of 53

[+] Feedback

CY8C28xxx

Table 12. CY8C28x43 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

RDI2RI

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

DBC20DR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

W

RW

#

ASC10CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RC

W

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

RW

PRT0IE

DBC20DR1

DBC20DR2

DBC20CR0

DBC21DR0

DBC21DR1

DBC21DR2

DBC21CR0

DCC22DR0

DCC22DR1

DCC22DR2

DCC22CR0

DCC23DR0

DCC23DR1

DCC23DR2

DCC23CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

DEC0_DH

DEC0_DL

DEC1_DH

DEC1_DL

DEC2_DH

DEC2_DL

DEC3_DH

DEC3_DL

MUL1_X

RDI2SYN

RDI2IS

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

#

W

RW

#

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

#

W

RW

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

#

W

RW

#

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CUR_PP

STK_PP

RW

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

AMX_IN

RW

#

AMUX_CFG

CLK_CR3

ARF_CR

RES_WDT

I2C1_SCR

I2C1_MSCR

DEC_CR0*

DEC_CR1*

MUL0_X

#

CMP_CR0

ASY_CR

#

W

RW

#

CMP_CR1

I2C1_DR

RW

W

#

W

RW

#

MUL1_Y

W

MUL0_Y

W

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

F1

F2

RDI0LT0

F3

#

RDI0LT1

F4

W

RW

#

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

F5

F6

CPU_F

F7

RL

#

F8

W

RW

#

RDI1SYN

RDI1IS

F9

FA

FB

FC

FD

FE

FF

RDI1LT0

#

RDI1LT1

W

RW

#

RDI1RO0

RDI1RO1

RDI1DSM

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 21 of 53

[+] Feedback

CY8C28xxx

Table 13. CY8C28x43 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

DBC20FN

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

RDI2RI

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

80

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

DBC20IN

SADC_TSCMPL

SADC_TSCMPH

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RDI2SYN

RDI2IS

DBC20OU

DBC20CR1

DBC21FN

DBC21IN

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

DBC21OU

DBC21CR1

DCC22FN

DCC22IN

DCC22OU

DCC22CR1

DCC23FN

DCC23IN

DCC23OU

DCC23CR1

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

DEC0_CR

DEC1_CR

DEC2_CR

DEC3_CR

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

RW

DEC0_CR0

DEC_CR3

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

DEC1_CR0

DEC_CR4

RW

DEC2_CR0

DEC_CR5

RW

DEC3_CR0

RW

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

DBC00FN

DBC00IN

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

CMP_GO_EN1

AMD_CR1

ALT_CR0

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

VLT_CMP

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

ALT_CR1

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3

SADC_CR4

I2C0_ADDR

I2C1_ADDR

AMUX_CLK

RDI0RI

IMO_TR

RW

CLK_CR2

AMUX_CFG1

I2C1_CFG

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ILO_TR

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

SADC_TSCR0

SADC_TSCR1

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

CPU_F

RL

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 22 of 53

[+] Feedback

CY8C28xxx

Table 14. CY8C28x45 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

RDI2RI

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

DBC20DR0

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

#

W

RW

#

ASC10CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RC

W

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

RW

PRT0IE

DBC20DR1

DBC20DR2

DBC20CR0

DBC21DR0

DBC21DR1

DBC21DR2

DBC21CR0

DCC22DR0

DCC22DR1

DCC22DR2

DCC22CR0

DCC23DR0

DCC23DR1

DCC23DR2

DCC23CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

DEC0_DH

DEC0_DL

DEC1_DH

DEC1_DL

DEC2_DH

DEC2_DL

DEC3_DH

DEC3_DL

MUL1_X

RDI2SYN

RDI2IS

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

#

W

RW

#

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

#

W

RW

#

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

#

W

RW

#

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CUR_PP

STK_PP

RW

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

AMX_IN

RW

#

AMUX_CFG

CLK_CR3

ARF_CR

RES_WDT

I2C1_SCR

I2C1_MSCR

DEC_CR0*

DEC_CR1*

MUL0_X

#

CMP_CR0

ASY_CR

#

W

RW

#

CMP_CR1

I2C1_DR

RW

W

#

W

RW

#

MUL1_Y

W

MUL0_Y

W

SADC_DH

SADC_DL

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

F1

F2

RDI0LT0

F3

#

RDI0LT1

F4

W

RW

#

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

F5

F6

CPU_F

F7

RL

#

F8

W

RW

#

RDI1SYN

RDI1IS

F9

FA

FB

FC

FD

FE

FF

RDI1LT0

#

RDI1LT1

DAC1_D

RW

#

W

RW

#

RDI1RO0

RDI1RO1

RDI1DSM

DAC0_D

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 23 of 53

[+] Feedback

CY8C28xxx

Table 15. CY8C28x45 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

DBC20FN

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

RDI2RI

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

DBC20IN

SADC_TSCMPL

SADC_TSCMPH

ACE_AMD_CR1

RDI2SYN

RDI2IS

DBC20OU

DBC20CR1

DBC21FN

DBC21IN

RDI2LT0

RDI2LT1

RDI2RO0

RDI2RO1

RDI2DSM

ACE_PWM_CR

ACE_ADC0_CR

ACE_ADC1_CR

DBC21OU

DBC21CR1

DCC22FN

DCC22IN

ACE_CLK_CR0

ACE_CLK_CR1

ACE_CLK_CR3

DCC22OU

DCC22CR1

DCC23FN

DCC23IN

ACE01CR1

ACE01CR2

ASE11CR0

DCC23OU

DCC23CR1

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

DEC0_CR

DEC1_CR

DEC2_CR

DEC3_CR

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

IDAC_CR1

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

DEC0_CR0

DEC_CR3

RW

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

DEC1_CR0

DEC_CR4

RW

DEC2_CR0

DEC_CR5

RW

DEC3_CR0

RW

DBC00FN

DBC00IN

RW

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

CMP_GO_EN1

AMD_CR1

ALT_CR0

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

VLT_CMP

ADC0_TR

ADC1_TR

IDAC_CR2

IMO_TR

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

ALT_CR1

SADC_CR0

SADC_CR1

SADC_CR2

SADC_CR3

SADC_CR4

I2C0_ADDR

I2C1_ADDR

AMUX_CLK

RDI0RI

CLK_CR2

AMUX_CFG1

I2C1_CFG

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ILO_TR

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

SADC_TSCR0

SADC_TSCR1

ACE_AMD_CR0

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

RDI0LT0

RDI0LT1

ACE_AMX_IN

RW

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

ACE_CMP_CR0

ACE_CMP_CR1

CPU_F

RL

ACE_CMP_GI_EN

ACE_ALT_CR0

ACE_ABF_CR0

RW

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

ACE0_CR1

ACE0_CR2

ACE0_CR3

RW

RDI1RO0

RDI1RO1

RDI1DSM

IDAC_CR0

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 24 of 53

[+] Feedback

CY8C28xxx

Table 16. CY8C28x52 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

ASC10CR0

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

RC

W

C0

PRT0IE

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

ASC12CR0

ASC12CR1

ASC12CR2

ASC12CR3

ASD13CR0

ASD13CR1

ASD13CR2

ASD13CR3

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

ASD22CR0

ASD22CR1

ASD22CR2

ASD22CR3

ASC23CR0

ASC23CR1

ASC23CR2

ASC23CR3

DEC0_DH

DEC0_DL

DEC1_DH

DEC1_DL

DEC2_DH

DEC2_DL

DEC3_DH

DEC3_DL

MUL1_X

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

CUR_PP

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

STK_PP

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C0_CFG

I2C0_SCR

I2C0_DR

PRT5GS

PRT5DM2

RW

#

I2C0_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

DBC00DR0

DBC00DR1

DBC00DR2

DBC00CR0

DBC01DR0

DBC01DR1

DBC01DR2

DBC01CR0

DCC02DR0

DCC02DR1

DCC02DR2

DCC02CR0

DCC03DR0

DCC03DR1

DCC03DR2

DCC03CR0

DBC10DR0

DBC10DR1

DBC10DR2

DBC10CR0

DBC11DR0

DBC11DR1

DBC11DR2

DBC11CR0

DCC12DR0

DCC12DR1

DCC12DR2

DCC12CR0

DCC13DR0

DCC13DR1

DCC13DR2

DCC13CR0

#

W

RW

#

AMX_IN

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

#

AMUX_CFG

CLK_CR3

ARF_CR

RES_WDT

#

CMP_CR0

ASY_CR

W

RW

#

CMP_CR1

RW

DEC_CR0*

DEC_CR1*

MUL0_X

RW

W

#

W

RW

#

MUL1_Y

W

MUL0_Y

W

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

R

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

R

#

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

ACB02CR3

ACB02CR0

ACB02CR1

ACB02CR2

ACB03CR3

ACB03CR0

ACB03CR1

ACB03CR2

RW

W

RW

#

W

RW

#

RDI0SYN

RDI0IS

RDI0LT0

#

RDI0LT1

W

RW

#

RDI0RO0

RDI0RO1

RDI0DSM

RDI1RI

CPU_F

RL

#

W

RW

#

RDI1SYN

RDI1IS

RDI1LT0

#

RDI1LT1

DAC1_D

RW

#

W

RW

#

RDI1RO0

RDI1RO1

RDI1DSM

DAC0_D

CPU_SCR1

CPU_SCR0

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 25 of 53

[+] Feedback

CY8C28xxx

Table 17. CY8C28x52 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

80

C0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

81

82

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

ACE_AMD_CR1

83

84

RW

ACE_PWM_CR

ACE_ADC0_CR

ACE_ADC1_CR

85

RW

86

87

88

ACE_CLK_CR0

ACE_CLK_CR1

ACE_CLK_CR3

89

RW

8A

8B

8C

8D

8E

8F

90

ACE01CR1

ACE01CR2

ASE11CR0

RW

GDI_O_IN

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

DEC0_CR0

DEC_CR3

91

RW

GDI_E_IN

GDI_O_OU

GDI_E_OU

DEC0_CR

DEC1_CR

DEC2_CR

DEC3_CR

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

IDAC_CR1

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

92

93

94

DEC1_CR0

DEC_CR4

95

RW

96

97

98

DEC2_CR0

DEC_CR5

99

RW

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

DEC3_CR0

RW

DBC00FN

DBC00IN

RW

CLK_CR0

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

GDI_O_IN_CR

GDI_E_IN_CR

GDI_O_OU_CR

GDI_E_OU_CR

RTC_H

RW

CLK_CR1

DBC00OU

DBC00CR1

DBC01FN

DBC01IN

ABF_CR0

AMD_CR0

CMP_GO_EN

CMP_GO_EN1

AMD_CR1

ALT_CR0

VLT_CMP

ADC0_TR

ADC1_TR

IDAC_CR2

IMO_TR

RTC_M

DBC01OU

DBC01CR1

DCC02FN

DCC02IN

DCC02OU

DCC02CR1

DCC03FN

DCC03IN

DCC03OU

DCC03CR1

DBC10FN

DBC10IN

RTC_S

RTC_CR

ALT_CR1

CLK_CR2

ILO_TR

AMUX_CFG1

BDG_TR

ECO_TR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

MUX_CR4

MUX_CR5

I2C0_ADDR

RW

AMUX_CLK

RDI0RI

RW

RDI0SYN

RDI0IS

DBC10OU

DBC10CR1

DBC11FN

DBC11IN

ACE_AMD_CR0

RW

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

RDIODSM

RDI1RI

ACE_AMX_IN

RW

DBC11OU

DBC11CR1

DCC12FN

DCC12IN

DCC12OU

DCC12CR1

DCC13FN

DCC13IN

DCC13OU

DCC13CR1

ACE_CMP_CR0

ACE_CMP_CR1

CPU_F

RL

ACE_CMP_GI_EN

ACE_ALT_CR0

ACE_ABF_CR0

RW

RDI1SYN

RDI1IS

FLS_PR1

RW

RDI1LT0

RDI1LT1

RDI1RO0

RDI1RO1

RDI1DSM

ACE0_CR1

ACE0_CR2

ACE0_CR3

RW

IDAC_CR0

CPU_SCR1

CPU_SCR0

RW

#

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

*Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-46339 Rev. *F

Page 26 of 53

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CY8C28xxx

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical

specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40^oC ≤ T ≤ 105^oC and T ≤ 120^oC, except where noted.

A

J

Figure 7. Voltage versus CPU Frequency

5.25

Valid

Operating

Region

4.75

3.00

93 kHz

12 MHz

24 MHz

CPU Frequency

The following table lists the units of measure that are used in this section.

Table 18. Units of Measure

Symbol

^oC

Unit of Measure

degree Celsius

Symbol

μW

Unit of Measure

microwatts

dB

decibels

mA

ms

mV

nA

ns

milli-ampere

milli-second

milli-volts

fF

femto farad

hertz

Hz

KB

Kbit

kHz

kΩ

1024 bytes

1024 bits

nanoampere

nanosecond

nanovolts

kilohertz

nV

Ω

kilohm

ohm

MHz

MΩ

μA

μF

μH

μs

μV

μVrms

megahertz

megaohm

pA

pF

pp

picoampere

picofarad

microampere

microfarad

microhenry

microsecond

microvolts

microvolts root-mean-square

peak-to-peak

parts per million

picosecond

kilo-samples per second

ppm

ps

ksps

∑

V

sigma: one standard deviation

volts

Document Number: 001-46339 Rev. *F

Page 27 of 53

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CY8C28xxx

Absolute Maximum Ratings

Table 19. Absolute Maximum Ratings

Symbol

Description

Storage Temperature

Min

Typ

Max

Units

^oC

Notes

T_STG

-55

+25

+105

Higher storage temperatures reduce

data retention time. Recommended

storage temperature is +25°C ±

25°C. Storage temperatures above

65^oC degrade reliability. Maximum

combined storage and operational

time at +105°C is 7000 hours.

T_A

Ambient Temperature with Power Applied

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-40

–

+105

+5.5

^oC

V

Vdd

V_IO

-0.5

Vss -

0.5

Vdd +

0.5

V

V_IOZ

DC Voltage Applied to Tri-state

Vss -

0.5

–

Vdd +

0.5

V

I_MIO

Maximum Current into any Port Pin

-25

-50

–

+25

+50

mA

I_MAIO

Maximum Current into any Port Pin

Configured as Analog Driver

ESD

LU

Static Discharge Voltage

Latch-up Current

2000

–

V

Human Body Model ESD.

200

mA

Operating Temperature

Table 20. Operating Temperature

Symbol

T_A

Description

Min

-40

Typ

–

Max

+105

+120

Units

^oC

Notes

Ambient Temperature

Junction Temperature

T_J

–

The temperature rise from ambient to

junction is package specific. See

ThermalImpedancesonpage48. The

user must limit the power

consumption to comply with this

requirement.

Document Number: 001-46339 Rev. *F

Page 28 of 53

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CY8C28xxx

DC Electrical Characteristics

DC Chip Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 21. DC Chip Level Specifications

Symbol

Vdd

Description

Min

4.75

–

Typ

–

Max

5.25

14

Units

V

Notes

Supply Voltage

Supply Current

I_DD

8

mA

Conditions are Vdd = 5.25V, -40 ^oC ≤

T_A≤ 105^oC, CPU = 3 MHz, SYSCLK

doublerdisabled,VC1=1.5MHz,VC2

= 93.75 kHz, VC3 = 93.75 kHz, analog

power = off.

I_DDP

Supply current when IMO = 6 MHz using

SLIMO mode

–

3.5

4

mA

Conditions are Vdd = 5.0V, T_A= 25°C,

CPU = 0.75 MHz, SYSCLK doubler

disabled, VC1 = 0.375 MHz, VC2 =

23.44 kHz, VC3 = 0.09 kHz.

I_SB

Sleep (Mode) Current with POR, LVD, Sleep

Timer, and WDT.^[11]

–

2.35

6.69

7

10

25

16

μA

Conditions are with internal slow

speed oscillator, Vdd = 5.25V, -40 ^oC

≤ T_A≤ 55 ^oC. Analog power = off.

Conditions are with internal slow

speed oscillator, Vdd = 5.25V, 55 ^oC <

T_A≤ 105 ^oC. Analog power = off.

Conditions are with properly loaded, 1

μW max, 32.768 kHz crystal. Vdd =

5.25V, -40 ^oC ≤ T_A≤ 55^oC. Analog

power = off.

I_SBH

Sleep (Mode) Current with POR, LVD, Sleep

Timer, and WDT.^[11]

I_SBXTL

Sleep (Mode) Current with POR, LVD, Sleep

Timer, and WDT.^[11]

I_SBXTLHSleep (Mode) Current with POR, LVD, Sleep

Timer, and WDT.^[11]

–

7

26

1

μA

Conditions are with properly loaded,

1μW max, 32.768 kHz crystal. Vdd =

5.25V, 55 ^oC < T_A≤ 105^oC. Analog

power = off.

I_SBRTC

Current Consumed by RTC during Sleep

0.5

µA

Extra current consumed by the RTC

during sleep. This number is typical at

25°C and 5V.

V_REF

Reference Voltage (Bandgap)

1.28

–

1.3

0.65

0.4

1.32

3

V

Trimmed for appropriate Vdd.

I_SXRES

Supply Current with XRES Asserted 5V

mA

Max is peak current after XRES;

Typical value is the steady state

current value. T_A=25°C.

–

1.5

Note

11. Standby (sleep) current includes all function

s

(POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have

similar functions enabled.

Document Number: 001-46339 Rev. *F

Page 29 of 53

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CY8C28xxx

DC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 22. DC GPIO Specifications

Symbol

R_PU

Description

Pull Up Resistor

Min

4

Typ

5.6

–

Max

Units

kΩ

Notes

8

–

R_PD

Pull Down Resistor

High Output Level

4

V_OH

3.5

V

IOH = 10 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])). 80

mA maximum combined IOH budget.

V_OL

Low Output Level

–

0.75

V

IOL = 25 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])). 150

mA maximum combined IOL budget.

I_OH

I_OL

High Level Source Current

Low Level Sink Current

10

25

–

mA

V_OH= Vdd-1.0V, see the limitations of

the total current in the note for V_OH.

V_OL= 0.75V, see the limitations of the

total current in the note for V_OL.

V_IL

V_IH

V_H

I_IL

Input Low Level

–

2.2

–

0.8

V

Vdd = 3.0 to 5.25.

Vdd = 4.75 to 5.25.

Input High Level

Input Hysteresis

110

1

–

mV

nA

pF

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

–

Gross tested to 1 μA.

Package and pin dependent. Temp =

25^oC.

C_IN

–

3.5

10

C_OUT

Capacitive Load on Pins as Output

–

3.5

10

pF

Package and pin dependent. Temp =

25^oC.

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifiers covered

by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks.

The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 23. DC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V_OSOACTInput Offset Voltage CT Block (absolute

value)

–

1.6

1.3

1.2

8

mV

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

V_OSOA

Input Offset Voltage SC and AGND

Opamps (absolute value)

–

1

6

mV

Applies to High and Low Opamp Bias.

TCV_OSOAAverage Input Offset Voltage Drift

–

7.0

200

4.5

35.0

–

μV/^oC

pA

I_EBOA

C_INOA

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Gross tested to 1 μA.

Package and pin dependent. Temp =

25^oC.

10

pF

Document Number: 001-46339 Rev. *F

Page 30 of 53

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CY8C28xxx

Table 23. DC Operational Amplifier Specifications (continued)

Symbol

Description

Min

0.0

0.5

Typ

–

Max

Units

Notes

V_CMOA

Common Mode Voltage Range

Common Mode Voltage Range (high

power or high opamp bias)

Vdd

Vdd - 0.5

V

The common-mode input voltage

range is measured through an analog

output buffer. The specification

includes the limitations imposed by

the characteristics of the analog

output buffer.

–

CMRR_OACommon Mode Rejection Ratio

Power = Low

–

dB

Specification is applicable at high

power. For all other bias modes

(except high power, high opamp

bias), minimum is 50 dB.

60

Power = Medium

Power = High

G_OLOA

Open Loop Gain

Power = Low

Specification is applicable at high

power. For all other bias modes

(except high power, high opamp

bias), minimum is 60 dB.

60

80

Power = Medium

Power = High

V_OHIGHOAHigh Output Voltage Swing (internal

signals)

Vdd -

0.2

Vdd -

0.2

–

V

Power = Low

Power = Medium

Power = High

Vdd -

0.5

V_OLOWOALow Output Voltage Swing (internal

signals)

–

0.2

0.5

V

Power = Low

Power = Medium

Power = High

I_SOA

Supply Current (including associated

AGND buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

–

200

400

700

1400

2400

4600

300

600

1100

2100

4000

8000

μA

PSRR_OASupply Voltage Rejection Ratio

60

–

dB

Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -

1.25V) ≤ VIN ≤ Vdd.

DC Type-E Operational Amplifier Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifiers covered

by these specifications are components of the Limited Type E Analog PSoC blocks.

Table 24. DC Type-E Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

Max

17

Units

mV

Notes

V_OSOA

Input Offset Voltage (absolute value)

For 0.2V < Vin < Vdd - 1.2V.

–

25

mV

For Vin = 0 to 0.2V and Vin > Vdd -

1.2V.

TCV_OSOAAverage Input Offset Voltage Drift

–

10

200

4.5

–

μV/^oC

pA

[12]

I_EBOA

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Gross tested to 1 μA.

C_INOA

9.5

pF

Package and pin dependent. Temp

= 25^oC.

V_CMOA

I_SOA

Common Mode Voltage Range

Amplifier Supply Current

0.0

–

Vdd - 1

35

V

10

μA

Document Number: 001-46339 Rev. *F

Page 31 of 53

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CY8C28xxx

Note

12. Atypical behavior: I_EBOAof Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

Document Number: 001-46339 Rev. *F

Page 32 of 53

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CY8C28xxx

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 25. DC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V_REFLPC

Low power comparator (LPC) reference

voltage range

0.2

–

Vdd - 1

V

V_OSLPC

I_SLPC

LPC voltage offset

LPC supply current

–

2.5

10

30

40

mV

μA

DC Analog Output Buffer Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 26. DC Analog Output Buffer Specifications

Symbol

Description

Min

–

Typ

3

Max

Units

mV

μV/°C

V

Notes

V_OSOB

Input Offset Voltage (Absolute Value)

18

TCV_OSOBInput Offset Voltage Drift

–

+6

–

20

V_CMOB

Common-Mode Input Voltage Range

Output Resistance

.5

–

Vdd - 1.0

R_OUTOB

1

–

W

V_OHIGHOBHigh Output Voltage Swing (Load = 32 ohms .5 x Vdd +

–

V

to Vdd/2)

1.3

V_OLOWOBLow Output Voltage Swing (Load = 32 ohms

to Vdd/2)

–

.5 x Vdd-

1.3

V

I_SOB

Supply Current Including Bias Cell (No Load)

Power = Low

Power = High

–

1.1

2.6

5.1

8.8

mA

PSRR_OB

Supply Voltage Rejection Ratio

50

64

–

dB

(0.5 x Vdd - 1.0) . VOUT . (0.5

x Vdd + 0.9).

Document Number: 001-46339 Rev. *F

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CY8C28xxx

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control

register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Reference control power is high.

Table 27. DC Analog Reference Specifications for High Power

Symbol

Description

Bandgap Voltage Reference 5V

AGND = Vdd/2^[13]

AGND = 2 x BandGap^[13]

AGND = P2[4] (P2[4] = Vdd/2)^[13]

AGND = BandGap^[13]

Min

1.28

Typ

1.30

Max

1.32

Units

V

V_BG5

–

Vdd/2 - 0.021

2.527

Vdd/2 - 0.001

2.593

Vdd/2 + 0.019

2.659

V

P2[4] - 0.015

1.28

P2[4] - 0.002

1.31

P2[4] + 0.011

1.34

V

AGND = 1.6 x BandGap^[13]

AGND Block to Block Variation (AGND = Vdd/2)^[13]

2.034

2.084

2.134

V

-34

0.000

34

V

RefHi = Vdd/2 + BandGap

Vdd/2 + 1.91

3.761

Vdd/2 + 1.273

3.874

Vdd/2 + 1.355

3.987

V

RefHi = 3 x BandGap

V

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[6] + 2.478

P2[4] + 1.195

P2[6] + 2.567

P2[4] + 1.273

P2[6] + 2.722

P2[4] + 1.405

V

P2[4] + P2[6] -

0.067

P2[4] + P2[6] +

0.028

P2[4] + P2[6] +

0.011

V

–

RefHi = 2 x BandGap

2.522

4.013

2.587

4.134

2.652

4.255

V

RefHi = 3.2 x BandGap

RefLo = Vdd/2 – BandGap

RefLo = BandGap

Vdd/2 - 1.371

1.247

Vdd/2 - 1.310

1.311

Vdd/2 - 1.249

1.375

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

2.513 - P2[6]

P2[4] - 1.352

2.586 - P2[6]

2.687 - P2[6]

P2[4] - 1.232

P2[4] - P2[6] -

0.008

–

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[4] - P2[6] -

0.028

P2[4] - P2[6] -

0.014

P2[4] - P2[6] -

0.056

V

Table 28. DC Analog Reference Specifications for Medium Power

Symbol

Description

Bandgap Voltage Reference 5V

AGND = Vdd/2^[13]

AGND = 2 x BandGap^[13]

AGND = P2[4] (P2[4] = Vdd/2)^[13]

AGND = BandGap^[13]

Min

1.28

Typ

1.30

Max

1.32

Units

V

V_BG5

–

Vdd/2 - 0.021

2.534

Vdd/2 -0.001

2.596

Vdd/2 + 0.019

2.658

V

P2[4] - 0.015

1.279

P2[4] -0.002

1.309

P2[4] + 0.011

1.339

V

AGND = 1.6 x BandGap^[13]

AGND Block to Block Variation (AGND = Vdd/2)^[13]

2.035

2.085

2.135

V

-34

0

34

V

RefHi = Vdd/2 + BandGap

Vdd/2 + 1.196

3.772

Vdd/2 +1.278

3.883

Vdd/2 + 1.360

3.994

V

RefHi = 3 x BandGap

V

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

P2[6] + 2.492

P2[4] + 1.200

P2[6] + 2.577

P2[4] + 1.278

P2[6] + 2.708

P2[4] + 1.400

V

Note

13. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Document Number: 001-46339 Rev. *F

Page 34 of 53

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CY8C28xxx

Table 28. DC Analog Reference Specifications for Medium Power (continued)

Symbol

Description

Min

Typ

Max

Units

–

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[4] + P2[6] -

0.058

P2[4] + P2[6]

-0.022

P2[4] + P2[6] +

0.014

V

–

RefHi = 2 x BandGap

2.523

4.02

2.589

4.141

2.655

4.262

V

RefHi = 3.2 x BandGap

RefLo = Vdd/2 – BandGap

RefLo = BandGap

Vdd/2 - 1.367

1.243

Vdd/2 -1.306

1.31

Vdd/2 - 1.245

1.377

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

2.516 - P2[6]

P2[4] - 1.359

2.588 - P2[6]

2.684 - P2[6]

P2[4] - 1.233

P2[4] - P2[6] -

0.004

–

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[4] - P2[6] -

0.033

P2[4] - P2[6] -

0.008

P2[4] - P2[6] +

0.049

V

Table 29. DC Analog Reference Specifications for Low Power

Symbol

Description

Bandgap Voltage Reference 5V

AGND = Vdd/2^[13]

Min

1.28

Typ

1.30

Max

1.32

Units

V

V_BG5

–

Vdd/2 - 0.021

2.534

Vdd/2 -0.001

2.597

Vdd/2 + 0.019

2.66

V

AGND = 2 x BandGap^[13]

V

AGND = P2[4] (P2[4] = Vdd/2)^[13]

AGND = BandGap^[13]

AGND = 1.6 x BandGap^[13]

P2[4] - 0.015

1.279

P2[4] -0.002

1.309

P2[4] + 0.011

1.339

V

2.036

2.086

2.136

V

AGND Block to Block Variation (AGND = Vdd/2)^[13]

-34

0

34

V

RefHi = Vdd/2 + BandGap

Vdd/2 + 1.196

3.773

Vdd/2 +1.278

3.886

Vdd/2 + 1.360

3.999

V

RefHi = 3 x BandGap

V

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[6] + 2.494

P2[4] + 1.201

P2[6] + 2.579

P2[4] + 1.280

P2[6] + 2.706

P2[4] + 1.399

V

P2[4] + P2[6] -

0.055

P2[4] + P2[6] -

0.020

P2[4] + P2[6] +

0.015

V

–

RefHi = 2 x BandGap

2.525

4.022

2.59

4.143

2.655

4.264

V

RefHi = 3.2 x BandGap

RefLo = Vdd/2 – BandGap

RefLo = BandGap

Vdd/2 - 1.367

1.243

Vdd/2 -1.304

1.31

Vdd/2 - 1.241

1.377

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

2.514 - P2[6]

P2[4] - 1.360

2.588 - P2[6]

2.686 - P2[6]

P2[4] - 1.234

P2[4] - P2[6] -

0.003

–

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

P2[4] - P2[6] -

0.031

P2[4] - P2[6] -

0.007

P2[4] - P2[6] +

0.045

V

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 30. DC Analog PSoC Block Specifications

Symbol

R_CT

Description

Min

–

Typ

12.24

80

Max

–

Units

kΩ

fF

Notes

Resistor Unit Value (Continuous Time)

Capacitor Unit Value (Switch Cap)

C_SC

–

Document Number: 001-46339 Rev. *F

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DC Analog Mux Bus Specifications

The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 31. DC Analog Mux Bus Specifications

Symbol

R_SW

R_VSS

Description

Min

–

Typ

–

Max

400

800

Units

W

Notes

Switch Resistance to Common Analog Bus

Resistance of Initialization Switch to VSS

Vdd ≥ 3.0V

–

W

DC SAR10 ADC Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 32. DC SAR10 ADC Specifications

Symbol

Description

Min

-2.5

-5

Typ

Max

2.5

5

Units

Notes

INL_SAR10

Integral nonlinearity for VREF ≥ 3

Integral nonlinearity for VREF < 3

Differential nonlinearity for VREF ≥ 3

Differential nonlinearity for VREF < 3

Active current consumption

-

LSB 10-bit resolution

mA

DNL_SAR10

-1.5

-4

-

1.5

4

I_SAR10

0.08

-

0.5

-

0.497

0.5

I_VREFSAR10Input current into P2[5] when configured as

the SAR10 ADC's VREF input.

mA

The internal voltage reference

buffer is disabled in this configu-

ration.

V_VREFSAR10Input reference voltage at P2[5] when

configured as the SAR10 ADC's external

voltage reference.

3.0

-

4.95

V

When VREF is buffered inside the

SAR10 ADC, the voltage level at

P2[5] (when configured as the

external reference voltage) must

always be at least 300 mV less

than the chip supply voltage level

on the Vdd pin.

(V_VREFSAR10< (Vdd - 300 mV) ).

V_OSSAR10

SAR_IMP

Offset voltage

5

-

7.7

10

-

mV

SAR input impedence

1.64

MΩ

Frequency dependant = 1/ Fs°C.

142.9 kHz (maximum) and Cin =

4.28 pF (typical)

Table 33. DC IDAC Specifications

Symbol

IDAC_DNL

IDAC_INL

IDAC_Gain

Description

Min

-5.0

282

Typ

2.0

Max

5.0

Units

LSB

nA

Notes

Differential nonlinearity

Valid for all 3 current ranges

Measured at full scale

Integral nonlinearity

2.0

5.0

Gain per bit - Range 1 (91 µA)

Gain per bit - Range 2 (318 µA)

Gain per bit - Range 3 (637 µA)

357

452

985

1250

2500

2.0%

1533

3057

20%

nA

1959

nA

IDACOffset

Offset at Code 0 vs LSB Ideal - Range 1

(91 µA)

%

Measured as a % of LSB (Current @

Code 0)/(LSB Ideal Current)

Offset at Code 0 vs LSB Ideal - Range 2

(318 µA)

1.0%

10%

%

Offset at Code 0 vs LSB Ideal - Range 3

(637 µA)

Document Number: 001-46339 Rev. *F

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DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip

Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register.

Table 34. DC POR and LVD Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Vdd Value for PPOR Trip (positive ramp)

V_PPOR1RPORLEV[1:0] = 01b

V_PPOR2RPORLEV[1:0] = 10b

–

4.39

4.55

4.49

4.65

V

Vdd Value for PPOR Trip (negative ramp)

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

V_PPOR1

V_PPOR2

–

4.39

4.55

4.49

4.64

V

PPOR Hysteresis

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

V_PH1

V_PH2

–

0

–

mV

Vdd Value for LVD Trip

VM[2:0] = 110b

VM[2:0] = 111b

V_LVD6

V_LVD7

4.62

4.71

4.80

4.83

4.92

V

Vdd Value for PPOR Trip (positive ramp)

V_PPOR1RPORLEV[1:0] = 01b

V_PPOR2RPORLEV[1:0] = 10b

–

4.39

4.55

–

V

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 35. DC Programming Specifications

Symbol

I_DDP

Description

Min

–

Typ

15

–

Max

25

Units

mA

V

Notes

Supply Current During Programming or Verify

V_ILP

V_IHP

I_ILP

Input Low Voltage During Programming or

Verify

–

0.8

Input High Voltage During Programming or

Verify

2.2

–

V

mA

V

Input Current when Applying Vilp to P1[0] or

P1[1] During Programming or Verify

0.21

1.5

Driving internal pull-down

resistor.

I_IHP

Input Current when Applying Vihp to P1[0] or

P1[1] During Programming or Verify

–

Driving internal pull-down

resistor.

V_OLV

V_OHV

Output Low Voltage During Programming or

Verify

–

Vss +

0.75

Output High Voltage During Programming or

Verify

3.5

Vdd

V

Flash_ENPBFlash Endurance (per block)^[14]

Flash_ENTFlash Endurance (total)^[14,15]

100

25,600

15

–

Erase/write cycles per block.

Erase/write cycles.

Flash_DR

Flash Data Retention^[16]

Years

Notes

14. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

15. A maximum of 256 x 100 block endurance cycles is allowed.

16. Flash data retention based on the use condition of ≤ 7000 hours at T ≤ 105°C and the remaining time at T ≤ 65°C.

A

Document Number: 001-46339 Rev. *F

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AC Electrical Characteristics

AC Chip Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 36. AC Chip Level Specifications

Symbol

F_IMO24

Description

Min

Typ

Max

Units

Notes

Internal Main Oscillator Frequency for 24 23.04

MHz

24

24.96

MHz Trimmed. Utilizing factory trim

values.

6

6.5^[17]

F

Internal Main Oscillator Frequency for

5.5

6 MHz

Trimmed for 5V or 3.3V operation

MHz

IMO6

using factory trim values. SLIMO

Mode = 1.

F_CPU1

CPU Frequency (5V Nominal)

Digital PSoC Block Frequency

Internal Low Speed Oscillator Frequency

0.90

–

12

–

12.48

–

24.96^[17]

MHz

F

MHz 4.75V< Vdd <5.25V

BLK5

3.0V<Vdd<3.6V

MHz

0

24

32

BLK33

F_32K1

15

64

kHz

Trimmed. Utilizing factory trim

values.

F_32K2

External Crystal Oscillator

–

5

32.768

–

kHz Accuracy is capacitor and crystal

dependent.

F

Internal Low Speed Oscillator Untrimmed

Frequency

After a reset and before the m8c

starts to run, the ILO is not trimmed.

See the System Resets section of

the PSoC Technical Reference

manual for details on timing this.

kHz

32K_U

F_PLL

PLL Frequency

–

23.986

–

MHz Is a multiple (x732) of crystal

frequency.

Jitter24M2 24 MHz RMS Period Jitter (PLL)

T_PLLSLEWPLL Lock Time

–

800

10

ps

ms

0.5

T_PLLSLEWSLPLL Lock Time for Low Gain Setting

50

OW

T_OS

External Crystal Oscillator Startup to 1%

–

1700

2800

2620

3800

ms

T_OSACC

External Crystal Oscillator Startup to 200

ppm

Jitter32k

T_XRST

32 kHz RMS Period Jitter

–

100

–

ns

μs

%

External Reset Pulse Width

24 MHz Duty Cycle

10

40

20

–

DC24M

50

60

80

DC

Internal Low Speed Oscillator Duty Cycle

50

%

ILO

Jitter24M1P 24 MHz RMS Period Jitter (IMO)

Peak-to-Peak

300

ps

Jitter24M1R 24 MHz RMS Period Jitter (IMO) Root

Mean Squared

–

0

–

600

12.48

–

ps

MHz

μs

F_MAX

Maximum Frequency of Signal on Row

Input or Row Output.

T_RAMP

Supply Ramp Time

Note

17. See the individual user module data sheets for information on maximum frequencies for user modules.

Document Number: 001-46339 Rev. *F

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Figure 8. PLL Lock Timing Diagram

PLL

Enable

T

24 MHz

PLLSLEW

F_PLL

PLL

Gain

0

Figure 9. PLL Lock for Low Gain Setting Timing Diagram

PLL

Enable

T

24 MHz

PLLSLEWLOW

F_PLL

PLL

Gain

1

Figure 10. External Crystal Oscillator Startup Timing Diagram

32K

32 kHz

Select

F_32K2

T

OS

Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F_24M

Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram

Jitter32k

F_32K2

Document Number: 001-46339 Rev. *F

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AC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 37. AC GPIO Specifications

Symbol

F_GPIO

Description

Min

0

Typ

–

Max

12.48

22

Units

Notes

GPIO Operating Frequency

MHz Normal Strong Mode

TRiseF

TFallF

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

3

–

ns

Vdd = 4.75 to 5.25V, 10% - 90%

2

–

22

Vdd = 4.75 to 5.25V, 10% - 90%

TRiseS

TFallS

9

27

22

–

9

–

Figure 13. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifiers covered

by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Table 38. AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T_ROA

Rising Settling Time from 80% of ΔV to 0.1% of

ΔV (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

(Active Probe Loading, Unity Gain)

–

3.9

0.72

0.62

μs

T_SOA

Falling Settling Time from 20% of ΔV to 0.1%

of ΔV (10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

(Active Probe Loading, Unity Gain)

–

5.9

0.92

0.72

μs

SR_ROA

Rising Slew Rate (20% to 80%)(10 pF load,

Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.15

1.7

6.5

–

V/μs

SR_FOA

Falling Slew Rate (20% to 80%)(10 pF load,

Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.01

0.5

4.0

–

V/μs

Document Number: 001-46339 Rev. *F

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Table 38. AC Operational Amplifier Specifications (continued)

Symbol

Description

Gain Bandwidth Product

Min

Typ

Max

Units

Notes

BW_OA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.75

3.1

5.4

–

MHz

E_NOA

Noise at 1 kHz

Power = Medium, Opamp Bias = High

–

100

–

nV/rt-Hz

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 14. Typical AGND Noise with P2[4] Bypass

VnAGND Emerald = 2*Vbg

-90

-100

-110

E0.0

E0.0 1

-120

-130

-140

-150

E0.1

E1.0

E10. 0

0.001

0.01

0.1

1

10

100

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high

frequencies, increased power level reduces the noise spectrum level.

Figure 15. Typical Opamp Noise

nV/rtHz

10000

PH_BH

PH_BL

PM_BL

PL_BL

1000

100

10

0.001

0.01

0.1

1

10

100

Freq (kHz)

Document Number: 001-46339 Rev. *F

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CY8C28xxx

AC Type-E Operational Amplifier Specifications

The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifiers covered

by these specifications are components of the Limited Type E Analog PSoC blocks.

Table 39. AC Type-E Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

50 mV Overdrive

T_COMP

Comparator Mode Response Time

–

75

100

ns

AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 40. AC Low Power Comparator Specifications

Symbol

Description

LPC Response Time

Min

Typ

Max

Units

Notes

T_RLPC

–

50

μs

≥ 50 mV overdrive comparator

reference set within V_REFLPC

.

AC Analog Mux Bus Specifications

The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 41. AC Analog Mux Bus Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

F_SW

Switch Rate

–

3.17

MHz

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 42. AC Digital Block Specifications

Function

Description

Min

Typ

Max

Units

Notes

All

Maximum Block Clocking Frequency

24.96

Functions

Timer

Capture Pulse Width

50^[18]

–

ns

Maximum Frequency, No Capture

Maximum Frequency, With Capture

Enable Pulse Width

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

Kill Pulse Width:

Asynchronous Restart Mode

Synchronous Restart Mode

Disable Mode

–

24.96

–

24.96

MHz 4.75V < Vdd < 5.25V.

MHz

ns

MHz 4.75V < Vdd < 5.25V.

MHz

–

50^[18]

–

Counter

–

Dead

Band

20

50^[18]

–

ns

Maximum Frequency

CRCPRS Maximum Input Clock Frequency

24.96

MHz 4.75V < Vdd < 5.25V.

–

(PRS

Mode)

CRCPRS Maximum Input Clock Frequency

(CRC

Mode)

–

24.96

4.16

MHz

SPIM

Maximum Input Clock Frequency

MHz Maximum data rate at 2.08 MHz

due to 2 x over clocking.

Document Number: 001-46339 Rev. *F

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Table 42. AC Digital Block Specifications (continued)

Function

SPIS

Description

Min

–

Typ

–

Max

2.08

–

Units

MHz

ns

Notes

Maximum Input Clock Frequency

Width of SS_ Negated Between Transmissions 50^[18]

Trans-

mitter

Maximum Input Clock Frequency

–

8.32

MHz Maximum data rate at 1.04 MHz

due to 8 x over clocking.

Receiver Maximum Input Clock Frequency

–

16

24.96

MHz Maximum data rate at 3.12 MHz

due to 8 x over clocking.

All

Maximum Block Clocking Frequency (> 4.75V)

4.75V < Vdd < 5.25V.

Functions

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 43. AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

T_ROB

Rising Settling Time to 0.1%, 1V Step, 100 pF

Load

Power = Low

Power = High

–

3

μs

T_SOB

Falling Settling Time to 0.1%, 1V Step, 100 pF

Load

Power = Low

Power = High

–

3

μs

SR_ROB

SR_FOB

BW_OB

Rising Slew Rate (20% to 80%), 1V Step, 100 pF

Load

Power = Low

Power = High

0.6

–

V/μs

Falling Slew Rate (80% to 20%), 1V Step, 100

pF Load

Power = Low

Power = High

0.6

–

V/μs

Small Signal Bandwidth, 20mV_pp, 3dB BW, 100

pF Load

Power = Low

Power = High

0.65

–

MHz

Large Signal Bandwidth, 1V_pp, 3dB BW, 100 pF

Load

Power = Low

300

–

kHz

Power = High

AC SAR10 ADC Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 44. AC SAR10 ADC Specifications

Symbol

Description

Min

–

Typ

–

Max

2.0

Units

Notes

F_INSAR10Input clock frequency for SAR10 ADC

MHz

F_SSAR10Sample rate for SAR10 ADC

SAR10 ADC Resolution = 10 bits

–

142.9

ksps For 10-bit resolution, the sample

rate is the ADC's input clock

divided by 14.

Note

18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 001-46339 Rev. *F

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AC External Clock Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 45. AC External Clock Specifications

Symbol

F_OSCEXT

Description

Min

0.093

20.6

150

Typ

–

Max

24.6

5300

–

Units

MHz

ns

Notes

Frequency

High Period

Low Period

–

ns

Power Up IMO to Switch

–

μs

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 46. AC Programming Specifications

Symbol

T_RSCLK

Description

Rise Time of SCLK

Min

1

Typ

–

Max

20

–

Units

ns

Notes

T_FSCLK

T_SSCLK

T_HSCLK

F_SCLK

Fall Time of SCLK

1

–

ns

Data Setup Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

40

0

–

ns

–

ns

–

8

MHz

ms

ns

T_ERASEB

T_WRITE

T_DSCLK

T_RSCLK

T_ERASEALL

Flash Erase Time (Block)

–

40

–

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

Rise Time of SCLK

–

55

70

–

1

–

ns

Flash Erase Time (Bulk)

–

80

ms

Erase all blocks and

protection fields at once.

T_{PROGRAM_HOT}Flash Block Erase + Flash Block Write Time

T_{PROGRAM_COLD}Flash Block Erase + Flash Block Write Time

–

100^[14]

200^[14]

ms

0°C ≤ Tj ≤ 100°C

-40°C ≤ Tj ≤ 0°C

2

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T_A≤ 105°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 47. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Fast Mode

Symbol

F_SCLI2C

Description

SCL Clock Frequency

Units

Notes

Min

0

Max

100

–

Min

0

Max

400

–

kHz

T_HDSTAI2C

HoldTime(repeated)STARTCondition. After

this period, the first clock pulse is generated.

4.0

0.6

μs

T_LOWI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

Setup Time for a Repeated START Condition

Data Hold Time

4.7

4.0

4.7

0

–

1.3

0.6

0

–

μs

T_HIGHI2C

T_SUSTAI2C

T_HDDATI2C

Document Number: 001-46339 Rev. *F

Page 44 of 53

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CY8C28xxx

Table 47. AC Characteristics of the I²C SDA and SCL Pins

Symbol Description

Data Setup Time

Standard Mode

Fast Mode

Units

Notes

Min

250

4.0

Max

Min

100^[19]

0.6

Max

T_SUDATI2C

T_SUSTOI2C

T_BUFI2C

–

ns

μs

Setup Time for STOP Condition

Bus Free Time Between a STOP and START

Condition

4.7

1.3

T_SPI2C

Pulse Width of spikes are suppressed by the

input filter.

–

0

50

ns

Figure 16. Definition for Timing for Fast/Standard Mode on the I²C Bus

SDA

SCL

T_SPI2C

T

LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

S

Sr

P

S

Note

19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

Š 250 ns must then be met. This is automatically the case

SU;DAT

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax

SU;DAT

Document Number: 001-46339 Rev. *F

Page 45 of 53

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CY8C28xxx

Packaging Information

This section illustrates the packaging specifications for the CY8C28xxx PSoC devices, along with the thermal impedances for each

package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to drawings at http://www.cypress.com/design/MR10161.

Packaging Dimensions

Figure 17. 20-Pin (210-Mil) SSOP

51-85077 *C

Document Number: 001-46339 Rev. *F

Page 46 of 53

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CY8C28xxx

Figure 18. 28-Pin (210-Mil) SSOP

51-85079*C

Figure 19. 44-Pin TQFP

51-85064 *C

Document Number: 001-46339 Rev. *F

Page 47 of 53

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CY8C28xxx

Thermal Impedances

Table 48. Thermal Impedances per Package

[20]

Package

Typical θ_JA

20 SSOP

28 SSOP

44 TQFP

80.8 °C/W

45.4 °C/W

24.0 °C/W

Capacitance on Crystal Pins

Table 49. Typical Package Capacitance on Crystal Pins

Package

Package Capacitance

20 SSOP

28 SSOP

44 TQFP

Pin9 = 0.0056 pF

Pin11 = 0.006048 pF

Pin13 = 0.006796 pF

Pin15 = 0.006755 pF

Pin16 = 0.009428 pF

Pin18 = 0.008635 pF

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 50. Solder Reflow Peak Temperature

Package

Minimum Peak Temperature^[21]Maximum Peak Temperature

20 SSOP

28 SSOP

44 TQFP

245 °C

260 °C

Notes

20. T = T + POWER x θ

J

A

JA

o

21. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications.

Document Number: 001-46339 Rev. *F

Page 48 of 53

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CY8C28xxx

Development Tool Selection

This section presents the development tools available for all current PSoC device families including the CY8C28xxx family.

Software

PSoC Designer

CY3210-ExpressDK PSoC Express Development Kit

At the core of the PSoC development software suite is PSoC

Designer. Utilized by thousands of PSoC developers, this robust

software has been facilitating PSoC designs for over half a

decade. PSoC Designer is available free of charge at

http://www.cypress.com/psocdesigner.

The CY3210-ExpressDK is for advanced prototyping and devel-

opment with PSoC Express (may be used with ICE-Cube

In-Circuit Emulator). It provides access to I²C buses, voltage

reference, switches, upgradeable modules and more. The kit

includes:

■

PSoC Express Software CD

Express Development Board

4 Fan Modules

PSoC Programmer

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or it can operate

directly from PSoC Designer. PSoC Programmer software is

compatible with both PSoC ICE-Cube In-Circuit Emulator and

PSoC MiniProg. PSoC Programmer is available free of charge

at http://www.cypress.com/psocprogrammer.

2 Proto Modules

MiniProg In-System Serial Programmer

MiniEval PCB Evaluation Board

Jumper Wire Kit

PSoC C Compilers

CY3202 is the optional upgrade to PSoC Designer that enables

the iMAGEcraft C compiler. It can be purchased from the

Cypress Online Store. At http://www.cypress.com, click the

Online Store shopping cart icon at the bottom of the web page,

and click PSoC (Programmable System-on-Chip) to view a

current list of available items.

USB 2.0 Cable

Serial Cable (DB9)

110 ~ 240V Power Supply, Euro-Plug Adapter

2 CY8C24423A-24PXI 28-PDIP Chip Samples

2 CY8C27443-24PXI 28-PDIP Chip Samples

2 CY8C29466-24PXI 28-PDIP Chip Samples

Development Kits

All development kits can be purchased from the Cypress Online

Store.

Evaluation Tools

CY3215-DK Basic Development Kit

All evaluation tools can be purchased from the Cypress Online

Store.

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface allows users to run, halt, and single step the processor

and view the content of specific memory locations. Advanced

emulation features are supported in PSoC Designer. The kit

includes:

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC

devices via the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

via a provided USB 2.0 cable. The kit includes:

■

PSoC Designer Software CD

ICE-Cube In-Circuit Emulator

Pod kit for CY8C29x66 PSoC Family

Cat-5 Adapter

■

MiniProg Programming Unit

MiniEval Socket Programming and Evaluation Board

28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

PSoC Designer Software CD

Mini-Eval Programming Board

110 ~ 240V Power Supply, Euro-Plug Adapter

ISSP Cable

Getting Started Guide

USB 2.0 Cable

USB 2.0 Cable and Blue Cat-5 Cable

2 CY8C29466-24PXI 28-PDIP Chip Samples

Document Number: 001-46339 Rev. *F

Page 49 of 53

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CY8C28xxx

CY3210-PSoCEval1

Device Programmers

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

All device programmers can be purchased from the Cypress

Online Store.

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

■

Evaluation Board with LCD Module

MiniProg Programming Unit

Note: The CY3207ISSP programmer needs the PSoC ISSP

software. It is not compatible with the PSoC Programmer

software. The latest PSoC ISSP software for this kit can be

downloaded from http://www.cypress.com. The kit includes:

28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

PSoC Designer Software CD

Getting Started Guide

■

CY3207 Programmer Unit

PSoC ISSP Software CD

USB 2.0 Cable

110 ~ 240V Power Supply, Euro-Plug Adapter

USB 2.0 Cable

Accessories (Emulation and Programming)

Table 51. Emulation and Programming Accessories

Part #

Pin Package

20SSOP

Pod Kit^[22]

CY3250-28XXX

Foot Kit^[23]

Adapter^[24]

CY8C28243-12PVXQ

CY3250-20SSOP-FK

CY3250-28SSOP-FK

CY8C28413-12PVXQ

CY8C28433-12PVXQ

CY8C28445-12PVXQ

CY8C28452-12PVXQ

28 SSOP

44 TQFP

Adapters can be found at

http://www.emulation.com.

CY8C28513-12AXQ

CY8C28533-12AXQ

CY8C28545-12AXQ

CY3250-28XXX

CY3250-44TQFP-FK

3rd-Party Tools

Build a PSoC Emulator into Your Board

Several tools have been specially designed by the following

3rd-party vendors to accompany PSoC devices during devel-

opment and production. Specific details for each of these tools

can be found at http://www.cypress.com under DESIGN

RESOURCES >> Evaluation Boards.

For details on how to emulate your circuit before going to volume

production using an on-chip debug (OCD) non-production PSoC

device, see Application Note “Debugging - Build a PSoC

Emulator

into

Your

Board

-

AN2323”

at

http://www.cypress.com/an2323.

Notes

22. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.

23. Foot kit includes surface mount feet that can be soldered to the target PCB.

24. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Document Number: 001-46339 Rev. *F

Page 50 of 53

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CY8C28xxx

Ordering Information

The following table lists the CY8C28xxx PSoC devices key package features and ordering codes

.

28-Pin (210 Mil) SSOP

CY8C28403-12PVXQ

CY8C28403-12PVXQT

-40 to 85

N

12

0

2

0

Y

24

8

0

16

1

Y

28-Pin (210 Mil) SSOP

(Tape and Reel)

28-Pin (210 Mil) SSOP

CY8C28413-12PVXQ

CY8C28413-12PVXQT

-40 to 105

Y

12

0

4

1

2

Y

24

0

16

1

Y

28-Pin (210 Mil) SSOP

(Tape and Reel)

44-Pin TQFP

CY8C28513-12AXQ

CY8C28513-12AXQT

-40 to 105

Y

12

0

4

1

2

Y

40

0

16

1

Y

44-Pin TQFP (Tape and

Reel)

28-Pin (210 Mil) SSOP

CY8C28433-12PVXQ

CY8C28433-12PVXQT

-40 to 105

Y

12

6

4

1

4

Y

24

2

16

1

Y

28-Pin (210 Mil) SSOP

(Tape and Reel)

44-Pin TQFP

CY8C28533-12AXQ

CY8C28533-12AXQT

-40 to 105

Y

12

6

4

1

4

Y

40

2

16

1

Y

44-Pin TQFP (Tape and

Reel)

20-Pin (210 Mil) SSOP

CY8C28243-12PVXQ

CY8C28243-12PVXQT

-40 to 105

N

12

0

2

4

Y

16

4

16

1

Y

20-Pin (210 Mil) SSOP

(Tape and Reel)

28-Pin (210 Mil) SSOP

CY8C28445-12PVXQ

CY8C28445-12PVXQT

-40 to 105

Y

12

4

2

4

Y

24

4

16

1

Y

28-Pin (210 Mil) SSOP

(Tape and Reel)

44-Pin TQFP

CY8C28545-12AXQ

CY8C28545-12AXQT

-40 to 105

Y

12

4

2

4

Y

40

4

16

1

Y

44-Pin TQFP (Tape and

Reel)

28-Pin (210 Mil) SSOP

CY8C28452-12PVXQ

CY8C28452-12PVXQT

-40 to 105

Y

8

12

4

1

4

N

24

4

16

1

Y

28-Pin (210 Mil) SSOP

(Tape and Reel)

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Document Number: 001-46339 Rev. *F

Page 51 of 53

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CY8C28xxx

Ordering Code Definitions

CY 8 C 28 xxx - SP xxxx

Package Type:

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb-free

SX = SOIC Pb-free

PVX = SSOP Pb-free

LTX/LFX/LKX = QFN Pb-free

AX = TQFP Pb-free

E = Extended

Speed: 12 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

Document Number: 001-46339 Rev. *F

Page 52 of 53

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CY8C28xxx

Document History Page

Document Title: CY8C28243, CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533,

CY8C28545, Extended Industrial PSoC® Programmable System-on-Chip

Document Number: 001-46339

Origin of

Change

Submission

Date

Revision ECN No.

Description of Change

**

2505101 KIY/HMI/AESA 06/26/2008

New document (Revision **).

*A

2593460 BTK/PYRS

2652217 BTK/PYRS

10/20/2008

Converted from Advance to Preliminary

Changed part numbers and title

Extensive updates to content

*B

02/02/09

Extensive updates to content.

Added registers maps.

Updated Getting Started section

Updated Development Tools section

Added some SAR10 ADC specifications.

Added more analog system figures.

*C

2675937 BTK

03/18/09

Updated DC Analog Reference Specifications

Changed temperature grade ratings in part numbers from E to Q

Minor content updates

*D

*E

2679015 HMI

2750217 TDU

03/26/2009

08/10/09

Post to external web.

Updates to Electrical Specificatons section

Minor content updates

*F

2805324 ALH

11/11/09

Added Contents page. Updated Electrical Specifications.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at www.cypress.com/sales.

Products

PSoC

psoc.cypress.com

clocks.cypress.com

wireless.cypress.com

memory.cypress.com

image.cypress.com

Clocks & Buffers

Wireless

Memories

Image Sensors

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-46339 Rev. *F

Revised November 10, 2009

Page 53 of 53

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced

herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights

to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document

may be the trademarks of their respective holders.

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型号：	CY8C28413-12PVXQ
厂家：	CYPRESS
描述：	Multifunction Peripheral, CMOS, PDSO28, 0.210 INCH, LEAD FREE, SSOP-28 光电二极管
文件：	总53页 (文件大小：1982K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C28413-12PVXQ [CYPRESS]

相关型号：

CY8C28413-12PVXQT

CY8C28413-24PVXI

CY8C28413-24PVXIT

CY8C28433

CY8C28433-12PVXQ

CY8C28433-12PVXQT

CY8C28433-24PVXI

CY8C28433-24PVXIT

CY8C28445

CY8C28445-24PVXI

CY8C28445-24PVXIT

CY8C28452