CY8C55_11_技术文档

PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®5 is a true system-level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip. The CY8C55 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C55 family can handle dozens of data acquisition channels and analog inputs on

every GPIO pin. The CY8C55 family is also a high-performance configurable digital system with some part numbers including

interfaces such as USB, multimaster I²C, and controller area network (CAN). In addition to communication interfaces, the CY8C55

family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM^®Cortex™-M3

microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean

primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C55 family provides unparalleled opportunities

for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware

updates.

❐ Library of advanced peripherals

Features

• Cyclic redundancy check (CRC)

■ 32-bit ARM Cortex-M3 CPU core

• Pseudo random sequence (PRS) generator

❐ DC to 67 MHz operation

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

^❐2^F0^la-^sy^hea^pr^rore^gt^re^an^mtio^mn^e, ^man^od^rym^{, u}u^plti^tp^ole²⁵s⁶ec^Ku^Bri^,ty¹⁰fe⁰a^,0tu⁰r⁰es^{write cycles,}

■ Analog peripherals (1.71 V ≤ V_DDA≤ 5.5 V)

❐ Up to 64 KB SRAM memory

❐ 1.024 V ±1% internal voltage reference across –40 °C to

^❐(²E^-KE^BPR^elO^ecM^tr)^icm^ae^llym^eo^rr^ay^s, ^a1^bm^leill^pio^ron^gc^ry^ac^mle^ms^a, a^bn^led^r2^e0^ady^-e^oaⁿr^ls^yr^met^ee^mnt^oio^ryn

+85 °C (128 ppm/°C)

❐ Configurable delta-sigma ADC with 8- to 20-bit resolution

• Sample rates up to 192 ksps

^❐A²⁴M^-cB^hA^anhⁿig^eh^l-^dpⁱe^rerf^co^tr^mm^ea^mnc^oe^rybu^as^cc(^eA^sH^sB⁽)^Db^Mu^As⁾a^wcc^ite^hs^ms ^ultilayer

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

• Programmable gain stage: ×0.25 to ×16

• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion

ratio (SINAD), ±1-bit INL/DNL

■ Low voltage, ultra low power

❐ Operating voltage range:1.8 V to 5.5 V

• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL

❐ Two SAR ADCs, each 12-bit at 1 Msps^[2]

^❐o^Hu^igtp^hu^-et ^{fficiency boost regulator from 1.8 V input to 5.0 V}

❐ Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs

❐ Four comparators with 95-ns response time

❐ 2 mA at 6 MHz

❐ Four uncommitted opamps with 25-mA drive capability

❐ Low power modes including:

^❐c^Fo^on^uf^rig^cu^orⁿa^ftⁱi^go^un^rs^aba^lr^ee^mpr^uo^ltg^ifr^uaⁿm^cm^tioaⁿbl^aeⁿg^aa^loin^ga^bm^lop^cl^kif^sie^.r^E(^xP^aG^mA^p)^le,

transimpedance amplifier (TIA), mixer, and Sample and Hold

❐ CapSense support

• 2-µA sleep mode with real time clock (RTC) and

low-voltage detect (LVD) interrupt

• 300-nA hibernate mode with RAM retention

■ Versatile I/O system

■ Programming, debug, and trace

^❐v^Ji^Te^Aw^Ger⁽⁴(S^wW^irV^e))^,,^sa^en^rd^iaT^{l w}RⁱA^reC^dE^eP^bO^uR^gT^(Sin^Wte^Dr⁾fa⁽c²e^ws^{ire), single wire}

❐ Cortex-M3 flash patch and breakpoint (FPB) block

^❐g^Ce^on^rte^er^xa^-t^Mes³a^En^min^bs^et^dru^dc^et^dio^Tn^rt^ar^ca^ece^Ms^atr^ce^roa^cm^e.^{ll™ (ETM™)}

❐ 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs)

❐ Any GPIO to any digital or analog peripheral routability

❐ LCD direct drive from any GPIO, up to 46×16 segments

❐ CapSense^®support from any GPIO^[1]

❐ 1.2 V to 5.5 V I/O interface voltages, up to 4 domains

❐ Maskable, independent IRQ on any pin or port

❐ Schmitt-trigger transistor-transistor logic (TTL) inputs

^❐t^Cra^oc^rte^exin^-Mfo³rm^da^at^ti^aon^{watchpoint and trace (DWT) generates data}

^❐u^Cs^oe^rd^tef^xo^-r^Mp³ri^Inⁿt^sf-^ts^ruty^mle^edⁿe^tab^tu^iogⁿgi^Tn^rg^{ace Macrocell (ITM) can be}

^❐a^Dn^Wd^Tt^,ra^Ec^Te^Ms^,y^asⁿte^dm^ITs^Mv^bia^lot^ch^ke^sS^cW^omV^mo^urⁿT^icR^aA^teC^wEⁱP^thO^oR^ffT^-chipdebug

^❐p^Au^llll^G-u^Pp^I/^Opu^sll^c-^odⁿo^fw^ign^u,^rH^abig^leh-^aZ^s, o^or^pestⁿro^dn^rg^ainou^htp^igu^ht^/low,

❐ 25 mA sink on SIO

■ Digital peripherals

❐ Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

■ Precision, programmable clocking

^❐d²i⁰gi^tt^oal²b⁴lo^pc^rk^os^gr(^aU^mD^mBs^a)^{ble logic device (PLD) based universal}

❐ Full CAN 2.0b 16 RX, 8 TX buffers^[2]

^❐v³o^tl^ota⁶g²e^Mra^Hn^zge^{internal oscillator over full temperature and}

❐ 4- to 25 MHz crystal oscillator for crystal PPM accuracy

❐ Internal PLL clock generation up to 67 MHz

❐ Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator

❐ Four 16-bit configurable timers, counters, and PWM blocks

^❐i⁶m⁷p^Mle^Hm^ze^,n²t⁴fi^-n^biⁱt^te^fii^xm^ep^du^pls^oeⁱⁿr^te^dsⁱp^go^itn^as^le^fil(^tF^erIR^b)^loa^cn^kd⁽i^Dnf^Fin^Bit⁾e^toimpulse

response (IIR) filters

❐ 32.768 KHz watch crystal oscillator

❐ Low power internal oscillator at 1, 33, and 100 kHz

❐ Library of standard peripherals

■ Temperature and packaging

❐ –40 °C to +85 °C industrial temperature

❐ 68-pin QFN and 100-pin TQFP package options.

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I²C

• Many others available in catalog

Notes

1. GPIOs with opamp outputs are not recommended for use with CapSense.

2. This feature on select devices only. See Ordering Information on page 105 for details.

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 001-66235 Rev. **

Revised March 28, 2011

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Contents

1. Architectural Overview ..................................................... 3

2. Pinouts ............................................................................... 5

3. Pin Descriptions ................................................................ 9

8.10 DAC ........................................................................ 53

8.11 Up/Down Mixer ....................................................... 54

8.12 Sample and Hold .................................................... 54

9. Programming, Debug Interfaces,

4. CPU ................................................................................... 10

4.1 ARM Cortex-M3 CPU ............................................... 10

4.2 Cache Controller ...................................................... 12

4.3 DMA and PHUB ....................................................... 12

Resources ............................................................................ 55

9.1 SWD Interface .......................................................... 55

9.2 JTAG Interface ......................................................... 55

9.3 Debug Features ........................................................ 55

9.4 Trace Features ......................................................... 55

9.5 SWV and TRACEPORT Interfaces .......................... 56

9.6 Programming Features ............................................. 56

9.7 Device Security ........................................................ 56

5. Memory ............................................................................. 16

5.1 Static RAM ............................................................... 16

5.2 Flash Program Memory ............................................ 16

5.3 Flash Security ........................................................... 16

5.4 EEPROM .................................................................. 16

5.5 Memory Map ............................................................ 17

10. Development Support ................................................... 57

10.1 Documentation ....................................................... 57

10.2 Online ..................................................................... 57

10.3 Tools ....................................................................... 57

6. System Integration .......................................................... 18

6.1 Clocking System ....................................................... 18

6.1.4 6.2 Power System ................................................. 21

11. Electrical Specifications ............................................... 58

11.1 Absolute Maximum Ratings .................................... 58

11.2 Device Level Specifications .................................... 59

11.3 Power Regulators ................................................... 61

11.1 Inputs and Outputs ................................................. 64

11.2 Analog Peripherals ................................................. 72

11.6 Digital Peripherals .................................................. 93

11.7 Memory .................................................................. 97

11.8 PSoC System Resources ....................................... 99

11.9 Clocking ................................................................ 101

7. Digital Subsystem ........................................................... 32

7.1 Example Peripherals ................................................ 32

7.4 DSI Routing Interface Description ............................ 39

7.5 CAN .......................................................................... 41

7.6 USB .......................................................................... 42

7.7 Timers, Counters, and PWMs .................................. 42

7.8 I²C ............................................................................ 43

7.9 Digital Filter Block ..................................................... 44

8. Analog Subsystem .......................................................... 44

8.1 Analog Routing ......................................................... 46

8.2 Delta-sigma ADC ...................................................... 48

8.3 Successive Approximation ADC ............................... 49

8.4 Comparators ............................................................. 49

8.5 Opamps .................................................................... 51

8.6 Programmable SC/CT Blocks .................................. 51

8.7 LCD Direct Drive ...................................................... 52

8.8 CapSense ................................................................. 53

8.9 Temp Sensor ............................................................ 53

12. Ordering Information ................................................... 105

12.1 Part Numbering Conventions ............................... 105

13. Packaging ..................................................................... 107

14. Acronyms ..................................................................... 109

15. Reference Documents ................................................. 110

16. Document Conventions .............................................. 111

16.1 Units of Measure .................................................. 111

17. Revision History .......................................................... 112

Document Number: 001-66235 Rev. **

Page 2 of 112

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

1. Architectural Overview

Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Analog Interconnect

Digital Interconnect

System Wide

Resources

Digital System

I2C

Master/

Slave

Universal Digital Block Array(24 x UDB)

CAN

2.0

8- Bit

Timer

Quadrature Decoder

16- Bit PRS

4- 25 MHz

( Optional)

16- Bit

PWM

UDB

22 Ω

Xtal

Osc

USB

PHY

UDB

8- Bit

FS USB

2.0

UDB

I 2C Slave

UDB

4x

Timer

8- Bit SPI

Logic

Timer

Counter

PWM

12- Bit SPI

UDB

IMO

Logic

32.768 KHz

( Optional)

UDB

UART

12- Bit PWM

RTC

Timer

System Bus

Program &

Debug

Memory System

CPU System

WDT

and

Wake

8051or

Interrupt

EEPROM

SRAM

Program

Cortex M3CPU

Controller

Debug&

Trace

Cache

Controller

PHUB

DMA

FLASH

EMIF

Boundary

Scan

ILO

Clocking System

Analog System

Digital

Filter

Block

Power Management

System

LCD Direct

Drive

+

4 x

ADCs

2 x

Opamp

POR and

LVD

3 per

Opamp

-

SAR

ADC

4 x SC/CT Blocks

(TIA, PGA, Mixer etc)

Sleep

Power

+

-

Temperature

Sensor

4 x

CMP

1.8 V LDO

SMP

1 x

Del Sig

ADC

4x DAC

CapSense

0. 5 to5.5 V

( Optional)

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Figure 1-1 illustrates the major components of the CY8C55

family. They are:

subsystem is a fast, accurate, configurable delta-sigma ADC

with these features:

■ ARM Cortex-M3 CPU subsystem

■ Nonvolatile subsystem

■ Programming, debug, and test subsystem

■ Inputs and outputs

■ Less than 0.5 mV offset

■ A gain error of 0.2%

■ Integral non linearity (INL) less than ±2 LSB

■ Differential non linearity (DNL) less than ±1 LSB

■ SINAD better than 84 dB in 16-bit mode

■ Clocking

■ Power

This converter addresses a wide variety of precision analog

applications including some of the most demanding sensors.

■ Digital subsystem

The CY8C55 family also offers up to two SAR ADCs. Featuring

12-bit conversions at up to 1 M samples per second, they also

offer low nonlinearity and offset errors and SNR better than

70 dB. They are well-suited for a variety of higher speed analog

applications.

■ Analog subsystem

PSoC’s digital subsystem provides half of its unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast, low

power UDBs. PSoC Creator provides a library of pre-built and

tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,

timer, counter, PWM, AND, OR, and so on) that are mapped to

the UDB array. The designer can also easily create a digital

circuit using boolean primitives by means of graphical design

entry. Each UDB contains programmable array logic

(PAL)/programmable logic device (PLD) functionality, together

with a small state machine engine to support a wide variety of

peripherals.

The output of any of the ADCs can optionally feed the

programmable DFB via DMA without CPU intervention. The

designer can configure the DFB to perform IIR and FIR digital

filters and several user defined custom functions. The DFB can

implement filters with up to 64 taps. It can perform a 48-bit

multiply-accumulate (MAC) operation in one clock cycle.

Four high-speed voltage or current DACs support 8-bit output

signals at an update rate of up to 8 Msps. They can be routed

out of any GPIO pin. You can create higher resolution voltage

DAC outputs using the UDB array. This can be used to create a

pulse width modulated (PWM) DAC of up to 10 bits, at up to

48 kHz. The digital DACs in each UDB support PWM, PRS, or

delta-sigma algorithms with programmable widths.

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C55 family, these blocks can include four 16-bit timers,

counters, and PWM blocks; I²C slave, master, and multimaster;

Full-Speed USB; and Full CAN 2.0b.

In addition to the ADCs, DACs, and DFB, the analog subsystem

provides multiple:

For more details on the peripherals see the “Example

Peripherals” section on page 32 of this data sheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 32 of this data sheet.

■ Comparators

■ Uncommitted opamps

■ Configurable switched capacitor/continuous time (SC/CT)

blocks. These support:

❐ Transimpedance amplifiers

❐ Programmable gain amplifiers

❐ Mixers

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 1% error over

temperature and voltage. The configurable analog subsystem

includes:

❐ Other similar analog components

■ Analog muxes

■ Comparators

■ Analog mixers

■ Voltage references

■ ADCs

See the “Analog Subsystem” section on page 44 of this data

sheet for more details.

PSoC’s CPU subsystem is built around a 32-bit three-stage

pipelined ARM Cortex-M3 processor running at up to 67 MHz.

The Cortex-M3 includes a tightly integrated nested vectored

interrupt controller (NVIC) and various debug and trace modules.

The overall CPU subsystem includes a DMA controller, flash

cache, and RAM. The NVIC provides low latency, nested

interrupts, and tail-chaining of interrupts and other features to

increase the efficiency of interrupt handling. The DMA controller

enables peripherals to exchange data without CPU involvement.

This allows the CPU to run slower (saving power) or use those

CPU cycles to improve the performance of firmware algorithms.

The flash cache also reduces system power consumption by

allowing less frequent flash access.

■ DACs

■ Digital filter block (DFB)

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals. One of the ADCs in the analog

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

PSoC’s nonvolatile subsystem consists of flash and

byte-writeable EEPROM. It provides up to 256 KB of on-chip

flash. The CPU can reprogram individual blocks of flash,

enabling boot loaders. A powerful and flexible protection model

secures the user's sensitive information, allowing selective

memory block locking for read and write protection. Two KB of

byte-writable EEPROM is available on-chip to store application

data.

The CY8C55 family supports a wide supply operating range from

1.71 to 5.5 V. This allows operation from regulated supplies such

as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly

from a wide range of battery types. In addition, it provides an

integrated high efficiency synchronous boost converter that can

power the device from supply voltages as low as 1.8 V. This

enables the device to be powered directly from a single battery

or solar cell. In addition, the designer can use the boost converter

to generate other voltages required by the device, such as a

3.3 V supply for LCD glass drive. The boost’s output is available

on the V_BOOSTpin, allowing other devices in the application to

be powered from the PSoC.

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the V_DDIOpins. Every GPIO

has analog I/O, LCD drive, flexible interrupt generation, slew rate

control, and digital I/O capability. The SIOs on PSoC allow V_OH

to be set independently of V_DDIOwhen used as outputs. When

SIOs are in input mode they are high impedance. This is true

even when the device is not powered or when the pin voltage

goes above the supply voltage. This makes the SIO ideally suited

for use on an I²C bus where the PSoC may not be powered when

other devices on the bus are. The SIO pins also have high

current sink capability for applications such as LED drives. The

programmable input threshold feature of the SIO can be used to

make the SIO function as a general purpose analog comparator.

For devices with FS USB, the USB physical interface is also

provided (USBIO). When not using USB, these pins may also be

used for limited digital functionality and device programming. All

the features of the PSoC I/Os are covered in detail in the “6.4 I/O

System and Routing” section on page 26 of this data sheet.

PSoC supports a wide range of low power modes. These include

a 300-nA hibernate mode with RAM retention and a 2-µA sleep

mode with RTC. In the second mode, the optional 32.768 kHz

watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 2 mA when the CPU is running at

6 MHz.

The details of the PSoC power modes are covered in the “6.2

Power System” section on page 21 of this data sheet.

PSoC uses a JTAG (4 wire) or SWD (2 wire) interface for

programming, debug, and test. Using these standard interfaces

enables the designer to debug or program the PSoC with a

variety of hardware solutions from Cypress or third party

vendors. The Cortex-M3 debug and trace modules include FPB,

DWT, ETM, and ITM. These modules have many features to help

solve difficult debug and trace problems. Details of the

programming, test, and debugging interfaces are discussed in

the “Programming, Debug Interfaces, Resources” section on

page 55 of this data sheet.

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The Internal Main Oscillator (IMO) is the master clock base for

the system, and has one-percent accuracy at 3 MHz. The IMO

can be configured to run from 3 MHz up to 62MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

system clock frequencies up to 67 MHz from the IMO, external

crystal, or external reference clock. It also contains a separate,

very low-power ILO for the sleep and watchdog timers. A

32.768 kHz external watch crystal is also supported for use in

RTC applications. The clocks, together with programmable clock

dividers, provide the flexibility to integrate most timing

requirements.

2. Pinouts

The V_DDIOpin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1 and

Figure 2-2. Using the V_DDIOpins, a single PSoC can support

multiple interface voltage levels, eliminating the need for off-chip

level shifters. Each V_DDIOmay sink up to 100 mA total to its

associated I/O pins and opamps. On the 68-pin and 100-pin

devices, each set of V_DDIOassociated pins may sink up to

100 mA. The 48 pin device may sink up to 100 mA total for all

Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all

Vddio1 plus Vddio3 associated I/O pins.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Figure 2-1. 68-pin QFN Part Pinout^[4]

(TRACEDATA[2], GPIO) P2[6]

(TRACEDATA[3], GPIO) P2[7]

(SIO) P12[4]

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

1

2

3

4

51

50

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

49

48

47

Lines show Vddio

to I/O supply

association

(SIO) P12[5]

Vssb

5

6

P12[3] (SIO)

P12[2] (SIO)

Vssd

Vdda

Vssa

Ind

46

45

Vboost

Vbat

7

8

9

44

43

QFN

(Top View)

Vssd

Vcca

10

42

41

XRES

(TMS, SWDIO) P1[0]

(TCK, SWDCK) P1[1]

(GPIO) P1[2]

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

11

12

13

40

39

P12[1] (SIO)

P12[0] (SIO)

(TDO, GPIO) P1[3] 14

38

37

36

35

(TDI, GPIO) P1[4]

(GPIO) P1[5]

Vddio1

15

16

17

P3[7] (GPIO, OpAmp3out)

P3[6] (GPIO, OpAmp1out)

Vddio3

Notes

3. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

4. The center pad on the QFN package should be connected to digital ground (V_SSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Figure 2-2. 100-pin TQFP Part Pinout

(TRACEDATA[1], GPIO) P2[5]

(TRACEDATA[2], GPIO) P2[6]

(TRACEDATA[3], GPIO) P2[7]

Vddio0

1

2

3

4

5

6

75

74

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

P0[1] (GPIO, OpAmp0out)

73

72

71

Lines show Vddio

to I/O supply

association

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

(GPIO) P6[4]

P0[0] (GPIO, OpAmp2out)

P4[1] (GPIO)

P4[0] (GPIO)

P12[3] (SIO)

P12[2] (SIO)

Vssd

70

69

(GPIO) P6[5]

(GPIO) P6[6]

(GPIO) P6[7]

7

8

9

68

67

66

65

10

Vssb

Ind

Vboost

Vbat

Vdda

Vssa

11

12

13

14

15

16

17

64

63

Vcca

NC

TQFP

Vssd

XRES

(GPIO) P5[0]

(GPIO) P5[1]

62

61

60

NC

59

58

57

56

55

(GPIO) P5[2]

(GPIO) P5[3]

(TMS, SWDIO, GPIO) P1[0]

18

19

20

21

22

NC

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

(TCK, SWDCK, GPIO) P1[1]

(configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, I2C1: SCL)

P3[7] (GPIO, OpAmp3out)

54

53

52

51

23

(TDI, GPIO) P1[4]

(nTRST, GPIO) P1[5]

24

25

P3[6] (GPIO, OpAmp1out)

Figure 2-3 and Figure 2-4 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal

analog performance on a two-layer board.

■ The two pins labeled V_DDDmust be connected together.

■ The two pins labeled V_CCDmust be connected together, with capacitance added, as shown in Figure 2-3 and 6.2 Power System on

page 21. The trace between the two V_CCDpins should be as short as possible.

■ The two pins labeled V_SSDmust be connected together.

For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board

Layout Considerations for PSoC® 3 and PSoC 5.

Note

5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-66235 Rev. **

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Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections

Vddd

C1

1 uF

C2

0.1 uF

Vddd

Vccd

C6

0.1 uF

Vssd

U2

CY8C55xx

Vssd

Vdda

Vddd

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P2[5]

P2[6]

P2[7]

P12[4], SIO

P12[5], SIO

P6[4]

P6[5]

P6[6]

P6[7]

Vssb

Ind

Vboost

Vbat

Vssd

XRES

P5[0]

P5[1]

P5[2]

P5[3]

P1[0], SWIO, TMS

P1[1], SWDIO, TCK

P1[2]

P1[3], SWV, TDO

P1[4], TDI

P1[5], nTRST

Vddio0

OA0-, REF0, P0[3]

C8

0.1 uF

C17

1 uF

OA0+, P0[2]

OA0out, P0[1]

OA2out, P0[0]

P4[1]

Vssd

P4[0]

Vssa

Vdda

SIO, P12[3]

SIO, P12[2]

Vssd

Vdda

Vssa

Vcca

Vdda

Vssa

Vcca

NC

Vssd

C9

1 uF

C10

0.1 uF

NC

Vssa

kHzXin, P15[3]

kHzXout, P15[2]

SIO, P12[1]

SIO, P12[0]

OA3out, P3[7]

OA1out, P3[6]

Vddd

C11

0.1 uF

C12

0.1 uF

C13

10 uF, 6.3 V 0.1 uF Vssd

C14

C15

1 uF

Vssd

C16

0.1 uF

Vssa

Vssd

Note The two V_CCDpins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-4.

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PSoC^®5: CY8C55 Family Datasheet

Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance

Vssa

Vssd

Vdda

Vddd

Vssa

Plane

Vssd

Plane

TCK. JTAG Test Clock programming and debug port connection.

3. Pin Descriptions

TDI. JTAG Test Data In programming and debug port

connection.

IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for

high-current DACs (IDAC).

TDO. JTAG Test Data Out programming and debug port

connection.

OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High

current output of uncommitted opamp.^[6]

TMS. JTAG Test Mode Select programming and debug port

connection.

Extref0, Extref1. External reference input to the analog system.

OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to

uncommitted opamp.

TRACECLK. Cortex-M3 TRACEPORT connection, clocks

TRACEDATA pins.

OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting

input to uncommitted opamp.

TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,

output data.

GPIO. Provides interfaces to the CPU, digital peripherals,

analog peripherals, interrupts, LCD segment drive, and

CapSense.^[6]

SWV. SWV output.

USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.

May be used as a digital I/O pin; it is powered from V_DDDinstead

of from a V_DDIO. Pins are Do Not Use (DNU) on devices without

USB.

Ind. Inductor connection to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi. 32.768 KHz crystal oscillator pin.

USBIO, D-. Provides D- connection directly to a USB 2.0 bus.

May be used as a digital I/O pin; it is powered from V_DDDinstead

of from a V_DDIO. Pins are Do Not Use (DNU) on devices without

USB.

MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator

pin. If a crystal is not used, then Xi must be shorted to ground

and Xo must be left floating.

nTRST. Optional JTAG Test Reset programming and debug port

connection to reset the JTAG connection.

V

_BOOST. Power sense connection to boost pump.

_BAT. Battery supply to boost pump.

SIO. Provides interfaces to the CPU, digital peripherals and

interrupts with a programmable high threshold voltage, analog

comparator, high sink current, and high impedance state when

the device is unpowered.

V

V_CCA. Output of analog core regulator and input to analog core.

Requires a 1 µF capacitor to V_SSA. Regulator output not for

external use.

SWDCK. SWD Clock programming and debug port connection.

V_CCD. Output of digital core regulator and input to digital core.

SWDIO. SWD Input and Output programming and debug port

connection.

The two V_CCDpins must be shorted together, with the trace

between them as short as possible, and a 1 µF capacitor to V_SSD

;

Notes

6. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

see 6.2 Power System on page 21. Regulator output not for

external use.

and must be less than or equal to V_DDA. If the I/O pins associated

with V_DDIO0, V_DDIO2or V_DDIO3are not used then that V_DDIO

should be tied to ground (V_SSDor V_SSA).

V_DDA. Supply for all analog peripherals and analog core

regulator. V_DDAmust be the highest voltage present on the

device. All other supply pins must be less than or equal to

XRES. External reset pin. Active low with internal pull-up.

V_DDA

.

4. CPU

V_DDD. Supply for all digital peripherals and digital core regulator.

V

_DDDmust be less than or equal to V_DDA

.

4.1 ARM Cortex-M3 CPU

V_SSA. Ground for all analog peripherals.

The CY8C55 family of devices has an ARM Cortex-M3 CPU

core. The Cortex-M3 is a low-power 32-bit three-stage pipelined

Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is

intended for deeply embedded applications that require fast

interrupt handling features.

V_SSB. Ground connection for boost pump.

V_SSD. Ground for all digital logic and I/O pins.

V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3. Supply for I/O pins. Each

V_DDIOmust be tied to a valid operating voltage (1.71 V to 5.5 V),

Figure 4-1. ARM Cortex-M3 Block Diagram

Data

Watchpoint and

Trace (DWT)

Nested

Interrupt Inputs

Cortex M3 CPU Core

Vectored

Interrupt

Controller

(NVIC)

Embedded

Trace Module

(ETM)

Instrumentation

Trace Module

(ITM)

D-Bus

C-Bus

I-Bus

S-Bus

Trace Pins:

5 for TRACEPORT or

1 for SWV mode

Debug Block

(JTAG and

SWD)

Trace Port

Interface Unit

(TPIU)

JTAG, SWD

Flash Patch

and Breakpoint

(FPB)

Cortex M3 Wrapper

AHB

32 KB

SRAM

Bus

Matrix

Bus

Matrix

256 KB

Flash

Cache

AHB

32 KB

SRAM

Bus

Matrix

AHB Bridge & Bus Matrix

DMA

PHUB

AHB Spokes

Prog.

Digital

Prog.

Analog

Special

Functions

GPIO

Peripherals

The Cortex-M3 CPU subsystem includes these features:

■ ARM Cortex-M3 CPU

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PSoC^®5: CY8C55 Family Datasheet

■ Programmable nested vectored interrupt controller (NVIC),

tightly integrated with the CPU core

The processor runs in the handler mode (always at the privileged

level) when handling an exception, and in the thread mode when

not.

■ Full featured debug and trace module, tightly integrated with

the CPU core

4.1.3 CPU Registers

■ Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB

of SRAM

The Cortex-M3 CPU registers are listed in Table 4-2. Registers

R0-R15 are all 32 bits wide.

Table 4-2. Cortex M3 CPU Registers

■ Cache controller

Register

R0-R12

Description

■ Peripheral HUB (PHUB)

■ DMA controller

General purpose registers R0-R12 have no

special architecturally defined uses. Most

instructions that specify a general purpose

register specify R0-R12.

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:

■ Lowregisters:RegistersR0-R7areaccessible

by all instructions that specify a general

purpose register.

■ 4 GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.

■ High registers: Registers R8-R12 are

accessiblebyall32-bitinstructionsthatspecify

a general purpose register; they are not

accessible by all 16-bit instructions.

®

■ The Thumb -2 instruction set, which offers ARM-level

performance at Thumb-level code density. This includes 16-bit

and 32-bit instructions. Advanced instructions include:

❐ Bit-field control

❐ Hardware multiply and divide

❐ Saturation

R13

R13 is the stack pointer register. It is a banked

register that switches between two 32-bit stack

pointers: the main stack pointer (MSP) and the

process stack pointer (PSP). The PSP is used

only when the CPU operates at the user level in

thread mode. The MSP is used in all other

privilege levels and modes. Bits[0:1] of the SP

are ignored and considered to be 0, so the SP is

always aligned to a word (4 byte) boundary.

❐ If-Then

❐ Wait for events and interrupts

❐ Exclusive access and barrier

❐ Special register access

The Cortex-M3 does not support ARM instructions.

■ Bit-band support. Atomic bit-level write and read operations.

R14

R15

R14 is the link register (LR). The LR stores the

return address when a subroutine is called.

■ Unaligned data storage and access. Contiguous storage of

data of different byte lengths.

R15 is the program counter (PC). Bit 0 of the PC

is ignoredand consideredto be0, so instructions

are always aligned to a half word (2 byte)

boundary.

■ Operation at two privilege levels (privileged and user) and in

two modes (thread and handler). Some instructions can only

be executed at the privileged level. There are also two stack

pointers: Main (MSP) and Process (PSP). These features

support a multitasking operating system running one or more

user-level processes.

xPSR

The program status registers are divided into

three status registers, which are accessed either

together or separately:

■ Application program status register (APSR)

holds program execution status bits such as

zero, carry, negative, in bits[27:31].

■ Extensive interrupt and system exception support.

4.1.2 Cortex-M3 Operating Modes

The Cortex-M3 operates at either the privileged level or the user

level, and in either the thread mode or the handler mode.

Because the handler mode is only enabled at the privileged level,

there are actually only three states, as shown in Table 4-1.

■ Interrupt program status register (IPSR) holds

the current exception number in bits[0:8].

■ Execution program status register (EPSR)

holds control bits for interrupt continuable and

IF-THEN instructions in bits[10:15] and

[25:26]. Bit 24 is always set to 1 to indicate

Thumb mode. Trying to clear it causes a fault

exception.

Table 4-1. Operational Level

Condition

Privileged

User

Running an exception Handler mode Not used

Running main program Thread mode

Thread mode

PRIMASK

A 1-bit interrupt mask register. When set, it

allows only the nonmaskable interrupt (NMI) and

hard fault exception. All other exceptions and

interrupts are masked.

At the user level, access to certain instructions, special registers,

configuration registers, and debugging components is blocked.

Attempts to access them cause a fault exception. At the

privileged level, access to all instructions and registers is

allowed.

FAULTMASK A 1-bit interrupt mask register. When set, it

allows only the NMI. All other exceptions and

interrupts are masked.

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Table 4-2. Cortex M3 CPU Registers (continued)

Table 4-3. PHUB Spokes and Peripherals

Register

Description

PHUB Spokes

Peripherals

BASEPRI

A register of up to nine bits that define the

masking priority level. When set, it disables all

interrupts of the same or higher priority value. If

set to 0 then the masking function is disabled.

0

1

2

SRAM

IOs, PICU

PHUB local configuration, Power manager,

Clocks, IC, EEPROM, Flash programming

interface

CONTROL

A 2-bit register for controlling the operating

mode.

Bit 0: 0 = privileged level in thread mode,

1 = user level in thread mode.

3

4

5

6

7

Analog interface and trim, Decimator

2

Bit 1: 0 = default stack (MSP) is used,

USB, CAN, I C, Timers, Counters, and PWMs

1 = alternate stack is used. If in thread mode or

user level then the alternate stack is the PSP.

There is no alternate stack for handler mode; the

bit must be 0 while in handler mode.

DFB

UDBs group 1

UDBs group 2

4.3.2 DMA Features

4.2 Cache Controller

The CY8C55 family has a 1 KB instruction cache between the

CPU and the flash memory. This improves instruction execution

rate and reduces system power consumption by requiring less

frequent flash access.

■ 24 DMA channels

■ Each channel has one or more transaction descriptors (TDs)

to configure channel behavior. Up to 127 total TDs can be

defined

4.3 DMA and PHUB

■ TDs can be dynamically updated

■ Eight levels of priority per channel

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

■ Anydigitallyroutablesignal, theCPU, oranotherDMAchannel,

can trigger a transaction

■ A central hub that includes the DMA controller, arbiter, and

router

■ Each channel can generate up to two interrupts per transfer

■ Transactions can be stalled or canceled

■ Multiple spokes that radiate outward from the hub to most

peripherals

■ Supports transaction size of infinite or 1 to 64k bytes

■ Large transactions may be broken into smaller bursts of 1 to

127 bytes

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

■ TDs may be nested and/or chained for complex transactions

4.3.3 Priority Levels

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100% of the bus bandwidth. If a tie occurs

on two DMA requests of the same priority level, a simple round

robin method is used to evenly share the allocated bandwidth.

The round robin allocation can be disabled for each DMA

channel, allowing it to always be at the head of the line. Priority

levels 2 to 7 are guaranteed the minimum bus bandwidth shown

in Table 4-4 after the CPU and DMA priority levels 0 and 1 have

satisfied their requirements.

4.3.1 PHUB Features

■ CPU and DMA controller are both bus masters to the PHUB

■ Eight Multi-layer AHB Bus parallel access paths (spokes) for

peripheral access

■ Simultaneous CPU and DMA access to peripherals located on

different spokes

■ Simultaneous DMA source and destination burst transactions

on different spokes

■ Supports 8-, 16-, 24-, and 32-bit addressing and data

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

Document Number: 001-66235 Rev. **

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Table 4-4. Priority Levels

4.3.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

Priority Level

% Bus Bandwidth

0

1

2

3

4

5

6

7

100.0

50.0

25.0

12.5

6.2

4.3.4.1 Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles are shown in

Figure 4-5. For more description on other transfer modes, refer

to the Technical Reference Manual.

3.1

1.5

Figure 4-5. DMA Timing Diagram

ADDRESS Phase

DATA Phase

ADDRESS Phase

DATA Phase

CLK

ADDR 16/32

WRITE

ADDR 16/32

A

B

A

B

WRITE

DATA

DATA (A)

DATA

READY

Basic DMA Read Transfer without wait states

Basic DMA Write Transfer without wait states

4.3.4.2 Auto Repeat DMA

4.3.4.6 Scatter Gather DMA

Auto repeat DMA is typically used when a static pattern is

repetitively read from system memory and written to a peripheral.

This is done with a single TD that chains to itself.

In the case of scatter gather DMA, there are multiple

noncontiguous sources or destinations that are required to

effectively carry out an overall DMA transaction. For example, a

packet may need to be transmitted off of the device and the

packet elements, including the header, payload, and trailer, exist

in various noncontiguous locations in memory. Scatter gather

DMA allows the segments to be concatenated together by using

multiple TDs in a chain. The chain gathers the data from the

multiple locations. A similar concept applies for the reception of

data onto the device. Certain parts of the received data may need

to be scattered to various locations in memory for software

processing convenience. Each TD in the chain specifies the

location for each discrete element in the chain.

4.3.4.3 Ping Pong DMA

A ping pong DMA case uses double buffering to allow one buffer

to be filled by one client while another client is consuming the

data previously received in the other buffer. In its simplest form,

this is done by chaining two TDs together so that each TD calls

the opposite TD when complete.

4.3.4.4 Circular DMA

Circular DMA is similar to ping pong DMA except it contains more

than two buffers. In this case there are multiple TDs; after the last

TD is complete it chains back to the first TD.

4.3.4.7 Packet Queuing DMA

Packet queuing DMA is similar to scatter gather DMA but

specifically refers to packet protocols. With these protocols,

there may be separate configuration, data, and status phases

associated with sending or receiving a packet.

4.3.4.5 Indexed DMA

In an indexed DMA case, an external master requires access to

locations on the system bus as if those locations were shared

memory. As an example, a peripheral may be configured as an

2

For instance, to transmit a packet, a memory mapped

SPI or I C slave where an address is received by the external

configuration register can be written inside a peripheral,

specifying the overall length of the ensuing data phase. The CPU

can set up this configuration information anywhere in system

memory and copy it with a simple TD to the peripheral. After the

configuration phase, a data phase TD (or a series of data phase

TDs) can begin (potentially using scatter gather). When the data

phase TD(s) finish, a status phase TD can be invoked that reads

some memory mapped status information from the peripheral

and copies it to a location in system memory specified by the

CPU for later inspection. Multiple sets of configuration, data, and

master. That address becomes an index or offset into the internal

system bus memory space. This is accomplished with an initial

“address fetch” TD that reads the target address location from

the peripheral and writes that value into a subsequent TD in the

chain. This modifies the TD chain on the fly. When the “address

fetch” TD completes it moves on to the next TD, which has the

new address information embedded in it. This TD then carries

out the data transfer with the address location required by the

external master.

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PSoC^®5: CY8C55 Family Datasheet

status phase “subchains” can be strung together to create larger

chains that transmit multiple packets in this way. A similar

concept exists in the opposite direction to receive the packets.

second TD. The second TD moves data as required by the

application. When complete, the second TD calls the first TD,

which again updates the second TD’s configuration. This

process repeats as often as necessary.

4.3.4.8 Nested DMA

One TD may modify another TD, as the TD configuration space

is memory mapped similar to any other peripheral. For example,

a first TD loads a second TD’s configuration and then calls the

4.4 Interrupt Controller

The Cortex-M3 NVIC supports 16 system exceptions and 32

interrupts from peripherals, as shown in Table 4-6.

Table 4-6. Cortex-M3 Exceptions and Interrupts

Exception

Number

Exception Table

Address Offset

Exception Type

Priority

Function

0x00

0x04

0x08

0x0C

Starting value of R13 / MSP

Reset

1

2

3

Reset

-3 (highest)

NMI

-2

-1

Non maskable interrupt

Hard fault

All classesoffault, whenthe correspondingfaulthandler

cannot be activated because it is currently disabled or

masked

4

5

6

MemManage

Bus fault

Programmable

0x10

0x14

0x18

Memory management fault, for example, instruction

fetch from a nonexecutable region

Error response received from the bus system; caused

by an instruction prefetch abort or data access error

Usage fault

Typically caused by invalid instructions or trying to

switch to ARM mode

7 – 10

11

-

0x1C – 0x28

0x2C

Reserved

SVC

Programmable

-

System service call via SVC instruction

Debug monitor

12

Debug monitor

-

0x30

13

0x34

Reserved

14

PendSV

SYSTICK

IRQ

Programmable

0x38

Deferred request for system service

System tick timer

15

0x3C

16 – 47

0x40 – 0x3FC

Peripheral interrupt request #0 - #31

Bit 0 of each exception vector indicates whether the exception is

executed using ARM or Thumb instructions. Because the

Cortex-M3 only supports Thumb instructions, this bit must

always be 1. The Cortex-M3 non maskable interrupt (NMI) input

can be routed to any pin, via the DSI, or disconnected from all

pins. See “DSI Routing Interface Description” section on

page 39.

■ Support for tail-chaining, and late arrival, of interrupts. This

enables back-to-back interrupt processing without the

overhead of state saving and restoration between interrupts.

■ Processor state automatically saved on interrupt entry, and

restored on interrupt exit, with no instruction overhead.

If the same priority level is assigned to two or more interrupts,

the interrupt with the lower vector number is executed first. Each

interrupt vector may choose from three interrupt sources: Fixed

Function, DMA, and UDB. The fixed function interrupts are direct

connections to the most common interrupt sources and provide

the lowest resource cost connection. The DMA interrupt sources

provide direct connections to the two DMA interrupt sources

provided per DMA channel. The third interrupt source for vectors

is from the UDB digital routing array. This allows any digital signal

available to the UDB array to be used as an interrupt source. All

interrupt sources may be routed to any interrupt vector using the

UDB interrupt source connections.

The Nested Vectored Interrupt Controller (NVIC) handles

interrupts from the peripherals, and passes the interrupt vectors

to the CPU. It is closely integrated with the CPU for low latency

interrupt handling. Features include:

■ 32 interrupts. Multiple sources for each interrupt.

■ Configurable number of priority levels: from 3 to 8.

■ Dynamic reprioritization of interrupts.

■ Priority grouping. This allows selection of preempting and non

preempting interrupt levels.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Table 4-7. Interrupt Vector Table

Interrupt # Cortex-M3 Exception #

Fixed Function

Low voltage detect (LVD)

Cache

DMA

phub_termout0[0]

phub_termout0[1]

phub_termout0[2]

phub_termout0[3]

phub_termout0[4]

phub_termout0[5]

phub_termout0[6]

phub_termout0[7]

phub_termout0[8]

phub_termout0[9]

phub_termout0[10]

phub_termout0[11]

phub_termout0[12]

phub_termout0[13]

phub_termout0[14]

phub_termout0[15]

phub_termout1[0]

phub_termout1[1]

phub_termout1[2]

phub_termout1[3]

phub_termout1[4]

phub_termout1[5]

phub_termout1[6]

phub_termout1[7]

phub_termout1[8]

phub_termout1[9]

phub_termout1[10]

phub_termout1[11]

phub_termout1[12]

phub_termout1[13]

phub_termout1[14]

phub_termout1[15]

UDB

udb_intr[0]

0

1

2

3

4

5

6

7

8

9

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

udb_intr[1]

udb_intr[2]

udb_intr[3]

udb_intr[4]

udb_intr[5]

udb_intr[6]

udb_intr[7]

udb_intr[8]

udb_intr[9]

udb_intr[10]

udb_intr[11]

udb_intr[12]

udb_intr[13]

udb_intr[14]

udb_intr[15]

udb_intr[16]

udb_intr[17]

udb_intr[18]

udb_intr[19]

udb_intr[20]

udb_intr[21]

udb_intr[22]

udb_intr[23]

udb_intr[24]

udb_intr[25]

udb_intr[26]

udb_intr[27]

udb_intr[28]

udb_intr[29]

udb_intr[30]

udb_intr[31]

Reserved

Sleep (Pwr Mgr)

PICU[0]

PICU[1]

PICU[2]

PICU[3]

PICU[4]

PICU[5]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

PICU[6]

PICU[12]

PICU[15]

Comparators Combined

Switched Caps Combined

2

I C

CAN

Timer/Counter0

Timer/Counter1

Timer/Counter2

Timer/Counter3

USB SOF Int

USB Arb Int

USB Bus Int

USB Endpoint[0]

USB Endpoint Data

Reserved

DFB Int

Decimator Int

phub_err_int

eeprom_fault_int

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

how to take full advantage of the security features in PSoC, see

the PSoC 5 TRM.

5. Memory

5.1 Static RAM

Table 5-1. Flash Protection

Protection

CY8C55 static RAM (SRAM) is used for temporary data storage.

Code can be executed at full speed from the portion of SRAM

that is located in the code space. This process is slower from

SRAM above 0x20000000. The device provides up to 64 KB of

SRAM. The CPU or the DMA controller can access all of SRAM.

The SRAM can be accessed simultaneously by the Cortex-M3

CPU and the DMA controller if accessing different 32-KB blocks.

Allowed

Not Allowed

Setting

Unprotected

External read and write

+ internal read and write

–

Factory

Upgrade

External write + internal External read

read and write

5.2 Flash Program Memory

Field Upgrade Internal read and write External read and

write

Flash memory in PSoC devices provides nonvolatile storage for

user firmware, user configuration data and bulk data storage.

The main flash memory area contains up to 256 KB of user

program space.

Full Protection Internal read

External read and

write + internal write

Up to an additional 32 KB of flash space is available for storing

device configuration data and bulk user data. User code may not

be run out of this flash memory section. The flash output is 9

bytes wide with 8 bytes of data and 1 additional byte.

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress datasheets. Cypress believes that its family of

products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

The CPU or DMA controller read both user code and bulk data

located in flash through the cache controller. This provides

higher CPU performance. Flash programming is performed

through a special interface and preempts code execution out of

flash. Code execution out of cache may continue during flash

programming as long as that code is contained inside the cache.

The flash programming interface performs flash erasing,

programming and setting code protection levels. Flash In

System Serial Programming (ISSP), typically used forproduction

programming, is possible through the JTAG and SWD interfaces.

In-system programming, typically used for bootloaders, is also

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

2

possible using serial interfaces such as I C, USB, UART, and

SPI, or any communications protocol.

5.3 Flash Security

5.4 EEPROM

All PSoC devices include a flexible flash protection model that

prevents access and visibility to on-chip flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of configuration or

general-purpose data.

PSoC EEPROM memory is a byte addressable nonvolatile

memory. The CY8C55 has 2 KB of EEPROM memory to store

user data. Reads from EEPROM are random access at the byte

level. Reads are done directly; writes are done by sending write

commands to an EEPROM programming interface. CPU code

execution can continue from flash during EEPROM writes.

EEPROM is erasable and writeable at the row level. The

EEPROM is divided into two sections, each containing 64 rows

of 16 bytes each.

The device offers the ability to assign one of four protection

levels to each row of flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a boot loader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security which

permanently disables all test, programming, and debug ports,

protecting your application from external access (see the

“Device Security” section on page 56). For more information on

The CPU cannot execute out of EEPROM.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Table 5-3. Peripheral Data Address Map (continued)

Address Range Purpose

5.5 Memory Map

The Cortex-M3 has a fixed address map, which allows

peripherals to be accessed by simple memory access

instructions.

2

0x40004900 – 0x400049FF I C controller

0x40004E00 – 0x40004EFF Decimator

5.5.1 Address Map

0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs

0x40005000 – 0x400051FF I/O ports control

0x40005800 – 0x40005FFF Analog Subsystem Interface

0x40006000 – 0x400060FF USB Controller

0x40006400 – 0x40006FFF UDB Configuration

0x40007000 – 0x40007FFF PHUB Configuration

0x40008000 – 0x400087FF EEPROM

The 4-GB address space is divided into the ranges shown in

Table 5-2:

Table 5-2. Address Map

Address Range

Size

Use

0x00000000 –

0x1FFFFFFF

0.5 GB

Program code. This includes the

exception vector table at power

up, which starts at address 0.

0x20000000 –

0x3FFFFFFF

0.5 GB

Static RAM. This includes a 1

MByte bit-band region starting at

0x20000000 and a 32 Mbyte

bit-band alias region starting at

0x22000000.

0x4000A000 – 0x4000A400 CAN

0x4000C000 – 0x4000C800 Digital Filter Block

0x40010000 – 0x4001FFFF Digital Interconnect Configuration

0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,

including NVIC, debug, and trace

0x40000000 –

0x5FFFFFFF

Peripherals. This includes a

1 MByte bit-band region starting

at 0x40000000 and a 32 Mbyte

bit-band alias region starting at

0x42000000.

The bit-band feature allows individual bits in words in the

bit-band region to be read or written as atomic operations. This

is done by reading or writing bit 0 of corresponding words in the

bit-band alias region. For example, to set bit 3 in the word at

address 0x20000000, write a 1 to address 0x2200000C. To test

the value of that bit, read address 0x2200000C and the result is

either 0 or 1 depending on the value of the bit.

0x60000000 –

0x9FFFFFFF

1 GB

External RAM.

0xA0000000 –

0xDFFFFFFF

1 GB

External peripherals.

0xE0000000 –

0xFFFFFFFF

0.5 GB

Internalperipherals,includingthe

NVIC and debug and trace

modules.

Most memory accesses done by the Cortex-M3 are aligned, that

is, done on word (4-byte) boundary addresses. Unaligned

accesses of words and 16-bit half-words on nonword boundary

addresses can also be done, although they are less efficient.

Table 5-3. Peripheral Data Address Map

Address Range

Purpose

5.5.2 Address Map and Cortex-M3 Buses

0x00000000 – 0x0003FFFF 256 KB flash

The ICode and DCode buses are used only for accesses within

the Code address range, 0 - 0x1FFFFFFF.

0x1FFF8000 – 0x1FFFFFFF 32 KB SRAM in Code region

0x20000000 – 0x20007FFF 32 KB SRAM in SRAM region

0x40004000 – 0x400042FF Clocking, PLLs, and oscillators

0x40004300 – 0x400043FF Power management

0x40004500 – 0x400045FF Ports interrupt control

0x40004700 – 0x400047FF Flash programming interface

0x40004800 – 0x400048FF Cache controller

The System bus is used for data accesses and debug accesses

within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000

- 0xFFFFFFFF. Instruction fetches can also be done within the

range 0x20000000 - 0x3FFFFFFF, although these can be slower

than instruction fetches via the ICode bus.

The private peripheral bus (PPB) is used within the Cortex-M3 to

access system control registers and debug and trace module

registers.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Key features of the clocking system include:

6. System Integration

■ Seven general purpose clock sources

❐ 3 to 62 MHz IMO, ±4% at 3 MHz

❐ 4- to 25 MHz external crystal oscillator (MHzECO)

❐ Clock doubler provides a doubled clock frequency output for

the USB block, see USB Clock Domain on page 21.

❐ DSI signal from an external I/O pin or other logic

❐ 24 to 67 MHz fractional phase-locked loop (PLL) sourced

from IMO, MHzECO, or DSI

6.1 Clocking System

The clocking system generates, divides, and distributes clocks

throughout the PSoC system. For the majority of systems, no

external crystal is required. The IMO and PLL together can

generate up to a 67 MHz clock, accurate to ±4% over voltage and

temperature. Additional internal and external clock sources allow

each design to optimize accuracy, power, and cost. All of the

system clock sources can be used to generate other clock

frequencies in the 16-bit clock dividers and UDBs for anything

you want, for example a UART baud rate generator.

❐ Clock Doubler

❐ 1 KHz, 33 KHz, 100 KHz ILO for watchdog timer (WDT) and

Sleep Timer

Clock generation and distribution is automatically configured

through the PSoC Creator IDE graphical interface. This is based

on the complete system’s requirements. It greatly speeds the

design process. PSoC Creator allows designers to build clocking

systems with minimal input. The designer can specify desired

clock frequencies and accuracies, and the software locates or

builds a clock that meets the required specifications. This is

possible because of the programmability inherent PSoC.

❐ 32.768 KHz external crystal oscillator (ECO) for RTC

■ Independently sourced clock dividers in all clocks

■ Eight 16-bit clock dividers for the digital system

■ Four 16-bit clock dividers for the analog system

■ Dedicated 16-bit divider for the CPU bus and CPU clock

■ Automatic clock configuration in PSoC Creator

Document Number: 001-66235 Rev. **

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Table 6-1. Oscillator Summary

Source

IMO

Fmin

3 MHz

4 MHz

Tolerance at Fmin

Fmax

62 MHz

25 MHz

Tolerance at Fmax

±10%

Startup Time

10 µs max

±4% over voltage and temperature

Crystal dependent

MHzECO

Crystal dependent

5 ms typ, max is

crystal dependent

DSI

PLL

0 MHz

Input dependent

66 MHz

67 MHz

48 MHz

100 kHz

Input dependent

–55%, +100%

Input dependent

250 µs max

1 µs max

24 MHz Input dependent

12 MHz Input dependent

Doubler

ILO

1 kHz

–50%, +100%

15 ms max in lowest

power mode

kHzECO

32 kHz

Crystal dependent

32 kHz

Crystal dependent

500 ms typ, max is

crystal dependent

Figure 6-1. Clocking Subsystem

External IO

or DSI

0-40 MHz

3-24 MHz

IMO

4-25 MHz

ECO

1,33,100 kHz

ILO

32 kHz ECO

12-48 MHz

Doubler

CPU

Clock

24-40 MHz

PLL

System

Clock Mux

Bus

Clock

Bus Clock Divider

16 bit

s

k

e

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

w

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

7

s

k

e

w

7

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

s

k

e

w

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

6.1.1 Internal Oscillators

6.1.1.1 Internal Main Oscillator

6.1.1.2 Clock Doubler

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler works for input frequency ranges of 6 to

24 MHz (providing 12 to 48 MHz at the output). It can be

configured to use a clock from the IMO, MHzECO, or the DSI

(external pin). The doubler is typically used to clock the USB.

In most designs the IMO is the only clock source required, due

to its ±4% accuracy. The IMO operates with no external

components and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±4% at 3 MHz, up to ±10% at 62 MHz. The

IMO, in conjunction with the PLL, allows generation of CPU and

system clocks up to the device's maximum frequency (see USB

Clock Domain on page 21). The IMO provides clock outputs at

3, 6, 12, 24, 48, and 62 MHz.

6.1.1.3 Phase-Locked Loop

The PLL allows low frequency, high accuracy clocks to be

multiplied to higher frequencies. This is a tradeoff between

higher clock frequency and accuracy and, higher power

consumption and increased startup time.

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The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 67 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The accuracy of the

PLL output depends on the accuracy of the PLL input source.

The most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate, to generate the CPU and system

clocks up to the device’s maximum frequency.

used then Xi must be shorted to ground and Xo must be left

floating. MHzECO accuracy depends on the crystal chosen.

Figure 6-2. MHzECO Block Diagram

XCLK_MHZ

4- 25 MHz

Crystal Osc

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO, or DSI (external pin). The PLL clock source can be

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low power modes.

Xo

Xi

6.1.1.4 Internal Low-Speed Oscillator

4– 25 MHz

crystal

The ILO provides clock frequencies for low power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

External

Components

Capacitors

The 1 KHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW). The central

timewheel is a 1 kHz, free running, 13-bit counter clocked by the

ILO. The central timewheel is always enabled except in

hibernate mode and when the CPU is stopped during debug on

chip mode. It can be used to generate periodic interrupts for

timing purposes or to wake the system from a low power mode.

Firmware can reset the central timewheel.

6.1.2.2 32.768 kHz ECO

The 32.768 KHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768 KHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1 second interrupt to

implement the RTC functionality in firmware. The oscillator works

in two distinct power modes. This allows users to trade off power

consumption with noise immunity from neighboring circuits. The

GPIO pins connected to the external crystal and capacitors are

fixed.

The central timewheel can be programmed to wake the system

periodically and optionally issue an interrupt. This enables

flexible, periodic wakeups from low power modes or coarse

timing applications. Systems that require accurate timing should

use the RTC capability instead of the central timewheel.

Figure 6-3. 32kHzECO Block Diagram

The 100 KHz clock (CLK100K) works as a low power system

clock to run the CPU. It can also generate time intervals such as

fast sleep intervals using the fast timewheel.

XCLK32K

32 kHz

The fast timewheel is a 100 KHz, 5-bit counter clocked by the

ILO that can also be used to wake the system. The fast

timewheel settings are programmable, and the counter

automatically resets when the terminal count is reached. This

enables flexible, periodic wakeups of the CPU at a higher rate

than is allowed using the central timewheel. The fast timewheel

can generate an optional interrupt each time the terminal count

is reached.

Crystal Osc

Xo

Xi

(Pin P15[2])

(Pin P15[3])

The 33 KHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768 KHz ECO clock with no need for a crystal.

32 kHz

crystal

External

Components

Capacitors

6.1.2 Internal Oscillators

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see

6.1.2.3 Digital System Interconnect

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and UDBs.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

Phase-Locked Loop on page 19). The GPIO pins connecting to

the external crystal and capacitors are fixed. If a crystal is not

Document Number: 001-66235 Rev. **

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generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48 MHz frequency. This frequency can be generated

from different sources, including DSI clock at 48 MHz or doubled

value of 24 MHz from internal oscillator, DSI signal, or crystal

oscillator.

6.1.3 Clock Distribution

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.

6.2 Power System

The power system consists of separate analog, digital, and I/O

supply pins, labeled V

, V

, and V

, respectively. It

■ The system clock is used to select and supply the fastest clock

in the system for general system clock requirements and clock

synchronization of the PSoC device.

DDA

DDD

DDIOX

also includes two internal 1.8 V regulators that provide the digital

(V ) and analog (V ) supplies for the internal core logic.

CCD

CCA

The output pins of the regulators (V

and V

) and the V

CCD

CCA DDIO

■ Bus clock 16-bit divider uses the system clock to generate the

system’s bus clock used for data transfers and the CPU. The

CPU clock is directly derived from the bus clock.

pins must have capacitors connected as shown in Figure 6-4.

The two V pins must be shorted together, with as short a

CCD

trace as possible, and connected to a 1 µF ±10% X5R capacitor.

The power system also contains a sleep regulator and a

hibernate regulator.

■ Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, theUDBsandfixedfunctiontimer/counter/PWMscan

also generate clocks.

■ Four16-bitclockdividersgenerateclocksfortheanalogsystem

components that require clocking, such as ADCs and mixers.

The analog clock dividers include skew control to ensure that

critical analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50% duty

cycle clocks, system clock resynchronization logic, and deglitch

logic. The outputs from each digital clock tree can be routed into

the digital system interconnect and then brought back into the

clock system as an input, allowing clock chaining of up to 32 bits.

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Figure 6-4. PSoC Power System

µF

Vddd

1

Vddio2

Vddio0

0.1 µF

I/O Supply

Vddio0

0.1 µF

I2C

Regulator

Sleep

Regulator

Digital

Vdda

Domain

Vdda

Vcca

Analog

Regulator

0.1 µF

Digital

Regulators

Vssd

.

µF

1

Vssa

Analog

Domain

Hibernate

Regulator

I/O Supply

0.1µF

0.1 µF

Vddd

Vddio1

Vddio3

Note The two V

pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

CCD

shown in Figure 2-4.

6.2.1 Power Modes

Active is the main processing mode. Its functionality is

configurable. Each power controllable subsystem is enabled or

PSoC 5 devices have four different power modes, as shown in

Table 6-2 and Table 6-3. The power modes allow a design to

easily provide required functionality and processing power while

simultaneously minimizing power consumption and maximizing

battery life in low power and portable devices.

disabled by using separate power configuration template

registers. In alternate active mode, fewer subsystems are

enabled, reducing power. In sleep mode most resources are

disabled regardless of the template settings. Sleep mode is

optimized to provide timed sleep intervals and RTC functionality.

The lowest power mode is hibernate, which retains register and

SRAM state, but no clocks, and allows wakeup only from I/O

pins. Figure 6-5 illustrates the allowable transitions between

power modes.

PSoC 5 power modes, in order of decreasing power

consumption are:

■ Active

■ Alternate active

■ Sleep

■ Hibernate

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Table 6-2. Power Modes

Power Modes

Description

EntryCondition WakeupSource Active Clocks

Regulator

Active

Primary mode of operation, all Wakeup, reset, Any interrupt

peripherals available (program- manual register

Any (program-

mable)

All regulators available.

Digital and analog

mable)

entry

regulators can be disabled

if external regulation used.

Alternate

Active

Similar to Active mode, and is

typically configured to have

fewer peripherals active to

reduce power. One possible

configuration is to use the UDBs

for processing, with the CPU

turned off

Manual register Any interrupt

entry

Any (program-

mable)

All regulators available.

Digital and analog

regulators can be disabled

if external regulation used.

Sleep

All subsystems automatically

disabled

Manual register Comparator,

ILO/kHzECO

Both digital and analog

regulators buzzed.

Digital and analog

entry

PICU, RTC,

CTW, LVD

regulators can be disabled

if external regulation used.

Hibernate

All subsystems automatically

disabled

Manual register PICU

entry

Only hibernate regulator

active.

Lowest power consuming mode

with all peripherals and internal

regulators disabled, except

hibernate regulator is enabled

Configuration and memory

contents retained

Table 6-3. Power Modes Wakeup Time and Power Consumption

Sleep

Modes

Wakeup Current

Code

Digital

Analog

Clock Sources

Available

Wakeup Sources Reset Sources

Time

(Typ)

Execution Resources Resources

[7]

Active

–

2 mA

–

Yes

All

–

All

Alternate

Active

User

defined

20 µs typ

2 µA

No

None

Comparator

None

ILO/kHzECO

None

Comparator,

PICU, RTC, CTW,

LVD

XRES, LVD,

WDR,

Sleep

Hibernate <100 µs 300 nA

No

PICU

XRES

Figure 6-5. Power Mode Transitions

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

Active

Manual

Sleep

Hibernate

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

Alternate

Active

Note

7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 59.

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6.2.1.2 Alternate Active Mode

Figure 6-6. Application for Boost Converter

Alternate Active mode is very similar to Active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

V_boostV_ddaV_ddd

Optional Schottky

Diode. Only

required when Vdd

6.2.1.3 Sleep Mode

IND

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

>3.6 V.

22 0.1

µF µF

PSoC

10 µH

6.2.1.4 Hibernate Mode

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

V_bat

V_ssb

22

µF

V_ssa

V_ssd

The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,

or 32 kHz to optimize efficiency and component cost. The

100 kHz, 400 kHz, and 2 MHz switching frequencies are

generated using oscillators internal to the boost converter block.

When the 32 KHz switching frequency is selected, the clock is

derived from a 32 kHz external crystal oscillator. The 32 KHz

external clock is primarily intended for boost standby mode.

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Interrupt sources include internally generated interrupts,

power supervisor, central timewheel, and I/O interrupts. Internal

interrupt sources can come from a variety of peripherals, such

as analog comparators and UDBs. The central timewheel

provides periodic interrupts to allow the system to wake up, poll

peripherals, or perform real-time functions. Reset event sources

include the external reset I/O pin (XRES), WDT, and Precision

Reset (PRES).

At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz

Vboost is limited to 4 × Vbat.

The boost converter can be operated in two different modes:

active and standby. Active mode is the normal mode of operation

where the boost regulator actively generates a regulated output

voltage. In standby mode, most boost functions are disabled,

thus reducing power consumption of the boost circuit. The

converter can be configured to provide low power, low current

regulation in the standby mode. The external 32 kHz crystal can

be used to generate inductor boost pulses on the rising and

falling edge of the clock when the output voltage is less than the

programmed value. This is called automatic thump mode (ATM).

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such

as solar or single cell battery supplies, may use the on-chip boost

converter. The boost converter may also be used in any system

that requires a higher operating voltage than the supply provides.

For instance, this includes driving 5.0 V LCD glass in a 3.3 V

system. The boost converter accepts an input voltage as low as

1.8 V. With one low cost inductor it produces a selectable output

voltage sourcing enough current to operate the PSoC and other

on-board components.

The boost typically draws 200 µA in active mode and 12 µA in

standby mode. The boost operating modes must be used in

conjunction with chip power modes to minimize the total chip

power consumption. Table 6-4 lists the boost power modes

available in different chip power modes.

Table 6-4. Chip and Boost Power Modes Compatibility

The boost converter accepts an input voltage from 1.8 V to 5.5 V

Chip Power Modes

Boost Power Modes

(V

), and can start up with V

as low as 1.8 V. The converter

BAT

Chip -Active mode

Boost can be operated in either active

or standby mode.

provides a user configurable output voltage of 1.8 to 5.0 V

(V ). V is typically less than V ; if V is greater

BOOST

BAT

BOOST

will be the same as V

BAT

Chip -Sleep mode

Boost can be operated in either active

or standby mode. However, it is recom-

mended to operate boost in standby

mode for low power consumption

than or equal to V

The block can deliver up to 50 mA (I

configuration.

, then V

.

BOOST

BAT

) depending on

BOOST

Four pins are associated with the boost converter: V

, V

,

BAT

SSB

Chip-Hibernate mode Boost can only be operated in active

mode. However, it is recommended not

to use boost in chip hibernate mode

due to high current consumption in

boost active mode

V

, and Ind. The boosted output voltage is sensed at the

pin and must be connected directly to the chip’s supply

BOOST

inputs. An inductor is connected between the V

and Ind pins.

BAT

The designer can optimize the inductor value to increase the

boost converter efficiency based on input voltage, output

voltage, current and switching frequency. The External Schottky

diode shown in Figure 6-6 is required only in cases when

If the boost converter is not used in a given application, tie the

V

, V

, and V pins to ground and leave the Ind pin

V

>3.6 V.

BAT

SSB

BOOST

unconnected.

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

It is set to approximately 1 volt, which is below the lowest

specified operating voltage but high enough for the internal

circuits to be reset and to hold their reset state. The monitor

generates a reset pulse that is at least 100 ns wide. It may be

much wider if one or more of the voltages ramps up slowly.

To save power the IPOR circuit is disabled when the internal

digital supply is stable. Voltage supervision is then handed off

to the precise low voltage reset (PRES) circuit. When the

voltage is high enough for PRES to release, the IMO starts.

6.3 Reset

CY8C55 has multiple internal and external reset sources

available. The reset sources are:

■ Power source monitoring - The analog and digital power

voltages, V

, V

, and V

are monitored in

DDA

DDD

CCA

CCD

several different modes during power up, active mode, and

sleep mode (buzzing). If any of the voltages goes outside

predetermined ranges then a reset is generated. The monitors

are programmable to generate an interrupt to the processor

under certain conditions before reaching the reset thresholds.

■ PRES - Precise Low Voltage Reset

This circuit monitors the outputs of the analog and digital

internal regulators after power up. The regulator outputs are

compared to a precise reference voltage. The response to a

PRES trip is identical to an IPOR reset.

■ External - The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull-up to Vddio1. V

, V

, and Vddio1 must all

DDD

DDA

have voltage applied before the part comes out of reset.

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The

PRES circuit is disabled automatically during sleep and

hibernate modes, with one exception: During sleep mode the

regulators are periodically activated (buzzed) to provide

supervisory services and to reduce wakeup time. At these

times the PRES circuit is also buzzed to allow periodic voltage

monitoring.

■ Watchdog timer - A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.

■ Software - The device can be reset under program control.

Figure 6-7. Resets

Vddd Vdda

■ ALVI,DLVI,AHVI-Analog/DigitalLowVoltageInterrupt,Analog

High Voltage Interrupt

Interrupt circuits are available to detect when V

go outside a voltage range. For AHVI, V

Power

Processor

and V

DDD

is compared to a

Voltage

Interrupt

DDA

Level

DDA

fixed trip level. For ALVI and DLVI, V

and V

are

Monitors

DDA

DDD

compared to trip levels that are programmable, as listed in

Table 6-5. ALVI and DLVI can also be configured to generate

a device reset instead of an interrupt.

Reset

External

Reset

Controller

System

Reset

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Normal

Voltage

Range

Available Trip

Interrupt Supply

Accuracy

Settings

Watchdog

Timer

DLVI

ALVI

AHVI

V

1.71 V-5.5 V 1.70 V-5.45 V in

250 mV

±2%

DDD

DDA

increments

Software

Reset

Register

1.71 V-5.5 V 1.70 V-5.45 V in

250 mV

±2%

increments

1.71 V-5.5 V 5.75 V

The term system reset indicates that the processor as well as

analog and digital peripherals and registers are reset.

The monitors are disabled until after IPOR. During sleep

mode these circuits are periodically activated (buzzed). If an

interrupt occurs during buzzing then the system first enters its

wakeup sequence. The interrupt is then recognized and may

be serviced.

A reset status register holds the source of the most recent reset

or power voltage monitoring interrupt. The program may

examine this register to detect and report exception conditions.

This register is cleared after a power on reset.

6.3.1.2 Other Reset Sources

■ XRES - External Reset

6.3.1 Reset Sources

CY8C55 has a dedicated XRES pin which holds the part in

reset while held active (low). The response to an XRES is the

same as to an IPOR reset. The external reset is active low. It

includes an internal pull-up resistor. XRES is active during

sleep and hibernate modes.

6.3.1.1 Power Voltage Level Monitors

■ IPOR - Initial Power on Reset

At initial power on, IPOR monitors the power voltages V

DDD

and V

, both directly at the pins and at the outputs of the

DDA

corresponding internal regulators. The trip level is not precise.

Document Number: 001-66235 Rev. **

Page 25 of 112

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

■ SRES - Software Reset

❐ Input or output or both for CPU and DMA

❐ Eight drive modes

❐ Every pin can be an interrupt source configured as rising

edge, falling edge or both edges. If required, level sensitive

interrupts are supported through the DSI

❐ Dedicated port interrupt vector for each port

❐ Slew rate controlled digital output drive mode

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

Another register bit exists to disable this function.

❐ Access port control and configuration registers on either port

■ WRES - Watchdog Timer Reset

basis or pin basis

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

❐ Separateportread(PS)andwrite(DR)dataregisterstoavoid

read modify write errors

❐ Special functionality on a pin by pin basis

■ Additional features only provided on the GPIO pins:

❐ LCD segment drive on LCD equipped devices

Note IPOR disables the watchdog function. The program

must enable the watchdog function at an appropriate point in

the code by setting a register bit. When this bit is set, it cannot

be cleared again except by an IPOR power on reset event.

[8]

❐ CapSense on CapSense equipped devices

❐ Analog input and output capability

❐ Continuous 100 µA clamp current capability

❐ Standard drive strength down to 1.71 V

6.4 I/O System and Routing

■ Additional features only provided on SIO pins:

❐ Higher drive strength than GPIO

PSoC I/Os are extremely flexible. Every GPIO has analog and

digital I/O capability. All I/Os have a large number of drive modes,

which are set at POR. PSoC also provides up to four individual

❐ Hot swap capability (5 V tolerance at any operating V

)

DD

❐ Programmable and regulated high input and output drive

levels down to 1.2 V

I/O voltage domains through the V

pins.

DDIO

There are two types of I/O pins on every device; those with USB

provide a third type. Both general purpose I/O (GPIO) and

special I/O (SIO) provide similar digital functionality. The primary

differences are their analog capability and drive strength.

Devices that include USB also provide two USBIO pins that

support specific USB functionality as well as limited GPIO

capability.

❐ No analog input or LCD capability

❐ Over voltage tolerance up to 5.5 V

❐ SIO can act as a general purpose analog comparator

■ USBIO features:

❐ Full speed USB 2.0 compliant I/O

❐ Highest drive strength for general purpose use

❐ Input, output, or both for CPU and DMA

❐ Input, output, or both for digital peripherals

❐ Digital output (CMOS) drive mode

All I/O pins are available for use as digital inputs and outputs for

both the CPU and digital peripherals. In addition, all I/O pins can

generate an interrupt. The flexible and advanced capabilities of

the PSoC I/O, combined with any signal to any pin routability,

greatly simplify circuit design and board layout. All GPIO pins can

❐ Each pin can be an interrupt source configured as rising

edge, falling edge, or both edges

[8]

be used for analog input, CapSense , and LCD segment drive,

while SIO pins are used for voltages in excess of V

programmable output voltages.

and for

DDA

■ Features supported by both GPIO and SIO:

❐ SeparateI/Osuppliesandvoltagesfor upto fourgroupsofI/O

❐ Digital peripherals use DSI to connect the pins

Note

8. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-66235 Rev. **

Page 26 of 112

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Figure 6-8. GPIO Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]CTL

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

PRT[x]SLW

PRT[x]SYNC_OUT

Vddio Vddio

PRT[x]DR

0

In

Digital System Output

PRT[x]BYP

1

Vddio

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Analog

1

0

1

0

1

Capsense Global Control

CAPS[x]CFG1

Switches

PRT[x]AG

Analog Global Enable

PRT[x]AMUX

Analog Mux Enable

LCD

Display

Data

PRT[x]LCD_COM_SEG

PRT[x]LCD_EN

Logic & MUX

LCD Bias Bus

5

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Figure 6-9. SIO Input/Output Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]SIO_HYST_EN

PRT[x]SIO_DIFF

Buffer

Thresholds

Reference Level

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

Reference Level

PRT[x]SIO_CFG

PRT[x]SLW

Driver

Vhigh

PRT[x]SYNC_OUT

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Figure 6-10. USBIO Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

USB Receiver Circuitry

PRT[x]DBL_SYNC_IN

USBIO_CR1[0,1]

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Interrupt

Logic

Digital Output Path

PRT[x]SYNC_OUT

USBIO_CR1[7]

D+ pin only

USB or I/O

Vddd

Vddd Vddd

USB SIE Control for USB Mode

Vddd

USBIO_CR1[4,5]

Digital System Output

PRT[x]BYP

0

1

In

Drive

Logic

5 k

1.5 k

USBIO_CR1[2]

USBIO_CR1[3]

USBIO_CR1[6]

D+ 1.5 k

D+D- 5 k

Open Drain

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

6.4.1 Drive Modes

if bypass mode is selected. Note that the actual I/O pin voltage

is determined by a combination of the selected drive mode and

the load at the pin. For example, if a GPIO pin is configured for

resistive pull-up mode and driven high while the pin is floating,

the voltage measured at the pin is a high logic state. If the same

GPIO pin is externally tied to ground then the voltage

unmeasured at the pin is a low logic state.

Each GPIO and SIO pin is individually configurable into one of

the eight drive modes listed in Table 6-6. Three configuration bits

are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]

registers. Figure 6-11 depicts a simplified pin view based on

each of the eight drive modes. Table 6-6 shows the I/O pin’s drive

state based on the port data register value or digital array signal

Figure 6-11. Drive Mode

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

0. High Impedance 1. High Impedance

Analog Digital

2. Resistive

Pull-Up

3. Resistive

Pull-Down

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

4. Open Drain,

Drives Low

5. Open Drain,

Drives High

6. Strong Drive

7. Resistive

Pull-Up and Pull-Down

Table 6-6. Drive Modes

Diagram

Drive Mode

PRTxDM2

PRTxDM1

PRTxDM0

PRTxDR = 1

High-Z

PRTxDR = 0

High-Z

0

1

2

3

4

5

6

7

High impedence analog

High Impedance digital

0

1

0

1

0

1

0

1

0

1

0

1

0

1

High-Z

[9]

Resistive pull-up

Res High (5K)

Strong High

High-Z

Strong Low

Res Low (5K)

Strong Low

High-Z

[9]

Resistive pull-down

Open drain, drives low

Open drain, drive high

Strong drive

Strong High

Res High (5K)

Strong Low

Res Low (5K)

[9]

Resistive pull-up and pull-down

■ High Impedance Analog

To achieve the lowest chip current in sleep modes, all I/Os

must either be configured to the high impedance analog

mode, or have their pins driven to a power supply rail by the

PSoC device or by external circuitry.

The default reset state with both the output driver and digital

input buffer turned off. This prevents any current from flowing

in the I/O’s digital input buffer due to a floating voltage. This

state is recommended for pins that are floating or that support

an analog voltage. High impedance analog pins do not

provide digital input functionality.

■ High Impedance Digital

The input buffer is enabled for digital signal input. This is the

standard high impedance (HiZ) state recommended for digital

inputs.

Note

9. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

■ Resistive Pull-up or Resistive Pull-down

6.4.5 Pin Interrupts

Resistive pull-up or pull-down, respectively, provides a series

resistance in one of the data states and strong drive in the

other. Pins can be used for digital input and output in these

modes. Interfacing to mechanical switches is a common

application for these modes. Resistive pull-up and pull-down

are not available with SIO in regulated output mode.

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own Port

Interrupt Control Unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to “1” and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

vector in the interrupt controller and the pin status register

providing easy determination of the interrupt source down to the

pin level.

■ Open Drain, Drives High and Open Drain, Drives Low

Open drain modes provide high impedance in one of the data

states and strong drive in the other. Pins can be used for

digital input and output in these modes. A common

2

application for these modes is driving the I C bus signal lines.

■ Strong Drive

Provides a strong CMOS output drive in either high or low

state. This is the standard output mode for pins. Strong Drive

mode pins must not be used as inputs under normal

circumstances. This mode is often used to drive digital output

signals or external FETs.

Port pin interrupts remain active in all sleep modes allowing the

PSoC device to wake from an externally generated interrupt.

While level sensitive interrupts are not directly supported;

Universal Digital Blocks (UDB) provide this functionality to the

system when needed.

■ Resistive Pull-up and Pull-down

6.4.6 Input Buffer Mode

Similar to the resistive pull-up and resistive pull-down modes

except the pin is always in series with a resistor. The high data

state is pull-up while the low data state is pull-down. This

mode is most often used when other signals that may cause

shorts can drive the bus. Resistive pull-up and pull-down are

not available with SIO in regulated output mode.

GPIO and SIO input buffers can be configured at the port level

for the default CMOS input thresholds or the optional LVTTL

input thresholds. All input buffers incorporate Schmitt triggers for

input hysteresis. Additionally, individual pin input buffers can be

disabled in any drive mode.

6.4.7 I/O Power Supplies

Up to four I/O pin power supplies are provided depending on the

device and package. Each I/O supply must be less than or equal

to the voltage on the chip’s analog (V

users to provide different I/O voltage levels for different pins on

the device. Refer to the specific device package pinout to

6.4.2 Pin Registers

Registers to configure and interact with pins come in two forms

that may be used interchangeably. All I/O registers are available

in the standard port form, where each bit of the register

corresponds to one of the port pins. This register form is efficient

for quickly reconfiguring multiple port pins at the same time.

) pin. This feature allows

DDA

determine V

capability for a given port and pin. The SIO port

DDIO

I/O registers are also available in pin form, which combines the

eight most commonly used port register bits into a single register

for each pin. This enables very fast configuration changes to

individual pins with a single register write.

pins support an additional regulated high output capability, as

described in 6.4.11 Adjustable Output Level.

6.4.8 Analog Connections

These connections apply only to GPIO pins. All GPIO pins may

be used as analog inputs or outputs. The analog voltage present

6.4.3 Bidirectional Mode

on the pin must not exceed the V

supply voltage to which

High speed bidirectional capability allows pins to provide both

the high impedance digital drive mode for input signals and a

second user selected drive mode such as strong drive (set using

PRTxDM[2:0] registers) for output signals on the same pin,

based on the state of an auxiliary control bus signal. The

bidirectional capability is useful for processor busses and

communications interfaces such as the SPI Slave MISO pin that

requires dynamic hardware control of the output buffer. The

auxiliary control bus routes up to 16 UDB or digital peripheral

generated output enable signals to one or more pins.

DDIO

the GPIO belongs. Each GPIO may connect to one of the analog

global busses or to one of the analog mux buses to connect any

pin to any internal analog resource such as ADC or comparators.

In addition, select pins provide direct connections to specific

analog features such as the high current DACs or uncommitted

opamps.

6.4.9 CapSense

This section applies only to GPIO pins. All GPIO pins may be

used to create CapSense buttons and sliders . See the

[10]

6.4.4 Slew Rate Limited Mode

“CapSense” section on page 53 for more information.

GPIO and SIO pins have fast and slow output slew rate options

for strong and open drain drive modes, not resistive drive modes.

Because it results in reduced EMI, the slow edge rate option is

recommended for signals that are not speed critical, generally

less than 1 MHz. The fast slew rate is for signals between 1 MHz

and 33 MHz. The slew rate is individually configurable for each

pin, and is set by the PRTxSLW registers.

6.4.10 LCD Segment Drive

This section applies only to GPIO pins. All GPIO pins may be

used to generate Segment and Common drive signals for direct

glass drive of LCD glass. See the “LCD Direct Drive” section on

page 52 for details.

Note

10. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-66235 Rev. **

Page 30 of 112

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

6.4.11 Adjustable Output Level

6.4.13 SIO as Comparator

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the 6.4.12 Adjustable Input

Level section can be used to construct a comparator. The

threshold for the comparator is provided by the SIO's reference

generator. The reference generator has the option to set the

analog signal routed through the analog global line as threshold

for the comparator. Note that a pair of SIO pins share the same

threshold.

The digital input path in Figure 6-9 on page 28 illustrates this

functionality. In the figure, ‘Reference level’ is the analog signal

routed through the analog global. The hysteresis feature can

also be enabled for the input buffer of the SIO, which increases

noise immunity for the comparator.

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a GPIO pin’s

protection diode.

interface to external signals that differ in voltage from V

. The

DDIO

reference sets the pins voltage threshold for a high logic level

(see Figure 6-12). Available input thresholds are:

■ 0.5 × V

DDIO

■ 0.4 × V

DDIO

■ 0.5 × V

6.4.15 Over Voltage Tolerance

REF

■ V

REF

All I/O pins provide an over voltage (V

tolerance feature at any operating V

< V < V

)

DDIO

IN

DDA

Typically a voltage DAC (VDAC) generates the V

reference.

.

REF

DD

“DAC” section on page 53 has more details on VDAC use and

reference routing to the SIO pins.

■ There are no currentlimitationsfor the SIO pins as they present

a high impedance load to the external circuit.

Figure 6-12. SIO Reference for Input and Output

■ TheGPIOpinsmustbelimitedto100µAusingacurrentlimiting

resistor. GPIO pins clamp the pin voltage to approximately one

Input Path

diode above the V

supply.

DDIO

Digital

Input

Vinref

■ In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the V

voltage to which the GPIO belongs.

supply

DDIO

A common application for this feature is connection to a bus such

2

as I C where different devices are running from different supply

2

voltages. In the I C case, the PSoC chip is configured into the

Open Drain, Drives Low mode for the SIO pin. This allows an

external pull-up to pull the I C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 1.8 V, and

an external device could run from 5 V. Note that the SIO pin’s V

2

Reference

Generator

SIO_Ref

IH

and V levels are determined by the associated V

supply

IL

DDIO

Voutref

pin.

Output Path

Driver

The I/O pin must be configured into a high impedance drive

Vhigh

mode, open drain low drive mode, or pull-down drive mode, for

over voltage tolerance to work properly. Absolute maximum

ratings for the device must be observed for all I/O pins.

6.4.16 Reset Configuration

Digital

Output

Drive

Logic

At reset, all I/Os are reset to the High Impedance Analog state.

6.4.17 Low Power Functionality

In all low power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low power modes.

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6.4.18 Special Pin Functionality

Figure 7-1. CY8C55 Digital Programmable Architecture

Some pins on the device include additional special functionality

in addition to their GPIO or SIO functionality. The specific special

function pins are listed in “Pinouts” on page 5. The special

features are:

Digital Core System

and Fixed Function Peripherals

■ Digital

❐ 4- to 25 MHz crystal oscillator

❐ 32.768 KHz crystal oscillator

❐ JTAG and SWD interface pins

❐ SWV interface pins

❐ External reset

DSI Routing Interface

UDB

■ Analog

❐ Opamp inputs and outputs

❐ High current IDAC outputs

❐ External reference inputs

DSI Routing Interface

7. Digital Subsystem

The digital programmable system creates application specific

combinations of both standard and advanced digital peripherals

and custom logic functions. These peripherals and logic are then

interconnected to each other and to any pin on the device,

providing a high level of design flexibility and IP security.

Digital Core System

and Fixed Function Peripherals

The features of the digital programmable system are outlined

here to provide an overview of capabilities and architecture.

Designers do not need to interact directly with the programmable

digital system at the hardware and register level. PSoC Creator

provides a high level schematic capture graphical interface to

automatically place and route resources similar to PLDs.

7.1 Example Peripherals

The flexibility of the CY8C55 family’s UDBs and analog blocks

allow the user to create a wide range of components

(peripherals). The most common peripherals were built and

characterized by Cypress and are shown in the PSoC Creator

component catalog, however, users may also create their own

custom components using PSoC Creator. Using PSoC Creator,

users may also create their own components for reuse within

their organization, for example sensor interfaces, proprietary

algorithms, and display interfaces.

The main components of the digital programmable system are:

■ Universal Digital Blocks (UDB) - These form the core

functionality of the digital programmable system. UDBs are a

collection of uncommitted logic (PLD) and structural logic

(Datapath) optimized to create all common embedded

peripherals and customized functionality that are application or

design specific.

The number of components available through PSoC Creator is

too numerous to list in the data sheet, and the list is always

growing. An example of a component available for use in

CY8C55 family, but, not explicitly called out in this data sheet is

the UART component.

■ Universal Digital Block Array - UDB blocks are arrayed within

a matrix of programmable interconnect. The UDB array

structure is homogeneous and allows for flexible mapping of

digital functions onto the array. The array supports extensive

and flexible routing interconnects between UDBs and the

Digital System Interconnect.

7.1.1 Example Digital Components

The following is a sample of the digital components available in

PSoC Creator for the CY8C55 family. The exact amount of

hardware resources (UDBs, routing, RAM, flash) used by a

component varies with the features selected in PSoC Creator for

the component.

■ Digital System Interconnect (DSI) - Digital signals from

Universal Digital Blocks (UDBs), fixed function peripherals, I/O

pins, interrupts, DMA, and other system core signals are

attached to the Digital System Interconnect to implement full

featureddeviceconnectivity.TheDSIallowsanydigitalfunction

to any pin or other feature routability when used with the

Universal Digital Block Array.

■ Communications

2

❐ I C (1 to 3 UDBs)

❐ UART (1 to 3 UDBs)

■ Functions

❐ PWM (1 to 2 UDBs)

■ Logic (x CPLD product terms per logic function)

❐ NOT

❐ OR

❐ XOR

❐ AND

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7.1.2 Example Analog Components

7.1.4 Designing with PSoC Creator

7.1.4.1 More Than a Typical IDE

The following is a sample of the analog components available in

PSoC Creator for the CY8C55 family. The exact amount of

hardware resources (SC/CT blocks, routing, RAM, flash) used

by a component varies with the features selected in PSoC

Creator for the component.

A successful design tool allows for the rapid development and

deployment of both simple and complex designs. It reduces or

eliminates any learning curve. It makes the integration of a new

design into the production stream straightforward.

■ Amplifiers

❐ TIA

❐ PGA

PSoC Creator is that design tool.

PSoC Creator is a full featured Integrated Development

Environment (IDE) for hardware and software design. It is

optimized specifically for PSoC devices and combines a modern,

powerful software development platform with a sophisticated

graphical design tool. This unique combination of tools makes

PSoC Creator the most flexible embedded design platform

available.

❐ opamp

■ ADCs

❐ Delta-Sigma

❐ Successive Approximation (SAR)

■ DACs

❐ Current

❐ Voltage

❐ PWM

Graphical design entry simplifies the task of configuring a

particular part. You can select the required functionality from an

extensive catalog of components and place it in your design. All

components are parameterized and have an editor dialog that

allows you to tailor functionality to your needs.

■ Comparators

■ Mixers

PSoC Creator automatically configures clocks and routes the I/O

to the selected pins and then generates APIs to give the

application complete control over the hardware. Changing the

PSoC device configuration is as simple as adding a new

component, setting its parameters, and rebuilding the project.

7.1.3 Example System Function Components

The following is a sample of the system function components

available in PSoC Creator for the CY8C55 family. The exact

amount of hardware resources (UDBs, DFB taps, SC/CT blocks,

routing, RAM, flash) used by a component varies with the

features selected in PSoC Creator for the component.

At any stage of development you are free to change the

hardware configuration and even the target processor. To

retarget your application (hardware and software) to new

devices, even from 8- to 32-bit families, just select the new

device and rebuild.

■ CapSense

■ LCD Drive

■ LCD Control

■ Filters

You also have the ability to change the C compiler and evaluate

an alternative. Components are designed for portability and are

validated against all devices, from all families, and against all

supported tool chains. Switching compilers is as easy as editing

the from the project options and rebuilding the application with

no errors from the generated APIs or boot code.

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PSoC^®5: CY8C55 Family Datasheet

Figure 7-2. PSoC Creator Framework

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PSoC^®5: CY8C55 Family Datasheet

7.1.4.2 Component Catalog

7.1.4.4 Software Development

Figure 7-3. Component Catalog

Figure 7-4. Code Editor

Anchoring the tool is a modern, highly customizable user

interface. It includes project management and integrated editors

for C and assembler source code, as well the design entry tools.

Project build control leverages compiler technology from top

®

commercial vendors such as ARM Limited, Keil™, and

CodeSourcery (GNU). Free versions of Keil C51 and GNU C

Compiler (GCC) for ARM, with no restrictions on code size or end

product distribution, are included with the tool distribution.

Upgrading to more optimizing compilers is a snap with support

for the professional Keil C51 product and ARM RealView™

compiler.

The component catalog is a repository of reusable design

elements that select device functionality and customize your

PSoC device. It is populated with an impressive selection of

content; from simple primitives such as logic gates and device

registers, through the digital timers, counters and PWMs, plus

analog components such as ADCs, DACs, and filters, and

7.1.4.5 Nonintrusive Debugging

Figure 7-5. PSoC Creator Debugger

2

communication protocols, such as I C, USB and CAN. See

“Example Peripherals” section on page 32 for more details about

available peripherals. All content is fully characterized and

carefully documented in datasheets with code examples, AC/DC

specifications, and user code ready APIs.

7.1.4.3 Design Reuse

The symbol editor gives you the ability to develop reusable

components that can significantly reduce future design time. Just

draw a symbol and associate that symbol with your proven

design. PSoC Creator allows for the placement of the new

symbol anywhere in the component catalog along with the

content provided by Cypress. You can then reuse your content

as many times as you want, and in any number of projects,

without ever having to revisit the details of the implementation.

With JTAG (4-wire) and SWD (2-wire) debug connectivity

available on all devices, the PSoC Creator debugger offers full

control over the target device with minimum intrusion.

Breakpoints and code execution commands are all readily

available from toolbar buttons and an impressive lineup of

windows—register, locals, watch, call stack, memory and

peripherals—make for an unparalleled level of visibility into the

system. PSoC Creator contains all the tools necessary to

complete a design, and then to maintain and extend that design

for years to come. All steps of the design flow are carefully

integrated and optimized for ease-of-use and to maximize

productivity.

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7.2.1 PLD Module

7.2 Universal Digital Block

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, look up tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

The Universal Digital Block (UDB) represents an evolutionary

step to the next generation of PSoC embedded digital peripheral

functionality. The architecture in first generation PSoC digital

blocks provides coarse programmability in which a few fixed

functions with a small number of options are available. The new

UDB architecture is the optimal balance between configuration

granularity and efficient implementation. A cornerstone of this

approach is to provide the ability to customize the devices digital

operation to match application requirements.

To achieve this, UDBs consist of a combination of uncommitted

logic (PLD), structured logic (Datapath), and a flexible routing

scheme to provide interconnect between these elements, I/O

connections, and other peripherals. UDB functionality ranges

from simple self contained functions that are implemented in one

UDB, or even a portion of a UDB (unused resources are

available for other functions), to more complex functions that

require multiple UDBs. Examples of basic functions are timers,

counters, CRC generators, PWMs, dead band generators, and

Figure 7-7. PLD 12C4 Structure

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

T C T C T C T C T C T C T C T C

AND

Array

2

communications functions, such as UARTs, SPI, and I C. Also,

the PLD blocks and connectivity provide full featured general

purpose programmable logic within the limits of the available

resources.

SELIN

(carry in)

Figure 7-6. UDB Block Diagram

PLD

Chaining

OUT0

OUT1

OUT2

OUT3

MC0

MC1

MC2

MC3

T

PLD

12C4

(8 PTs)

PLD

12C4

(8 PTs)

Clock

and Reset

Control

SELOUT

(carry out)

OR

Array

Status and

Control

Datapath

Chaining

One 12C4 PLD block is shown in Figure 7-7. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

Routing Channel

The main component blocks of the UDB are:

■ PLD blocks - There are two small PLDs per UDB. These blocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.

7.2.2 Datapath Module

■ Datapath Module - This 8-bit wide datapath contains structured

logic to implement a dynamically configurable ALU, a variety

ofcompare configurations andconditiongeneration. Thisblock

alsocontainsinput/outputFIFOs, whicharetheprimaryparallel

data interface between the CPU/DMA system and the UDB.

■ Status and Control Module - The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.

The datapath contains an 8-bit single cycle ALU, with associated

compare and condition generation logic. This datapath block is

optimized to implement embedded functions, such as timers,

counters, integrators, PWMs, PRS, CRC, shifters and dead band

generators and many others.

■ Clock and Reset Module - This block provides the UDB clocks

and reset selection and control.

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Figure 7-8. Datapath Top Level

PHUB System Bus

R/W Access to All

Registers

F1

FIFOs

F0

Output

Muxes

Input

Muxes

A0

A1

D0

D1

Input from

Programmable

Routing

Output to

Programmable

Routing

6

D1

Data Registers

D0

To/From

Chaining

A1

Accumulators

A0

PI

Parallel Input/Output

(To/From Programmable Routing)

PO

ALU

Shift

Mask

7.2.2.1 Working Registers

sequence, and can be routed from any block connected to the

UDB routing matrix, most typically PLD logic, I/O pins, or from

the outputs of this or other datapath blocks.

The datapath contains six primary working registers, which are

accessed by CPU firmware or DMA during normal operation.

ALU

Table 7-1. Working Datapath Registers

The ALU performs eight general purpose functions. They are:

Name

Function

Description

■ Increment

■ Decrement

■ Add

A0 and A1 Accumulators

These are sources and sinks for

the ALU and also sources for the

compares.

D0 and D1 Data Registers These are sources for the ALU

and sources for the compares.

■ Subtract

F0 and F1 FIFOs

These are the primary interface

to the system bus. They can be a

data source for the data registers

and accumulators or they can

capture data from the accumu-

lators or ALU. Each FIFO is four

bytes deep.

■ Logical AND

■ Logical OR

■ Logical XOR

■ Pass, used to pass a value through the ALU to the shift register,

mask, or another UDB register

Independent of the ALU operation, these functions are available:

7.2.2.2 Dynamic Datapath Configuration RAM

■ Shift left

Dynamic configuration is the ability to change the datapath

function and internal configuration on a cycle-by-cycle basis,

under sequencer control. This is implemented using the 8-word

x 16-bit configuration RAM, which stores eight unique 16-bit wide

configurations. The address input to this RAM controls the

■ Shift right

■ Nibble swap

■ Bitwise OR mask

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7.2.2.3 Conditionals

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.2.9 Datapath I/O

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

7.2.2.4 Variable MSB

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

7.2.3 Status and Control Module

7.2.2.5 Built in CRC/PRS

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

The datapath has built in support for single cycle Cyclic

Redundancy Check (CRC) computation and Pseudo Random

Sequence (PRS) generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

Figure 7-10. Status and Control Registers

System Bus

7.2.2.6 Input/Output FIFOs

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

Routing Channel

Figure 7-9. Example FIFO Configurations

The bits of the control register, which may be written to by the

system bus, are used to drive into the routing matrix, and thus

provide firmware with the opportunity to control the state of UDB

processing. The status register is read-only and it allows internal

UDB state to be read out onto the system bus directly from

internal routing. This allows firmware to monitor the state of UDB

processing. Each bit of these registers has programmable

connections to the routing matrix and routing connections are

made depending on the requirements of the application.

System Bus

F0

F1

D0/D1

D0

A0

D1

A1

A0/A1/ALU

F0

A0/A1/ALU

F1

7.2.3.1 Usage Examples

As an example of control input, a bit in the control register can

be allocated as a function enable bit. There are multiple ways to

enable a function. In one method the control bit output would be

routed to the clock control block in one or more UDBs and serve

as a clock enable for the selected UDB blocks. A status example

is a case where a PLD or datapath block generated a condition,

such as a “compare true” condition that is captured and latched

by the status register and then read (and cleared) by CPU

firmware.

F1

System Bus

Dual Capture

TX/RX

Dual Buffer

7.2.3.2 Clock Generation

7.2.2.7 Chaining

Each subcomponent block of a UDB including the two PLDs, the

datapath, and Status and Control, has a clock selection and

control block. This promotes a fine granularity with respect to

allocating clocking resources to UDB component blocks and

allows unused UDB resources to be used by other functions for

maximum system efficiency.

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

7.2.2.8 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

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utilize the unused PLD blocks in the 8-bit Timer UDB.

Programmable resources in the UDB array are generally

homogeneous so functions can be mapped to arbitrary

boundaries in the array.

7.3 UDB Array Description

Figure 7-11 shows an example of a 16 UDB array. In addition to

the array core, there are a DSI routing interfaces at the top and

bottom of the array. Other interfaces that are not explicitly shown

include the system interfaces for bus and clock distribution. The

UDB array includes multiple horizontal and vertical routing

channels each comprised of 96 wires. The wire connections to

UDBs, at horizontal/vertical intersection and at the DSI interface

are highly permutable providing efficient automatic routing in

PSoC Creator. Additionally the routing allows wire by wire

segmentation along the vertical and horizontal routing to further

increase routing flexibility and capability.

Figure 7-12. Function Mapping Example in a Bank of UDBs

8-Bit

Timer

16-Bit

PWM

Quadrature Decoder

16-Bit PYRS

UDB

HV

A

HV

B

HV

A

HV

B

Figure 7-11. Digital System Interface Structure

UDB

8-Bit

UDB

8-Bit SPI

System Connections

UDB

Timer

Logic

I2C Slave

UDB

12-Bit SPI

UDB

HV

B

HV

A

HV

B

HV

A

UDB

HV

B

HV

A

HV

B

HV

A

HV

A

HV

B

HV

A

HV

B

Logic

UDB

UART

12-Bit PWM

7.4 DSI Routing Interface Description

HV

B

HV

A

HV

B

HV

A

The DSI routing interface is a continuation of the horizontal and

vertical routing channels at the top and bottom of the UDB array

core. It provides general purpose programmable routing

between device peripherals, including UDBs, I/Os, analog

peripherals, interrupts, DMA and fixed function peripherals.

UDB

HV

A

HV

B

HV

A

HV

B

Figure 7-13 illustrates the concept of the digital system

interconnect, which connects the UDB array routing matrix with

other device peripherals. Any digital core or fixed function

peripheral that needs programmable routing is connected to this

interface.

System Connections

Signals in this category include:

7.3.1 UDB Array Programmable Resources

■ Interrupt requests from all digital peripherals in the system.

■ DMA requests from all digital peripherals in the system.

■ Digital peripheral data signals that need flexible routing to I/Os.

■ Digital peripheral data signals that need connections to UDBs.

■ Connections to the interrupt and DMA controllers.

■ Connection to I/O pins.

Figure 7-12 shows an example of how functions are mapped into

a bank of 16 UDBs. The primary programmable resources of the

UDB are two PLDs, one datapath and one status/control register.

These resources are allocated independently, because they

have independently selectable clocks, and therefore unused

blocks are allocated to other unrelated functions.

An example of this is the 8-bit Timer in the upper left corner of

the array. This function only requires one datapath in the UDB,

and therefore the PLD resources may be allocated to another

function. A function such as a Quadrature Decoder may require

more PLD logic than one UDB can supply and in this case can

■ Connection to analog system digital signals.

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Figure 7-13. Digital System Interconnect

the system clock (see Figure 6-1). Normally all inputs from pins

are synchronized as this is required if the CPU interacts with the

signal or any signal derived from it. Asynchronous inputs have

rare uses. An example of this is a feed through of combinational

PLD logic from input pins to output pins.

Timer

Interrupt

DMA

IO Port

Pins

Global

Clocks

CAN

I2C

Counters

Controller

Figure 7-15. I/O Pin Synchronization Routing

Digital System Routing I/F

UDB ARRAY

DO

DI

Digital System Routing I/F

Figure 7-16. I/O Pin Output Connectivity

8 IO Data Output Connections from the

UDB Array Digital System Interface

Global

Clocks

IO Port

Pins

SC/CT

Blocks

EMIF

Del-Sig

DACs

Comparators

Interrupt and DMA routing is very flexible in the CY8C55

programmable architecture. In addition to the numerous fixed

function peripherals that can generate interrupt requests, any

data signal in the UDB array routing can also be used to generate

a request. A single peripheral may generate multiple

independent interrupt requests simplifying system and firmware

design. Figure 7-14 shows the structure of the IDMUX

(Interrupt/DMA Multiplexer).

DO

PIN 0

DO

PIN1

DO

PIN2

DO

PIN3

DO

PIN5

DO

PIN6

DO

PIN7

PIN4

Port i

Figure 7-14. Interrupt and DMA Processing in the IDMUX

There are four more DSI connections to a given I/O port to

implement dynamic output enable control of pins. This

connectivity gives a range of options, from fully ganged 8-bits

controlled by one signal, to up to four individually controlled pins.

The output enable signal is useful for creating tri-state

bidirectional pins and buses.

Interrupt and DMA Processing in IDMUX

Fixed Function IRQs

0

1

Interrupt

Controller

IRQs

2

3

Figure 7-17. I/O Pin Output Enable Connectivity

UDB Array

Edge

Detect

4 IO Control Signal Connections from

UDB Array Digital System Interface

DRQs

DMA termout (IRQs)

0

Fixed Function DRQs

DMA

Controller

1

2

Edge

Detect

7.4.1 I/O Port Routing

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16

for data and four for drive strength control.

OE

PIN 0

PIN1

PIN2

PIN3

PIN4

PIN5

PIN6

PIN7

When an I/O pin is connected to the routing, there are two

primary connections available, an input and an output. In

conjunction with drive strength control, this can implement a

bidirectional I/O pin. A data output signal has the option to be

single synchronized (pipelined) and a data input signal has the

option to be double synchronized. The synchronization clock is

Port i

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reliability at a low cost. Because of its success in automotive

applications, CAN is used as a standard communication protocol

for motion oriented machine control networks (CANOpen) and

factory automation applications (DeviceNet). The CAN controller

features allow the efficient implementation of higher level

protocols without affecting the performance of the

microcontroller CPU. Full configuration support is provided in

PSoC Creator.

7.5 CAN

The CAN peripheral is a fully functional Controller Area Network

(CAN) supporting communication baud rates up to 1 Mbps. The

CAN controller implements the CAN2.0A and CAN2.0B

specifications as defined in the Bosch specification and

conforms to the ISO-11898-1 standard. The CAN protocol was

originally designed for automotive applications with a focus on a

high level of fault detection. This ensures high communication

Figure 7-18. CAN Bus System Implementation

CAN Node 1

PSoC

CAN Node 2

CAN Node n

CAN

Drivers

CAN Controller

En

Tx Rx

CAN Transceiver

CAN_H

CAN_L

CAN_H

CAN_L

CAN Bus

7.5.1 CAN Features

■ Receive path

❐ 16 receive buffers each with its own message filter

❐ Enhanced hardware message filter implementation that

covers the ID, IDE and RTR

❐ DeviceNet addressing support

❐ Multiple receive buffers linkable to build a larger receive

message array

■ CAN2.0A/B protocol implementation - ISO 11898 compliant

❐ Standard and extended frames with up to 8 bytes of data per

frame

❐ Message filter capabilities

❐ Remote Transmission Request (RTR) support

❐ Programmable bit rate up to 1 Mbps

❐ Automatic transmission request (RTR) response handler

❐ Lost received message notification

■ Listen Only mode

■ Transmit path

■ SW readable error counter and indicator

❐ Eight transmit buffers

❐ Programmable transmit priority

❐ Round robin

❐ Fixed priority

❐ Message transmissions abort capability

■ Sleep mode: Wake the device from sleep with activity on the

Rx pin

■ Supports two or three wire interface to external transceiver (Tx,

Rx, and Enable). The three-wire interface is compatible with

the Philips PHY; the PHY is not included on-chip. The three

wires can be routed to any I/O

7.5.2 Software Tools Support

CAN Controller configuration integrated into PSoC Creator:

■ Enhanced interrupt controller

❐ CAN receive and transmit buffers status

❐ CAN controller error status including BusOff

■ CAN Configuration walkthrough with bit timing analyzer

■ Receive filter setup

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Figure 7-19. CAN Controller Block Diagram

TxMessage0

TxReq

TxAbort

TxMessage1

TxReq

TxAbort

Tx Buffer

Status

TxReq

Bit Timing

Pending

Priority

Arbiter

Tx

TxMessage6

TxReq

TxAbort

Tx

CAN

Framer

CRC

Generator

TxInterrupt

Request

(if enabled)

TxMessage7

TxReq

TxAbort

Error Status

Error Active

Error Passive

Bus Off

Tx Error Counter

Rx Error Counter

RTR RxMessages

0-15

RxMessage0

RxMessage1

Acceptance Code 0

Acceptance Mask 0

Acceptance Mask 1

Rx Buffer

Status

RxMessage

Available

Acceptance Code 1

Rx

RxMessage

Handler

CAN

Framer

CRC Check

RxMessage14

RxMessage15

Acceptance Code 14

Acceptance Code 15

Acceptance Mask 14

Acceptance Mask 15

RxInterrupt

Request

(if enabled)

WakeUp

Request

Error Detection

CRC

Form

ACK

Bit Stuffing

Bit Error

Overload

Arbitration

ErrInterrupt

Request

(if enabled)

Figure 7-20. USB

7.6 USB

PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0

transceiver supporting all four USB transfer types: control,

interrupt, bulk, and isochronous. PSoC Creator provides full

configuration support. USB interfaces to hosts through two

dedicated USBIO pins, which are detailed in the “6.4 I/O System

and Routing” section on page 26.

512 X 8

SRAM

Arbiter

External 22 Ω

Resistors

D+

S I E

(Serial Interface

Engine)

USB

I/O

D–

USB includes the following features:

Interrupts

■ Eight unidirectional data endpoints

48 MHz

IMO

■ One bidirectional control endpoint 0 (EP0)

■ Shared 512-byte buffer for the eight data endpoints

■ Dedicated 8-byte buffer for EP0

7.7 Timers, Counters, and PWMs

The Timer/Counter/PWM peripheral is a 16-bit dedicated

■ Two memory modes

peripheral providing three of the most common embedded

peripheral features. As almost all embedded systems use some

combination of timers, counters, and PWMs. Four of them have

been included on this PSoC device family. Additional and more

advanced functionality timers, counters, and PWMs can also be

instantiated in Universal Digital Blocks (UDBs) as required.

PSoC Creator allows designers to choose the timer, counter, and

PWM features that they require. The tool set utilizes the most

optimal resources available.

❐ Manual Memory Management with No DMA Access

❐ Manual Memory Management with Manual DMA Access

■ Internal 3.3 V regulator for transceiver

■ Internal 48 MHz oscillator that auto locks to USB bus clock,

requiring no external crystal for USB (USB equipped parts only)

■ Interrupts on bus and each endpoint event, with device wakeup

■ USB Reset, Suspend, and Resume operations

■ Bus powered and self powered modes

The Timer/Counter/PWM peripheral can select from multiple

clock sources, with input and output signals connected through

the DSI routing. DSI routing allows input and output connections

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

2

to any device pin and any internal digital signal accessible

through the DSI. Each of the four instances has a compare

output, terminal count output (optional complementary compare

output), and programmable interrupt request line. The

Timer/Counter/PWMs are configurable as freerunning, one shot,

or Enable input controlled. The peripheral has timer reset and

capture inputs, and a kill input for control of the comparator

outputs. The peripheral supports full 16-bit capture.

communication bus. The bus is compliant with Philips ‘The I C

Specification’ version 2.1. Additional I C interfaces can be

instantiated using Universal Digital Blocks (UDBs) in PSoC

Creator, as required.

2

To eliminate the need for excessive CPU intervention and

2

overhead, I C specific support is provided for status detection

and generation of framing bits. I C operates as a slave, a master,

2

or multimaster (Slave and Master). In slave mode, the unit

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

Timer/Counter/PWM features include:

■ 16-bit timer/counter/PWM (down count only)

■ Selectable clock source

■ PWM comparator (configurable for LT, LTE, EQ, GTE, GT)

■ Period reload on start, reset, and terminal count

■ Interrupt on terminal count, compare true, or capture

■ Dynamic counter reads

2

externally generated Start conditions. I C interfaces through the

DSI routing and allows direct connections to any GPIO or SIO

pins.

2

I C features include:

■ Slave and Master, Transmitter, and Receiver operation

■ Byte processing for low CPU overhead

■ Timer capture mode

■ Count while enable signal is asserted mode

■ Free run mode

■ Interrupt or polling CPU interface

■ Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)

■ One-shot mode (stop at end of period)

■ Complementary PWM outputs with deadband

■ PWM output kill

■ 7 or 10-bit addressing (10-bit addressing requires firmware

support)

■ SMBus operation (through firmware support - SMBus

supported in hardware in UDBs)

Figure 7-21. Timer/Counter/PWM

Clock

Reset

Enable

Capture

Kill

Data transfers follow the format shown in Figure 7-22. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

However, if a master still wishes to communicate on the bus, it

can generate a repeated START condition (Sr) and address

another slave without first generating a STOP condition. Various

combinations of read/write formats are then possible within such

IRQ

Timer / Counter /

PWM 16-bit

TC / Compare!

Compare

2

7.8 I C

2

The I C peripheral provides a synchronous two wire interface

2

designed to interface the PSoC device with a two wire I C serial

Figure 7-22. I²C Complete Transfer Timing

SDA

SCL

8

9

1 - 7

8

9

1 - 7

8

9

1 - 7

START

Condition

STOP

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

7.9 Digital Filter Block

8. Analog Subsystem

Some devices in the CY8C55 family of devices have a dedicated

HW accelerator block used for digital filtering. The DFB has a

dedicated multiplier and accumulator that calculates a 24-bit by

24-bit multiply accumulate in one system clock cycle. This

enables the mapping of a direct form FIR filter that approaches

a computation rate of one FIR tap for each clock cycle. The MCU

can implement any of the functions performed by this block, but

at a slower rate that consumes significant MCU bandwidth.

The analog programmable system creates application specific

combinations of both standard and advanced analog signal

processing blocks. These blocks are then interconnected to

each other and also to any pin on the device, providing a high

level of design flexibility and IP security. The features of the

analog subsystem are outlined here to provide an overview of

capabilities and architecture.

■ Flexible, configurable analog routing architecture provided by

analog globals, analog mux bus, and analog local buses

The PSoC Creator interface provides a wizard to implement FIR

and IIR digital filters with coefficients for LPF, BPF, HPF, Notch

and arbitrary shape filters. 64 pairs of data and coefficients are

stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of

either FIR or IIR formulation.

■ High resolution Delta-Sigma ADC

■ Two successive approximation (SAR) ADCs

■ Four 8-bit DACs that provide either voltage or current output

Figure 7-23. DFB Application Diagram (pwr/gnd not shown)

■ FourcomparatorswithoptionalconnectiontoconfigurableLUT

outputs

BUSCLK

read_data

write_data

Data

Source

(PHUB)

■ Four configurable switched capacitor/continuos time (SC/CT)

blocks for functions that include opamp, unity gain buffer,

programmable gain amplifier, transimpedance amplifier, and

mixer

System

Bus

addr

Digital

Routing

Digital Filter

Block

Data

Dest

(PHUB)

■ Four opamps for internal use and connection to GPIO that can

DMA

Request

be used as high current output buffers

DMA

CTRL

■ CapSense subsystem to enable capacitive touch sensing

■ Precision reference for generating an accurate analog voltage

for internal analog blocks

The typical use model is for data to be supplied to the DFB over

the system bus from another on-chip system data source such

as an ADC. The data typically passes through main memory or

is directly transferred from another chip resource through DMA.

The DFB processes this data and passes the result to another

on chip resource such as a DAC or main memory through DMA

on the system bus.

Data movement in or out of the DFB is typically controlled by the

system DMA controller but can be moved directly by the MCU.

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Figure 8-1. Analog Subsystem Block Diagram

SAR

ADC

SAR

ADC

DAC

A

N

A

L

O

G

A

N

A

L

O

G

Precision

Reference

SC/CT Block

R

O

U

T

I

R

O

U

T

I

GPIO

Port

GPIO

Port

SC/CT Block

N

G

N

G

Comparators

CMP CMP

CMP

CapSense Subsystem

Config&

Status

Registers

Analog

Interface

PHUB

CPU

DSI

Array

Clock

Distribution

Decimator

The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and

various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries

that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage

DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the

communication between the analog peripheral and CPU/Memory.

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

■ Eight analog local buses (abus) to route signals between the

different analog blocks

8.1 Analog Routing

The CY8C38 family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks.

■ Multiplexers and switches for input and output selection of the

analog blocks

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the CY8C38 family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-2. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-2.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

8.1.1 Features

■ Flexible, configurable analog routing architecture

■ 16 analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks

■ Each GPIO is connected to one analog global and one analog

mux bus

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Figure 8-2. CY8C55 Analog Interconnect

*

swinp

*

swinn

*

AMUXBUSR

AMUXBUSL

AGR[4]

AGR[5]

AGL[4]

AGL[5]

AGL[6]

AGL[7]

AGR[6]

AGR[7]

ExVrefL

ExVrefL1

ExVrefL2

44

swinp

swinn

GPIO

P3[5]

GPIO

P3[4]

GPIO

P3[3]

GPIO

P3[2]

GPIO

P3[1]

GPIO

P3[0]

GPXT

opamp3

swfol

opamp1

swfol

opamp0

swfol

opamp2

swfol

swinp

swinn

0123

3210

76543210

01234567

GPIO

P0[4]

GPIO

P0[5]

GPIO

P0[6]

GPIO

swinp

swinn

LPF

swout

in0

in1

abuf_vref_int

(1.024V)

abuf_vref_int

(1.024V)

i0

i2

*

5

ExVrefR

swin

out0

out1

comp0

comp1

+

-

+

-

*

P0[7]

i3

i1

COMPARATOR

cmp0_vref

(1.024V)

cmp0_vref

(1.024V)

+

-

+

-

GPIO

P4[2]

GPIO

P4[3]

GPIO

cmp_muxvn[1:0]

vref_cmp1

comp2

90 comp3

cmp1_vref

(0.256V)

*

bg_vda_res_en

P15[1]

GPXT

P15[0]

bg_vda_swabusl0

Vdda

Vdda/2

out

ref

in

out

ref

in

refbuf_vref1 (1.024V)

CAPSENSE

refbufl

refbuf_vref1 (1.024V)

refbuf_vref2 (1.2V)

*

refbuf_vref2 (1.2V)

refbufr

refsel[1:0]

P4[4]

GPIO

P4[5]

GPIO

P4[6]

GPIO

P4[7]

vssa

Vssa

sc0

Vin

Vref

out

sc1

Vin

Vref

sc2_bgref

(1.024V)

sc0_bgref

(1.024V)

*

out

sc1_bgref

(1.024V)

sc3_bgref

(1.024V)

Vccd

SC/CT

Vin

Vref

out

sc2

Vin

Vref

out

sc3

*

Vssd

*

104

*

Vccd

Vddd

*

Vssd

ABUSL0

ABUSL1

ABUSL2

ABUSL3

ABUSR0

ABUSR1

ABUSR2

ABUSR3

*

Vddd

GPIO

P6[0]

GPIO

v0

i0

v1

DAC1

i1

USB IO

DAC0

*

P15[7]

VIDAC

USB IO

v2

i2

36

v3

DAC3

i3

*

DAC2

P15[6]

GPIO

P6[1]

GPIO

P6[2]

GPIO

P6[3]

GPIO

P15[4]

GPIO

P15[5]

GPIO

P2[0]

GPIO

P2[1]

GPIO

P2[2]

GPIO

dac_vref (0.256V)

P5[7]

GPIO

P5[6]

GPIO

P5[5]

GPIO

P5[4]

SIO

P12[7]

SIO

P12[6]

GPIO

vcmsel[1:0]

en_resvpwra

+

DSM0

vpwra

vpwra/2

dsm0_vcm_vref1

(0.8V)

DSM

refs

-

vssa

28

vcm

qtz_ref

vref_vss_ext

dsm0_vcm_vref2 (0.7V)

dsm0_qtz_vref2 (1.2V)

dsm0_qtz_vref1 (1.024V)

Vdda

Vdda/4

ExVrefL

ExVrefR

refmux[2:0]

en_resvda

*

P1[7]

GPIO

AMUXBUSL

AMUXBUSR

76543210

0123

ANALOG

BUS

*

P1[6]

01234567

3210

ANALOG

ANALOG ANALOG

BUS GLOBALS

*

P2[3]

GPIO

P2[4]

GLOBALS

*

VBE

TS

ADC

*

:

Vss ref

Vddio2

LPF

AGR[3]

AGR[2]

AGL[3]

AGL[2]

AGR[1]

AGL[1]

AGR[0]

AGL[0]

AMUXBUSR

AMUXBUSL

*

13

Mux Group

*

Switch Group

Connection

*

Switch Resistance

Notes:

Small ( ~870 Ohms )

Large ( ~200 Ohms)

* Denotes pins on all packages

LCD signals are not shown.

Rev #51

2-April-2010

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

Analog local buses (abus) are routing resources located within

the analog subsystem and are used to route signals between

different analog blocks. There are eight abus routes in CY8C38,

four in the left half (abusl [0:3]) and four in the right half (abusr

[0:3]) as shown in Figure 8-2. Using the abus saves the analog

globals and analog mux buses from being used for

8.2.1 Functional Description

The ADC connects and configures three basic components,

input buffer, delta-sigma modulator, and decimator. The basic

block diagram is shown in Figure 8-4. The signal from the input

muxes is delivered to the delta-sigma modulator either directly or

through the input buffer. The delta-sigma modulator performs the

actual analog to digital conversion. The modulator over-samples

the input and generates a serial data stream output. This high

speed data stream is not useful for most applications without

some type of post processing, and so is passed to the decimator

through the Analog Interface block. The decimator converts the

high speed serial data stream into parallel ADC results. The

interconnecting the analog blocks.

Multiplexers and switches exist on the various buses to direct

signals into and out of the analog blocks. A multiplexer can have

only one connection on at a time, whereas a switch can have

multiple connections on simultaneously. In Figure 8-2,

multiplexers are indicated by grayed ovals and switches are

indicated by transparent ovals.

4

modulator/decimator frequency response is [(sin x)/x] ; a typical

frequency response is shown in Figure 8-5.

8.2 Delta-sigma ADC

Figure 8-4. Delta-sigma ADC Block Diagram

The CY8C38 device contains one delta-sigma ADC. This ADC

offers differential input, high resolution and excellent linearity,

making it a good ADC choice for both audio signal processing

and measurement applications. The converter's nominal

operation is 16 bits at 48 ksps. The ADC can be configured to

output 20-bit resolution at data rates of up to 187 sps. At a fixed

clock rate, resolution can be traded for faster data rates as

shown in Table 8-1 and Figure 8-3.

Positive

Input Mux

Delta

Sigma

Modulator

Input

Buffer

12 to 20 Bit

Result

Decimator

(Analog Routing)

Negative

Input Mux

EOC

SOC

Table 8-1. Delta-sigma ADC Performance

MaximumSampleRate

Figure 8-5. Delta-sigma ADC Frequency Response, Normal-

ized to Output, Sample Rate = 48 kHz

Bits

SINAD (dB)

(sps)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20

16

12

8

187

–

48 k

84

66

43

192 k

384 k

Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V

1000000

100000

10000

1000

100

1,000

10,000

100,000

1,000,000

Input Frequency, Hz

Input frequency, Hz

Resolution and sample rate are controlled by the Decimator.

Data is pipelined in the decimator; the output is a function of the

last four samples. When the input multiplexer is switched, the

output data is not valid until after the fourth sample after the

switch.

Continuous

Multi-Sample

100

10

1

Multi-SampleTurbo

8.2.2 Operational Modes

The ADC can be configured by the user to operate in one of four

modes: Single Sample, Multi Sample, Continuos, or Multi

Sample (Turbo). All four modes are started by either a write to

the start bit in a control register or an assertion of the Start of

Conversion (SoC) signal. When the conversion is complete, a

status bit is set and the output signal End of Conversion (EoC)

asserts high and remains high until the value is read by either the

DMA controller or the CPU.

6

8

10

12

14

16

18

20

22

Resolution,bits

Resolution, bits

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

8.2.2.1 Single Sample

Figure 8-6. SAR ADC Block Diagram

In Single Sample mode, the ADC performs one sample

conversion on a trigger. In this mode, the ADC stays in standby

state waiting for the SoC signal to be asserted. When SoC is

signaled the ADC performs four successive conversions. The

first three conversions prime the decimator. The ADC result is

valid and available after the fourth conversion, at which time the

EoC signal is generated. To detect the end of conversion, the

system may poll a control register for status. When the transfer

is done the ADC reenters the standby state where it stays until

another SoC event.

vin

S/H

DAC

array

SAR

digital

comparator

D0:D11

vrefp

vrefn

autozero

reset

clock

power

filtering

POWER

GROUND

vrefp

vrefn

8.2.2.2 Continuous

Continuous sample mode is used to take multiple successive

samples of a single input signal. Multiplexing multiple inputs

should not be done with this mode. There is a latency of three

conversion times before the first conversion result is available.

This is the time required to prime the decimator. After the first

result, successive conversions are available at the selected

sample rate.

The input is connected to the analog globals and muxes. The

frequency of the clock is 16 times the sample rate; the maximum

clock rate is 16 MHz.

8.3.2 Conversion Signals

Writing a start bit or assertion of a start of frame (SOF) signal is

used to start a conversion. SOF can be used in applications

where the sampling period is longer than the conversion time, or

when the ADC needs to be synchronized to other hardware. This

signal is optional and does not need to be connected if the SAR

ADC is running in a continuous mode. A digital clock or UDB

output can be used to drive this input. When the SAR is first

powered up or awakened from any of the sleeping modes, there

is a power up wait time of 10 µs before it is ready to start the first

conversion.

8.2.2.3 Multi Sample

Multi sample mode is similar to continuous mode except that the

ADC is reset between samples. This mode is useful when the

input is switched between multiple signals. The decimator is

re-primed between each sample so that previous samples do not

affect the current conversion. Upon completion of a sample, the

next sample is automatically initiated. The results can be

transferred using either firmware polling, interrupt, or DMA.

When the conversion is complete, a status bit is set and the

output signal end of frame (EOF) asserts and remains asserted

until the value is read by either the DMA controller or the CPU.

The EOF signal may be used to trigger an interrupt or a DMA

request.

8.2.2.4 Multi Sample (Turbo)

The multi sample (turbo) mode operates identical to the

Multi-sample mode for resolutions of 8 to 16 bits. For resolutions

of 17 to 20 bits, the performance is about four times faster than

the multi sample mode, because the ADC is only reset once at

the end of conversion.

8.3.3 Operational Modes

A ONE_SHOT control bit is used to set the SAR ADC conversion

mode to either continuous or one conversion per SOF signal.

DMA transfer of continuous samples, without CPU intervention,

is supported.

More information on output formats is provided in the Technical

Reference Manual.

8.2.3 Start of Conversion Input

8.4 Comparators

The SoC signal is used to start an ADC conversion. A digital

clock or UDB output can be used to drive this input. It can be

used when the sampling period must be longer than the ADC

conversion time or when the ADC must be synchronized to other

hardware. This signal is optional and does not need to be

connected if ADC is running in a continuous mode.

The CY8C55 family of devices contains four comparators.

Comparators have these features:

■ Input offset factory trimmed to less than 5 mV

■ Rail-to-rail common mode input range (V

to V

)

SSA

CCA

■ Speed and power can be traded off by using one of three

modes: fast, slow, or ultra low power

8.3 Successive Approximation ADC

The CY8C55 family of devices has two Successive

■ Comparator outputs can be routed to look up tables to perform

simple logic functions and can also be routed to digital blocks

Approximation (SAR) ADCs. These ADCs are 12-bit at up to 1

Msps, with single-ended or differential inputs, making them

useful for a wide variety of sampling and control applications.

■ The positive input ofthe comparators may be optionally passed

through a low pass filter. Two filters are provided

■ Comparator inputs can be connections to GPIO, DAC outputs

8.3.1 Functional Description

and SC block outputs

In a SAR ADC an analog input signal is sampled and compared

with the output of a DAC. A binary search algorithm is applied to

the DAC and used to determine the output bits in succession

from MSB to LSB. A block diagram of one SAR ADC is shown in

Figure 8-6.

Document Number: 001-66235 Rev. **

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PRELIMINARY

PSoC^®5: CY8C55 Family Datasheet

8.4.1 Input and Output Interface

The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus

and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The

output of that LUT is routed to the UDB DSI.

Figure 8-7. Analog Comparator

ANAIF

From

Analog

Routing

+

comp0

+

_

From

Analog

Routing

_

comp1

From

Analog

Routing

+

comp3

_

+

From

Analog

Routing

comp2

_

4

LUT0

LUT1

LUT2

LUT3

UDBs

8.4.2 LUT

Table 8-2. LUT Function vs. Program Word and Inputs

The CY8C55 family of devices contains four LUTs. The LUT is a

two input, one output lookup table that is driven by any one or

two of the comparators in the chip. The output of any LUT is

routed to the digital system interface of the UDB array. From the

digital system interface of the UDB array, these signals can be

connected to UDBs, DMA controller, I/O, or the interrupt

controller.

Control Word

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

Output (A and B are LUT inputs)

FALSE (‘0’)

A AND B

A AND (NOT B)

A

(NOT A) AND B

B

The LUT control word written to a register sets the logic function

on the output. The available LUT functions and the associated

control word is shown in Table 8-2.

A XOR B

A OR B

1000b

1001b

1010b

1011b

1100b

1101b

1110b

A NOR B

A XNOR B

NOT B

A OR (NOT B)

NOT A

(NOT A) OR B

A NAND B

TRUE (‘1’)

1111b

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operation at low current output, within 50 mV of the rails. When

driving high current loads (about 25 mA) the output voltage may

only get within 500 mV of the rails.

8.5 Opamps

The CY8C55 family of devices contain four general purpose

opamps.

8.6 Programmable SC/CT Blocks

Figure 8-8. Opamp

The CY8C55 family of devices contains four switched

capacitor/continuous time (SC/CT) blocks. Each switched

capacitor/continuous time block is built around a single rail-to-rail

high bandwidth opamp.

GPIO

Analog

Global Bus

Switched capacitor is a circuit design technique that uses

capacitors plus switches instead of resistors to create analog

functions. These circuits work by moving charge between

capacitors by opening and closing different switches.

Nonoverlapping in phase clock signals control the switches, so

that not all switches are ON simultaneously.

Opamp

Analog

Global Bus

GPIO

VREF

Analog

Internal Bus

=

Analog Switch

GPIO

The PSoC Creator tool offers a user friendly interface, which

allows you to easily program the SC/CT blocks. Switch control

and clock phase control configuration is done by PSoC Creator

so users only need to determine the application use parameters

The opamp is uncommitted and can be configured as a gain

stage or voltage follower on external or internal signals.

such as gain, amplifier polarity, V

connection, and so on.

REF

See Figure 8-9. In any configuration, the input and output signals

can all be connected to the internal global signals and monitored

with an ADC, or comparator. The configurations are

The same opamps and block interfaces are also connectable to

an array of resistors which allows the construction of a variety of

continuous time functions.

implemented with switches between the signals and GPIO pins.

The opamp and resistor array is programmable to perform

various analog functions including

Figure 8-9. Opamp Configurations

a) Voltage Follower

■ Naked Operational Amplifier - Continuous Mode

■ Unity-Gain Buffer - Continuous Mode

■ Programmable Gain Amplifier (PGA) - Continuous Mode

■ Transimpedance Amplifier (TIA) - Continuous Mode

■ Up/Down Mixer - Continuous Mode

Opamp

Vout to Pin

Vin

■ Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode

■ First Order Analog to Digital Modulator - Switched Cap Mode

b) External Uncommitted

Opamp

8.6.1 Naked Opamp

Vout to GPIO

Opamp

The Naked Opamp presents both inputs and the output for

connection to internal or external signals. The opamp has a unity

gain bandwidth greater than 6.0 MHz and output drive current up

to 650 µA. This is sufficient for buffering internal signals (such as

DAC outputs) and driving external loads greater than 7.5 kohms.

Vp to GPIO

Vn to GPIO

8.6.2 Unity Gain

c) Internal Uncommitted

Opamp

The Unity Gain buffer is a Naked Opamp with the output directly

connected to the inverting input for a gain of 1.00. It has a -3 dB

bandwidth greater than 6.0 MHz.

Vn

8.6.3 PGA

To Internal Signals

Vout to Pin

GPIO Pin

Opamp

The PGA amplifies an external or internal signal. The PGA can

be configured to operate in inverting mode or noninverting mode.

The PGA function may be configured for both positive and

negative gains as high as 50 and 49 respectively. The gain is

adjusted by changing the values of R1 and R2 as illustrated in

Figure 8-10. The schematic in Figure 8-10 shows the

Vp

The opamp has three speed modes, slow, medium, and fast. The

slow mode consumes the least amount of quiescent power and

the fast mode consumes the most power. The inputs are able to

swing rail-to-rail. The output swing is capable of rail-to-rail

configuration and possible resistor settings for the PGA. The

gain is switched from inverting and non inverting by changing the

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shared select value of the both the input muxes. The bandwidth

for each gain case is listed in Table 8-3.

Figure 8-11. Continuous Time TIA Schematic

R

fb

Table 8-3. Bandwidth

Gain

1

Bandwidth

6.0 MHz

340 kHz

220 kHz

215 kHz

I

in

24

48

50

V

out

V

ref

Figure 8-10. PGA Resistor Settings

The TIA configuration is used for applications where an external

sensor's output is current as a function of some type of stimulus

such as temperature, light, magnetic flux etc. In a common

application, the voltage DAC output can be connected to the

R1

R2

V_in

0

1

V_ref

20 k or 40 k

20 k to 980 k

V

TIA input to allow calibration of the external sensor bias

REF

current by adjusting the voltage DAC output voltage.

S

8.7 LCD Direct Drive

V_ref

V_in

0

1

The PSoC Liquid Crystal Display (LCD) driver system is a highly

configurable peripheral designed to allow PSoC to directly drive

a broad range of LCD glass. All voltages are generated on chip,

eliminating the need for external components. With a high

multiplex ratio of up to 1/16, the CY8C55 family LCD driver

system can drive a maximum of 736 segments. The PSoC LCD

driver module was also designed with the conservative power

budget of portable devices in mind, enabling different LCD drive

modes and power down modes to conserve power.

The PGA is used in applications where the input signal may not

be large enough to achieve the desired resolution in the ADC, or

dynamic range of another SC/CT block such as a mixer. The gain

is adjustable at runtime, including changing the gain of the PGA

prior to each ADC sample.

8.6.4 TIA

PSoC Creator provides an LCD segment drive component. The

component wizard provides easy and flexible configuration of

LCD resources. You can specify pins for segments and

commons along with other options. The software configures the

device to meet the required specifications. This is possible

because of the programmability inherent to PSoC devices.

The Transimpedance Amplifier (TIA) converts an internal or

external current to an output voltage. The TIA uses an internal

feedback resistor in a continuous time configuration to convert

input current to output voltage. For an input current Iin, the output

voltage is Iin x Rfb +V

, where V

is the value placed on the

REF

non inverting input. The feedback resistor Rfb is programmable

between 20 KΩ and 1 MΩ through a configuration register.

Table 8-4 shows the possible values of Rfb and associated

configuration settings.

Key features of the PSoC LCD segment system are:

■ LCD panel direct driving

■ Type A (standard) and Type B (low power) waveform support

■ Wide operating voltage range support (2 V to 5 V) for LCD

panels

■ Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels

■ Internal biasvoltage generation through internal resistor ladder

■ Up to 62 total common and segment outputs

■ Up to 1/16 multiplex for a maximum of 16 backplane/common

outputs

■ Up to 62 front plane/segment outputs for direct drive

■ Drives up to 736 total segments (16 backplane x 46 front plane)

■ Up to 64 levels of software controlled contrast

Table 8-4. Feedback Resistor Settings

Configuration Word

Nominal R (KΩ)

fb

000b

001b

010b

011b

100b

101b

110b

111b

20

30

40

60

120

250

500

1000

■ Ability to move display data from memory buffer to LCD driver

through DMA (without CPU intervention)

■ Adjustable LCD refresh rate from 10 Hz to 150 Hz

■ Ability to invert LCD display for negative image

■ Three LCD driver drive modes, allowing power optimization

■ LCD driver configurable to be active when PSoC is in limited

active mode

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PSoC^®5: CY8C55 Family Datasheet

Figure 8-12. LCD System

voltages plus ground, based on the selected bias ratio. The bias

voltages are driven out to GPIO pins on a dedicated LCD bias

bus, as required.

LCD

DAC

Global

Clock

8.8 CapSense

The CapSense system provides a versatile and efficient means

for measuring capacitance in applications such as touch sense

buttons, sliders, proximity detection, etc. The CapSense system

uses a configuration of system resources, including a few

hardware functions primarily targeted for CapSense. Specific

resource usage is detailed in the CapSense component in PSoC

Creator.

UDB

LCD Driver

Block

Display

DMA

RAM

A capacitive sensing method using a Delta-Sigma Modulator

(CSD) is used. It provides capacitance sensing using a switched

capacitor technique with a delta-sigma modulator to convert the

sensing current to a digital code.

PHUB

8.7.1 LCD Segment Pin Driver

8.9 Temp Sensor

Each GPIO pin contains an LCD driver circuit. The LCD driver

buffers the appropriate output of the LCD DAC to directly drive

the glass of the LCD. A register setting determines whether the

pin is a common or segment. The pin’s LCD driver then selects

one of the six bias voltages to drive the I/O pin, as appropriate

for the display data.

Die temperature is used to establish programming parameters

for writing flash. Die temperature is measured using a dedicated

sensor based on a forward biased transistor. The temperature

sensor has its own auxiliary ADC.

8.10 DAC

8.7.2 Display Data Flow

The CY8C55 parts contain four Digital to Analog Convertors

(DACs). Each DAC is 8-bit and can be configured for either

voltage or current output. The DACs support CapSense, power

supply regulation, and waveform generation. Each DAC has the

following features.

The LCD segment driver system reads display data and

generates the proper output voltages to the LCD glass to

produce the desired image. Display data resides in a memory

buffer in the system SRAM. Each time you need to change the

common and segment driver voltages, the next set of pixel data

moves from the memory buffer into the Port Data Registers via

DMA.

■ Adjustable voltage or current output in 255 steps

■ Programmable step size (range selection)

■ Eight bits of calibration to correct ± 25% of gain error

■ Source and sink option for current output

■ 8 Msps conversion rate for current output

■ 1 Msps conversion rate for voltage output

■ Monotonic in nature

8.7.3 UDB and LCD Segment Control

A UDB is configured to generate the global LCD control signals

and clocking. This set of signals is routed to each LCD pin driver

through a set of dedicated LCD global routing channels. In

addition to generating the global LCD control signals, the UDB

also produces a DMA request to initiate the transfer of the next

frame of LCD data.

■ Data and strobe inputs can be provided by the CPU or DMA,

or routed directly from the DSI

8.7.4 LCD DAC

The LCD DAC generates the contrast control and bias voltage

for the LCD system. The LCD DAC produces up to five LCD drive

■ Dedicated low-resistance output pin for high-current mode

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Figure 8-13. DAC Block Diagram

I _sourceRange

1x,8x, 64x

Vout

Reference

Source

Scaler

Iout

R

3R

I _sinkRange

1x,8x, 64x

8.10.1 Current DAC

8.12 Sample and Hold

The current DAC (IDAC) can be configured for the ranges 0 to

32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be

configured to source or sink current.

The main application for a sample and hold, is to hold a value

stable while an ADC is performing a conversion. Some

applications require multiple signals to be sampled

simultaneously, such as for power calculations (V and I).

8.10.2 Voltage DAC

Figure 8-15. Sample and Hold Topology

(Φ1 and Φ2 are opposite phases of a clock)

For the voltage DAC (VDAC), the current DAC output is routed

through resistors. The two ranges available for the VDAC are 0

to 1.024 V and 0 to 4.096 V. In voltage mode any load connected

to the output of a DAC should be purely capacitive (the output of

the VDAC is not buffered).

Φ₁

C₁

C₂

V ⁱ

V_ref

n

V _out

Φ ₁

Φ₂

Φ²

Φ ₂

8.11 Up/Down Mixer

In continuous time mode, the SC/CT block components are used

to build an up or down mixer. Any mixing application contains an

input signal frequency and a local oscillator frequency. The

polarity of the clock, Fclk, switches the amplifier between

inverting or noninverting gain. The output is the product of the

input and the switching function from the local oscillator, with

frequency components at the local oscillator plus and minus the

signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level

frequency components at odd integer multiples of the local

oscillator frequency. The local oscillator frequency is provided by

the selected clock source for the mixer.

Φ¹

Φ₂

Φ₁

Φ₂

Φ ₁

Φ²

V _ref

V

ref

C₃

C₄

8.12.1 Down Mixer

The S+H can be used as a mixer to down convert an input signal.

This circuit is a high bandwidth passive sample network that can

sample input signals up to 14 MHz. This sampled value is then

held using the opamp with a maximum clock rate of 4 MHz. The

output frequency is at the difference between the input frequency

and the highest integer multiple of the Local Oscillator that is less

than the input.

Continuous time up and down mixing works for applications with

input signals and local oscillator frequencies up to 1 MHz.

Figure 8-14. Mixer Configuration

C2 = 1.7 pF

8.12.2 First Order Modulator - SC Mode

C1 = 850 fF

A first order modulator is constructed by placing the switched

capacitor block in an integrator mode and using a comparator to

provide a 1-bit feedback to the input. Depending on this bit, a

reference voltage is either subtracted or added to the input

signal. The block output is the output of the comparator and not

the integrator in the modulator case. The signal is downshifted

and buffered and then processed by a decimator to make a

delta-sigma converter or a counter to make an incremental

converter. The accuracy of the sampled data from the first-order

modulator is determined from several factors. The main

application for this modulator is for a low frequency ADC with

high accuracy. Applications include strain gauges,

R

^mix0 20 k or 40 k

sc_clk

R^mix0 20 k or 40 k

Vin

Vout

0

1

Vref

sc_clk

thermocouples, precision voltage, and current measurement.

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PSoC^®5: CY8C55 Family Datasheet

pins are useful for in system programming of USB solutions that

would otherwise require a separate programming connector.

One pin is used for the data clock and the other is used for data

input and output. SWD can be enabled on only one of the pin

pairs at a time. SWD is used for debugging or for programming

the flash memory. In addition, the SWD interface supports the

SWV trace output if desired.

9. Programming, Debug Interfaces,

Resources

The Cortex-M3 has internal debugging components, tightly

integrated with the CPU, providing the following features:

■ JTAG or SWD access

■ Flash Patch and Breakpoint (FPB) block for implementing

breakpoints and code patches

■ Data Watchpoint and Trigger (DWT) block for implementing

9.2 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four pins.

The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU

clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock

frequency for 32-bit transfers, whichever is least. The JTAG

interface is used for programming the flash memory and

debugging.

watchpoints, trigger resources, and system profiling

■ Embedded Trace Macrocell (ETM) for instruction trace

■ InstrumentationTraceMacrocell(ITM)forsupportofprintf-style

debugging

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

JTAG and SWD support all programming and debug features of

the device. The SWV and TRACEPORT provide trace output

from the DWT, ETM, and ITM. TRACEPORT is faster but uses

more pins. SWV is slower but uses only one pin.

Note that, while the debug interface at reset is always SWD, any

standard SWD or JTAG debugging tool can switch from SWD to

4-pin JTAG or vice versa without requiring port acquisition, using

a standard sequence defined by ARM.

When using JTAG pins as standard GPIO, make sure that the

GPIO functionality and PCB circuits do not interfere with JTAG

use.

Cortex-M3 debug and trace functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC interfaces are fully compatible

with industry standard third party tools.

9.3 Debug Features

The CY8C55 supports the following debug features:

■ Halt and single-step the CPU

■ View and change CPU and peripheral registers, and RAM

addresses

■ Six program address breakpoints and two literal access

breakpoints

■ Data watchpoint events to CPU

■ Patch and remap instruction from flash to SRAM

■ Debugging at the full speed of the CPU

■ Debug operations are possible while the device is reset, or in

low power modes

■ CompatiblewithPSoCCreatorandMiniProg3programmerand

debugger

■ Standard JTAG or SWD programming and debugging interface

makes CY8C55 compatible with other popular third-party tools

(for example, ARM / Keil)

All Cortex-M3 debug and trace modules are disabled by default

and can only be enabled in firmware. If not enabled, the only way

to reenable them is to erase the entire device, clear flash

protection, and reprogram the device with new firmware that

enables them. Disabling debug and trace features, robust flash

protection, and hiding custom analog and digital functionality

inside the PSoC device provide a level of security not possible

with multichip application solutions. Additionally, all device

interfaces can be permanently disabled (Device Security) for

applications concerned about phishing attacks due to a

maliciously reprogrammed device. Permanently disabling

interfaces is not recommended in most applications because the

designer then cannot access the device. Because all

9.4 Trace Features

The following trace features are supported:

■ Instruction trace

■ Data watchpoint on access to data address, address range, or

programming, debug, and test interfaces are disabled when

Device Security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

data value

9.1 SWD Interface

■ Trace trigger on data watchpoint

■ Debug exception trigger

■ Code profiling

■ Counters for measuring clock cycles, folded instructions,

load/store operations, sleep cycles, cycles per instruction,

interrupt overhead

SWD is the default debug interface and is always enabled after

any reset, including POR. This means that the two pins used for

SWD (P1.0 and P1.1) should not generally be used for any other

purpose since they always revert to being SWD pins after any

reset.

■ Interrupt events trace

The SWD interface is the preferred alternative to JTAG, as it

requires only two pins. The SWD clock frequency can be up to

1/3 of the CPU clock frequency.

■ Software event monitoring, “printf-style” debugging

SWD uses two pins, either two port 1 pins or the USBIO D+ and

D- pins. The SWD pins cannot be used as GPIO. The USBIO

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PSoC^®5: CY8C55 Family Datasheet

majority is not reached. When the output is 1, the Write Once NV

latch locks the part out of Debug and Test modes; it also

permanently gates off the ability to erase or alter the contents of

the latch. Matching all bits is intentionally not required, so that

single (or few) bit failures do not deassert the WOL output. The

state of the NVL bits after wafer processing is truly random with

no tendency toward 1 or 0.

The WOL only locks the part after the correct 32-bit key

(0x50536F43) is loaded into the NVL's volatile memory,

programmed into the NVL's nonvolatile cells, and the part is

reset. The output of the WOL is only sampled on reset and used

to disable the access. This precaution prevents anyone from

reading, erasing, or altering the contents of the internal memory.

9.5 SWV and TRACEPORT Interfaces

The SWV and TRACEPORT interfaces provide trace data to a

debug host via the Cypress MiniProg3 or an external trace port

analyzer. The 5 pin TRACEPORT is used for rapid transmission

of large trace streams. The single pin SWV mode is used to

minimize the number of trace pins. SWV is shared with a JTAG

pin. If debugging and tracing are done at the same time then

SWD may be used with either SWV or TRACEPORT, or JTAG

may be used with TRACEPORT, as shown in Table 9-1.

Table 9-1. Debug Configurations

Debug and Trace

GPIO Pins Used

Configuration

The user can write the key into the WOL to lock out external

access only if no flash protection is set (see “Flash Security”

section on page 16). However, after setting the values in the

WOL, a user still has access to the part until it is reset. Therefore,

a user can write the key into the WOL, program the flash

protection data, and then reset the part to lock it.

If the device is protected with a WOL setting, Cypress cannot

perform failure analysis and, therefore, cannot accept RMAs

from customers. The WOL can be read out via Serial Wire Debug

(SWD) port to electrically identify protected parts. The user can

write the key in WOL to lock out external access only if no flash

protection is set. For more information on how to take full

advantage of the security features in PSoC see the PSoC 5

TRM.

All debug and trace

disabled

0

JTAG

4

2

1

5

9

3

7

SWD

SWV

TRACEPORT

JTAG + TRACEPORT

SWD + SWV

SWD + TRACEPORT

9.6 Programming Features

Disclaimer

The JTAG or SWD interface provides full programming support.

The entire device can be erased, programmed, and verified.

Designers can increase flash protection levels to protect

firmware IP. Flash protection can only be reset after a full device

erase. Individual flash blocks can be erased, programmed, and

verified, if block security settings permit.

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress datasheets. Cypress believes that its family of

products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

9.7 Device Security

PSoC 5 offers an advanced security feature called device

security, which permanently disables all test, programming, and

debug ports, protecting your application from external access.

The device security is activated by programming a 32-bit key

(0x50536F43) to a Write Once Latch (WOL). The WOL must be

programmed at V

≤ 3.3 V.

DDD

The Write Once Latch is a type of nonvolatile latch (NVL). The

cell itself is an NVL with additional logic wrapped around it. Each

WOL device contains four bytes (32 bits) of data. The wrapper

outputs a ‘1’ if a super-majority (28 of 32) of its bits match a

pre-determined pattern (0x50536F43); it outputs a ‘0’ if this

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PSoC^®5: CY8C55 Family Datasheet

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

10. Development Support

The CY8C55 family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit

Technical Reference Manual: PSoC Creator makes designing

with PSoC as easy as dragging a peripheral onto a schematic,

but, when low level details of the PSoC device are required, use

the technical reference manual (TRM) as your guide.

Note Visit www.arm.com for detailed documentation about the

Cortex-M3 CPU.

psoc.cypress.com/getting-started to find out more.

10.1 Documentation

A suite of documentation, to ensure that you can find answers to

your questions quickly, supports the CY8C55 family. This section

contains a list of some of the key documents.

10.2 Online

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

10.3 Tools

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component datasheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

With industry standard cores, programming, and debugging

interfaces, the CY8C55 family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

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PSoC^®5: CY8C55 Family Datasheet

11. Electrical Specifications

Specifications are valid for -40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC

Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example

Peripherals” section on page 32 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings DC Specifications

Parameter

Description

Storage temperature

Conditions

Min

Typ

Max

Units

T

Recommended storage temper-

ature is +25 °C ±25 °C. Extended

duration storage temperatures

above 85 °C degrade reliability.

–55

25

100

°C

STG

V

Analog supply voltage relative to

–0.5

–

6

V

DDA

V

SSA

Digital supply voltage relative to

DDD

V

SSD

V

I/O supply voltage relative to V

–0.5

–

6

V

DDIO

CCA

CCD

SSA

SSD

Direct analog core voltage input

Direct digital core voltage input

Analog ground voltage

1.95

V

– 0.5

V

+

SSD

0.5

SSD

[11]

V

DC input voltage on GPIO

DC input voltage on SIO

Includes signals sourced by V

and routed internal to the pin.

– 0.5

–

V

+

V

GPIO

SIO

DDA

SSD

DDIO

0.5

V

Output disabled

Output enabled

V

– 0.5

–

7

6

V

SSD

V

Voltage at boost converter input

Boost converter supply

0.5

5.5

20

2

V

IND

V

– 0.5

V

BAT

SSD

Ivddio

Current per V

supply pin

–

mA

V

DDIO

Vextref

LU

ADC external reference inputs

Pins P0[3], P3[2]

–

[12]

Latch up current

–140

750

500

140

–

mA

V

ESD

Electrostatic discharge voltage

ESD voltage

Human body model

Charge device model

HBM

CDM

–

V

Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to

maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above

normal operating conditions the device may not operate to specification.

Notes

11. The V

supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V

≤ V

.

DDIO

DDA

12. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

11.2 Device Level Specifications

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.2.1 Device Level Specifications

Table 11-2. DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V

Analog supply voltage and input to analog core

regulator

Analog core regulator enabled

1.8

–

5.5

V

DDA

V

Analog supply voltage, analog regulator bypassed Analog core regulator disabled

Digital supply voltage relative to V Digital core regulator enabled

Digital supply voltage, digital regulator bypassed Digital core regulator disabled

I/O supply voltage relative to V

1.71

1.8

–

1.89

V

DDA

DDD

DDIO

CCA

[13]

V

SSD

DDA

1.71

1.8

–

1.89

[14]

[13]

SSIO

DDA

Direct analog core voltage input (Analog regulator Analog core regulator disabled

bypass)

1.8

1.89

V

Direct digital core voltage input (Digital regulator Digital core regulator disabled

bypass)

1.71

1.8

1.89

V

CCD

[15]

I

Active Mode, V = 1.71 V–5.5 V

DD

Execute from Flash cache, see Cache Controller CPU at 6 MHz

on page 12 and Flash Program Memory on page 16

T = –40 °C

T = 25 °C

T = 85 °C

–

2

–

mA

[16]

Sleep Mode

CPU = OFF

V

= V

= 4.5–5.5 V

= 2.7–3.6 V

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

–

2

–

µA

DD

DDIO

RTC = ON (= ECO32K ON, in low power mode)

[17]

Sleep timer = ON (= ILO ON at 1 kHz)

WDT = OFF

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input, unregulated output

mode

= 1.71–1.95 V T = –40 °C

T = 25 °C

T = 85 °C

Comparator = ON

= 2.7–3.6V

T = 25 °C

CPU = OFF

RTC = OFF

Sleep timer = OFF

WDT = OFF

POR = ON

Boost = OFF

SIO pins in single ended input, unregulated output

mode

[18]

Hibernate Mode

V

= V

= 4.5–5.5 V

T = –40 °C

T = 25 °C

T = 85 °C

–

nA

DD

DDIO

Hibernate mode current

All regulators and oscillators off.

SRAM retention

–

= 2.7 – 3.6 V T = –40 °C

T = 25 °C

–

GPIO interrupts are active

Boost = OFF

300

–

SIO pins in single ended input, unregulated output

mode

T = 85 °C

= 1.71–1.95 V T = –40 °C

T = 25 °C

–

T = 85 °C

–

Notes

13. The power supplies can be brought up in any sequence however once stable Vdda must be greater than or equal to all other supplies.

14. The V supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V

≤ V .

DDA

DDIO

15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in

PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular

system from the device data sheet and component datasheets.

16. If V

and V

are externally regulated, the voltage difference between V

and V

must be less than 50 mV.

CCD

CCA

CCD

CCA

17. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.

Document Number: 001-66235 Rev. **

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[19]

Table 11-3. AC Specifications

Parameter Description

CPU frequency

Bus frequency

ramp rate

Conditions

Min

DC

–

Typ

–

Max

67.01

1

Units

MHz

V/ns

µs

F

1.71 V ≤ V

≤ 5.5 V

CPU

DDD

F

–

BUSCLK

DDD

Svdd

V

–

DD

T

Time from V

/V /V /V

–

10

IO_INIT

DDD DDA CCD CCA

≥ IPOR to I/O ports set to their reset

states

T

Time from V

/V

V

/V

= regulated from V /V ,

DDA DDD

–

66

–

µs

STARTUP

DDD DDA CCD CCA

CCA CCD

≥ PRES to CPU executing code at no PLL used, IMO boot mode 12 MHz typ.

reset vector

T

Wakeup from limited active mode –

Application of non-LVD interrupt to

beginning of execution of next CPU

instruction

20

SLEEP

T

Wakeup form hibernate mode –

Application of external interrupt to

beginning of execution of next CPU

instruction

–

100

µs

HIBERNATE

Notes

18. If V

and V

are externally regulated, the voltage difference between V

and V

must be less than 50 mV.

CCD

CCA

CCD

CCA

19. Based on device characterization (Not production tested).

Document Number: 001-66235 Rev. **

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11.3 Power Regulators

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.3.1 Digital Core Regulator

Table 11-4. Digital Core Regulator DC Specifications

Parameter Description

Input voltage

Conditions

Min

1.8

–

Typ

–

Max

5.5

–

Units

V

DDD

Output voltage

1.80

1

V

CCD

Regulator output capacitor

±10%, X5R ceramic or better. The two V

–

µF

CCD

pins must be shorted together, with as short

a trace as possible, see 6.2 Power System

on page 21

Figure 11-1. Regulators V_CCvs V_DD

Figure 11-2. Digital Regulator PSRR vs Frequency and V_DDy

11.3.2 Analog Core Regulator

Table 11-3. Analog Core Regulator DC Specifications

Parameter

Description

Input voltage

Output voltage

Conditions

Min

1.8

–

Typ

–

1.80

1

Max

5.5

–

Units

V

DDA

CCA

Regulator output capacitor

±10%, X5R ceramic or better

–

µF

Figure 11-3. Analog Regulator PSRR vs Frequency and V_DD

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11.3.3 Inductive Boost Regulator.

Table 11-6. Inductive Boost Regulator DC Specifications

Unless otherwise specified, operating conditions are: V

= 2.4 V, V

= 2.7 V, I

= 40 mA, F

= 400 kHz, L

= 10 µH,

BAT

OUT

SW

BOOST

C

= 22 µF || 0.1 µF

BOOST

Parameter

Description

Input voltage

Includes startup

Conditions

Min

Typ

Max

Units

V

1.8

–

3.6

V

BAT

[20, 21]

I

Load current

V

= 1.8 – 3.6 V, V

= 3.6 – 5.0 V,

= 1.8 – 3.6 V,

–

50

75

mA

OUT

BAT

OUT

external diode

V

= 1.8 – 3.6 V, V

BAT

OUT

internal diode

I

Inductor peak current

Quiescent current

–

700

–

mA

µA

LPK

Q

Boost active mode

200

12

Boost standby mode, 32 khz external crystal

oscillator, I < 1 µA

–

OUT

V

[22, 23]

OUT

Boost voltage range

1.8 V

1.71

1.81

1.90

2.28

2.57

2.85

3.14

3.42

4.75

–

1.80

1.90

2.00

2.40

2.70

3.00

3.30

3.60

5.00

–

1.89

2.00

2.10

2.52

2.84

3.15

3.47

3.78

5.25

3.8

V

1.9 V

2.0 V

V

2.4 V

V

2.7 V

V

3.0 V

V

3.3 V

V

3.6 V

V

5.0 V

External diode required

V

Reg

Load regulation

Line regulation

Efficiency

%

LOAD

–

4.1

LINE

L

= 10 µH

= 22 µH

70

85

–

η

BOOST

82

90

–

Table 11-7. Inductive Boost Regulator AC Specifications

Unless otherwise specified, operating conditions are: V

= 2.4 V, V

= 2.7 V, I

= 40 mA, F

= 400 kHz, L

= 10 µH,

BAT

OUT

SW

BOOST

C

= 22 µF || 0.1 µF.

BOOST

Parameter

Description

Ripple voltage

Conditions

= 400 kHz, I = 10 mA

OUT

Min

Typ

Max

Units

V

= 1.8 V, F

–

100

mV

RIPPLE

OUT

SW

(peak-to-peak)

F

Switching frequency

–

0.1, 0.4,

or 2

–

MHz

SW

Notes

20. For output voltages above 3.6 V, an external diode is required.

21. Maximum output current applies for output voltages ≤ 4x input voltage.

22. Based on device characterization (Not production tested).

23. At boost frequency of 2 MHz, V

is limited to 2 x V

At 400 kHz,V

is limited to 4 x V

.

OUT

BAT.

OUT

BAT

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PSoC^®5: CY8C55 Family Datasheet

Table 11-8. Recommended External Components for Boost Circuit

Parameter

Description

Boost inductor

Conditions

Min

4.7

10

1

Typ

10

22

–

Max

47

–

Units

µH

µF

L

BOOST

[24]

C

Filter capacitor

BOOST

I

External Schottky diode

average forward current

External Schottky diode is required for

A

F

V

> 3.6 V

OUT

V

20

–

V

R

Figure 11-4. Efficiency vs V_OUT

= 30 mA, V ranges from 0.7 V to V

Figure 11-5. Efficiency vs V_BAT

I

, L

= 22 µH

I

= 30 mA, V

= 3.3 V, L = 22 µH

OUT

BAT

OUT BOOST

OUT

BOOST

Figure 11-6. Efficiency vs I_OUT

= 2.4 V, V = 3.3 V

Figure 11-7. Efficiency vs I_OUT

ranges from 0.7 V to 3.3 V, L

V

= 22 µH

BOOST

BAT

OUT

BAT

Note

24. Based on device characterization (Not production tested).

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PSoC^®5: CY8C55 Family Datasheet

Figure 11-8. Efficiency vs Switching Frequency

= 3.3 V, V = 2.4 V, I = 40 mA

V

OUT

BAT

OUT

11.1 Inputs and Outputs

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted. Unless otherwise specified, all charts and graphs show typical values.

11.1.1 GPIO

Table 11-1. GPIO DC Specifications

Parameter

Description

Conditions

CMOS Input, PRT[x]CTL = 0

Min

Typ

–

Max

–

Units

V

Input voltage high threshold

Input voltage low threshold

0.7 × V

V

IH

DDIO

V

–

0.3 ×

IL

V

DDIO

V

Input voltage high threshold

Input voltage low threshold

LVTTL Input, PRT[x]CTL = 1, V

< 2.7 V 0.7 x V

DDIO

–

V

IH

IL

DDIO

≥ 2.7 V

2.0

–

< 2.7 V

–

0.3 x

V

DDIO

V

Input voltage low threshold

Output voltage high

LVTTL Input, PRT[x]CTL = 1, V

≥ 2.7 V

–

0.8

V

IL

DDIO

V

I

= 4 mA at 3.3 V

= 1 mA at 1.8 V

V

– 0.6

– 0.5

–

OH

OL

DDIO

–

V

DDIO

V

Output voltage low

Pull-up resistor

= 8 mA at 3.3 V

= 4 mA at 1.8 V

–

0.6

8.5

2

V

OL

–

V

Rpullup

3.5

–

5.6

–

kΩ

nA

Rpulldown Pull-down resistor

I

Input leakage current (absolute 25 °C, V

= 3.0 V

IL

DDIO

[25]

value)

[25]

C

Input capacitance

GPIOs without opamp outputs

GPIOs with opamp outputs

–

7

18

–

pF

IN

V

Input voltage hysteresis

40

mV

H

[25]

(Schmitt-Trigger)

Idiode

Current through protection diode

–

100

µA

to V

and V

DDIO

Resistance pin to analog global bus

SSIO

Rglobal

Rmux

Note

25 °C, V

= 3.0 V

–

320

220

–

Ω

DDIO

Resistance pin to analog mux bus 25 °C, V

DDIO

25. Based on device characterization (Not production tested).

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Figure 11-9. GPIO Output High Voltage and Current

Figure 11-10. GPIO Output Low Voltage and Current

Table 11-11. GPIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

–

Typ

–

Max

12

Units

ns

[26]

Rise time in Fast Strong Mode

3.3 V V

Cload = 25 pF

DDIO

[26]

TfallF

Fall time in Fast Strong Mode

Cload = 25 pF

–

12

ns

TriseS

TfallS

Rise time in Slow Strong Mode

–

60

ns

[26]

Fall time in Slow Strong Mode

–

60

ns

GPIO output operating frequency

2.7 V < V

< 5.5 V, fast strong drive mode

90/10% V

into 25 pF

–

33

20

7

MHz

DDIO

Fgpioout

1.71 V < V

< 2.7 V, fast strong drive mode 90/10% V

DDIO

3.3 V < V

< 5.5 V, slow strong drive mode 90/10% V

DDIO

1.71 V < V

< 3.3 V, slow strong drive mode 90/10% V

3.5

DDIO

GPIO input operating frequency

1.71 V < V < 5.5 V

Fgpioin

90/10% V

–

66

MHz

DDIO

Figure 11-11. GPIO Output Rise and Fall Times, Fast Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-12. GPIO Output Rise and Fall Times, Slow Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Note

26. Based on device characterization (Not production tested).

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11.1.2 SIO

Table 11-13. SIO DC Specifications

Parameter

Vinmax

Description

Conditions

Min

Typ

Max

Units

Maximum input voltage

All allowed values of Vddio and

Vddd, see Section 11.2.1

–

5.5

V

Vinref

Input voltage reference (differential

input mode)

0.5

–

0.52 × V

V

DDIO

Output voltage reference (regulated output mode)

Voutref

V

> 3.7

< 3.7

1

–

V

– 1

DDIO

V

DDIO

V

– 0.5

DDIO

Input voltage high threshold

GPIO mode

V

CMOS input

0.7 × V

SIO_ref + 0.2

–

V

IH

DDIO

[27]

Differential input mode

Hysteresis disabled

–

Input voltage low threshold

GPIO mode

V

CMOS input

–

0.3 × V

SIO_ref – 0.2

V

IL

DDIO

[27]

Differential input mode

Hysteresis disabled

Output voltage high

Unregulated mode

I

= 4 mA, V

= 1 mA

= 3.3 V

V – 0.4

DDIO

–

V

OH

DDIO

V

OH

[27]

Regulated mode

SIO_ref – 0.65

SIO_ref – 0.3

SIO_ref + 0.2

[27]

Regulated mode

= 0.1 mA

Output voltage low

V

= 3.30 V, I = 25 mA

–

0.8

0.4

8.5

V

OL

DDIO

OL

= 1.80 V, I = 4 mA

–

DDIO

OL

Rpullup

Pull-up resistor

3.5

5.6

kΩ

Rpulldown

Pull-down resistor

I

Input leakage current (absolute

value)

IL

[28]

V

< Vddsio

> Vddsio

25 °C, Vddsio = 3.0 V, V = 3.0 V

–

14

10

7

nA

µA

pF

IH

25 °C, Vddsio = 0 V, V = 3.0 V

IH

[28]

C

Input Capacitance

–

IN

Input voltage hysteresis

(Schmitt-Trigger)

Single ended mode (GPIO mode)

Differential mode

40

35

–

mV

µA

V

[28]

H

–

Current through protection diode to

100

Idiode

V

SSIO

Notes

27. See Figure 6-9 on page 28 and Figure 6-12 on page 31 for more information on SIO reference.

28. Based on device characterization (Not production tested).

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Figure 11-13. SIO Output High Voltage and Current,

Unregulated Mode

Figure 11-14. SIO Output Low Voltage and Current,

Unregulated Mode

Figure 11-15. SIO Output High Voltage and Current, Regulat-

ed Mode

Table 11-16. SIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

Typ

Max

Units

Rise time in fast strong mode

Cload = 25 pF, V

= 3.3 V

–

12

ns

DDIO

[29]

(90/10%)

TfallF

TriseS

TfallS

Fall time in fast strong mode

Cload = 25 pF, V

= 3.3 V

= 3.0 V

–

12

75

60

ns

[29]

(90/10%)

Rise time in slow strong mode Cload = 25 pF, V

[29]

(90/10%)

Fall time in slow strong mode

Cload = 25 pF, V

[29]

(90/10%)

Note

29. Based on device characterization (Not production tested).

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Table 11-16. SIO AC Specifications (continued)

Parameter Description

SIO output operating frequency

2.7 V < V < 5.5 V, Unregu- 90/10% V

Conditions

Min

Typ

Max

Units

into 25 pF

–

33

MHz

DDIO

lated output (GPIO) mode, fast

strong drive mode

1.71 V < V

< 2.7 V, Unregu- 90/10% V

into 25 pF

–

16

5

MHz

DDIO

lated output (GPIO) mode, fast

strong drive mode

3.3 V < V

< 5.5 V, Unregu- 90/10% V

DDIO

lated output (GPIO) mode, slow

strong drive mode

1.71 V < V

lated output (GPIO) mode, slow

< 3.3 V, Unregu- 90/10% V

4

DDIO

Fsioout

strong drive mode

2.7 V < V

Regulated output mode, fast

< 5.5 V,

Output continuously switching

into 25 pF

20

10

2.5

DDIO

strong drive mode

1.71 V < V

Regulated output mode, fast

< 2.7 V,

Output continuously switching

into 25 pF

DDIO

strong drive mode

1.71 V < V

Regulated output mode, slow

< 5.5 V,

Output continuously switching

into 25 pF

DDIO

strong drive mode

SIO input operating frequency

Fsioin

1.71 V < V

< 5.5 V

90/10% V

–

66

MHz

DDIO

Figure 11-16. SIO Output Rise and Fall Times, Fast Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-17. SIO Output Rise and Fall Times, Slow Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

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11.1.3 USBIO

For operation in GPIO mode, the standard range for V

applies, see Device Level Specifications on page 59.

DDD

Table 11-18. USBIO DC Specifications

Parameter

Rusbi

Description

USB D+ pull-up resistance

Static output high

Conditions

Min

0.900

1.425

2.8

Typ

–

Max

1.575

3.090

3.6

Units

kΩ

With idle bus

Rusba

While receiving traffic

–

kΩ

Vohusb

15 kΩ ±5% to Vss, internal pull-up

–

V

enabled

Volusb

Static output low

15 kΩ ±5% to Vss, internal pull-up

enabled

–

0.3

V

Vihgpio

Vilgpio

Vohgpio

Volgpio

Vdi

Input voltage high, GPIO mode

Input voltage low, GPIO mode

Output voltage high, GPIO mode

Output voltage low, GPIO mode

Differential input sensitivity

V

I

≥ 3 V

2

–

0.8

–

V

DDD

= 4 mA, V

≥ 3 V

2.4

–

V

OH

DDD

I

0.3

0.2

2.5

2

V

OL

DDD

|(D+)–(D–)|

–

V

Vcm

Differential input common mode range

Single ended receiver threshold

PS/2 pull-up resistance

0.8

3

V

Vse

V

Rps2

In PS/2 mode, with PS/2 pull-up

enabled

7

kΩ

Rext

Zo

External USB series resistor

In series with each USB pin

21.78

(–1%)

22

22.22

(+1%)

Ω

USB driver output impedance

Including Rext

28

–

44

20

2

Ω

C

USB transceiver input capacitance

pF

nA

IN

I

Input leakage current (absolute value) 25 °C, V

= 3.0 V

–

IL

DDD

Figure 11-18. USBIO Output High Voltage and Current, GPIO

Mode

Figure 11-19. USBIO Output Low Voltage and Current, GPIO

Mode

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Table 11-20. USBIO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Tdrate

Full-speed data rate average bit rate

12 – 0.25%

12

12 +

0.25%

MHz

Tjr1

Tjr2

Receiver data jitter tolerance to next

transition

–8

–5

–

8

ns

Receiver data jitter tolerance to pair

transition

5

Tdj1

Driver differential jitter to next transition

Driver differential jitter to pair transition

–3.5

–4

–

3.5

4

ns

Tdj2

Tfdeop

Source jitter for differential transition to

SE0 transition

–2

5

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

Receiver SE0 interval of EOP

160

82

–

175

–

ns

Width of SE0 interval during differential

transition

14

Fgpio_out GPIO mode output operating frequency 3 V ≤ V

≤ 5.5 V

–

20

6

MHz

ns

DDD

V

= 1.71 V

DDD

Tr_gpio

Tf_gpio

Rise time, GPIO mode, 10%/90% V

V

> 3 V, 25 pF load

= 1.71 V, 25 pF load

> 3 V, 25 pF load

= 1.71 V, 25 pF load

12

40

12

40

DDD DDD

V

ns

DDD

Fall time, GPIO mode, 90%/10% V

V

ns

DDD DDD

V

ns

DDD

Figure11-20. USBIOOutputRiseandFallTimes, GPIOMode,

V_DDD= 3.3 V, 25 pF Load

Table 11-21. USB Driver AC Specifications

Parameter

Tr

Description

Transition rise time

Conditions

Min

–

Typ

–

Max

20

Units

ns

Tf

Transition fall time

–

20

ns

TR

Rise/fall time matching

V

, V

, see USB DC

90%

–

111%

USB_5

USB_3.3

Specifications on page 96

Vcrs

Output signal crossover voltage

1.3

–

2

V

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11.1.4 XRES

Table 11-22. XRES DC Specifications

Parameter

Description

Input voltage high threshold

Input voltage low threshold

Pull-up resistor

Conditions

Min

Typ

–

Max

Units

V

0.7 × V

–

IH

IL

DDIO

V

–

3.5

–

0.3× V

V

DDIO

Rpullup

5.6

3

8.5

kΩ

pF

[30]

C

Input capacitance

IN

H

V

Input voltage hysteresis

–

100

–

mV

[30]

(Schmitt-Trigger)

Idiode

Current through protection diode to

and V

–

100

µA

V

DDIO

SSIO

Table 11-23. XRES AC Specifications

Parameter Description

Reset pulse width

Conditions

Min

Typ

Max

Units

T

1

–

µs

RESET

Note

30. Based on device characterization (Not production tested).

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11.2 Analog Peripherals

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.2.1 Opamp

Table 11-24. Opamp DC Specifications

Parameter Description

Input offset voltage

Conditions

Min

–

Typ

–

Max

2

Units

mV

V

IOFF

Vos

–

2.5

2

mV

Operating temperature –40 °C to

70 °C

–

mV

TCVos

Ge1

Cin

Input offset voltage drift with temperature Power mode = high

–

±12

–

µV / °C

Gain error, unity gain buffer mode

Input capacitance

Rload = 1 kΩ

±0.1

18

%

pF

V

Routing from pin

–

Vo

Output voltage range

1 mA, source or sink, power mode = V

high

+ 0.05

–

V

–

DDA

SSA

0.05

Iout

Output current, source or sink

V

+ 500 mV ≤ Vout ≤ V

25

16

–

mA

SSA

DDA

–500 mV, V

> 2.7 V

DDA

V

+ 500 mV ≤ Vout ≤ V

–

SSA

DDA

–500 mV, 1.7 V = V

Power mode = min

Power mode = low

≤ 2.7 V

DDA

Idd

Quiescent current

–

200

250

330

1000

–

270

400

950

2500

–

uA

dB

Power mode = med

Power mode = high

–

CMRR

PSRR

Common mode rejection ratio

Power supply rejection ratio

80

85

70

Vdda ≥ 2.7 V

Vdda < 2.7 V

–

Figure 11-21. Opamp Voffset Histogram, 3388 samples/847

parts, 25 °C, Vdda = 5 V

Figure 11-22. Opamp Voffset vs Temperature, Vdda = 5V

Note

31. Based on device characterization (Not production tested).

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Figure 11-23. Opamp Voffset vs Vcommon and

Vdda, 25 °C

Figure 11-24. Opamp Output Voltage vs Load Current and

Temperature, High Power Mode, 25 °C, Vdda = 2.7 V

Figure 11-25. Opamp Operating Current vs Vdda and Power

Mode

O

Table 11-19. Opamp AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

GBW

Gain-bandwidth product

Power mode = minimum, 200 pF

load

1

–

MHz

Power mode = low, 200 pF load

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

Power mode = low, 200 pF load

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

2

1

–

MHz

3

–

MHz

SR

Slew rate, 20% - 80%

Input noise density

1.1

0.9

3

–

V/µs

–

V/µs

–

V/µs

e

Power mode = high, Vdda = 5 V, at

100 kHz

–

45

nV/sqrtHz

n

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Figure 11-26. Opamp Noise vs Frequency, Power Mode =

High, Vdda = 5V

Figure 11-27. Opamp Step Response, Rising

Figure 11-28. Opamp Step Response, Falling

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PSoC^®5: CY8C55 Family Datasheet

11.2.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

■ Operation in continuous sample mode

■ fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits

■ Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

■ Unless otherwise specified, all charts and graphs show typical values

Table 11-20. 20-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

8

–

20

bits

No. of

GPIO

Number of channels, single ended

–

Differential pair is formed using a

pair of GPIOs.

No. of

GPIO/2

Number of channels, differential

Monotonic

–

Yes

–

Buffered, buffer gain = 1, Range =

±1.024 V, 16-bit mode, 25 °C

Ge

Gain error

±0.2

%

Buffered, buffer gain = 1, Range =

±1.024 V, 16-bit mode

ppm/°

C

Gd

Gain drift

–

50

±0.5

55

Buffered, 16-bit mode, V

25 °C

= 2.7 V,

DDA

Vos

TCVos

Input offset voltage

mV

Temperature coefficient, input offset

voltage

Buffer gain = 1, 16-bit,

Range = ±1.024 V

–

µV/°C

[32]

Input voltage range, single ended

V

SSA

DDA

Input voltage range, differential unbuf-

V

[32]

fered

Input voltage range, differential,

–

V

– 1

V

[32]

SSA

DDA

buffered

Buffer gain = 1, 16-bit,

Range = ±1.024 V

[32]

PSRRb

CMRRb

INL20

DNL20

INL16

DNL16

INL12

DNL12

INL8

Power supply rejection ratio, buffered

90

85

–

dB

Buffer gain = 1, 16 bit,

Range = ±1.024 V

[32]

Common mode rejection ratio, buffered

–

dB

Range=±1.024 V,unbuffered,using

external clock source

[32]

Integral non linearity

±32

LSB

Range=±1.024 V,unbuffered,using

external clock source

[32]

Differential non linearity

–

±1

±2

±1

Range=±1.024 V,unbuffered,using

external clock source

[32]

Integral non linearity

–

Range=±1.024 V,unbuffered,using

external clock source

[32]

Differential non linearity

–

Range=±1.024 V,unbuffered,using

external clock source

[32]

Integral non linearity

–

Range=±1.024 V,unbuffered,using

external clock source

[32]

Differential non linearity

–

Range=±1.024 V,unbuffered,using

external clock source

[32]

Integral non linearity

–

Range=±1.024 V,unbuffered,using

external clock source

[32]

DNL8

Differential non linearity

–

±1

–

LSB

Rin_Buff

ADC input resistance

Input buffer used

10

MΩ

Notes

32. Based on device characterization (not production tested).

33. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional

to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

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Table 11-20. 20-bit Delta-sigma ADC DC Specifications (continued)

Parameter

Description

Conditions

Min

Typ

Max

Units

Input buffer bypassed, 16-bit, Range

= ±1.024 V

[33]

Rin_ADC16 ADC input resistance

Rin_ADC12 ADC input resistance

–

74

–

kΩ

Input buffer bypassed, 12 bit, Range

= ±1.024 V

[33]

–

148

–

kΩ

ADC external reference input voltage, see

also internal reference in Voltage

Reference on page 79

Vextref

Pins P0[3], P3[2]

0.9

–

1.3

V

Current Consumption

[34]

I

Current consumption, 20 bit

Current consumption, 16 bit

Current consumption, 12 bit

187 sps, unbuffered

48 ksps, unbuffered

192 ksps, unbuffered

–

1.25

1.2

mA

DD_20

DD_16

DD_12

BUFF

1.4

[34]

Buffer current consumption

2.5

Table 11-21. Delta-sigma ADC AC Specifications

Parameter

Description

Conditions

Min

Typ

–

Max

Units

Samples

%

Startup time

Total harmonic distortion

–

4

[34]

THD

Buffer gain = 1, 16 bit,

Range = ±1.024 V

–

0.0032

20-Bit Resolution Mode

[34]

SR20

BW20

Sample rate

Input bandwidth at max sample rate

Range = ±1.024 V, unbuffered

7.8

–

187

–

sps

Hz

[34]

40

16-Bit Resolution Mode

[34]

SR16

BW16

Sample rate

Input bandwidth at max sample rate

Range = ±1.024 V, unbuffered

Range = ±1.024V, unbuffered

2

–

11

–

48

–

ksps

kHz

dB

SINAD16int Signal to noise ratio, 16-bit, internal

81

–

[34]

reference

SINAD16ext Signal to noise ratio, 16-bit, external

Range = ±1.024 V, unbuffered

84

–

dB

[34]

reference

12-Bit Resolution Mode

[34]

SR12

BW12

Sample rate, continuous, high power

Range = ±1.024 V, unbuffered

4

–

44

–

192

–

ksps

kHz

dB

[34]

Input bandwidth at max sample rate

SINAD12int Signal to noise ratio, 12-bit, internal

66

–

[34]

reference

8-Bit Resolution Mode

SR8

Sample rate, continuous, high power

Range = ±1.024 V, unbuffered

8

–

88

–

384

–

ksps

kHz

dB

[34]

BW8

Input bandwidth at max sample rate

SINAD8int

Signal to noise ratio, 8-bit, internal

43

–

[34]

reference

Note

34. Based on device characterization (not production tested).

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Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024 V

Continuous

Multi-Sample

Min

Multi-Sample Turbo

Resolution,

Bits

Min

Max

91701

74024

64673

55351

46900

38641

32855

28054

11861

2965

741

Min

1829

1489

1307

1123

956

791

674

577

489

282

105

15

Max

87771

71441

62693

53894

45850

37925

32336

27675

11725

6766

8

8000

6400

5566

4741

4000

3283

2783

2371

2000

500

384000

307200

267130

227555

192000

157538

133565

113777

48000

12000

3000

1911

1543

1348

1154

978

806

685

585

495

124

31

9

10

11

12

13

14

15

16

17

18

19

20

125

2513

16

375

4

93

357

8

187.5

2

46

8

183

Figure 11-29. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Figure 11-30. Delta-sigma ADC Noise Histogram, 1000 Sam-

Continuous Sample Mode, Input Buffer Bypassed

ples, 20-Bit, 187 sps, Ext Ref, V_IN= V_REF/2, Range = ±1.024 V

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Figure 11-31. Delta-sigma ADC Noise Histogram, 1000 sam- Figure 11-32. Delta-sigma ADC Noise Histogram, 1000 sam-

ples, 16-bit, 48 ksps, Ext Ref, V_IN= V_REF/2, Range = ±1.024 V ples, 16-bit, 48 ksps, Int Ref, V_IN= V_REF/2, Range = ±1.024 V

Table 11-23. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended

Sample rate,

sps

Input Voltage Range

0 to VREF

1.21

0 to VREF x 2

VSSA to VDDA

0 to VREF x 6

0.99

2000

1.02

1.15

1.22

1.33

1.50

1.60

1.14

1.25

1.38

1.43

1.85

3000

1.28

1.22

6000

1.36

1.22

12000

24000

48000

1.44

1.40

1.67

1.53

1.91

1.67

Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential

Sample rate,

sps

Input Voltage Range

±VREF

0.56

0.58

0.53

0.58

0.60

0.58

0.59

±VREF / 2

0.65

±VREF / 4

0.74

±VREF / 8

1.02

±VREF / 16

1.77

2000

4000

0.72

0.81

1.10

1.98

8000

0.72

0.82

1.12

2.18

15625

32000

43750

48000

0.72

0.85

1.13

2.20

0.76

INVALID OPERATING REGION

0.75

Table11-25. Delta-sigmaADCRMSNoiseinCountsvs. InputRangeandSampleRate, 20-bit, ExternalReference, SingleEnded

Sample rate,

Input Voltage Range

sps

8

0 to VREF

1.28

0 to VREF x 2

VSSA to VDDA

0 to VREF x 6

0.97

1.24

1.28

1.26

0.91

1.06

6.02

6.09

6.28

6.84

7.97

23

45

90

187

1.33

0.98

1.77

0.96

1.65

0.95

1.87

1.01

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Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential

Sample rate, sps

Input Voltage Range

±VREF

0.70

0.69

0.73

0.76

0.75

0.73

±VREF / 2

0.84

±VREF / 4

1.02

±VREF / 8

1.40

±VREF / 16

2.65

8

11.3

22.5

45

0.86

0.96

1.40

2.69

0.82

1.25

1.77

2.67

0.94

1.02

1.76

2.75

61

1.01

1.13

1.65

2.98

170

187

0.98

INVALID OPERATING REGION

Figure 11-33. Delta-sigma ADC DNL vs Output Code, 16-bit,

48 ksps, 25 °C V_DDA= 3.3 V

Figure 11-34. Delta-sigma ADC INL vs Output Code, 16-bit,

48 ksps, 25 °C V_DDA= 3.3 V

11.5.3 Voltage Reference

Table 11-25. Voltage Reference Specifications

See also ADC external reference specifications in Section 11.2.2.

Parameter

Description

Conditions

Initial trimming

Min

Typ

Max

Units

V

Precision reference voltage

1.017

1.024

1.033

V

REF

(–0.7%)

(+0.9%)

[35]

Temperature drift

–

20

–

ppm/°C

ppm/Khr

ppm

Long term drift

100

[35]

Thermal cycling drift (stability)

–

Note

35. Based on device characterization (Not production tested).

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11.5.4 SAR ADC

Table 11-26. SAR ADC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

Units

Resolution

Number of channels – single-ended

12

bits

–

No of

GPIO

Number of channels – differential Differential pair is formed using a

pair of neighboring GPIO.

–

No of

GPIO/2

[36]

Monotonicity

Yes

–

Gain error

±0.1

±0.2

500

%

mV

µA

V

Input offset voltage

Current consumption

Input voltage range –

–

V

SSA

DDA

[36]

single-ended

[36]

Input voltage range – differential

V

–

8

V

SSA

DDA

[36]

Input resistance

–

2

KΩ

pF

[36]

C

Input capacitance

7

9

IN

Table 11-27. SAR ADC AC Specifications

Parameter Description

Conditions

Min

–

Typ

–

Max

Units

µV/µs

dB

[36]

Sample and hold droop

1

–

[36]

PSRR

Power supply rejection ratio

80

–

CMRR

Common mode rejection ratio

–

dB

[36]

Sample rate

–

1

Msps

dB

[36]

SNR

Signal-to-noise ratio (SNR)

70

–

[36]

Input bandwidth

500

–

KHz

LSB

%

[36]

INL

Integral non linearity

Internal reference

–

±1

0.005

[36]

DNL

THD

Differential non linearity

–

[36]

Total harmonic distortion

–

11.5.5 Analog Globals

Table 11-28. Analog Globals AC Specifications

Parameter

Rppag

Description

Conditions

= 3.0 V

Min

Typ

Max

Units

Resistance pin-to-pin through

V

–

939

1461

Ω

DDA

[37]

analog global

Rppmuxbus

Resistance pin-to-pin through

= 3.0 V

–

721

1135

Ω

DDA

[37]

analog mux bus

Note

36. Based on device characterization (Not production tested).

37. The resistance of the analog global and analog mux bus is high if V

≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

DDA

mux bus under these conditions is not recommended.

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11.5.6 Comparator

Table 11-29. Comparator DC Specifications

Parameter

Description

Input offset voltage in fast mode

Conditions

Min

Typ

Max

Units

Factory trim, Vdda > 2.7 V,

–

10

mV

Vin ≥ 0.5 V

V

OS

Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V

–

9

4

–

mV

[39]

Input offset voltage in fast mode

Input offset voltage in slow mode

Custom trim

–

V

OS

[39]

Input offset voltage in ultra low

power mode

±12

OS

V

Hysteresis

Hysteresis enable mode

High current / fast mode

Low current / slow mode

Ultra low power mode

–

10

–

32

mV

V

HYST

Input common mode voltage

V

– 0.1

DDA

ICM

SSA

V

–

V

DDA

–

V

– 0.9

SSA

DDA

CMRR

Common mode rejection ratio

–

50

–

dB

µA

[40]

I

High current mode/fast mode

–

400

100

–

CMP

[40]

Low current mode/slow mode

–

[40]

Ultra low power mode

6

Table 11-30. Comparator AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Response time, high current

mode

50 mV overdrive, measured

pin-to-pin

–

75

110

ns

[40]

Response time, low current

mode

50 mV overdrive, measured

pin-to-pin

–

155

55

200

–

ns

µs

T

[40]

RESP

Response time, ultra low power

50 mV overdrive, measured

pin-to-pin

[40]

mode

Notes

38. The resistance of the analog global and analog mux bus is high if V

≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

DDA

mux bus under these conditions is not recommended.

39. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.

40. Based on device characterization (Not production tested).

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11.5.7 Current Digital-to-analog Converter (IDAC)

See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-31. IDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

8

Units

bits

Resolution

I

Output current at code = 255

Range = 2.048 mA, code = 255,

–

2.048

–

mA

OUT

V

≥ 2.7 V, Rload = 600 Ω

DDA

Range = 2.048 mA, High mode,

–

2.048

–

mA

code = 255, V

300 Ω

≤ 2.7 V, Rload =

DDA

Range=255µA, code=255, Rload

= 600 Ω

–

255

–

µA

Range = 31.875 µA, code = 255,

31.875

Rload = 600 Ω

Monotonicity

Zero scale error

Gain error

–

0

–

Yes

±2.5

±5

Ezs

LSB

%

Eg

TC_Eg

Temperature coefficient of gain

error

Range = 2.048 mA

Range = 255 µA

0.04

0.05

±3

% / °C

LSB

Range = 31.875 µA

INL

Integral nonlinearity

Range = 255 µA, Codes 8 – 255,

Rload = 2.4 kΩ, Cload = 15 pF

DNL

Differential nonlinearity,

non-monotonic

Range = 255 µA, Rload = 2.4 kΩ,

–

1

–

±0.6

–

LSB

V

Cload = 15 pF

Vcompliance

Dropout voltage, source or sink

mode

Voltage headroom at max current,

Rload to Vdda or Rload to Vssa,

Vdiff from Vdda

Note

41. Based on device characterization (Not production tested).

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Table 11-31. IDAC DC Specifications (continued)

Parameter

Description

Conditions

Min

Typ

Max

Units

I

Operating current, code = 0

Slow mode, source mode, range =

31.875 µA

–

44

100

µA

DD

Slow mode, source mode, range =

255 µA,

–

33

100

500

µA

Slow mode, source mode, range =

2.04 mA

Slow mode, sink mode, range =

31.875 µA

36

Slow mode, sink mode, range =

255 µA

33

Slow mode, sink mode, range =

2.04 mA

33

Fast mode, source mode, range =

31.875 µA

310

305

310

300

Fast mode, source mode, range =

255 µA

Fast mode, source mode, range =

2.04 mA

Fast mode, sink mode, range =

31.875 µA

Fast mode, sink mode, range =

255 µA

Fast mode, sink mode, range =

2.04 mA

Figure 11-35. IDAC INL vs Input Code, Range = 255 µA,

Source Mode

Figure 11-36. IDAC INL vs Input Code, Range = 255 µA, Sink

Mode

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Figure 11-37. IDAC DNL vs Input Code, Range = 255 µA,

Source Mode

Figure 11-38. IDAC DNL vs Input Code, Range = 255 µA, Sink

Mode

Figure 11-39. IDAC INL vs Temperature, Range = 255 µA, Fast

Mode

Figure 11-40. IDAC DNL vs Temperature, Range = 255 µA,

Fast Mode

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Figure 11-41. IDAC Full Scale Error vs Temperature, Range

= 255 µA, Source Mode

Figure 11-42. IDAC Full Scale Error vs Temperature, Range

= 255 µA, Sink Mode

Figure 11-43. IDAC Operating Current vs Temperature,

Range = 255 µA, Code = 0, Source Mode

Figure 11-44. IDAC Operating Current vs Temperature,

Range = 255 µA, Code = 0, Sink Mode

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Table 11-32. IDAC AC Specifications

Parameter

Description

Update rate

Settling time to 0.5 LSB

Conditions

Min

–

Typ

–

Max

8

Units

Msps

ns

F

DAC

T

Range = 31.875 µA or 255 µA, full

scale transition, fast mode, 600 Ω

15-pF load

–

125

SETTLE

Figure 11-45. IDAC Step Response, Codes 0x40 - 0xC0,

255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V

Figure 11-46. IDAC Glitch Response, Codes 0x7F - 0x80,

255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V

Figure 11-47. IDAC PSRR vs Frequency

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11.5.8 Voltage Digital to Analog Converter (VDAC)

See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-48. VDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

8

Max

–

Units

Resolution

bits

INL1

Integral nonlinearity

Differential nonlinearity

Output resistance

1 V scale

4 V scale

–

±2.1

±0.3

4

±2.5

±1

LSB

DNL1

Rout

–

LSB

–

kΩ

–

16

1

–

kΩ

V

Output voltage range, code = 255 1 V scale

–

V

OUT

4 V scale, Vdda = 5 V

–

4

–

V

Monotonicity

Zero scale error

Gain error

–

Yes

±0.9

±2.5

0.03

100

500

–

V

–

0

LSB

OS

Eg

1 V scale

4 V scale

–

%

–

TC_Eg

Temperature coefficient, gain error 1 V scale

4 V scale

–

%FSR / °C

µA

–

I

Operating current

Slow mode

Fast mode

–

DD

–

µA

Figure 11-48. VDAC INL vs Input Code, 1 V Mode

Figure 11-49. VDAC DNL vs Input Code, 1 V Mode

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Figure 11-50. VDAC INL vs Temperature, 1 V Mode

Figure 11-51. VDAC DNL vs Temperature, 1 V Mode

Figure 11-52. VDAC Full Scale Error vs Temperature, 1 V

Mode

Figure 11-53. VDAC Full Scale Error vs Temperature, 4 V

Mode

Figure 11-54. VDAC Operating Current vs Temperature, 1V

Mode, Slow Mode

Figure 11-55. VDAC Operating Current vs Temperature, 1 V

Mode, Fast Mode

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Table 11-34. VDAC AC Specifications

Parameter

Description

Update rate

Conditions

Min

–

Typ

–

Max

1000

250

1

Units

ksps

µs

F

1 V scale

4 V scale

DAC

–

TsettleP

TsettleN

Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF

75%

–

0.45

4 V scale, Cload = 15 pF

–

0.8

3.2

1

µs

Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF

25%

0.45

4 V scale, Cload = 15 pF

–

0.7

3

µs

Figure 11-56. VDAC Step Response, Codes 0x40 - 0xC0, 1 V

Mode, Fast Mode, Vdda = 5 V

Figure 11-57. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V

Mode, Fast Mode, Vdda = 5 V

Figure 11-58. VDAC PSRR vs Frequency

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11.5.9 Mixer

The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-59. Mixer DC Specifications

Parameter

Description

Input offset voltage

Conditions

Min

–

Typ

–

Max

20

2

Units

mV

V

OS

Quiescent current

Gain

–

0.9

0

mA

G

–

dB

Table 11-60. Mixer AC Specifications

Parameter

Description

Local oscillator frequency

Input signal frequency

Local oscillator frequency

Input signal frequency

Slew rate

Conditions

Min

–

Typ

–

Max

4

Units

MHz

V/µs

f

Down mixer mode

LO

f

Down mixer mode

Up mixer mode

–

14

1

in

LO

–

f

–

1

in

SR

3

–

11.5.10 Transimpedance Amplifier

The TIA is created using a SC/CT analog block; see the TIA component data sheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-61. Transimpedance Amplifier (TIA) DC Specifications

Parameter

Description

Input offset voltage

Conversion resistance

Conditions

Min

–

Typ

–

Max

20

Units

mV

%

V

IOFF

[42]

Rconv

R = 20K; 40 pF load

–25

–

+35

2

R = 30K; 40 pF load

R = 40K; 40 pF load

R = 80K; 40 pF load

R = 120K; 40 pF load

R = 250K; 40 pF load

R= 500K; 40 pF load

R = 1M; 40 pF load

–

%

–

%

–

%

–

%

–

%

–

%

–

%

Quiescent current

1.1

mA

Table 11-62. Transimpedance Amplifier (TIA) AC Specifications

Parameter

BW

Description

Conditions

Min

Typ

Max

Units

Input bandwidth (–3 dB)

R = 20K; –40 pF load, V

≥ 1.9 V 1500

–

kHz

DDA

R = 120K; –40 pF load,

240

–

kHz

V

≥ 1.9 V

DDA

R = 1M; –40 pF load, V

≥ 1.9 V

25

DDA

Note

42. Conversion resistance values are not calibrated. Calibrated values and details about calibrationare provided in PSoC Creator component datasheets. External precision

resistors can also be used.

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11.5.11 Programmable Gain Amplifier

The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications

and APIs.

Unless otherwise specified, operating conditions are:

■ Operating temperature = 25 °C for typical values

■ Unless otherwise specified, all charts and graphs show typical values

Table 11-63. PGA DC Specifications

Parameter

Vin

Description

Input voltage range

Input offset voltage

Conditions

Min

Vssa

–

Typ

–

Max

Vdda

20

Units

V

Power mode = minimum

Vos

Power mode = high,

gain = 1

–

mV

TCVos

Input offset voltage drift

with temperature

Power mode = high,

gain = 1

–

±30

µV/°C

Ge1

Gain error, gain = 1

Gain error, gain = 16

Gain error, gain = 50

DC output nonlinearity

–

±0.61

±6.1

±9

%

Ge16

Ge50

Vonl

Gain = 1

±0.01

% of

FSR

Cin

Input capacitance

–

7

–

pF

V

Voh

Output voltage swing

Power mode = high,

V

– 0.15

DDA

gain = 1, Rload = 100 kΩ

to V

/ 2

DDA

Vol

Output voltage swing

Power mode = high,

–

V

+ 0.15

V

SSA

gain = 1, Rload = 100 kΩ

to V

/ 2

DDA

Vsrc

Output voltage under load

Operating current

Iload = 250 µA, Vdda ≥

2.7V, power mode = high

300

mV

Idd

Power mode = high

–

1.5

–

1.65

–

mA

dB

PSRR

Power supply rejection

ratio

48

Figure 11-59. PGA Voffset Histogram, 4096 samples/

1024 parts

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Table 11-40. PGA AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

BW1

–3 dB bandwidth

Power mode = high,

gain = 1, input = 100 mV

peak-to-peak

6.7

8

–

MHz

SR1

Slew rate

Power mode = high,

gain = 1, 20% to 80%

3

–

V/µs

e

Input noise density

Power mode = high,

43

nV/sqrtHz

n

Vdda = 5 V, at 100 kHz

Figure 11-60. Bandwidth vs. Temperature, at Different Gain

Settings, Power Mode = High

Figure 11-61. Noise vs. Frequency, Vdda = 5 V,

Power Mode = High

11.5.12 Temperature Sensor

Table 11-41. Temperature Sensor Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Temp sensor accuracy

Range: –40 °C to +85 °C

–

±8

–

°C

11.5.13 LCD Direct Drive

Table 11-42. LCD Direct Drive DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

I

LCD system operating current

Device sleep mode with wakeup at

400-Hz rate to refresh LCDs, bus

clock = 3 Mhz, Vddio = Vdda = 3 V,

4 commons, 16 segments, 1/4 duty

cycle, 50 Hz frame rate, no glass

connected

–

63

–

μA

CC

I

Current per segment driver

Strong drive mode

–

2

260

–

5

µA

V

CC_SEG

V

LCD bias range (V

refers to the

V

≥ 3 V and V

≥ V

BIAS

DDA

BIAS

main output voltage(V0) of LCD DAC)

LCD bias step size

V

≥ 3 V and V

–

9.1 × V

500

–

mV

pF

DDA

BIAS

DDA

LCD capacitance per

Drivers may be combined

5000

segment/common driver

Long term segment offset

–

20

mV

µA

I

Output drive current per segment

driver)

Vddio = 5.5V, strong drive mode

355

710

OUT

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Table 11-43. LCD Direct Drive AC Specifications

Parameter

Description

LCD frame rate

Conditions

Min

Typ

Max

Units

f

10

50

150

Hz

LCD

11.6 Digital Peripherals

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.6.1 Timer

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for

more information, see the Timer component data sheet in PSoC Creator.

Table 11-44. Timer DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit timer, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-45. Timer AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

13

30

13

30

13

30

Typ

–

Max

Units

MHz

ns

67.01

Capture pulse width (Internal)

Capture pulse width (external)

Timer resolution

–

ns

–

ns

Enable pulse width

–

ns

Enable pulse width (external)

Reset pulse width

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.2 Counter

The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in

UDBs; for more information, see the Counter component data sheet in PSoC Creator.

Table 11-46. Counter DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit counter, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-47. Counter AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

13

Typ

–

Max

67.01

–

Units

MHz

ns

Capture pulse

Resolution

–

13

–

ns

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Table 11-47. Counter AC Specifications (continued)

Parameter Description

Conditions

Min

13

30

13

30

13

30

Typ

Max

Units

ns

Pulse width

–

Pulse width (external)

Enable pulse width

ns

–

ns

Enable pulse width (external)

Reset pulse width

ns

Reset pulse width (external)

ns

11.6.3 Pulse Width Modulation

The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented

in UDBs; for more information, see the PWM component data sheet in PSoC Creator.

Table 11-48. PWM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit PWM, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-49. PWM AC Specifications

Parameter

Description

Operating frequency

Conditions

Min

DC

13

30

13

30

13

30

13

30

Typ

–

Max

Units

MHz

ns

67.01

Pulse width

–

Pulse width (external)

Kill pulse width

–

ns

–

ns

Kill pulse width (external)

Enable pulse width

–

ns

–

ns

Enable pulse width (external)

Reset pulse width

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.4 I²C

Table 11-50. Fixed I²C DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

64

Units

µA

Block current consumption

Enabled, configured for 100 kbps

Enabled, configured for 400 kbps

–

74

µA

Table 11-51. Fixed I²C AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

–

1

Mbps

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[43]

Controller Area Network

Table 11-53. CAN DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

I

Block current consumption

–

200

µA

DD

Table 11-52. CAN AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

Minimum 8 MHz clock

–

1

Mbit

11.6.5 Digital Filter Block

Table 11-54. DFB DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

DFB operating current

64-tap FIR at F

DFB

100 kHz (1.3 ksps)

500 kHz (6.7 ksps)

1 MHz (13.4 ksps)

10 MHz (134 ksps)

48 MHz (644 ksps)

67 MHz (900 ksps)

–

0.03

0.16

0.33

3.3

0.05

0.27

0.53

5.3

mA

15.7

21.8

25.5

35.6

Table 11-55. DFB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

F

DFB operating frequency

DC

–

67.01

MHz

DFB

Note

43. Refer to ISO 11898 specification for details.

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11.6.6 USB

Table 11-56. USB DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V

Device supply for USB operation

USB configured, USB regulator

enabled

4.35

–

5.25

V

USB_5

USB configured, USB regulator

bypassed

3.15

2.85

–

3.6

V

USB_3.3

USB configured, USB regulator

USB_3

[44]

bypassed

I

Devicesupplycurrentindeviceactive V

= 5 V, F = 1.5 MHz

CPU

–

10

8

–

mA

USB_Configured

DDD

mode, bus clock and IMO = 24 MHz

V

= 3.3 V, F

= 1.5 MHz

CPU

I

Device supply current in device sleep V

mode

= 5 V, connected to USB

0.5

USB_Suspended

host, PICU configured to wake on

USB resume signal

V

= 5 V, disconnected from

–

0.3

0.5

–

mA

DDD

USB host

V

= 3.3 V, connected to USB

DDD

host, PICU configured to wake on

USB resume signal

V

= 3.3 V, disconnected from

–

0.3

–

mA

DDD

USB host

11.6.7 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Table 11-57. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

F

Maximum frequency of 16-bit timer in

a UDB pair

–

67.01

MHz

MAX_TIMER

MAX_ADDER

MAX_CRC

Maximum frequency of 16-bit adder in

a UDB pair

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

PLD Performance

F

Maximum frequency of a two-pass

PLD function in a UDB pair

–

67.01

MHz

MAX_PLD

Clock to Output Performance

t

Propagation delay for clock in to data 25 °C, Vddd ≥ 2.7 V

out, see Figure 11-62.

–

20

–

25

55

ns

CLK_OUT

t

Propagation delay for clock in to data Worst-case placement, routing,

out, see Figure 11-62. and pin selection

CLK_OUT

Note

44. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 70.

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Figure 11-62. Clock to Output Performance

11.7 Memory

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.7.1 Flash

Table 11-57. Flash DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

V

1.71

–

5.5

V

DDD

Table 11-58. Flash AC Specifications

Parameter

Description

Row write time (erase + program)

Row erase time

Min

–

Typ

15

10

5

Max

20

Units

ms

T

WRITE

ERASE

–

13

ms

Row program time

–

7

ms

T

Bulk erase time (256 KB)

Sector erase time (16 KB)

–

320

15

ms

BULK

–

ms

Total device program time

(including JTAG or SWD and other

overhead

–

20

Seconds

Flash data retention time, retention

period measured from last erase cycle T ≤ 55 °C, 100 K erase/program

Average ambient temp.

20

10

–

Years

A

cycles

–40 °C ≤ T ≤ 85 °C, 10 K

A

erase/program cycles

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11.7.2 EEPROM

Table 11-59. EEPROM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

1.71

–

5.5

V

Table 11-60. EEPROM AC Specifications

Parameter

Description

Single row erase/write cycle time

EEPROM endurance

Conditions

Min

–

Typ

2

Max

20

–

Units

T

ms

WRITE

1M

–

program/

erase

cycles

EEPROM data retention time

Retention period measured from

last erase cycle (up to 100 K cycles)

20

–

years

11.7.3 SRAM

Table 11-61. SRAM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V

SRAM retention voltage

1.2

–

V

SRAM

Table 11-62. SRAM AC Specifications

Parameter

Description

Min

Typ

Max

Units

F

SRAM operating frequency

DC

–

67.01

MHz

SRAM

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11.8 PSoC System Resources

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.8.1 POR with Brown Out

For brown out detect in regulated mode, V

mode.

and V

must be ≥ 2.0 V. Brown out detect is not available in externally regulated

DDD

DDA

Table 11-63. Precise Power On Reset (PRES) with Brown Out DC Specifications

Parameter

Description

Precise POR (PPOR)

Conditions

Min

Typ

Max

Units

PRESR

PRESF

Rising trip voltage

Falling trip voltage

Factory trim

1.64

1.62

–

1.68

1.66

V

Table 11-64. Power On Reset (POR) with Brown Out AC Specifications

Parameter

PRES_TR Response time

/V droop rate

Description

Conditions

Min

–

Typ

–

Max

0.5

–

Units

µs

V

Sleep mode

–

5

V/sec

DDD DDA

11.8.2 Voltage Monitors

Table 11-65. Voltage Monitors DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

LVI

Trip voltage

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Trip voltage

1.68

1.89

2.14

2.38

2.62

2.87

3.11

3.35

3.59

3.84

4.08

4.32

4.56

4.83

5.05

5.30

5.57

1.73

1.95

2.20

2.45

2.71

2.95

3.21

3.46

3.70

3.95

4.20

4.45

4.70

4.98

5.21

5.47

5.75

1.77

2.01

2.27

2.53

2.79

3.04

3.31

3.56

3.81

4.07

4.33

4.59

4.84

5.13

5.37

5.63

5.92

V

HVI

Table 11-66. Voltage Monitors AC Specifications

Parameter Description

Response time

Conditions

Min

Typ

Max

Units

–

1

µs

Document Number: 001-66235 Rev. **

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11.8.3 Interrupt Controller

Table 11-67. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from interrupt signal input to ISR

code execution from main line code

–

12

Tcy CPU

Delay from interrupt signal input to ISR

code execution from ISR code

(tail-chaining)

–

6

Tcy CPU

11.8.4 JTAG Interface

[45]

Table 11-68. JTAG Interface AC Specifications

Parameter

f_TCK

Description

TCK frequency

Conditions

Min

Typ

–

Max

Units

MHz

ns

[46]

3.3 V ≤ V

≤ 5 V

–

14

DDD

[46]

1.71 V ≤ V

< 3.3 V

–

(T/10) – 5

T/4

–

7

DDD

T_TDI_setup

TDI setup before TCK high

–

T_TMS_setup TMS setup before TCK high

–

T_TDI_hold

T_TDO_valid

T_TDO_hold

TDI, TMS hold after TCK high

TCK low to TDO valid

T = 1/f_TCK

T/4

–

2T/5

–

TDO hold after TCK high

T/4

–

11.8.5 SWD Interface

[45]

Table 11-69. SWD Interface AC Specifications

Parameter

Description

SWDCLK frequency

Conditions

Min

–

Typ

–

Max

Units

MHz

[47]

f_SWDCK

3.3 V ≤ V

≤ 5 V

14

DDD

[47]

1.71 V ≤ V

< 3.3 V

–

7

DDD

[47]

1.71 V ≤ V

< 3.3 V, SWD over

–

5.5

DDD

USBIO pins

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold SWDIO input hold after SWDCK high

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

2T/5

–

T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max

T/4

11.8.6 TPIU Interface

[45]

Table 11-70. TPIU Interface AC Specifications

Parameter

Description

TRACEPORT (TRACECLK) frequency

SWV bit rate

Conditions

Min

–

Typ

–

Max

Units

MHz

Mbit

[48]

33

[48]

–

33

Notes

45. Based on device characterization (Not production tested).

46. f_TCK must also be no more than 1/3 CPU clock frequency.

47. f_SWDCK must also be no more than 1/3 CPU clock frequency.

48. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see “GPIO AC Specifications” on page 65.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

11.9 Clocking

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted. Unless otherwise specified, all charts and graphs show typical values.

11.9.1 32 kHz External Crystal

[49]

Table 11-71. 32 kHz External Crystal DC Specifications

Parameter

Description

Operating current

Conditions

Min

–

Typ

0.25

6

Max

1.0

–

Units

µA

I

Low power mode

CC

CL

DL

External crystal capacitance

Drive level

–

pF

–

1

µW

Table 11-72. 32 kHz External Crystal AC Specifications

Parameter

Description

Conditions

Min

–

Typ

32.768

1

Max

–

Units

kHz

s

F

Frequency

T

Startup time

High power mode

–

ON

11.9.2 Internal Main Oscillator)

Table 11-73. IMO DC Specifications

Parameter

Description

Supply current

Conditions

Min

Typ

Max

Units

62.6 MHz

48 MHz

24 MHz

12 MHz

6 MHz

–

600

500

300

200

180

150

µA

3 MHz

Note

49. Based on device characterization (Not production tested).

Document Number: 001-66235 Rev. **

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Figure 11-63. IMO Current vs. Frequency

Table 11-1. IMO AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

IMO frequency stability (with factory trim)

62.6 MHz

48 MHz

24 MHz

12 MHz

6 MHz

–10

–6

–4

–

10

6

%

µs

F

IMO

6

4

3 MHz

4

[49]

Startup time

Fromenable(duringnormalsystem

operation) or wakeup from low

power state

12

[50]

Jitter (peak to peak)

Jp-p

F = 24 MHz

F = 3 MHz

–

0.9

1.6

–

ns

[19]

Jitter (long term)

Jperiod

F = 24 MHz

F = 3 MHz

–

0.9

12

–

ns

Figure 11-64. IMO Frequency Variation vs. Temperature

Figure 11-65. IMO Frequency Variation vs. V_DD

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

11.9.3 Internal Low Speed Oscillator

Table 11-66. ILO DC Specifications

Parameter

Description

Operating current

Conditions

= 1 kHz

Min

–

Typ

0.3

1.0

2.0

Max

1.7

2.6

15

Units

µA

F

OUT

I

= 33 kHz

–

µA

CC

= 100 kHz

–

µA

Leakage current

Power down mode

–

nA

Table 11-67. ILO AC Specifications

Parameter

Description

Startup time, all frequencies

ILO frequencies (trimmed)

100 kHz

Conditions

Turbo mode

Min

Typ

Max

Units

–

2

ms

45

100

1

200

2

kHz

1 kHz

0.5

F

ILO

ILO frequencies (untrimmed)

100 kHz

30

100

1

300

3.5

kHz

1 kHz

0.3

Figure 11-66. ILO Frequency Variation vs. Temperature

Figure 11-67. ILO Frequency Variation vs. V_DD

Note

50. Based on device characterization (Not production tested).

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

11.9.4 External Crystal Oscillator

Table 11-68. ECO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

F

Crystal frequency range

4

–

25

MHz

11.9.5 External Clock Reference

[51]

Table 11-69. External Clock Reference AC Specifications

Parameter

Description

External frequency range

Input duty cycle range

Input edge rate

Conditions

Min

0

Typ

–

Max

33

70

–

Units

MHz

%

Measured at V /2

30

0.1

50

–

DDIO

V

to V

V/ns

IL

IH

11.9.6 Phase-Locked Loop

Table 11-70. PLL DC Specifications

Parameter

Description

PLL operating current

Conditions

Min

–

Typ

400

200

Max

–

Units

µA

I

In = 3 MHz, Out = 67 MHz

In = 3 MHz, Out = 24 MHz

DD

–

µA

Table 11-71. PLL AC Specifications

Parameter

Description

Conditions

Min

1

Typ

–

Max

48

Units

MHz

µs

[52]

Fpllin

PLL input frequency

[53]

PLL intermediate frequency

Output of prescaler

1

–

3

[52]

Fpllout

PLL output frequency

24

–

67

Lock time at startup

–

250

[51]

Jperiod-rms Jitter (rms)

–

ps

Notes

51. Based on device characterization (Not production tested).

52. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.

53. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

12. Ordering Information

In addition to the features listed in Table 12-1, every CY8C55 device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a

2

precision on-chip voltage reference, precision oscillators, flash, DMA, a fixed function I C, JTAG/SWD programming and debug, and

more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in

selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.

All CY8C55 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.

Table 12-1. CY8C55 Family with ARM Cortex-M3 CPU

[56]

MCU Core

Analog

Digital

I/O

Part Number

Package

JTAG ID

CY8C5568AXI-060 67 256 64

CY8C5568LTI-114 67 256 64

CY8C5567AXI-019 67 128 32

CY8C5567LTI-079 67 128 32

CY8C5566AXI-061 67 64 16

CY8C5566LTI-017 67 64 16

2

✔

1x 20-bit Del-Sig

4

✔

24

4

✔

70 60

46 36

70 60

46 36

70 60

46 36

8

2

100-pin TQFP 0x0E116069

68-pin QFN 0x0E134069

100-pin TQFP 0x0E141069

68-pin QFN 0x0E114069

100-pin TQFP 0x0E143069

68-pin QFN 0x0E13C069

2x 12-bit SAR

1x 20-bit Del-Sig

2x 12-bit SAR

1x 20-bit Del-Sig

1x 12-bit SAR

1x 20-bit Del-Sig

1x 12-bit SAR

1x 20-bit Del-Sig

1x 12-bit SAR

1x20-bit Del-Sig

1x12-bit SAR

12.1 Part Numbering Conventions

PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,

B, …, Z) unless stated otherwise.

CY8Cabcdefg-xxx

■ a: Architecture

❐ 3: PSoC 3

❐ 5: PSoC 5

❐ Two character alphanumeric

❐ AX: TQFP

❐ LT: QFN

■ b: Family group within architecture

❐ 2: CY8C52 family

❐ 3: CY8C53 family

■ g: Temperature range

❐ C: commercial

❐ I: industrial

❐ 4: CY8C54 family

❐ A: automotive

❐ 5: CY8C55 family

■ xxx: Peripheral set

❐ Three character numeric

❐ No meaning is associated with these three characters

■ c: Speed grade

❐ 4: 40 MHz

❐ 8: 67 MHz

■ d: Flash capacity

❐ 5: 32 KB

❐ 6: 64 KB

❐ 7: 128 KB

❐ 8: 256 KB

■ ef: Package code

Notes

54. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 32 for more information on how analog blocks

can be used.

55. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or

multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs can be used.

56. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See 6.4 I/O System and Routing on page 26 for details on the functionality of each of

these types of I/O.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

CY8C

5

8

8 AX/PV I

- x x x

Examples

Cypress Prefix

5: PSoC 5

Architecture

Family Group within Architecture

Speed Grade

5: CY8C55 Family

8: 80 MHz

8: 256 KB

Flash Capacity

AX: TQFP

Package Code

I: Industrial

Temperature Range

Peripheral Set

All devices in the PSoC 5 CY8C55 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free

products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress

uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.

A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package

Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the

absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of

life” requirements.

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

13. Packaging

Table 13-1. Package Characteristics

Parameter

Description

Conditions

Min

–40

–

Typ

25

Max

85

100

–

Units

°C

T

Operating ambient temperature

Operating junction temperature

Package θJA (68-pin QFN)

Package θJA (100-pin TQFP)

Package θJC (68-pin QFN)

Package θJC (100-pin TQFP)

A

T

–

°C

J

Tja

Tjc

10.93

29.50

6.08

7.32

°C/Watt

–

Table 13-2. Solder Reflow Peak Temperature

Maximum Peak

Package

Maximum Time at

Peak Temperature

Temperature

68-pin QFN

260 °C

30 seconds

100-pin TQFP

Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

68-pin QFN

100-pin TQFP

MSL

MSL 3

Figure 13-1. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)

001-09618 *C

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Figure 13-2. 100-pin TQFP (14 x 14 x 1.4 mm) Package Outline

51-85048 *E

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Table 14-1. Acronyms Used in this Document (continued)

Acronym Description

FS

14. Acronyms

Table 14-1. Acronyms Used in this Document

full-speed

Acronym

abus

Description

GPIO

general-purpose input/output, applies to a PSoC

analog local bus

ADC

AG

analog-to-digital converter

analog global

HVI

IC

high-voltage interrupt, see also LVI, LVD

integrated circuit

AHB

AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an ARM data

transfer bus

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

2

ALU

arithmetic logic unit

I C, or IIC

Inter-Integrated Circuit, a communications

protocol

AMUXBUS analog multiplexer bus

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

API

application programming interface

ILO

IMO

INL

APSR

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

®

ARM

ATM

BW

I/O

bandwidth

IPOR

IPSR

IRQ

ITM

LCD

LIN

CAN

Controller Area Network, a communications

protocol

interrupt program status register

interrupt request

CMRR

CPU

common-mode rejection ratio

central processing unit

instrumentation trace macrocell

liquid crystal display

CRC

cyclic redundancy check, an error-checking

protocol

Local Interconnect Network, a communications

protocol.

DAC

DFB

DIO

digital-to-analog converter, see also IDAC, VDAC

digital filter block

LR

link register

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

LUT

LVD

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

DMA

DNL

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LVI

LVTTL

MAC

MCU

MISO

NC

DNU

DR

port write data registers

microcontroller unit

DSI

digital system interconnect

data watchpoint and trace

external crystal oscillator

master-in slave-out

DWT

ECO

EEPROM

no connect

NMI

nonmaskable interrupt

non-return-to-zero

electrically erasable programmable read-only

memory

NRZ

NVIC

NVL

opamp

PAL

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

EMI

electromagnetic interference

end of conversion

EOC

EOF

EPSR

ESD

ETM

FIR

end of frame

programmable array logic, see also PLD

program counter

execution program status register

electrostatic discharge

PC

PCB

PGA

PHUB

PHY

printed circuit board

embedded trace macrocell

finite impulse response, see also IIR

flash patch and breakpoint

programmable gain amplifier

peripheral hub

FPB

physical layer

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

Table 14-1. Acronyms Used in this Document (continued)

Acronym Description

PICU port interrupt control unit

Table 14-1. Acronyms Used in this Document (continued)

Acronym

SPI

Description

Serial Peripheral Interface, a communications

protocol

PLA

programmable logic array

programmable logic device, see also PAL

phase-locked loop

SR

slew rate

PLD

PLL

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

PMDD

POR

PRES

PRS

PS

package material declaration datasheet

power-on reset

serial wire debug, a test protocol

single-wire viewer

precise power-on reset

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

pseudo random sequence

port read data register

THD

TIA

®

PSoC

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

TRM

TTL

TX

random-access memory

reduced-instruction-set computing

root-mean-square

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

UDB

universal digital block

Universal Serial Bus

real-time clock

USB

register transfer language

remote transmission request

receive

USBIO

USB input/output, PSoC pins used to connect to

a USB port

RTR

RX

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

2

I C serial clock

WRES

XRES

XTAL

2

SDA

S/H

I C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

15. Reference Documents

special input/output, GPIO with advanced

features. See GPIO.

PSoC® 3, PSoC® 5 Architecture TRM

PSoC® 5 Registers TRM

SOC

SOF

start of conversion

start of frame

Document Number: 001-66235 Rev. **

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16. Document Conventions

16.1 Units of Measure

Table 16-1. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibels

dB

fF

femtofarads

hertz

Hz

KB

kbps

Khr

kHz

kΩ

1024 bytes

kilobits per second

kilohours

kilohertz

kilohms

ksps

LSB

Mbps

MHz

MΩ

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

megaohms

megasamples per second

microamperes

microfarads

microhenrys

microseconds

microvolts

µF

µH

µs

µV

µW

mA

ms

mV

nA

microwatts

milliamperes

milliseconds

millivolts

nanoamperes

nanoseconds

nanovolts

ns

nV

Ω

ohms

pF

picofarads

ppm

ps

parts per million

picoseconds

seconds

s

sps

sqrtHz

V

samples per second

square root of hertz

volts

Document Number: 001-66235 Rev. **

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PSoC^®5: CY8C55 Family Datasheet

17. Revision History

Description Title: PSoC^®5: CY8C55 Family Datasheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-66235

Submission

Date

Orig. of

Change

Rev.

ECN No.

Description of Change

**

3198501

03/17/2011

MKEA

New data sheet.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Clocks & Buffers

Interface

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,

life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical

components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-66235 Rev. **

Revised March 28, 2011

Page 112 of 112

®

CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced

herein are property of the respective corporations.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided

that the system conforms to the I2C Standard Specification as defined by Philips.

ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.

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型号：	CY8C55_11
厂家：	CYPRESS
描述：	Programmable System-on-Chip (PSoC?) 可编程系统级芯片（ PSoC® ）
文件：	总112页 (文件大小：4126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C55_11 [CYPRESS]

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