CYDM128B16-55BVXC [CYPRESS]
1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM; 1.8V 4K / 8K / 16K ×16和8K / 16K ×8 MoBL㈢双口静态RAM
| 型号： | CYDM128B16-55BVXC |
| 厂家： | 
CYPRESS |
| 描述： | 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL® Dual-Port Static RAM |
| 文件： | 总24页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYDM064B16, CYDM128B16, CYDM256B16
1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL®
Dual-Port Static RAM
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Expandable data bus to 32 bits with Master or Slave chip select
when using more than one device
■ 4, 8, or 16K × 16 organization
■ On-chip arbitration logic
■ Ultra Low operating power
❐ Active: ICC = 15 mA (typical) at 55 ns
❐ Standby: ISB3 = 2 μA (typical)
■ Semaphores included to permit software handshaking
between ports
■ Input read registers and output drive registers
■ INT flag for port-to-port communication
■ Separate upper-byte and lower-byte control
■ Industrial temperature ranges
■ Small footprint: Available in a 6x6 mm 100-pin Pb-free vfBGA
■ Port independent 1.8V, 2.5V, and 3.0V IOs
■ Full asynchronous operation
■ Automatic power down
■ Pin select for Master or Slave
Selection Guide for V = 1.8V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Unit
(-55)
Port IO Voltages (P1-P2)
1.8V -1.8V
V
Maximum Access Time
55
15
2
ns
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
mA
μA
μA
2
Selection Guide for V = 2.5V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Unit
(-55)
Port IO Voltages (P1-P2)
2.5V-2.5V
V
Maximum Access Time
55
28
6
ns
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
mA
μA
μA
4
Selection Guide for V = 3.0V
CC
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Unit
(-55)
Port IO Voltages (P1-P2)
3.0V-3.0V
V
Maximum Access Time
55
42
7
ns
Typical Operating Current
Typical Standby Current for ISB1
Typical Standby Current for ISB3
mA
μA
μA
6
Cypress Semiconductor Corporation
Document #: 001-00217 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 31, 2008
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Logic Block Diagram [1, 2]
IO[15:0]R
UBR
IO[15:0]L
UBL
LBL
LBR
IO
IO
Control
Control
16K X 16
Dual Ported Array
Address Decode
Address Decode
A[13:0]L
CE L
A [13:0]R
CE R
Interrupt
Arbitration
Semaphore
OE L
R/W L
SEML
OE R
R/W R
SEMR
BUSY R
BUSY L
M/S
INTL
Mailboxes
INTR
Input Read
Register and
Output Drive
Register
CEL
OEL
CE R
OE R
R/W R
R/WL
IRR0 ,IRR1
ODR0 - ODR4
SFEN
Notes
1. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.
0
11
0
12
0
13
2. BUSY is an output in master mode and an input in slave mode.
Document #: 001-00217 Rev. *F
Page 2 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Pinouts
Figure 1. Ball Diagram - 100-Ball 0.5 mm Pitch BGA (Top View) [3, 4, 5, 6, 7]
CYDM064B16, CYDM128B16, CYDM256B16
1
2
3
4
5
6
7
8
9
10
A5R
A3R
A0R
A8R
A4R
A1R
A11R
A7R
A2R
UBR
A9R
A6R
VSS SEMR IO15R IO12R IO10R
CER R/WR OER VDDIOR IO9R
VSS
IO6R
VSS
IO2R
VSS
A
B
C
D
E
F
A
B
C
D
E
F
IRR1[6]
LBR
A10R
VSS
VCC
OEL
CEL
VCC
IO14R IO11R IO7R
[3]
BUSYR INTR
IO13R IO8R
IO4R VDDIOR IO1R
IO3R
IO11L IO12L IO14L IO13L
IO5R
ODR4 ODR2
A12R
VSS
INTL
VSS
VSS
IO3L
M/S ODR3
BUSYL A1L
IO0R IO15L VDDIOL
SFEN ODR1
[3]
A2L
A4L
A7L
A8L
2
A5L
A9L
A10L
A11L
3
G
H
J
ODR0
A0L
A3L
A6L
1
A12L
G
H
J
NC[7] NC[7]
LBL
IO1L VDDIOL
IO10L
IO9L
IO7L
10
IRR0[5]
VSS
IO4L
IO0L
7
IO6L
IO2L
8
IO8L
IO5L
9
UBL SEML R/WL
K
K
4
5
6
Notes
3. A12L and A12R are NC pins for CYDM064B16.
4. IRR functionality is not supported for the CYDM256B16 device.
5. This pin is A13L for CYDM256B16 device.
6. This pin is A13R for CYDM256B16 device.
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document #: 001-00217 Rev. *F
Page 3 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Table 1. Pin Definitions - 100-Ball 0.5 mm Pitch BGA (CYDM064B16, CYDM128B16, CYDM256B16)
Left Port Right Port Description
CER
Chip Enable
CEL
Read or Write Enable
Output Enable
R/WL
R/WR
OEL
OER
A0L–A13L
IO0L–IO15L
A0R–A13R
IO0R–IO15R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices)
Data Bus Input or Output for x16 devices
Semaphore Enable
SEML
UBL
SEMR
UBR
Upper Byte Select (IO8–IO15
Lower Byte Select (IO0–IO7)
Interrupt Flag
)
LBL
LBR
INTL
INTR
BUSYR
Busy Flag
BUSYL
IRR0, IRR1
Input Read Register for CYDM064B16 and CYDM128B16
A13L and A13R for CYDM256B16.
ODR0-ODR4
SFEN
Output Drive Register. These outputs are Open Drain.
Special Function Enable
Master or Slave Select
M/S
VCC
Core Power
GND
VDDIOL
VDDIOR
NC
Ground
Left Port IO Voltage
Right Port IO Voltage
No Connect. Leave this pin Unconnected.
Document #: 001-00217 Rev. *F
Page 4 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Read Operation
Functional Description
When reading the device, the user must assert both the OE and
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multi-
processor designs, communications status buffering, and
dual-port video or graphics memory.
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the
CYDM256B16) is the mailbox for the right port and the
second-highest memory location (FFE for the CYDM064B16,
1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program must be run and
the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy are
summarized in Table 3 on page 7.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Busy
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (contention). If both port CEs are asserted and an
address match occurs within tPS of each other, the busy logic
determines which port has access. If tPS is violated, one port
definitely gains permission to the location. However, which port
gets this permission cannot be predicted. BUSY is asserted tBLA
after an address match or tBLC after CE is taken LOW.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V, or 3.0V, as long as it
is lower than or equal to the IO voltage.
Each port can operate on independent IO voltages. This is
determined by what is connected to the VDDIOL and VDDIOR pins.
The supported IO standards are 1.8V or 2.5V LVCMOS and 3.0V
LVTTL.
Write Operation
Master/Slave
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 5 on page 18) or the CE pin
(see Figure 6 on page 18). Required inputs for noncontention
operations are summarized in Table 2 on page 7.
An M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, as a result, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output. Otherwise, the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Document #: 001-00217 Rev. *F
Page 5 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits and
DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
When writing to the semaphore, only IO0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port requests the semaphore
(written a zero) while the left port has control, the right port
immediately owns the semaphore as soon as the left port
releases it. Table 6 on page 8 shows sample semaphore
operations.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is available
for memory accesses.
The inputs are 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending
on the core voltage supply (VCC). Refer to Table 4 on page 8 for
Input Read Register operation.
IRR is not available in the CYDM256B16, because the IRR pins
are used as extra address pins A13L and A13R
.
Output Drive Register
When reading a semaphore, all sixteen data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore. On power up, both ports must write
“1” to all eight semaphores.
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages (1.5V
≤ VDDIO ≤ 3.5V) but the combined current cannot exceed 40 mA
(8 mA max for each external device). The status of the ODR bits
are set using standard write accesses from either port to address
x0001 with a “1” corresponding to on and “0” corresponding to
off.
Architecture
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses. When
SFEN = VIH, the ODR is inactive and address x0001 can be used
for standard accesses.
The CYDM256B16, CYDM128B16, and CYDM064B16 consist
of an array of 4K, 8K, or 16K words of 16 dual-port RAM cells,
IO and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes or reads to
the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be used for port-to-port communication.
Two Semaphore (SEM) control pins are used to allocate shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the
device.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 5 on page 8 for Output
Drive Register operation.
Semaphore Operation
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
eight semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port is successful (reads a zero), it assumes
control of the shared resource. Otherwise (reads a one), it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Document #: 001-00217 Rev. *F
Page 6 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Table 2. NonContending Read/Write
Inputs
Outputs
Operation
IO8–IO15
High Z
IO0–IO7
High Z
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
Deselected: Power down
Deselected: Power down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
X
L
H
L
X
X
H
X
H
L
X
X
H
X
H
X
L
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data In
Data Out
Data Out
Data In
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
L
L
X
X
X
X
L
L
X
X
L
L
X
L
Not Allowed
Table 3. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[8]
Left Port
Right Port
Function
A0L–13L
R/WL
CEL
OEL
INTL R/WR
CER
OER
A0R–13R
INTR
L
L
X
X
X
X
X
L
X
X
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
3FFF[11]
X
L[10]
3FFF[11]
H[9]
X
X
X
X
X
X
L
X
X
L
L
L
L
X
X
L[9]
3FFE[11]
X
X
X
X
X
Reset Left INTL Flag
3FFE[11]
H[10]
Notes
8. See Interrupts Functional Description for specific highest memory locations by device.
9. If BUSY = L, then no change.
R
10. If BUSY = L, then no change.
L
11. See section Functional Description on page 5 for specific addresses by device.
Document #: 001-00217 Rev. *F
Page 7 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Table 4. Input Read Register Operation[12, 15]
SFEN
CE
L
R/W
H
OE
L
UB
L
LB
L
ADDR
x0000-Max
x0000
IO0–IO1 IO2–IO15
Mode
Standard Memory Access
IRR Read
VALID[13] VALID[13]
H
L
VALID[14]
X
L
H
L
X
L
Table 5. Output Drive Register [16]
SFEN
CE
L
R/W
H
OE
UB
LB
ADDR
x0000-Max
x0001
IO0–IO4 IO5–IO15
Mode
X[17]
X
L[13]
X
L[13]
L
VALID[13] VALID[13]
H
L
L
Standard Memory Access
VALID[14]
X
ODR Write[16, 18]
ODR Read[16]
L
L
VALID[14]
X
L
H
L
X
L
x0001
Table 6. Semaphore Operation Example
Function
No action
IO0–IO15 Left
IO0–IO15 Right
Status
1
0
0
1
1
1
Semaphore free
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left Port has semaphore token
Nochange. Rightside hasnowrite access
to semaphore.
Left port writes 1 to semaphore
Left port writes 0 to semaphore
1
1
0
0
Right port obtains semaphore token
No change. Left port has no write access
to semaphore.
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
0
1
1
1
0
1
1
1
0
1
1
1
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes
12. SFEN = V for IRR reads
IL
13. UB or LB = V . If LB = V , then DQ<7:0> are valid. If UB = V then DQ<15:8> are valid.
IL
IL
IL
14. LB must be active (LB = V ) for these bits to be valid.
IL
15. SFEN active when either CE = V or CE = V . It is inactive when CE = CE = V .
IH
L
IL
R
IL
L
R
16. SFEN = V for ODR reads and writes.
IL
17. Output enable must be low (OE = V ) during reads for valid data to be output.
IL
18. During ODR writes data are also written to the memory.
Document #: 001-00217 Rev. *F
Page 8 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Static Discharge Voltage.......................................... > 2000V
Latch-up Current ................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings[19] may shorten the useful life of the
device. User guidelines are not tested.
Operating Range
Storage Temperature .................................–65°C to +150°C
Range
Ambient Temperature
VCC
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Commercial
0°C to +70°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Supply Voltage to Ground Potential............... –0.5V to +3.3V
Industrial
–40°C to +85°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VCC + 0.5V
DC Input Voltage[20]...............................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW) .............................90 mA
Electrical Characteristics for V = 1.8V
CC
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
P1 IO Voltage P2 IO Voltage
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
1.8V (any port)
2.5V (any port)
3.0V (any port)
Min
VDDIO – 0.2
2.0
Typ.
Max
VOH
Output HIGH Voltage (IOH = –100 μA)
Output HIGH Voltage (IOH = –2 mA)
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 100 μA)
Output HIGH Voltage (IOL = 2 mA)
Output HIGH Voltage (IOL = 2 mA)
ODR Output LOW Voltage (IOL = 8 mA)
V
V
2.1
V
VOL
0.2
V
0.4
V
0.4
V
VOL ODR
0.2
V
0.2
V
0.2
V
VIH
Input HIGH Voltage
1.2
1.7
2.0
–0.2
–0.3
–0.2
–1
VDDIO + 0.2
V
VDDIO + 0.3
V
VDDIO + 0.2
V
VIL
Input LOW Voltage
0.4
0.6
0.7
1
V
V
V
IOZ
Output Leakage Current
ODR Output Leakage Current.
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
1.8V
2.5V
3.0V
μA
μA
μA
μA
μA
μA
μA
μA
μA
–1
1
–1
1
ICEX ODR
–1
1
VOUT = VDDIO
–1
1
–1
1
IIX
Input Leakage Current
–1
1
–1
1
–1
1
Notes
19. The voltage on any input or IO pin can not exceed the power pin during power up.
20. Pulse width < 20 ns.
Document #: 001-00217 Rev. *F
Page 9 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for V
Over the Operating Range
= 1.8V (continued)
CC
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
P1 IO Voltage P2 IO Voltage
Min
Typ.
Max
ICC
Operating Current (VCC = Max.,
OUT = 0 mA) Outputs Disabled
Ind.
Ind.
1.8V
1.8V
15
25
mA
I
ISB1
Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
1.8V
1.8V
2
6
μA
ISB2
ISB3
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind.
1.8V
1.8V
1.8V
1.8V
8.5
2
14
6
mA
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
μA
ISB4
Standby Current (One Port CMOS Ind.
Level) CEL | CER ≥ VIH, f = fMAX
1.8V
1.8V
8.5
14
mA
[21]
Electrical Characteristics for V = 2.5V
CC
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
VOH
VOL
Description
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 2 mA)
ODR Output LOW Voltage (IOL = 8 mA)
Input HIGH Voltage
Unit
P1 IO Voltage P2 IO Voltage
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
2.5V (any port)
3.0V (any port)
Min
2.0
2.1
Typ.
Max
V
V
0.4
0.4
V
V
VOL ODR
0.2
V
0.2
V
VIH
VIL
IOZ
1.7
2.0
–0.3
–0.2
–1
VDDIO + 0.3
V
VDDIO + 0.2
V
Input LOW Voltage
0.6
0.7
1
V
V
Output Leakage Current
2.5V
3.0V
2.5V
3.0V
2.5V
3.0V
2.5V
2.5V
3.0V
2.5V
3.0V
2.5V
3.0V
2.5V
μA
μA
μA
μA
μA
μA
mA
–1
1
ICEX ODR
ODR Output Leakage Current.
VOUT = VCC
–1
1
–1
1
IIX
Input Leakage Current
–1
1
–1
1
ICC
Operating Current (VCC = Max.,
OUT = 0 mA) Outputs Disabled
Ind.
28
40
I
Notes
21. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
.
MAX
RC
RC
SB3
Document #: 001-00217 Rev. *F
Page 10 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for V
Over the Operating Range
= 2.5V (continued)
CC
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
ISB1
Description
Unit
P1 IO Voltage P2 IO Voltage
Min
Typ.
Max
Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEML= SEMR = VCC – 0.2, f = fMAX
Ind.
Ind.
2.5V
2.5V
6
8
μA
ISB2
ISB3
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
2.5V
2.5V
2.5V
2.5V
18
4
25
6
mA
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
μA
ISB4
Standby Current (One Port CMOS Ind.
Level) CEL | CER ≥ VIH, f = fMAX
2.5V
2.5V
18
25
mA
[21]
Electrical Characteristics for 3.0V Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
P1 IO Voltage P2 IO Voltage
3.0V (any port)
Min
Typ.
Max
VOH
VOL
Output HIGH Voltage (IOH = –2 mA)
Output LOW Voltage (IOL = 2 mA)
ODR Output LOW Voltage (IOL = 8 mA)
Input HIGH Voltage
2.1
V
V
3.0V (any port)
0.4
VOL ODR
3.0V (any port)
0.2
V
VIH
VIL
IOZ
3.0V (any port)
2.0
–0.2
–1
VDDIO + 0.2
V
Input LOW Voltage
3.0V (any port)
0.7
1
V
Output Leakage Current
3.0V
3.0V
3.0V
3.0V
μA
μA
ICEX ODR
ODR Output Leakage Current.
–1
1
VOUT = VCC
IIX
Input Leakage Current
3.0V
3.0V
3.0V
3.0V
–1
1
μA
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Ind.
Ind.
42
7
60
mA
ISB1
Standby Current (Both Ports TTL
Level) CEL and CER ≥ VCC – 0.2,
SEML = SEMR = VCC – 0.2, f = fMAX
3.0V
3.0V
10
μA
ISB2
ISB3
Standby Current (One Port TTL
Level) CEL | CER ≥ VIH, f = fMAX
Ind.
3.0V
3.0V
3.0V
3.0V
25
6
35
8
mA
Standby Current (Both Ports CMOS Ind.
Level) CEL and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC – 0.2V, f = 0
μA
ISB4
Standby Current (One Port CMOS Ind.
Level) CEL | CER ≥ VIH, f = fMAX
3.0V
3.0V
25
35
mA
[21]
Capacitance[22]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
9
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 3.0V
V
COUT
10
pF
Note
22. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00217 Rev. *F
Page 11 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
AC Test Loads and Waveforms
3.0V/2.5V/1.8V
3.0V/2.5V/1.8V
RTH = 6 kΩ
R1
OUTPUT
C = 30 pF
OUTPUT
R1
OUTPUT
C = 30 pF
R2
C = 5 pF
R2
VTH = 0.8V
(a) Normal Load
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
ALL INPUT PULSES
3.0V/2.5V
1022Ω
1.8V
1.8V
GND
R1
R2
13500Ω
10800Ω
90%
90%
10%
≤ 3 ns
10%
792Ω
≤ 3 ns
Switching Characteristics for V = 1.8V
CC
Over the Operating Range[23]
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
Min
55
5
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
55
tOHA
tACE
tDOE
[24]
55
30
[25, 26, 27]
5
5
0
tLZOE
[25, 26, 27]
OE HIGH to High Z
25
25
tHZOE
[25, 26, 27]
[25, 26, 27]
CE LOW to Low Z
tLZCE
CE HIGH to High Z
tHZCE
[27]
CE LOW to Power up
CE HIGH to Power down
Byte Enable Access Time
tPU
[27]
55
55
tPD
[24]
tABE
Notes
23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V , and output loading of the specified I /I
CC
CC
OI OH
and 30 pF load capacitance.
24. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
25. At any given temperature and voltage condition for any given device, t
26. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
waveform.
Document #: 001-00217 Rev. *F
Page 12 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for V
= 1.8V (continued)
CC
Over the Operating Range[23]
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
Min
Max
Write Cycle
tWC
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[24]
CE LOW to Write End
tSCE
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
[24]
tSA
tPWE
tSD
0
40
30
0
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
[26, 27]
25
tHZWE
[26, 27]
R/W HIGH to Low Z
0
tLZWE
[28]
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
80
80
tWDD
[28]
tDDD
Busy Timing[29]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Setup for Priority
[30]
5
0
tPS
tWB
tWH
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
35
[31]
40
tBDD
Interrupt Timing[29]
tINS
INT Set Time
45
45
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
15
10
10
ns
ns
ns
ns
tSAA
55
Notes
28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
29. Test conditions used are Load 2.
30. Add 2ns to this parameter if V and V
are <1.8V, and V
is >2.5V at temperature <0°C.
CC
DDIOR
DDIOL
31. t
is a calculated parameter and is the greater of t
– t
(actual) or t
– t (actual).
DDD SD
BDD
WDD
PWE
Document #: 001-00217 Rev. *F
Page 13 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for V = 2.5V
CC
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Unit
Min
55
5
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
55
tOHA
tACE
tDOE
[24]
55
30
[25, 26, 27]
2
2
0
tLZOE
[25, 26, 27]
OE HIGH to High Z
25
25
tHZOE
[25, 26, 27]
CE LOW to Low Z
tLZCE
[25, 26, 27]
CE HIGH to High Z
tHZCE
[27]
CE LOW to Power up
CE HIGH to Power down
Byte Enable Access Time
tPU
[27]
55
55
tPD
[24]
tABE
Write Cycle
tWC
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[24]
CE LOW to Write End
tSCE
tAW
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
tHA
[24]
0
tSA
tPWE
tSD
40
30
0
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
[26, 27]
25
tHZWE
[26, 27]
R/W HIGH to Low Z
0
tLZWE
[28]
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
80
80
tWDD
[28]
tDDD
Busy Timing[29]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Setup for Priority
[30]
5
0
tPS
tWB
tWH
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
35
[31]
40
tBDD
Document #: 001-00217 Rev. *F
Page 14 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for V
Over the Operating Range
= 2.5V (continued)
CC
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
Min
Max
Interrupt Timing[29]
tINS
tINR
Semaphore Timing
INT Set Time
45
45
ns
ns
INT Reset Time
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
15
10
10
ns
ns
ns
ns
tSAA
55
Switching Characteristics for V = 3.0V
CC
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
Min
55
5
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
55
tOHA
tACE
tDOE
[24]
55
30
[25, 26, 27]
1
1
0
tLZOE
[25, 26, 27]
OE HIGH to High Z
25
25
tHZOE
[25, 26, 27]
CE LOW to Low Z
tLZCE
[25, 26, 27]
CE HIGH to High Z
tHZCE
[27]
CE LOW to Power up
CE HIGH to Power down
Byte Enable Access Time
tPU
[27]
55
55
tPD
[24]
tABE
Write Cycle
tWC
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
[24]
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
tSCE
tAW
tHA
[24]
0
tSA
tPWE
tSD
40
30
0
Data Setup to Write End
Data Hold From Write End
tHD
Document #: 001-00217 Rev. *F
Page 15 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for V
Over the Operating Range
= 3.0V (continued)
CC
CYDM256B16, CYDM128B16, CYDM064B16
-55
Parameter
Description
Unit
Min
Max
[26, 27]
R/W LOW to High Z
25
ns
ns
ns
ns
tHZWE
[26, 27]
R/W HIGH to Low Z
0
tLZWE
[28]
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
80
80
tWDD
[28]
tDDD
Busy Timing[29]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Setup for Priority
[30]
5
0
tPS
tWB
tWH
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
35
[31]
40
tBDD
Interrupt Timing[29]
tINS
INT Set Time
45
45
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
15
10
10
ns
ns
ns
ns
tSAA
55
Document #: 001-00217 Rev. *F
Page 16 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms
Figure 2. Read Cycle No.1 (Either Port Address Access) [32, 33, 34]
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Figure 3. Read Cycle No.2 (Either Port CE/OE Access) [32, 35, 36]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
ICC
t
LZCE
t
PU
t
PD
CURRENT
ISB
Figure 4. Read Cycle No. 3 (Either Port) [32, 34, 37, 38]
t
RC
ADDRESS
UB or LB
t
AA
t
OHA
t
t
HZCE
t
t
LZCE
t
ABE
CE
HZCE
t
ACE
LZCE
DATA OUT
Notes
32. R/W is HIGH for read cycles.
33. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
34. OE = V
.
IL
35. Address valid before or coincident with CE transition LOW.
36. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IL
IH
IH
37. R/W must be HIGH during all address transitions.
38. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
Document #: 001-00217 Rev. *F
Page 17 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 5. Write Cycle No.1: R/W Controlled Timing [37, 38, 39, 40, 41, 42]
t
WC
ADDRESS
OE
[43]
t
HZOE
t
AW
[41, 42]
CE
[40]
PWE
t
t
t
HA
SA
R/W
DATA OUT
DATA IN
[43]
HZWE
t
t
LZWE
NOTE 44
NOTE 44
t
t
HD
SD
Figure 6. Write Cycle No. 2: CE Controlled Timing [37, 38, 39, 44]
t
WC
ADDRESS
t
AW
[41, 42]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes
39. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
40. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the IO drivers to turn off and data to be
PWE
HZWE SD
placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
SD
specified t
.
PWE
41. To access RAM, CE = V , SEM = V
.
IH
IL
42. To access upper byte, CE = V , UB = V , SEM = V .
IH
IL
IL
To access lower byte, CE = V , LB = V , SEM = V .
IH
IL
IL
43. Transition is measured ±0 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
44. During this period, the IO pins are in the output state, and input signals must not be applied.
Document #: 001-00217 Rev. *F
Page 18 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 7. Semaphore Read After Write Timing (Either Side) [45, 46]
t
t
OHA
SAA
A0–A2
VALID ADRESS
VALID ADRESS
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
IO0
DATAIN VALID
DATAOUT VALID
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Figure 8. Timing Diagram of Semaphore Contention [47, 48]
A0L–A2L
MATCH
R/WL
SEML
t
SPS
A0R–A2R
MATCH
R/WR
SEMR
Notes
45. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
46. CE = HIGH for the duration of the above timing (both write and read cycle).
47. IO = IO = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
48. If t
is violated, the semaphore is definitely obtained by one side or the other, but the side that gets the semaphore cannot be predicted.
SPS
Document #: 001-00217 Rev. *F
Page 19 of 24
[+] Feedback
CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 9. Timing Diagram of Read with BUSY (M/S = HIGH) [49]
t
WC
ADDRESSR
R/WR
MATCH
t
PWE
t
t
HD
SD
DATA INR
VALID
t
PS
ADDRESSL
MATCH
t
BLA
t
BHA
BUSYL
t
BDD
t
DDD
DATAOUTL
VALID
t
WDD
Figure 10. Write Timing with Busy Input (M/S = LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note
49. CE = CE = LOW.
L
R
Document #: 001-00217 Rev. *F
Page 20 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 11. Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First[50]
ADDRESSL,R
ADDRESS MATCH
CEL
CER
t
PS
t
t
BHC
BLC
BUSYR
CER Valid First
ADDRESSL,R
ADDRESS MATCH
CER
CEL
t
PS
t
t
BHC
BLC
BUSYL
Figure 12. Busy Timing Diagram No.2 (Address Arbitration) [50]
Left Address Valid First
t
or t
WC
RC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSR
t
t
BHA
BLA
BUSYR
Right Address Valid First
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSYL
t
t
BHA
BLA
Note
50. If t is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY iS asserted.
PS
Document #: 001-00217 Rev. *F
Page 21 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 13. Interrupt Timing Diagrams
Left Side Sets INTR
t
WC
ADDRESSL
CEL
WRITE 1FFF (OR 1/3FFF)
[51]
t
HA
R/WL
INTR
[52]
t
INS
Right Side Clears INTR
t
RC
READ 1FFF
(OR 1/3FFF)
ADDRESSR
CER
[52]
t
INR
R/WR
OER
INTR
Right Side Sets INTL
t
WC
ADDRESSR
CER
WRITE 1FFE (OR 1/3FFE)
[51]
HA
t
R/WR
INTL
[52]
INS
t
Left Side Clears INTL
t
RC
READ 1FFE
OR 1/3FFE)
ADDRESSL
CEL
[52]
INR
t
R/WL
OEL
INTL
Notes
51. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
52. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document #: 001-00217 Rev. *F
Page 22 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Ordering Information
Table 7. 16K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CYDM256B16-55BVXC
CYDM256B16-55BVXI
Package Name
BZ100
Package Type
Operating Range
Commercial
55
55
100-ball Pb-free 0.5 mm Pitch BGA
100-ball Pb-free 0.5 mm Pitch BGA
BZ100
Industrial
Table 8. 8K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CYDM128B16-55BVXC
CYDM128B16-55BVXI
Package Name
BZ100
Package Type
Operating Range
Commercial
55
55
100-ball Pb-free 0.5 mm Pitch BGA
100-ball Pb-free 0.5 mm Pitch BGA
BZ100
Industrial
Table 9. 4K x16 1.8V Asynchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CYDM064B16-55BVXC
CYDM064B16-55BVXI
Package Name
BZ100
Package Type
Operating Range
Commercial
55
55
100-ball Pb-free 0.5 mm Pitch BGA
100-ball Pb-free 0.5 mm Pitch BGA
BZ100
Industrial
Package Diagram
Figure 14. 100 VFBGA (6 x 6 x 1.0 mm) BZ100A
"/44/- 6)%7
!ꢀ #/2.%2
4/0 6)%7
ꢁꢂꢁꢃ - #
ꢁꢂꢀꢃ - # ! "
!ꢀ #/2.%2
ꢁꢂꢄꢁ¼ꢁꢂꢁꢃꢅꢀꢁꢁ8ꢆ
ꢀ
ꢈ ꢄ ꢇ ꢃ ꢊ ꢎ ꢉ ꢌ ꢀꢁ
ꢀꢁ
ꢌ
ꢉ
ꢎ ꢊ ꢃ ꢇ ꢄ ꢈ ꢀ
!
!
"
#
$
%
"
#
$
%
&
&
'
'
(
(
*
*
+
+
ꢈꢂꢈꢃ
!
!
ꢁꢂꢃꢁ
ꢇꢂꢃꢁ
"
ꢊꢂꢁꢁ¼ꢁꢂꢀꢁ
"
ꢊꢂꢁꢁ¼ꢁꢂꢀꢁ
ꢁꢂꢀꢃꢅꢇ8ꢆ
2%&%2%.#% *%$%# -/ꢋꢀꢌꢃ#
0+'ꢂ7%)'(4ꢍ4"$ ꢅ.%7 0+'ꢂꢆ
3%!4).' 0,!.%
#
51-85209 *B
Document #: 001-00217 Rev. *F
Page 23 of 24
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CYDM064B16, CYDM128B16, CYDM256B16
Document History Page
DocumentTitle:CYDM064B16, CYDM128B16, CYDM256B161.8V4K/8K/16Kx16and8K/16Kx8MoBL® Dual-PortStaticRAM
Document Number: 001-00217
Orig. of
Change
Submission
Date
REV.
ECN NO.
Description of Change
**
369423
381721
YDT
YDT
New data sheet
*A
Updated 2.5V/3.0V ICC, ISB1, ISB2, ISB4
Updated VOL ODR to 0.2V
*B
*C
396697
404777
KGH
KGH
Updated ISB2 and ISB4 typo to mA.
Updated tINS and tINR for -55 to 31ns.
Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
VOL
Replaced -35 speed bin with -40
Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
Included note 35
*D
*E
426637
733676
KGH
HKH
Removed part numbers CYDM128B08 and CYDM064B08
Corrected typo for power supply description in page 4 (3.0V instead of 3.3V)
Updated tDDD timing value to be consistent with tWDD
*F
2545957 OGC/AESA 07/31/2008 Removed all details of -40ns parts. Updated data sheet template.
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© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-00217 Rev. *F
Revised July 31, 2008
Page 24 of 24
MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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