CYF0072V18L-133BGXI [CYPRESS]
18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO; 18/36/72百万位元可编程的FIFO主复位清除整个FIFO
| 型号： | CYF0072V18L-133BGXI |
| 厂家： | 
CYPRESS |
| 描述： | 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO |
| 文件： | 总29页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYF0018V, CYF0036V
CYF0072V
18/36/72 Mbit Programmable FIFOs
18/36/72/144 Mbit Programmable FIFOs
Features
Functional Description
■ Memory organization
❐ Industry's largest first in first out (FIFO) memory densities:
18 Mbit, 36 Mbit, and 72 Mbit
❐ Selectable memory organization: ×9, ×12, ×16, ×18, ×20,
×24, ×32, ×36
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable user to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different domains.
■ Up to 133-MHz clock operation
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks up to a
maximum ratio of two enabling data buffering across clock
domains
❐ Supports multiple I/O voltage standard: low voltage comple-
mentary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio between read and write clock
is in the range of 0.5 to 2. Appropriate flags are set whenever the
FIFO is empty, full, half-full, almost-full, or almost-empty.
■ Input and output enable control for write mask and read skip
operations
■ Mark and retransmit: resets read pointer to user marked
position
■ Empty, full, half-full, and programmable almost-empty and
almost-full status flags with preselected offsets
■ Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
■ Configure programmable flags and registers through serial or
parallel modes
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All product features and specs are common to all densities (
CYF0072V, CYF0036V, and CYF0018V) unless otherwise
specified. All descriptions are given assuming the device is
CYF0072V operated in ×36 mode. They hold good for other
densities (CYF0036V, and CYF0018V) and all port sizes ×9, ×12,
×16, ×18, ×20, ×24 and ×32 unless otherwise specified. the only
difference will be in the input and output bus width. Table 1 shows
the part of bus with valid data from D[35:0] and Q[35:0] in ×9,
×12, ×16, ×18, ×20, ×24, ×32 and ×36 modes.
■ Separate serial clock (SCLK) input for serial programming
■ Master reset to clear entire FIFO
■ Partial reset to clear data but retain programmable settings
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Cypress Semiconductor Corporation
Document Number: 001-53687 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 31, 2011
CYF0018V, CYF0036V
CYF0072V
Logic Block Diagram
Document Number: 001-53687 Rev. *H
Page 2 of 29
CYF0018V, CYF0036V
CYF0072V
Contents
Pin Definitions ......................................................... 5
Architecture ............................................................. 7
Reset Logic......................................................... 7
Flag Operation.................................................... 7
Full Flag.............................................................. 7
Half-Full Flag ...................................................... 7
Empty Flag ......................................................... 7
Programmable Almost-Empty and
Almost-Full Flags................................................ 7
Retransmit from Mark Operation ........................ 7
Flow-through Mailbox Register........................... 7
Selecting Word Sizes ......................................... 8
Power Up.................................................................. 8
Write Mask and Read Skip Operation ................ 8
Programming Flag Offsets and
Maximum Ratings ................................................. 13
Operating Range ................................................... 13
Switching Characteristics .................................... 15
Switching Waveforms........................................... 16
Ordering Information ............................................ 24
Ordering Code Definition.................................. 24
Package Diagram .................................................. 25
Acronyms............................................................... 26
Document Conventions........................................ 26
Units of Measure .............................................. 26
Document History Page........................................ 27
Sales, Solutions, and Legal Information............. 29
Worldwide Sales and Design Support.............. 29
Products ........................................................... 29
PSoC Solutions ................................................ 29
Configuration Registers...................................... 8
Width Expansion Configuration ........................ 10
Memory Organization for Different Port Sizes.. 11
Read/Write Clock Requirements ...................... 11
JTAG Operation................................................ 12
Document Number: 001-53687 Rev. *H
Page 3 of 29
CYF0018V, CYF0036V
CYF0072V
G
Pin Diagram for CYF 0 XXX V
Figure 1. 209-Ball FBGA (Top View)
1
2
3
4
5
PORTSZ0
DNU
6
PORTSZ1
PORTSZ2
DNU
7
DNU
8
9
10
Q0
11
Q1
A
B
C
D
E
F
FF
D0
D1
DNU
DNU
DNU
VCC1
VCC2
VSS
DNU
DNU
DNU
VCC1
VCC2
VSS
RT
EF
D2
D3
DNU
REN
RCLK
Vss
Q2
Q3
D4
D5
WEN
VSS
VCC1
DNU
VCC1
DNU
Q4
Q5
D6
D7
LD
Q6
Q7
D8
D9
VCC2
VSS
VCCIO
VSS
VCCIO
DNU
VCCIO
VSS
VCC2
VSS
Q8
Q9
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
PAF
TDO
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
PAE
HF
Q10
Q12
Q14
Q16
VCCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
Q11
Q13
Q15
Q17
VCCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
G
H
J
VCC2
VSS
VCC2
VSS
VCCIO
VSS
VCC1
VCC1
VCC1
IE
VCCIO
VSS
VCC2
VSS
VCC2
VSS
VCC2
WCLK
VCC2
VSS
VCC2
DNU
VCC2
VSS
VCCIO
VSS
VCCIO
VSS
VCC2
DNU
VCC2
VSS
VCC2
VCCIO
VCC2
VSS
K
L
VCCIO
VSS
VCC1
VCC1
VCC1
SPI_SEN
VCCIO
SPI_SI
DNU
VCCIO
VSS
M
N
P
R
T
VCC2
VSS
VCC2
VSS
VCCIO
VSS
VCCIO
VSS
VCC2
VSS
VCC2
VSS
VCC2
VSS
VCC2
VCC1
D31
VCCIO
VCC1
PRS
VCCIO
VCC1
SPI_SCLK
MB
VCC2
VCC1
Vref
VCC2
VSS
U
V
W
D30
OE
D32
D33
DNU
MRS
DNU
TCK
MARK
Vref
D34
D35
TDI
TRST
TMS
Document Number: 001-53687 Rev. *H
Page 4 of 29
CYF0018V, CYF0036V
CYF0072V
Pin Definitions
Pin Name
D[35:0]
I/O
Input
Output Data outputs: Data outputs for a 36-bit bus
Pin Description
Data inputs: Data inputs for a 36-bit bus
Q[35:0]
WEN
REN
IE
Input
Input
Input
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for 'write masking' or incrementing the write pointer without writing into a location.
OE
Input
Input
Input
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
WCLK
RCLK
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
EF
Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Output Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
PAF
LD
Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchronized to WCLK.
Input
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO
RT
Input
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
MRS
Input
Master reset: MRS initializes the internal read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the configuration registers are all set to default values and flags are
reset.
PRS
Input
Input
Partial reset: PRS initializes the internal read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the configuration register settings are all retained and flags are reset.
SPI_SCLK
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
SPI_SI
SPI_SEN
MARK
Input
Input
Input
Serial input: Serial input data in SPI mode.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
MB
Input
Input
Input
Input
Input
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Test clock (TCK) Pin for JTAG
TCK
TRST
TMS
TDI
Reset pin for JTAG
Test mode select (TMS) pin for JTAG
Test data in (TDI) pin for JTAG
TDO
HF
Output Test data out (TDO) for JTAG
Output Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK.
Document Number: 001-53687 Rev. *H
Page 5 of 29
CYF0018V, CYF0036V
CYF0072V
Pin Definitions (continued)
Pin Name
DVal
I/O
Pin Description
Output Data valid: Active low data valid signal to indicate valid data on Q[35:0]
PORTSZ [2:0]
VCC1
Input
Port word size select: Port word width select pins (common for read and write ports)
Core voltage supply 1: 1.8V supply voltage
Power
Supply
VCC2
VCCIO
Vref
Power
Supply
Core voltage supply 2: 1.5V supply voltage
Supply for I/Os
Power
Supply
Input
Reference
Reference voltage: Reference voltage (regardless of I/O standard used)
VSS
Ground Ground
Do not use: These pins need to be left floating
DNU
–
Document Number: 001-53687 Rev. *H
Page 6 of 29
CYF0018V, CYF0036V
CYF0072V
have to be read back in order for full flag to get de-asserted.The
minimum number of reads required to de-assert full-flag is two
and the maximum number of reads required to de-assert full flag
is six.
Architecture
The CYF0072V, CYF0036V, and CYF0018V are of memory
arrays of 72 Mbit, 36 Mbit, and 18 Mbit respectively. The memory
organization is user configurable and word sizes can be selected
as x9, x12, x16, x18, x20, x24, x32, or x36. The logic blocks to
implement FIFO functionality and the associated features are
built around these memory arrays.
Half-Full Flag
The Half-Full (HF) flag goes LOW when half of the memory array
is written. The assertion of HF is synchronized to WCLK. The
assertion and de-assertion of Half-Full flag with associated
latencies is explained in Table 12
The input and output data buses have a maximium width of 36
bits. The input data bus goes to an input register and the data
flow from the input register to the memory is controlled by the
write logic block. The inputs to the write logic block are WCLK,
WEN and IE. When the writes are enabled through WEN and if
the inputs are enabled by IE, then the data on the input bus is
written into the memory array at the rising edge of WCLK. This
also increments the write pointer. Enabling writes but disabling
the data input pins through IE only increments the write pointer
without doing any writes or altering the contents of the location.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, that is, it is
exclusively updated by each rising edge of RCLK. The assertion
and de-assertion of empty flag with associated latencies is
explained in Table 12
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, OE, RT and MARK. When reads are
enabled by REN and outputs are enabled through OE, the data
from the memory pointed by the read pointer is transferred to the
output data bus at the rising edge of RCLK along with active low
DVal. If the outputs are disabled but the reads enabled, the
outputs are in high impedance state, but internally the read
pointer is incremented.
Programmable Almost-Empty and Almost-Full Flags
The CYF0072V includes programmable Almost-Empty and
Almost-Full flags. Each flag is programmed (see Programming
Flag Offsets and Configuration Registers on page 8) a specific
distance from the corresponding boundary flags (Empty or Full).
(offset can range from 16 to 1024) When the FIFO contains the
number of words (or fewer) for which the flags are programmed,
the PAF or PAE is asserted, signifying that the FIFO is either
almost-full or almost-empty. The PAF flag signal transition is
caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock. The
assertion and de-assertion of empty flag with associated
latencies is explained in Table 12
During write operation, the number of writes performed is always
a even number (i.e., minimum write burst length is two and
number of writes always a multiple of two). Whereas during read
operation, the number of reads performed can be even or odd
(i.e., minimum read burst length is one).
Retransmit from Mark Operation
The MARK signal is used to ‘mark’ the location from which data
is retransmitted when requested.
The retransmit feature is useful for transferring packets of data
repeatedly. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
feature is used when the number of writes after MARK is equal
to or less than the depth of the FIFO and at least one word has
been read since the last reset cycle. A HIGH pulse on RT resets
the internal read pointer to a physical location of the FIFO that is
marked by the user (using the MARK pin). With every valid read
cycle after retransmit, previously accessed data is read and the
read pointer is incremented until it is equal to the write pointer.
Flags are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data written
to FIFO after activation of RT are also transmitted. The full depth
of the FIFO can be repeatedly retransmitted.
Reset Logic
The FIFO can be reset in two ways: Master Reset (MRS) and
Partial Reset (PRS). The MRS initializes the read and write
pointers to zero and sets the output register to all zeroes. It also
resets the configuration registers to their default values. The
word size is configured through pins; values of the three
PORTSZ pins are latched during MRS. A Master Reset is
required after power-up before accessing the FIFO. The PRS
resets only the read and write pointer to the first location and
does not affect the programmed configuration registers.
Flag Operation
To mark a location, the Mark pin is asserted when reading that
particular location.
This device provides five flag pins to indicate the condition of the
FIFO contents.
Flow-through Mailbox Register
Full Flag
This feature transfers data from input to output directly by
bypassing the FIFO sequence. When MB signal is asserted the
data present in D[35:0] will be available at Q[35:0] after two
WCLK cycles. Normal read and write operations are not allowed
during flow-through mailbox operation. Before starting
Flow-through mailbox operation FIFO read should be completed
to make data valid DVal high in order to avoid data loss from
FIFO. The width of flow-through mailbox register always corre-
sponds to port size.
The Full Flag (FF) goes LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is exclu-
sively updated by each rising edge of WCLK. The worst case
assertion latency for Full Flag is four. As the user cannot know
that the FIFO is full for four clock cycles, it is possible that user
continues writing data during this time. In this case, the four data
word written will be stored to prevent data loss and these words
Document Number: 001-53687 Rev. *H
Page 7 of 29
CYF0018V, CYF0036V
CYF0072V
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
keeping track of REN to data output latency. This signal also
helps when write and read operations are performed continu-
ously at different frequencies by indicating when valid data is
available at the output port Q[35:0].
Selecting Word Sizes
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. Table 1.
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is less than ×36. If word size is
less than ×36, the unused output pins are tri-stated by the device
and unused input pins will be ignored by the internal logic. The
pins with valid data input D[N:0] and output Q[N:0] is given in
Table 1.
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
Vref attain minimum stable voltage required as given in Recom-
mended DC Operating Conditions on page 13. The device can
be accessed tPU time after these supplies attain the minimum
required level (see Switching Characteristics on page 15). There
is no particular power sequencing required for the device.
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal, synchronized to RCLK
and is provided for easy capture of output data to the user. When
Table 1. Word Size Selection
PORTSZ[2:0]
Word Size
×9
Active Input Data Pins D[X:0] Active Output Data Pins Q[X:0]
000
001
010
011
100
101
110
111
D[8:0]
D[11:0]
D[15:0]
D[17:0]
D[19:0]
D[23:0]
D[31:0]
D[35:0]
Q[8:0]
Q[11:0]
Q[15:0]
Q[17:0]
Q[19:0]
Q[23:0]
Q[31:0]
Q[35:0]
×12
×16
×18
×20
×24
×32
×36
pin. A low on the SPI_SEN selects the serial method for writing
into the registers. For serial programming, there is a separate
SCLK and a Serial Input (SI). In parallel mode, a low on the load
(LD) pin causes the write and read operation to these registers.
The write and read operation happens from the first location
(0x1) to the last location (0xA) in a sequence. If LD is high, the
writes occur to the FIFO.
Write Mask and Read Skip Operation
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows user to move the
write pointer without actually writing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
In addition to loading register values into the FIFO, it is also
possible to read the current register values. Register values can
be read through the parallel output port regardless of the
programming mode selected (serial or parallel). Register values
cannot be read serially. The registers may be programmed (and
reprogrammed) any time after master reset, regardless of
whether serial or parallel programming is selected.
Similarly, during a read operation, if the outputs are disabled by
having the OE high, the read data does not appear on the output
bus; however, the read pointer is incremented.
Programming Flag Offsets and Configuration
Registers
See Table 3 on page 9 and Table 4 on page 10 for access to
configuration registers in serial and parallel modes.
The CYF0072V has ten 8-bit user configurable registers. These
registers contain the almost-full offset (M) and almost-empty (N)
values which decide when the PAF and PAE flags are asserted.
In parallel mode, the read and write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations should be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles(WCLK) cycles.
These registers can be programmed into the FIFO in one of two
ways: using either the serial or parallel loading method. The
loading method is selected using the SPI_SEN (Serial Enable)
Document Number: 001-53687 Rev. *H
Page 8 of 29
CYF0018V, CYF0036V
CYF0072V
Table 2. Configuration Registers
ADDR Configuration Register
Default
0x00
Bit [7] Bit [6] Bit [5] Bit [4]
Bit [3] Bit [2] Bit [1] Bit [0]
0x1 Reserved
0x2 Reserved
0x3 Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x00
0x00
X
X
X
X
X
X
X
X
0x4 Almost-Empty Flag generation 0x7F
address - (LSB) (N)
D7
D6
D5
D4
D3
D2
D1
D0
0x5 Almost-Empty Flag generation 0x00
address - (MSB) (N)
X
X
X
X
X
X
D9
D8
0x6 Reserved
0x00
0x7F
X
X
X
X
X
X
X
X
0x7 Almost-Full Flag generation
address - (LSB) (M)
D7
D6
D5
D4
D3
D2
D1
D0
0x8 Almost-Full Flag generation
address - (MSB) (M)
0x00
X
X
X
X
X
X
D9
D8
0x9 Reserved
0x00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0xA Fast CLK Bit Register
1XXXXXXXb Fast CLK
bit
Table 3. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
0
1
First rising edge
because both LD and
REN are low
X
X
Parallel write to first register
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Second rising edge
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Parallel write to second register
Third rising edge
Parallel write to third register
Fourth rising edge
Parallel write to fourth register
Tenth rising edge
Eleventh rising edge
Parallel write to tenth register
Parallel write to first register
(roll back)
1
1
0
0
1
1
0
0
X
X
Firstrisingedgesince
both LD and REN are
low
X
X
Parallel read from first register
Second rising edge
Parallel read from second
register
1
1
0
0
1
1
0
0
X
X
Third rising edge
Fourth rising edge
X
X
Parallel read from third register
Parallel read from fourth
register
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
Tenth rising edge
Parallel read from tenth
register
Document Number: 001-53687 Rev. *H
Page 9 of 29
CYF0018V, CYF0036V
CYF0072V
Table 3. Writing and Reading Configuration Registers in Parallel Mode (continued)
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
1
0
X
Eleventh rising edge
X
Parallel read from first register
(roll back)
1
X
X
0
X
1
1
0
1
0
1
X
0
1
X
X
X
X
X
X
No operation
Rising edge
X
Write to FIFO memory
Read from FIFO memory
Illegal operation
X
X
X
X
Rising edge
X
Table 4. Writing into Configuration Registers in Serial Mode
SPI_SEN
LD
WEN
REN
WCLK
RCLK
SCLK
Operation
0
1
X
X
X
X
EachrisingoftheSCLKclocks
in one bit from the SI (Serial
In). Any of the 10 registers can
be addressed and written to,
following the SPI protocol.
Rising edge
X
X
1
1
0
X
0
X
X
X
Parallel write to FIFO memory.
Rising edge
X
X
Parallel read from FIFO
memory.
Rising edge
1
0
1
1
X
X
X
This corresponds to parallel
mode (refer to Table 3).
Figure 2. Serial WRITE to Configuration Register
Width Expansion Configuration
The width of CYFX072V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line
inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE
and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 on page 11 demonstrates an example
of 72 bit-word width by using two 36-bit word CYFX072Vs.
Document Number: 001-53687 Rev. *H
Page 10 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 3. Using Two CYFX072V for Width Expansion
DATAIN (D)
72
36
36
READCLOCK(RCLK)
READENABLE(REN)
OUTPUT ENABLE(OE)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
PAF
CYFX072V
CYFX072V
PAE
HF
EF
DATAOUT (Q)
EF
FF
FF
EF
36
72
FF
36
Memory Organization for Different Port Sizes
Read/Write Clock Requirements
The 72-Mbit memory has different organization for different port
sizes. Table 5 shows the depth of the FIFO for all port sizes.
The read and write clocks must satisfy the following
requirements:
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
■ Both read (RCLK) and write (WCLK) clocks should be
free-running.
■ The clock frequency for both clocks should be between the
minimum and maximum range given in Table 10 on page 13.
Table 5. Word Size Selection
■ The WCLK to RCLK ratio should be in the range of 0.5 to 2.
PORTSZ[2:0]
Word Size
x9
FIFO Depth
8 Meg
Memory Size
72 Mbit
48 Mbit
64 Mbit
72 Mbit
40 Mbit
48 Mbit
64 Mbit
72 Mbit
000
001
010
011
100
101
110
111
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
by using counters after the MRS cycle. The device uses two
10-bit counters inside (one running on RCLK and other on
WCLK), which count 1,024 cycles of read and write clock after
MRS. The clock of the counter which reaches its terminal count
first is used as master clock inside the FIFO.
x12
4 Meg
x16
4 Meg
x18
4 Meg
x20
2 Meg
x24
2 Meg
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
x32
2 Meg
x36
2 Meg
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
Document Number: 001-53687 Rev. *H
Page 11 of 29
CYF0018V, CYF0036V
CYF0072V
JTAG Operation
CYFX072V has two devices connected internally in a JTAG chain as shown in Figure 4
Figure 4. Device Connection in a JTAG Chain
TRST
TMS
TCK
TDI
TDO
Table 6 shows the IR register length and device ID
Table 6. JTAG IDCODES
IR Register Length
Device ID (HEX)
“Ignore”
Bypass Register Length
Device-1
Device-2
3
8
1
1
1E3261CF
Table 7. JTAG Instructions for Device-1
Device-1
Opcode (Binary)
111
BYPASS
Table 8. JTAG Instructions for Device-2
Device-2
EXTEST
Opcode (HEX)
00
07
01
FF
0F
HIGHZ
SAMPLE/PRELOAD
BYPASS
IDCODE
Document Number: 001-53687 Rev. *H
Page 12 of 29
CYF0018V, CYF0036V
CYF0072V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
I/O port supply voltage (VCCIO) ............................–0.3 V to 3.7 V
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (LOW) .............................. 20 mA
Storage temperature (without bias) ............ –65 C to +150 C
Ambient temperature with
power applied
Static discharge voltage........................................... > 2001 V
(per MIL–STD–883, Method 3015)
–55 C to +125 C
Core supply voltage 1 (VCC1) to
ground potential.................................................–0.3 V to 2.5 V
Operating Range
Core supply voltage 2 (VCC2) to
ground potential...............................................–0.3 V to 1.65 V
Range
Ambient Temperature
–40 C to +85 C
Industrial
Latch up current ....................................................>100mA
Table 9. Recommended DC Operating Conditions
Parameter
VCC1
Description
Min
1.70
1.425
0.7
Typ
1.80
1.5
Max
1.90
1.575
0.8
Unit
Core supply voltage 1
Core supply voltage 2
V
V
V
V
V
VCC2
Vref
Reference voltage (irrespective of I/O standard used)
I/O supply voltage, read and write LVCMOS33
0.75
3.30
1.8
VCCIO
3.00
1.70
3.60
1.90
banks.
LVCMOS18
Table 10. Electrical Characteristics
Parameter Description
Icc Active current
Conditions
Min
–
Typ
–
Max
300
600
Unit
mA
mA
VCC1=VCC1MAX
,
VCC2=VCC2MAX
All I/O switching,
133 MHz)
,
–
–
VCCIO = VCCIOMAX
(All outputs disabled)
–
–
100
mA
II
Input pin leakage current VIN = VCCIOmax to 0 V
I/O pin leakage current VO = VCCIOmax to 0 V
–15
–15
–
–
–
–
15
15
16
µA
µA
pF
IOZ
CP
Capacitance for TMS
and TCK
–
CPIO
Capacitance for all other –
pins except TMS and
TCK
–
–
8
pF
Document Number: 001-53687 Rev. *H
Page 13 of 29
CYF0018V, CYF0036V
CYF0072V
Table 11. I/O Characteristics
(Over the operating range)
Nominal
I/O standard I/O supply
voltage
Input Voltage (V)
VIL(max) VIH(min)
Output voltage (V)
Output Current (mA)
VOL(max)
VOH(min)
IOL(max)
IOH(max)
LVCMOS33
LVCMOS18
3.3 V
1.8 V
0.80
2.20
0.45
0.45
2.40
24
16
24
16
30% VCCIO
65% VCCIO
VCCIO – 0.45
Table 12. Latency Table
Latency Parameter Number of cycles
Detail
Min=0
LFF_ASSERT
LEF_ASSERT
LPRS_TO_ACTIVE
LMAILBOX
Max=4
Last data write to FF going low
Last data read to EF going low
PRS to normal operation
0
1
2
4
Latency from write port to read port when MB = 1 (wrt WCLK)
Latency when REN is asserted low to first data output from FIFO
LREN_TO_DATA
Latency when REN is asserted along with LD to first data read from configuration
registers
LREN_TO_CONFIG
LWEN_TO_PAE_HI
LWEN_TO_PAF_LO
LREN_TO_PAE_LO
LREN_TO_PAF_HI
LFF_DEASSERT
LRT_TO_REN
4
5
5
7
7
8
9
Write to PAE going low
Write to PAF going low
Read to PAE going high
Read to PAF going high
Read to FF going high
RT fifth cycle to REN going low for read
Min=19
Max=21
LRT_TO_DATA
LIN
RT fifth cycle to valid data on Q[35:0]
Min=25
Max=26
Initial latency for data read after FIFO goes empty during
simultaneous read/write
Min=23
Max=24
LEF_DEASSERT
Write to EF going high
Document Number: 001-53687 Rev. *H
Page 14 of 29
CYF0018V, CYF0036V
CYF0072V
Switching Characteristics
-133
Unit
Parameter
Description
Min
–
Max
2
tPU
Power-up time after all supplies reach minimum value
ms
MHz
MHz
ns
tS
Clock cycle frequency
Clock cycle frequency
Data access time
Clock cycle time
Clock high time
3.3 V LVCMOS
1.8 V LVCMOS
24
24
133
133
10
41.67
–
tS
tA
tCLK
tCLKH
tCLKL
tDS
7.5
ns
3.375
ns
Clock low time
3.375
–
ns
Data setup time
Data hold time
3
3
–
ns
tDH
–
ns
tENS
tENH
tENS_SI
tENH_SI
tRATE_SPI
tRS
Enable setup time
Enable hold time
3
–
ns
3
–
ns
Setup time for SPI_SI and SPI_SEN pins
Hold time for SPI_SI and SPI_SEN pins
Frequency of SCLK
5
–
ns
5
–
ns
–
25
–
MHz
ns
Reset pulse width
100
25
25
–
tPZS
tPZH
tRSF
tPRT
Port size select to MRS seup time
MRS to port size select hold time
Reset to flag output time
–
ns
–
ns
50
–
ns
Retransmit pulse width
5
RCLK
cycles
tOLZ
Output enable to output in Low Z
Output enable to output valid
Output enable to output in High Z
Write clock to FF
4
–
15
15
15
8.5
8.5
17
17
17
1024
–
ns
ns
tOE
tOHZ
–
ns
tWFF
–
ns
tREF
Read clock to EF
–
ns
tPAF
Clock to PAF flag
–
ns
tPAE
Clock to PAE flag
–
ns
tHF
Clock to HF flag
–
ns
tPLL
Time required to synchronize PLL
JTAG TCK cycle time
–
cycles
ns
tRATE_JTAG
tS_JTAG
tH_JTAG
tCO_JTAG
100
5
Setup time for JTAG TMS,TDI
Hold time for JTAG TMS,TDI
JTAG TCK low to TDO valid
–
ns
5
–
ns
–
10
ns
Document Number: 001-53687 Rev. *H
Page 15 of 29
CYF0018V, CYF0036V
CYF0072V
Switching Waveforms
Figure 5. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
D[35:0]
t
t
DH
DS
t
ENH
t
ENS
WEN, IE
NO OPERATION
Figure 6. Read Cycle Timing
t
CLK
RCLK
t
t
ENH
ENS
REN
NO OPERATION
LREN_TO_DATA
t
A
VALID DATA
Q[35:0]
t
OLZ
t
OHZ
OE
DVal
Document Number: 001-53687 Rev. *H
Page 16 of 29
CYF0018V, CYF0036V
CYF0072V
Switching Waveforms (continued)
Figure 7. Reset Timing
t
RS
MRS
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
OE=1
OE=0
Q[35:0]
–
Figure 8. MRS to PORTSZ[2:0]
WCLK/RCLK
MRS
tPZS
tPZH
PORTSZ[2:0]
Document Number: 001-53687 Rev. *H
Page 17 of 29
CYF0018V, CYF0036V
CYF0072V
Switching Waveforms (continued)
Figure 9. Empty Flag Timing
RCLK
t
REF
EF
REN
OE
Q[35:0]
Q(Last)-3
Q(Last)
Invalid Data
Q(Last)-2
Q(Last)-1
DVal
Figure 10. Full Flag Timing
WCLK
t
DS
D[35:0]
D0 (written)
D3 (not written)
D4 (not written)
D1 (written)
D2 (written)
t
WFF
FF
WEN
Document Number: 001-53687 Rev. *H
Page 18 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 11. Initial Data Latency
n
1
2
WCLK
/RCLK
D[35:0]
D0
D3
Q0
D4
Q1
D1
D2
t
A
WEN/REN
OE
Q[35:0]
DVal
L
(initial latency)
IN
Figure 12. Flow-through Mailbox Operation
2
3
1
WCLK
D[35:0]
DO
D1
D2
D3
D4
REN / WEN
L MAILBOX
MB
Q[35:0]
QO
Q1
Q2
Q3
Q4
DVal
Document Number: 001-53687 Rev. *H
Page 19 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 13. Configuration Register Write
WCLK
tENS
WEN / IE
LD
tDH
tDS
D[35:0]
config-reg 0
config-reg 1
config-reg 2
config-reg 3
config-reg 4
config-reg 5
Figure 14. Configuration Register Read
WCLK
/RCLK
REN
LREN_TO_CONFIG
t
A
LD
Q[35:0]
Reg - 1
Figure 15. Empty Flag Deassertion
WCLK
/ IE
WEN
D0
D1
D[35:0]
EF
L EF_DEASSERT
tREF
RCLK
REN
Document Number: 001-53687 Rev. *H
Page 20 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 16. Empty Flag Assertion
1
2
3
4
5
RCLK
REN
tA
Q
LAST
Q[35:0]
DVal
EF
L REN_TO_DATA
tREF
Figure 17. Full Flag Assertion
WCLK
/ IE
WEN
NOT
WRITTEN
D
0
D
1
D
x
D
D
LAST
NOT
WRITTEN
D[35:0]
FF
LAST-1
Figure 18. Full Flag Deassertion
WCLK
WEN / IE
D[35:0] LDAST-5
FF
D
D
D
D
D
LAST
LAST-4
LAST-3
LAST-2
LAST-1
L FF_DEASSERT
1
2
3
7
8
RCLK
REN
Document Number: 001-53687 Rev. *H
Page 21 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 19. PAE Assertion and Deassertion
WCLK
WEN/ IE
RCLK
REN
WEN for
OFFSET +1
LOCATION
L WEN_TO_PAE_HI
1 READ
L REN_TO_PAE_LO
PAE
tPAE
tPAE
Figure 20. PAF Assertion and Deassertion
WCLK
WEN/ IE
FULL - (OFFSET +1)
WRITE
RCLK
REN
PAF
L REN_TO_PAF_HI
1 READ
L WEN_TO_PAF_LO
tPAF
tPAF
Figure 21. HF Assertion and Deassertion
WCLK
/ IE
WEN
FULL / 2
WRITE
RCLK
REN
HF
L WEN_TO_PAF_LO
L REN_TO_PAF_HI
1 READ
tHF
tHF
Document Number: 001-53687 Rev. *H
Page 22 of 29
CYF0018V, CYF0036V
CYF0072V
Figure 22. Mark
RCLK
REN
tENS
tENH
MARK
Q[35:0]
DVal
Q (N+3)
Q (N+5)
Q (N-2)
Q (N-1)
Q (N)
Q (N+1)
Q (N+2)
Q (N+4)
Q (N+6)
DATA MARKED
Figure 23. Retransmit
RCLK
REN
tPRT
LRT_TO_REN
LRT_TO_DATA
RT_FL
Q[35:0]
Q (N+1)
Q (N)
RETRANSMIT FROM
DATA MARKED
DVal
Document Number: 001-53687 Rev. *H
Page 23 of 29
CYF0018V, CYF0036V
CYF0072V
Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
133 CYF0018V33L-133BGXI
CYF0036V33L-133BGXI
CYF0072V33L-133BGXI
CYF0018V18L-133BGXI
CYF0036V18L-133BGXI
CYF0072V18L-133BGXI
51-85167 209-ball fine-pitch ball grid array (FPBGA) (14 × 22 × 1.76 mm) Industrial
Ordering Code Definition
CY F X XXX VXX X - XXX BGXI
Speed:
133 MHz
I/O Standard:
L = LVCMOS
I/O Voltage:
18 = 1.8 V
33 = 3.3 V
Density:
018 = 18M
036 = 36M
072 = 72M
0 - single-queue
FIFO
Cypress
Document Number: 001-53687 Rev. *H
Page 24 of 29
CYF0018V, CYF0036V
CYF0072V
Package Diagram
Figure 24. 209-Ball FBGA (14 × 22 × 1.76 mm), 51-85167
51-85167 *A
Document Number: 001-53687 Rev. *H
Page 25 of 29
CYF0018V, CYF0036V
CYF0072V
Acronyms
Document Conventions
Units of Measure
Acronym
FF
Description
Full flag
Symbol
°C
Unit of Measure
degrees Celsius
FIFO
HF
First in first out
Half full
A
microampere
milliampere
millisecond
megahertz
nanosecond
ohm
mA
ms
MHz
ns
HSTL
IE
High-speed transceiver logic
Input enable
I/O
Input/output
FPBGA
JTAG
LVCMOS
fine-pitch ball grid array
Joint test action group
pF
pico Farad
volt
Low voltage complementary metal oxide
semiconductor
V
W
watt
MB
Mailbox
MRS
OE
Master reset
Output enable
Programmable almost-full
Programmable almost-empty
Partial reset
PAF
PAE
PRS
RCLK
REN
RCLK
SCLK
TDI
Read clock
Read enable
Read clock
Serial clock
Test data in
TDO
TCK
TMS
WCLK
WEN
Test data out
Test clock
Test mode select
Write clock
Write enable
Document Number: 001-53687 Rev. *H
Page 26 of 29
CYF0018V, CYF0036V
CYF0072V
Document History Page
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 Mbit Programmable FIFOs
Document Number: 001-53687
Orig. of Submission
Rev.
**
ECN No.
Change
Date
Description of Change
2711566 VKN/PYRS
05/27/09 New data sheet
*A
2725088
2839536
NXR
NXR
06/26/2009 Included pinout, AC and DC specs, timing diagrams and package diagram
*B
01/28/2010 Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU,
Balls C5, C7, G6, H6, J6, L6, M6, N6, T5, T7 FROM NC to VCC1,
Balls K9, K10, K11 From NC to VCCIOR
Ball W9 from NC to Vref in pin configuration table
Swapped Voltage range of VSS1 and VSS
2
Updated ICC spec
Removed TSKEW parameter
Added Ordering Information table
Added Part Numbering Nomenclature.
Changed title to CYF0018V/CYF0036V/CYF0072V/CYFX144VXXX, 18/36/72
Mbit Programmable FIFOs.
*C
*D
2884377
2963225
HKV
02/25/2010 Post to external web.
AJU/HPV 06/28/2010 Changed frequency of operation from 250 MHz to 150 MHz
Removed Depth Expansion feature and changed associated pin functionality
Removed Independent Port size selectability feature
Added Data Valid (DVal) signal feature
Updated Logic Block Diagram to reflect above changes.
Pinout changes:
Balls V5, V8, A7, B7, D7, and C6 renamed DNU
Ball U1 changed from RXO to DVal
Ball V2 changed from WXO/HF to HF
Ball A5, A6, B6 changed from WPORTSZ to PORTSZ
Ball A9 changed from RT/FL to RT
Renamed pwr as POWER, gnd as GND
Added Table 3
Table 6 – LD changed to ‘1’ for serial writes
Updated Electrical Characteristics and I/O Characteristics
Switching Characteristics Table:
Renamed tPC as tPU
Min frequency changed from 110MH to 24MHz
Changed tCLKH and tCLKL to 3.15 ns
Changed All setup and hold times to 3 ns
Changed tRSF to 50 ns
Removed tRSR
Changed All clock-to-flag timing to min=8 ns and max=14 ns
T
PLL changed to 6 ms
Changed all OE-related parameters to 15 ns
Scaled ICC for reduced frequency
Updated all waveforms
Added the following tables:
Word Size Selection, JTAG Operation, and Latency Table
Added Acronyms.
*E
*F
2994379
3101023
AJU
07/26/2010 Updated Ordering Information
SIVS
12/03/2010 Added supply-wise current consumption data in Electrical Characteristics.
Changed initial latency LIN from 34 to 26 and added initial latency LIN for
110 MHz part in Latency Table.
Added 110 MHz part information in JTAG Operation
Added details for the 110 MHz part in Switching Characteristics.
Added details for the 110 MHz part in Ordering Information.
*G
3129722
HKV
01/06/2011 Post to external web.
Document Number: 001-53687 Rev. *H
Page 27 of 29
CYF0018V, CYF0036V
CYF0072V
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 Mbit Programmable FIFOs
Document Number: 001-53687
Orig. of Submission
Rev.
ECN No.
Change
Date
Description of Change
*H
3197271
SIVS
03/31/2011 Removed 144 Mbit parts from the data sheet
Removed multi-queue information from data sheet
Removed 2.5 V and 1.5 V options
Removed HSTL I/II I/O standard
Added clock ratio requirement between RCLK and WCLK
Removed redundant Xs from part number to improve readability
Removed tie to GND option on DNU pins in pin description
Added information on Flag operations to add clarity
Added explanation for flow-through mailbox operation
Added details on active pins in various port sizes in Table 1.
Added Configuration register write to normal operation latency details.
Changed configuration register definitions and default values
Changed number of unusable locations to four to eight
Added JTAG related operation
Added latch-up current parameter in maximum operating conditions.
Removed 2.5 V and 1.5 V options from DC operating condition table 6.
Removed 110 MHz part details and added Cpio parameter in table 7.
Removed 2.5 V and 1.5 V options from Table 8.
Added latency parameters in Table 9.
changed Vol(max) value of LVCMOS33 in table11
Removed 110 MHz part detail from switching characteristics
Added timing waveform to improve clarity.
Modified ordering information and definition.
Document Number: 001-53687 Rev. *H
Page 28 of 29
CYF0018V, CYF0036V
CYF0072V
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53687 Rev. *H
Revised March 31, 2011
Page 29 of 29
All product and company names mentioned in this document are the trademarks of their respective holders.
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