CYRF69213-40LTXC_技术文档

CYRF69213

Programmable Radio on Chip Low Power

❐ Automatic Gain Control (AGC)

PRoC™ LP Features

■ Component Reduction

❐ Integrated 3.3 V regulator

❐ Integrated pull up on D–

■ USB 2.0-USB-IF certified (TID # 40000552)

■ Single Device, Two Functions

❐ 8-bit, FlashbasedUSBperipheralMCUfunctionand2.4 GHz

radio transceiver function in a single device

❐ GPIOs that require no external components

❐ Operates off a single crystal

■ Flash Based Microcontroller Function

■ Flexible I/O

❐ M8C based 8-bit CPU, optimized for Human Interface

❐ 2 mA source current on all GPIO pins. Configurable 8 mA or

Devices (HID) applications

50 mA/pin current sink on designated pins

❐ 256 bytes of SRAM

❐ Each GPIO pin supports high impedance inputs, configurable

pull up, open-drain output, CMOS/TTL inputs and CMOS

output

❐ 8 Kbytes of Flash memory with EEPROM emulation

❐ In-System reprogrammable through D+/D– pins

❐ 16-bit free running timer

❐ Maskable interrupts on all I/O pins

❐ Low power wake up timer

❐ 12-bit Programmable Interval Timer with interrupts

❐ Watchdog timer

■ USB Specification Compliance

❐ Conforms to USB Specification Version 2.0

❐ Conforms to USB HID Specification Version 1.1

❐ Supports one Low Speed USB device address

❐ Supports one control endpoint and two data end points

❐ Integrated USB Transceiver

■ Industry-Leading 2.4 GHz Radio Transceiver Function

❐ Operates in the unlicensed worldwide Industrial, Scientific

and Medical (ISM) band (2.4 GHz to 2.483 GHz)

❐ DSSS data rates of up to 250 Kbps

❐ GFSK data rate of 1 Mbps

❐ –97 dBm receive sensitivity

❐ Programmable output power of up to +4 dBm

❐ Auto Transaction Sequencer (ATS)

❐ Framing CRC and Auto ACK

■ Operating Voltage from 4.0 V to 5.5 V DC

■ Operating Temperature from 0 to 70C

■ Pb-free 40-pin QFN Package

■ Advanced Development Tools Based on Cypress’s PSoC^®

Tools

❐ Received Signal Strength Indication (RSSI)

Block Diagram

1ohm

Vbus

4.7uF

1-2 uF

470nF

RFbias

RFp

RFn

Microcontroller

Function

Radio

Function

P0_1,3,4,7

P1_6:7

P2_0:1

D+/D-

4

2

IRQ/GPIO

MISO/GPIO

XOUT/GPIO

PACTL/GPIO

P1.5/MOSI

P1.4/SCK

P1.3/nSS

. . . . .

. . . . . . .

470nF

12MHz

Cypress Semiconductor Corporation

Document Number: 001-07552 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 18, 2012

CYRF69213

Contents

Applications ......................................................................3

Functional Description .....................................................3

Functional Overview ........................................................3

2.4 GHz Radio Function ..............................................3

Data Transmission Modes ...........................................3

USB Microcontroller Function ......................................3

Pinouts ..............................................................................4

Pin Configurations ...........................................................5

PRoC LP Functional Overview ........................................6

DDR Mode ...................................................................6

SDR Mode ...................................................................7

Functional Block Overview ..............................................8

2.4 GHz Radio .............................................................8

Frequency Synthesizer ................................................8

Baseband and Framer .................................................8

Packet Buffers .............................................................9

Auto Transaction Sequencer (ATS) ............................9

Interrupts .....................................................................9

Clocks ..........................................................................9

GPIO Interface ..........................................................10

Power On Reset/Low Voltage Detect ........................10

Power Management ..................................................10

Timers .......................................................................10

USB Interface ............................................................10

Low Noise Amplifier (LNA) and Received Signal Strength

Indication (RSSI) ..............................................................10

SPI Interface ....................................................................11

3-Wire SPI Interface ..................................................11

4-Wire SPI Interface ..................................................11

SPI Communication and Transactions ......................11

SPI I/O Voltage References ......................................12

SPI Connects to External Devices ............................12

CPU Architecture ............................................................12

CPU Registers .................................................................13

Flags Register ...........................................................13

Accumulator Register ................................................13

Index Register ...........................................................14

Stack Pointer Register ...............................................14

CPU Program Counter High Register .......................14

CPU Program Counter Low Register ........................14

Addressing Modes .........................................................15

Source Immediate .....................................................15

Source Direct .............................................................15

Source Indexed .........................................................15

Destination Direct ......................................................15

Destination Indexed ...................................................16

Destination Direct Source Immediate ........................16

Destination Indexed Source Immediate ....................16

Source Indirect Post Increment .................................17

Destination Indirect Post Increment ..........................17

Instruction Set Summary ...............................................18

Memory Organization .....................................................19

Flash Program Memory Organization .......................19

Data Memory Organization .......................................20

Flash ..........................................................................20

SROM ........................................................................20

SROM Function Descriptions ....................................21

SROM Table Read Description ......................................24

Clocking ..........................................................................25

Clock Architecture Description ..................................26

CPU Clock During Sleep Mode .................................32

Reset ................................................................................32

Power on Reset ...............................................................34

Watchdog Timer Reset ..............................................34

Sleep Mode ......................................................................34

Sleep Sequence ........................................................34

Wakeup Sequence ....................................................35

Low Voltage Detect Control ...........................................37

POR Compare State .................................................37

ECO Trim Register ....................................................38

General-Purpose I/O Ports .............................................38

Port Data Registers ...................................................38

GPIO Port Configuration ...........................................39

GPIO Configurations for Low Power Mode: ..............44

Serial Peripheral Interface (SPI) ....................................45

SPI Data Register ......................................................46

SPI Configure Register .............................................46

Timer Registers ..............................................................48

Registers ...................................................................48

Interrupt Controller .........................................................51

Architectural Description ...........................................51

Interrupt Processing ..................................................52

Interrupt Latency .......................................................52

Interrupt Registers .....................................................52

USB Transceiver .............................................................56

USB Transceiver Configuration .................................56

VREG Control ............................................................56

USB Serial Interface Engine (SIE) .................................57

USB Device .....................................................................57

Endpoint 0 Mode .......................................................59

Endpoint Data Buffers ...............................................60

USB Mode Tables ...........................................................62

Mode Column ............................................................62

Encoding Column ......................................................62

SETUP, IN, and OUT Columns .................................62

Details of Mode for Differing Traffic Conditions ..........63

Register Summary ..........................................................66

Radio Function Register Descriptions .........................69

Absolute Maximum Ratings ..........................................70

DC Characteristics .........................................................70

RF Characteristics ..........................................................73

AC Test Loads and Waveforms for Digital Pins ..........74

AC Electrical Characteristics ........................................75

Ordering Information ......................................................81

Package Diagram ............................................................82

Document History Page .................................................84

Sales, Solutions, and Legal Information ......................85

Worldwide Sales and Design Support .......................85

Products ....................................................................85

PSoC Solutions .........................................................85

Document Number: 001-07552 Rev. *G

Page 2 of 85

CYRF69213

Data Transmission Modes

Applications

The radio supports four different data transmission modes:

The CYRF69213 PRoC LP Low Speed is targeted for the

following applications:

■ In GFSK mode, data is transmitted at 1 Mbps without any DSSS

■ USB Bridge for Human Interface Devices (HID)

❐ Wireless mice

■ In 8DR mode, 1 byte is encoded in each PN code symbol trans-

mitted

❐ Wireless keyboards

❐ Remote controls

❐ Gaming applications

■ In DDR mode, 2 bits are encoded in each PN code symbol

transmitted

■ In SDR mode, a single bit is encoded in each PN code symbol

■ USB Bridge for General Purpose Applications

❐ Consumer electronics

❐ Industrial applications

❐ White goods

transmitted

Both 64-chip and 32-chip data PN codes are supported. The four

data transmission modes apply to the data after the Start of

Packet (SOP). In particular, the packet length, data and CRC are

all sent in the same mode.

❐ Home automation

❐ Personal health

USB Microcontroller Function

Functional Description

The microcontroller function is based on the powerful

CYRF69213 microcontroller. It is an 8-bit Flash programmable

microcontroller with integrated low speed USB interface.

PRoC LP devices are integrated radio and microcontroller

functions in the same package to provide a dual role single-chip

solution.

The microcontroller has up to 14 GPIO pins to support USB,

PS/2 and other applications. Each GPIO port supports high

impedance inputs, configurable pull up, open drain output,

CMOS/TTL inputs and CMOS output. Up to two pins support

programmable drive strength of up to 50 mA. Additionally each

I/O pin can be used to generate a GPIO interrupt to the

microcontroller. Each GPIO port has its own GPIO interrupt

vector with the exception of GPIO Port 0.

Communication between the microcontroller and the radio is via

the SPI interface between both functions.

Functional Overview

The CYRF69213 is a complete Radio System-on-Chip device,

providing a complete RF system solution with a single device and

a few discrete components. The CYRF69213 is designed to

implement low cost wireless systems operating in the worldwide

2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band

(2.400 GHz–2.4835 GHz).

The microcontroller features an internal oscillator. With the

presence of USB traffic, the internal oscillator can be set to

precisely tune to USB timing requirements (24 MHz ± 1.5%).

The PRoC LP has up to 8 Kbytes of Flash for user’s firmware

code and up to 256 bytes of RAM for stack space and user

variables.

2.4 GHz Radio Function

The radio meets the following world wide regulatory

requirements:

The PRoC LP includes a Watchdog timer, a vectored interrupt

controller, a 12-bit programmable interval timer with configurable

1 ms interrupt and a 16-bit free running timer with capture

registers.

■ Europe

❐ ETSI EN 301 489-1 V1.4.1

❐ ETSI EN 300 328-1 V1.3.1

■ North America

❐ FCC CFR 47 Part 15

■ Japan

❐ ARIB STD-T66

Document Number: 001-07552 Rev. *G

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CYRF69213

Pinouts

Figure 1. 40-pin QFN pinout

Corner

tabs

P0.4

1

2

3

4

5

6

7

8

9

30 XOUT/ GPIO

29 MISO/ GPIO

28 P1. 5 / MOSI

27 IRQ / GPIO

26 P1. 4 / SCK

25 P1. 3 / SS

XTAL

V_CC

CYRF69213

WirelessUSB LP

P0.3

P0.1

V_BAT1

V_CC

24 P1. 2 /V_{REG_ MICRO}

23 V_{DD_Micro}

P2.1

V_BAT2

22 P1.1/D-

*E- PAD Bottom Side

RF_BIAS10

21 P1.0/D+

Document Number: 001-07552 Rev. *G

Page 4 of 85

CYRF69213

Pin Configurations

Name

Function

1

P0.4

Individually configured GPIO

2

Xtal_in

12 MHz Crystal. External clock in

Connected to pin 24 via 0.047 F capacitor

Individually configured GPIO

3, 7, 16

V

CC

4

P0.3

P0.1

5

Individually configured GPIO

6, 9, 39

V

Connected to pin 24 via 0.047 Fshunt capacitor

GPIO. Port 2 Bit 1

bat

8

P2.1

10

RF Bias

RF pin voltage reference

11

RF

Differential RF input to/from antenna

Ground

p

12

GND

RF

13

Differential RF to/from antenna

n

14, 17, 18, 20, 36

NC

P2.0

15

19

21

22

23

24

25

26

27

28

29

30

31

32

33

34

GPIO. Port 2 Bit 0

RESV

Reserved. Must connect to GND

P1.0 / D+ GPIO 1.0 / Low speed USB I/O

P1.1 / D– GPIO 1.1 / Low speed USB I/O

V

4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU

DD_micro

P1.2 / V

Must be configured as 3.3 V output. It must have a 1–2 F output capacitor

REG

P1.3 / nSS Slave select SPI Pin

P1.4 / SCK Serial Clock Pin from MCU function to radio function

IRQ

Interrupt output, configure high/low or GPIO

P1.5 / MOSI Master Out Slave In

MISO

XOUT

PACTL

P1.6

Master In Slave Out, from radio function. Can be configured as GPIO

Bufferd CLK, PACTL_n or GPIO

Control for external PA or GPIO

GPIO. Port 1 Bit 6

V

I/O interface voltage. Connected to pin 24 via 0.047 F

IO

Reset

Radio Reset. Connected to V via 0.47 F capacitor or to microcontroller GPIO pin. Must have

a RESET = HIGH event the very first time power is applied to the radio otherwise the state of the

radio function control registers is unknown

DD

35

36

37

38

40

41

42

P1.7

GPIO. Port 1 Bit 7

V

Regulated logic bypass. Connected via 0.47 F to GND

Connected to GND

DD_1.8

L/D

P0.7

GPIO. Port 0 Bit 7

V

Connected to pin 24

reg

E-pad

Must be connected to GND

Corner Tabs Do not connect corner tabs

Document Number: 001-07552 Rev. *G

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CYRF69213

supported bit rates, except SDR, enabling the implementation of

mixed-rate systems in which different devices use different data

rates. This also enables the implementation of dynamic data rate

systems, which use high data rates at shorter distances and/or

in a low moderate interference environment, and change to lower

data rates at longer distances and/or in high interference

environments.

PRoC LP Functional Overview

The SoC is designed to implement wireless device links

operating in the worldwide 2.4 GHz ISM frequency band. It is

intended for systems compliant with worldwide regulations

covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1

V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry

Canada) and TELEC ARIB_T66_March, 2003 (Japan).

The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver,

packet data buffering, packet framer, DSSS baseband controller,

Received Signal Strength Indication (RSSI), and SPI interface

for data transfer and device configuration.

The MCU function is an 8-bit Flash programmable

microcontroller with integrated low speed USB interface. The

instruction set has been optimized specifically for USB

operations, although it can be used for a variety of other

embedded applications.

The radio supports 98 discrete 1 MHz channels (regulations may

limit the use of some of these channels in certain jurisdictions).

The MCU function has up to eight Kbytes of Flash for user’s code

and up to 256 bytes of RAM for stack space and user variables.

In

DSSS modes the

baseband

performs

DSSS

spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK)

the baseband performs Start of Frame (SOF), End of Frame

(EOF) detection and CRC16 generation and checking. The

baseband may also be configured to automatically transmit

Acknowledge (ACK) handshake packets whenever a valid

packet is received.

In addition, the MCU function includes a Watchdog timer, a

vectored interrupt controller, a 16-bit Free-Running Timer, and

12-bit Programmable Interrupt Timer.

The MCU function supports in-system programming by using the

D+ and D– pins as the serial programming mode interface. The

programming protocol is not USB.

When in receive mode, with packet framing enabled, the device

is always ready to receive data transmitted at any of the

DDR Mode

Table 1. DDR Mode

Register

TX_CFG_ADR

RX_CFG_ADR

Value

0X16

Description

32 chip PN Code, DDR, PA = 6

0X4B

AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device

uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled

and the RX buffer is configured to receive eight bytes maximum.

XACT_CFG_ADR

0X05

AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to

Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs.

FRAMING_CFG_ADR 0X00

TX_OVERRIDE_ADR 0X04

RX_OVERRIDE_ADR 0X14

All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.

Disable Transmit CRC-16.

The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the

receiver accepts bad packets that do not match the seed in CRC_seed registers. Basically

this helps in communication with the first generation radio that does not have CRC capabilities.

ANALOG_CTRL_ADR 0X01

DATA32_THOLD_ADR 0X03

Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow

channels in the first generation radio.

Sets the number of allowed corrupted bits to 3.

EOP_CTRL_ADR

PREAMBLE_ADR

0x01

Sets the number of consecutive symbols for non correlation to detect end of packet.

0xAAAA05 AAAA are the two preamble bytes.Other Bytes can also be written into the preamble register

file. The number of preamble bytes to be sent should be >4.

Document Number: 001-07552 Rev. *G

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CYRF69213

SDR Mode

Table 2. SDR Mode

Register

TX_CFG_ADR

RX_CFG_ADR

Value

0X3E

Description

64 chip PN code, SDR mode, PA = 6.

0X4B

AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device

uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled

and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new

packets to be loaded into the receive buffer. This also enables the VALID bit which is used by

the first generation radio’s error correction firmware.

XACT_CFG_ADR

0X05

AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to

Idle mode after Receive or Transmit. ACK timeout is set to 128 µs.

FRAMING_CFG_ADR 0X00

TX_OVERRIDE_ADR 0X04

RX_OVERRIDE_ADR 0X14

All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.

Disable Transmit CRC-16.

The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the

receiver accepts bad packets that do not match the seed in the CRC_seed registers. Basically

this helps in communication with the first generation radio that does not have CRC capabilities.

ANALOG_CTRL_ADR 0X01

DATA64_THOLD_ADR 0X07

Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow

channels in the first generation radio, for manual ACK consistency

Sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value.

Sets the number of consecutive symbols for non correlation to detect end of packet.

EOP_CTRL_ADR

PREAMBLE_ADR

0xA1

0xAAAA09 AAAA are the two preamble bytes. Any other byte can also be written into the preamble

register file. The number of preamble bytes to be sent should be >8.

Document Number: 001-07552 Rev. *G

Page 7 of 85

CYRF69213

sent in the same mode. In general, lower data rates reduces

packet error rate in any given environment.

Functional Block Overview

All the blocks that make up the PRoC LP are presented here.

2.4 GHz Radio

By combining the DATA_CODE_ADR code lengths and data

transmission modes described above, the CYRF69213 IC

supports the following data rates:

The radio transceiver is a dual conversion low IF architecture

optimized for power and range/robustness. The radio employs

channel-matched filters to achieve high performance in the

presence of interference. An integrated Power Amplifier (PA)

provides up to +4 dBm transmit power, with an output power

control range of 34 dB in 7 steps. The supply current of the

device is reduced as the RF output power is reduced.

■ 1000 kbps (GFSK)

■ 250 kbps (32-chip 8DR)

■ 125 kbps (64-chip 8DR)

■ 62.5 kbps (32-chip DDR)

■ 31.25 kbps (64-chip DDR)

■ 15.625 kbps (64-chip SDR)

Table 3. Internal PA Output Power Step Table

Lower data rates typically provide longer range and/or a more

robust link.

PA Setting

Typical Output Power (dBm)

7

6

5

4

3

2

1

0

+4

0

Link Layer Modes

The CYRF69213 IC device supports the following data packet

framing features:

–5

–10

–15

–20

–25

–30

SOP – Packets begin with a 2-symbol Start of Packet (SOP)

marker. This is required in GFSK and 8DR modes, but is optional

in DDR mode and is not supported in SDR mode; if framing is

disabled then an SOP event is inferred whenever two successive

correlations are detected. The SOP_CODE_ADR code used for

the SOP is different from that used for the ‘body’ of the packet,

and if desired may be a different length. SOP must be configured

to be the same length on both sides of the link.

Frequency Synthesizer

EOP – There are two options for detecting the end of a packet.

If SOP is enabled, then a packet length field may be enabled.

GFSK and 8DR must enable the length field. This is the first

8 bits after the SOP symbol, and is transmitted at the payload

data rate. If the length field is enabled, an End of Packet (EOP)

condition is inferred after reception of the number of bytes

defined in the length field, plus two bytes for the CRC16 (if

enabled—see below). The alternative to using the length field is

to infer an EOP condition from a configurable number of

successive non correlations; this option is not available in GFSK

mode and is only recommended when using SDR mode.

Before transmission or reception may commence, it is necessary

for the frequency synthesizer to settle. The settling time varies

depending on channel; 25 fast channels are provided with a

maximum settling time of 100 s.

The ‘fast channels’ (<100 s settling time) are every third

frequency, starting at 2400 MHz up to and including 2472 MHz

(for example, 0,3,6,9…....69 & 72).

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding

and decoding, SOP generation and reception and CRC16

generation and checking, and EOP detection and length field.

CRC16 – The device may be configured to append a 16-bit

CRC16 to each packet. The CRC16 uses the USB CRC

polynomial with the added programmability of the seed. If

enabled, the receiver verifies the calculated CRC16 for the

payload data against the received value in the CRC16 field. The

starting value for the CRC16 calculation is configurable, and the

CRC16 transmitted may be calculated using either the loaded

seed value or a zero seed; the received data CRC16 is checked

against both the configured and zero CRC16 seeds.

Data Rates and Data Transmission Modes

The SoC supports four different data transmission modes:

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

■ In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR

derived code symbol transmitted.

CRC16 detects the following errors:

■ Any one bit in error

■ In DDR mode, 2-bits are encoded in each DATA_CODE_ADR

derived code symbol transmitted. (As in the CYWUSB6934

DDR mode).

■ Any two bits in error (irrespective of how far apart, which

column, and so on)

■ In SDR mode, 1 bit is encoded in each DATA_CODE_ADR

derived code symbol transmitted. (As in the CYWUSB6934

standard modes.)

■ Any odd number of bits in error (irrespective of the location)

■ An error burst as wide as the checksum itself

Figure 2 on page 9 shows an example packet with SOP, CRC16

and lengths fields enabled.

Both 64-chip and 32-chip DATA_CODE_ADR codes are

supported. The four data transmission modes apply to the data

after the SOP. In particular the length, data, and CRC16 are all

Document Number: 001-07552 Rev. *G

Page 8 of 85

CYRF69213

Figure 2. Example Default Packet Format

Preamble

n x 16us

2nd Framing

Symbol*

P

SOP 1

SOP 2

Length

CRC 16

Payload Data

Packet

length

1 Byte

Period

1st Framing

Symbol*

*Note:32 or 64us

in transaction mode, firmware simply needs to retrieve the fully

received packet in response to an interrupt request indicating

reception of a packet.

Packet Buffers

Packet data and configuration registers are accessed through

the SPI interface. All configuration registers are directly

addressed through the address field in the SPI packet.

Configuration registers are provided to allow configuration of

DSSS PN codes, data rate, operating mode, interrupt masks,

interrupt status, and others.

Interrupts

The radio function provides an interrupt (IRQ) output, which is

configurable to indicate the occurrence of various different

events. The IRQ pin may be programmed to be either active high

or active low, and be either a CMOS or open drain output. The

IRQ pin can be multiplexed on the SPI if routed to an external pin.

Packet Buffers

All data transmission and reception uses the 16-byte packet

buffers—one for transmission and one for reception.

The radio function features three sets of interrupts: transmit,

receive, and system interrupts. These interrupts all share a

single pin (IRQ), but can be independently enabled/disabled. In

transmit mode, all receive interrupts are automatically disabled,

and in receive mode all transmit interrupts are automatically

disabled. However, the contents of the enable registers are

preserved when switching between transmit and receive modes.

The transmit buffer allows a complete packet of up to 16 bytes of

payload data to be loaded in one burst SPI transaction.This is

then transmitted with no further MCU intervention. Similarly, the

receive buffer allows an entire packet of payload data up to 16

bytes to be received with no firmware intervention required until

packet reception is complete.

If more than one radio interrupt is enabled at any time, it is

necessary to read the relevant status register to determine which

event caused the IRQ pin to assert. Even when a given interrupt

source is disabled, the status of the condition that would

otherwise cause an interrupt can be determined by reading the

appropriate status register. It is therefore possible to use the

devices without making use of the IRQ pin by polling the status

register(s) to wait for an event, rather than using the IRQ pin.

The CYRF69213 IC supports packet length of up to 40 bytes;

interrupts are provided to allow an MCU to use the transmit and

receive buffers as FIFOs. When transmitting a packet longer

than 16 bytes, the MCU can load 16 bytes initially, and add

further bytes to the transmit buffer as transmission of data

creates space in the buffer. Similarly, when receiving packets

longer than 16 bytes, the MCU function must fetch received data

from the FIFO periodically during packet reception to prevent it

from overflowing.

The microcontroller function supports 23 maskable interrupts in

the vectored interrupt controller. Interrupt sources include a USB

bus reset, LVR/POR, a programmable interval timer, a 1.024-ms

output from the Free Running Timer, three USB endpoints, two

capture timers, five GPIO Ports, three GPIO pins, two SPI, a

16-bit free running timer wrap, an internal wakeup timer, and a

bus active interrupt. The wakeup timer causes periodic interrupts

when enabled. The USB endpoints interrupt after a USB

transaction complete is on the bus. The capture timers interrupt

whenever a new timer value is saved due to a selected GPIO

edge event. A total of eight GPIO interrupts support both TTL or

CMOS thresholds. For additional flexibility, on the edge sensitive

GPIO pins, the interrupt polarity is programmable to be either

rising or falling.

Auto Transaction Sequencer (ATS)

The CYRF69213 IC provides automated support for

transmission and reception of acknowledged data packets.

When transmitting a data packet, the device automatically starts

the crystal and synthesizer, enters transmit mode, transmits the

packet in the transmit buffer, and then automatically switches to

receive mode and waits for a handshake packet — and then

automatically reverts to sleep mode or idle mode when either an

ACK packet is received, or a timeout period expires.

Similarly, when receiving in transaction mode, the device waits

in receive mode for a valid packet to be received, then

automatically transitions to transmit mode, transmits an ACK

packet, and then switches back to receive mode to await the next

packet. The contents of the packet buffers are not affected by the

transmission or reception of ACK packets.

Clocks

The radio function has a 12 MHz crystal (30-ppm or better)

directly connected between XTAL and GND without the need for

external capacitors. A digital clock out function is provided, with

selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This

output may be used to clock an external microcontroller (MCU)

or ASIC. This output is enabled by default, but may be disabled.

In each case, the entire packet transaction takes place without

any need for MCU firmware action; to transmit data the MCU

simply needs to load the data packet to be transmitted, set the

length, and set the TX GO bit. Similarly, when receiving packets

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CYRF69213

Following are the requirements for the crystal to be directly

connected to XTAL pin and GND:

Figure 3. Power Management From Internal Regulator

1 ohm

■ Nominal Frequency: 12 MHz

■ Operating Mode: Fundamental Mode

■ Resonance Mode: Parallel Resonant

■ Frequency Stability: ±30 ppm

■ Series Resistance: <60 ohms

■ Load Capacitance: 10 pF

0.047µF

■ Drive Level:100 W

The MCU function features an internal oscillator. With the

presence of USB traffic, the internal oscillator can be set to

precisely tune to USB timing requirements (24 MHz ±1.5%). The

clock generator provides the 12 MHz and 24 MHz clocks that

remain internal to the microcontroller.

P1.2 / V_Reg

PRoC LP

V_DD

GPIO Interface

V_{DD_MICRO}

The MCU function features up to 20 general purpose I/O (GPIO)

pins to support USB, PS/2, and other applications. The I/O pins

are grouped into five ports (Port 0 to 4). The pins on Port 0 and

Port 1 may each be configured individually while the pins on

Ports 2, 3, and 4 may only be configured as a group. Each GPIO

port supports high impedance inputs, configurable pull up, open

drain output, CMOS/TTL inputs, and CMOS output with up to five

pins that support programmable drive strength of up to 50 mA

sink current. GPIO Port 1 features four pins that interface at a

voltage level of 3.3 volts. Additionally, each I/O pin can be used

to generate a GPIO interrupt to the microcontroller. Each GPIO

port has its own GPIO interrupt vector with the exception of GPIO

Port 0. GPIO Port 0 has three dedicated pins that have

independent interrupt vectors (P0.3–P0.4).

0.1µF

Timers

The free-running 16-bit timer provides two interrupt sources: the

programmable interval timer with 1 s resolution and the

1.024 ms outputs. The timer can be used to measure the

duration of an event under firmware control by reading the timer

at the start and at the end of an event, then calculating the

difference between the two values.

Power On Reset/Low Voltage Detect

USB Interface

The power on reset circuit detects logic when power is applied

to the device, resets the logic to a known state, and begins

executing instructions at Flash address 0x0000. When power

falls below a programmable trip voltage, it generates reset or

may be configured to generate interrupt. There is a low voltage

The MCU function includes an integrated USB serial interface

engine (SIE) that allows the chip to easily interface to a USB

host. The hardware supports one USB device address with three

endpoints.

detect circuit that detects when

V

drops below a

CC

Low Noise Amplifier (LNA) and Received Signal

Strength Indication (RSSI)

programmable trip voltage. It may be configurable to generate an

LVD interrupt to inform the processor about the low voltage

event. POR and LVD share the same interrupt. There is not a

separate interrupt for each. The Watchdog timer can be used to

ensure the firmware never gets stalled in an infinite loop.

The gain of the receiver may be controlled directly by clearing

the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit

of the RX_CFG_ADR register. When the LNA bit is cleared, the

receiver gain is reduced by approximately 20 dB, allowing

accurate reception of very strong received signals (for example

when operating a receiver very close to the transmitter). An

additional 20 dB of receiver attenuation can be added by setting

the Attenuation (ATT) bit; this allows data reception to be limited

to devices at very short ranges. Disabling AGC and enabling

LNA is recommended unless receiving from a device using

external PA.

Power Management

The device draws its power supply from the USB V

line. The

bus

V

supplies power to the MCU function, which has an internal

bus

3.3 V regulator. This 3.3 V is supplied to the radio function via

P1.2/V after proper filtering as shown in Figure 3.

REG

The RSSI register returns the relative signal strength of the

on-channel signal power.

When receiving, the device may be configured to automatically

measure and store the relative strength of the signal being

received as a 5-bit value. When enabled, an RSSI reading is

taken and may be read through the SPI interface. An RSSI

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CYRF69213

reading is taken automatically when the start of a packet is

detected. In addition, a new RSSI reading is taken every time the

previous reading is read from the RSSI register, allowing the

background RF energy level on any given channel to be easily

measured when RSSI is read when no signal is being received.

A new reading can occur as fast as once every 12 s.

4-Wire SPI Interface

The 4-wire SPI communications interface consists of MOSI,

MISO, SCK, and SS.

The device receives SCK from the MCU function on the SCK pin.

Data from the MCU function is shifted in on the MOSI pin. Data

to the MCU function is shifted out on the MISO pin. The active

low SS pin must be asserted for the two functions to

communicate. The IRQ function may be optionally multiplexed

with the MOSI pin; when this option is enabled the IRQ function

is not available while the SS pin is low. When using this

configuration, user firmware should ensure that the MOSI

function on MCU function is in a high impedance state whenever

SS is high.

Receive Spurious Response

The transmitter may exhibit spurs around 50MHz offset at levels

approximately 50dB to 60dB below the carrier power. Receivers

operating at the transmit spur frequency may receive the spur if

the spur level power is greater than the receive sensitivity level.

The workaround for this is to program an additional byte in the

packet header which contains the transmitter channel number.

After the packet is received, the channel number can be

checked. If the channel number does not match the receive

channel then the packet is rejected.

Figure 5. 4-WIRE SPI Mode

SPI Interface

Radio Function

MCU Function

The SPI interface between the MCU function and the radio

function is a 3-wire SPI Interface. The three pins are MOSI

(Master Out Slave In), SCK (Serial Clock), SS (Slave Select).

There is an alternate 4-wire MISO Interface that requires the

connection of two external pins. The SPI interface is controlled

by configuring the SPI Configure Register (SICR Address:

0x3D).

P1.5/MOSI

MOSI

SCK

P1.6/MISO

MISO

P1.4/SCK

P1.3/nSS

nSS

3-Wire SPI Interface

The radio function receives a clock from the MCU function on the

SCK pin. The MOSI pin is multiplexed with the MISO pin.

Bidirectional data transfer takes place between the MCU function

and the radio function through this multiplexed MOSI pin. When

using this mode the user firmware should ensure that the MOSI

pin on the MCU function is in a high impedance state, except

when the MCU is actively transmitting data. Firmware must also

control the direction of data flow and switch directions between

MCU function and radio function by setting the SWAP bit [Bit 7]

of the SPI Configure Register. The SS pin is asserted prior to

initiating a data transfer between the MCU function and the radio

function. The IRQ function may be optionally multiplexed with the

MOSI pin; when this option is enabled the IRQ function is not

available while the SS pin is low. When using this configuration,

user firmware should ensure that the MOSI function on MCU

function is in a high impedance state whenever SS is high.

This connection is external to the PRoC LP Chip

SPI Communication and Transactions

The SPI transactions can be single byte or multi-byte. The MCU

function initiates a data transfer through a Command/Address

byte. The following bytes are data bytes. The SPI transaction

format is shown in Figure 6.

The DIR bit specifies the direction of data transfer. 0 = Master

reads from slave. 1 = Master writes to slave.

The INC bit helps to read or write consecutive bytes from

contiguous memory locations in a single burst mode operation.

Figure 4. 3-Wire SPI Mode

If Slave Select is asserted and INC = 1, then the master MCU

function reads a byte from the radio, the address is incremented

by a byte location, and then the byte at that location is read, and

so on. If Slave Select is asserted and INC = 0, then the MCU

function reads/writes the bytes in the same register in burst

mode, but if it is a register file then it reads/writes the bytes in

that register file.

Radio Function

MCU Function

The SPI interface between the radio function and the MCU is not

dependent on the internal 12 MHz oscillator of the radio.

Therefore, radio function registers can be read from or written

into while the radio is in sleep mode.

P1.5/MOSI

MOSI

MOSI/MISO multiplexed

on one MOSI pin

P1.4/SCK

P1.3/nSS

SCK

nSS

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SPI I/O Voltage References

SPI Connects to External Devices

The SPI interfaces between MCU function and the radio and the

The three SPI wires, MOSI, SCK, and SS are also drawn out of

the package as external pins to allow the user to interface their

own external devices (such as optical sensors and others)

through SPI. The radio function also has its own SPI wires MISO

and IRQ, which can be used to send data back to the MCU

function or send an interrupt request to the MCU function. They

can also be configured as GPIO pins.

IRQ and RST have a separate voltage reference V , enabling

IO

the radio function to directly interface with the MCU function,

which operates at higher supply voltage. The internal SPIO pins

between the MCU function and radio function should be

connected with a regulated voltage of 3.3 V (by setting [bit4] of

Registers P13CR, P14CR, P15CR, and P16CR of the MCU

function) and the internal 3.3 V regulator of the MCU function

should be turned on.

Figure 6. SPI Transaction Format

Byte 1

Byte 1+N

Bit#

7

6

[5:0]

[7:0]

Data

Bit Name DIR

INC

Address

The Accumulator Register (CPU_A) is the general purpose

register that holds the results of instructions that specify any of

the source addressing modes.

CPU Architecture

This family of microcontroller is based on a high performance,

8-bit, Harvard-architecture microprocessor. Five registers

control the primary operation of the CPU core. These registers

are affected by various instructions, but are not directly

accessible through the register space by the user.

The Index Register (CPU_X) holds an offset value that is used

in the indexed addressing modes. Typically, this is used to

address a block of data within the data memory space.

The Stack Pointer Register (CPU_SP) holds the address of the

current top-of-stack in the data memory space. It is affected by

the PUSH, POP, LCALL, CALL, RETI, and RET instructions,

which manage the software stack. It can also be affected by the

SWAP and ADD instructions.

Table 4. CPU Registers and Register Names

Register

Register Name

CPU_F

The Flag Register (CPU_F) has three status bits: Zero Flag bit

[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global

Interrupt Enable bit [0] is used to globally enable or disable

interrupts. The user cannot manipulate the Supervisory State

status bit [3]. The flags are affected by arithmetic, logic, and shift

operations. The manner in which each flag is changed is

dependent upon the instruction being executed (for example,

AND, OR, XOR). See Table 21 on page 18.

Flags

Program Counter

Accumulator

Stack Pointer

Index

CPU_PC

CPU_A

CPU_SP

CPU_X

The 16-bit Program Counter Register (CPU_PC) allows for direct

addressing of the full eight Kbytes of program memory space.

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CYRF69213

CPU Registers

Flags Register

The Flags Register can only be set or reset with logical instruction.

Table 5. CPU Flags Register (CPU_F) [R/W]

Bit #

Field

7

6

5

4

3

2

1

0

Global IE

RW

Reserved

XIO

R/W

0

Super

Carry

RW

0

Zero

RW

1

Read/Write –

–

0

–

0

R

0

Default

Bits 7:5

Bit 4

0

Reserved

XIO

Set by the user to select between the register banks

0 = Bank 0

1 = Bank 1

Bit 3

Super

Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)

0 = User Code

1 = Supervisor Code

Bit 2

Carry

Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation

0 = No Carry

1 = Carry

Bit 1

Zero

Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation

0 = Not Equal to Zero

1 = Equal to Zero

Bit 0

Global IE

Determines whether all interrupts are enabled or disabled

0 = Disabled

1 = Enabled

Note CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be

used to set and clear the CPU_F bits

Accumulator Register

Table 6. CPU Accumulator Register (CPU_A)

Bit #

Field

7

6

5

4

3

2

1

0

CPU Accumulator [7:0]

Read/Write –

Default

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Bits 7:0 CPU Accumulator [7:0]

8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode

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CYRF69213

Index Register

Table 7. CPU X Register (CPU_X)

Bit #

7

6

5

4

3

2

1

0

Field

X [7:0]

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Bits 7:0X [7:0]

8-bit data value holds an index for any instruction that uses an indexed addressing mode

Stack Pointer Register

Table 8. CPU Stack Pointer Register (CPU_SP)

Bit #

7

6

5

4

3

2

1

0

Field

Stack Pointer [7:0]

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Bits 7:0 Stack Pointer [7:0]

8-bit data value holds a pointer to the current top-of-stack

CPU Program Counter High Register

Table 9. CPU Program Counter High Register (CPU_PCH)

Bit #

7

6

5

4

3

2

1

0

Field

Program Counter [15:8]

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Bits 7:0Program Counter [15:8]

8-bit data value holds the higher byte of the program counter

CPU Program Counter Low Register

Table 10. CPU Program Counter Low Register (CPU_PCL)

Bit #

7

6

5

4

3

2

1

0

Field

Program Counter [7:0]

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Bits 7:0 Program Counter [7:0]

8-bit data value holds the lower byte of the program counter

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Source Indexed

Addressing Modes

The result of an instruction using this addressing mode is placed

in either the A register or the X register, which is specified as part

of the instruction opcode. Operand 1 is added to the X register

forming an address that points to a location in either the RAM

memory space or the register space that is the source for the

instruction. Arithmetic instructions require two sources; the

second source is the A register or X register specified in the

opcode. Instructions using this addressing mode are two bytes

in length.

Examples of the different addressing modes are discussed in

this section and example code is given.

Source Immediate

The result of an instruction using this addressing mode is placed

in the A register, the F register, the SP register, or the X register,

which is specified as part of the instruction opcode. Operand 1

is an immediate value that serves as a source for the instruction.

Arithmetic instructions require two sources. Instructions using

this addressing mode are two bytes in length.

Table 13. Source Indexed

Table 11. Source Immediate

Opcode

Operand 1

Source Index

Opcode

Operand 1

Immediate Value

Instruction

Examples

ADD

A,

[X+7]

;In this case, the value in

;the memory location at

;address X + 7 is added with

;the Accumulator, and the

;result is placed in the

;Accumulator.

ADD

A,

7

;In this case, the immediate value

;of 7 is added with the Accumulator,

;and the result is placed in the

;Accumulator.

MOV

AND

X,

F,

8

9

;In this case, the immediate value

;of 8 is moved to the X register.

MOV

X,

REG[X+8]

;In this case, the value in

;the register space at

;address X + 8 is moved to

;the X register.

;In this case, the immediate value

;of 9 is logically ANDed with the F

;register and the result is placed

;in the F register.

Destination Direct

Source Direct

The result of an instruction using this addressing mode is placed

within either the RAM memory space or the register space.

Operand 1 is an address that points to the location of the result.

The source for the instruction is either the A register or the X

register, which is specified as part of the instruction opcode.

Arithmetic instructions require two sources; the second source is

the location specified by Operand 1. Instructions using this

addressing mode are two bytes in length.

The result of an instruction using this addressing mode is placed

in either the A register or the X register, which is specified as part

of the instruction opcode. Operand 1 is an address that points to

a location in either the RAM memory space or the register space

that is the source for the instruction. Arithmetic instructions

require two sources; the second source is the A register or X

register specified in the opcode. Instructions using this

addressing mode are two bytes in length.

Table 12. Source Direct

Table 14. Destination Direct

Opcode

Operand 1

Source Address

Opcode

Operand 1

Instruction

Destination Address

Examples

ADD

[7],

A

;In this case, the value in

;the memory location at

ADD

A,

[7]

;In this case, the value in

;the RAM memory location at

;address 7 is added with the

;Accumulator, and the result

;is placed in the Accumulator.

;address 7 is added with the

;Accumulator, and the result

;is placed in the memory

;location at address 7. The

;Accumulator is unchanged.

MOV

X,

REG[8] ;In this case, the value in

;the register space at address

;8 is moved to the X register.

MOV

REG[8],

A

;In this case, the Accumula-

;tor is moved to the regis-

;ter space location at

;address 8. The Accumulator

;is unchanged.

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CYRF69213

Destination Indexed

Destination Indexed Source Immediate

The result of an instruction using this addressing mode is placed

within either the RAM memory space or the register space.

Operand 1 is added to the X register forming the address that

points to the location of the result. The source for the instruction

is the A register. Arithmetic instructions require two sources; the

second source is the location specified by Operand 1 added with

the X register. Instructions using this addressing mode are two

bytes in length.

The result of an instruction using this addressing mode is placed

within either the RAM memory space or the register space.

Operand 1 is added to the X register to form the address of the

result. The source for the instruction is Operand 2, which is an

immediate value. Arithmetic instructions require two sources; the

second source is the location specified by Operand 1 added with

the X register. Instructions using this addressing mode are three

bytes in length.

Table 17. Destination Indexed Immediate

Table 15. Destination Indexed

Opcode

Operand 1

Operand 2

Opcode

Operand 1

Destination Index

Instruction

Destination Index

Immediate Value

Instruction

Examples

Example

ADD

[X+7],

5

6

;In this case, the value in

;the memory location at

;address X+7 is added with

;the immediate value of 5,

;and the result is placed

;in the memory location at

;address X+7.

ADD [X+7],

A

;In this case, the value in the

;memory location at address X+7

;is added with the Accumulator,

;and the result is placed in

;the memory location at address

;x+7. The Accumulator is

;unchanged.

MOV

REG[X+8],

;In this case, the immedi-

;ate value of 6 is moved

;into the location in the

;register space at

Destination Direct Source Immediate

The result of an instruction using this addressing mode is placed

within either the RAM memory space or the register space.

Operand 1 is the address of the result. The source for the

instruction is Operand 2, which is an immediate value. Arithmetic

instructions require two sources; the second source is the

location specified by Operand 1. Instructions using this

addressing mode are three bytes in length.

;address X+8.

Destination Direct Source Direct

The result of an instruction using this addressing mode is placed

within the RAM memory. Operand 1 is the address of the result.

Operand 2 is an address that points to a location in the RAM

memory that is the source for the instruction. This addressing

mode is only valid on the MOV instruction. The instruction using

this addressing mode is three bytes in length.

Table 16. Destination Direct Immediate

Opcode

Operand 1

Operand 2

Instruction

Destination Address

Immediate Value

Table 18. Destination Direct Source Direct

Opcode

Operand 1

Operand 2

Examples

Instruction

Destination Address

Source Address

ADD [7],

5

6

;In this case, value in the mem-

;ory location at address 7 is

;added to the immediate value of

;5, and the result is placed in

;the memory location at address 7.

Example

MOV

[7], [8] ;In this case, the value in the

;memory location at address 8 is

;moved to the memory location at

;address 7.

MOV REG[8],

;In this case, the immediate

;value of 6 is moved into the

;register space location at

;address 8.

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CYRF69213

Source Indirect Post Increment

Destination Indirect Post Increment

The result of an instruction using this addressing mode is placed

in the Accumulator. Operand 1 is an address pointing to a

location within the memory space, which contains an address

(the indirect address) for the source of the instruction. The

indirect address is incremented as part of the instruction

execution. This addressing mode is only valid on the MVI

instruction. The instruction using this addressing mode is two

bytes in length. Refer to the PSoC Designer: Assembly

Language User Guide for further details on MVI instruction.

The result of an instruction using this addressing mode is placed

within the memory space. Operand 1 is an address pointing to a

location within the memory space, which contains an address

(the indirect address) for the destination of the instruction. The

indirect address is incremented as part of the instruction

execution. The source for the instruction is the Accumulator. This

addressing mode is only valid on the MVI instruction. The

instruction using this addressing mode is two bytes in length.

Table 20. Destination Indirect Post Increment

Table 19. Source Indirect Post Increment

Opcode

Operand 1

Opcode

Operand 1

Instruction

Destination Address Address

Instruction

Source Address Address

Example

MVI

[8],

A

;In this case, the value in

;the memory location at

MVI

A,

[8] ;In this case, the value in the

;memory location at address 8 is

;an indirect address. The memory

;location pointed to by the indi-

;rect address is moved into the

;Accumulator. The indirect

;address 8 is an indirect

;address. The Accumulator is

;moved into the memory loca-

;tion pointed to by the indi-

;rect address. The indirect

;address is then incremented.

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Instruction Set Summary

The instruction set is summarized in Table 21 numerically and serves as a quick reference. If more information is needed, the

Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on

www.cypress.com).

[1, 2]

Table 21. Instruction Set Summary Sorted Numerically by Opcode Order

Instruction Format

Flags

Instruction Format

Flags

Instruction Format

Flags

00 15

1

2

3

1

2

3

SSC

2D

2E

8

9

2

3

1

2

3

2

OR [X+expr], A

OR [expr], expr

Z

5A

5B

5C

5D

5E

5

4

6

7

2

1

2

3

2

3

1

2

1

2

MOV [expr], X

MOV A, X

01

02

03

04

05

06

4

6

7

8

9

ADD A, expr

ADD A, [expr]

C, Z

Z

C, Z

2F 10

OR [X+expr], expr

HALT

MOV X, A

ADD A, [X+expr]

ADD [expr], A

30

31

32

33

34

35

36

9

MOV A, reg[expr]

MOV A, reg[X+expr]

MOV [expr], [expr]

MOV reg[expr], A

MOV reg[X+expr], A

MOV reg[expr], expr

MOV reg[X+expr], expr

ASL A

Z

4

XOR A, expr

Z

ADD [X+expr], A

ADD [expr], expr

ADD [X+expr], expr

PUSH A

6

7

8

9

XOR A, [expr]

5F 10

XOR A, [X+expr]

XOR [expr], A

60

61

62

63

64

65

66

67

68

5

6

8

9

07 10

08

09

0A

0B

0C

0D

0E

4

XOR [X+expr], A

XOR [expr], expr

XOR [X+expr], expr

ADD SP, expr

4

ADC A, expr

C, Z

6

7

8

9

ADC A, [expr]

37 10

4

C, Z

ADC A, [X+expr]

ADC [expr], A

38

39

3A

3B

3C

3D

5

7

8

7

8

4

7

ASL [expr]

CMP A, expr

if (A=B)

Z=1

if (A<B)

C=1

ASL [X+expr]

ASR A

ADC [X+expr], A

ADC [expr], expr

3 ADC [X+expr], expr

1 PUSH X

CMP A, [expr]

CMP A, [X+expr]

3 CMP [expr], expr

3 CMP [X+expr], expr

2 MVI A, [ [expr]++ ]

2 MVI [ [expr]++ ], A

1 NOP

ASR [expr]

2 ASR [X+expr]

1 RLC A

0F 10

C, Z

8

9

69

8

4

7

8

4

7

8

4

7

8

4

7

8

C, Z

Z

10

11

12

13

14

15

16

4

6

7

8

9

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

2 SUB A, expr

2 SUB A, [expr]

2 SUB A, [X+expr]

2 SUB [expr], A

2 SUB [X+expr], A

3 SUB [expr], expr

3 SUB [X+expr], expr

1 POP A

C, Z

Z

3E 10

3F 10

Z

2 RLC [expr]

2 RLC [X+expr]

1 RRC A

40

41

4

9

3 AND reg[expr], expr

3 AND reg[X+expr], expr

3 OR reg[expr], expr

3 OR reg[X+expr], expr

3 XOR reg[expr], expr

3 XOR reg[X+expr], expr

3 TST [expr], expr

3 TST [X+expr], expr

3 TST reg[expr], expr

3 TST reg[X+expr], expr

1 SWAP A, X

Z

2 RRC [expr]

2 RRC [X+expr]

2 AND F, expr

2 OR F, expr

2 XOR F, expr

1 CPL A

42 10

43

44 10

45

46 10

9

17 10

18

19

5

4

6

7

8

9

2 SBB A, expr

2 SBB A, [expr]

2 SBB A, [X+expr]

2 SBB [expr], A

2 SBB [X+expr], A

3 SBB [expr], expr

3 SBB [X+expr], expr

1 POP X

C, Z

1A

1B

1C

1D

1E

47

48

49

8

9

1 INC A

C, Z

1 INC X

2 INC [expr]

2 INC [X+expr]

1 DEC A

4A 10

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5

7

5

4

5

6

5

6

8

9

4

6

7

1F 10

2 SWAP A, [expr]

2 SWAP X, [expr]

1 SWAP A, SP

1 DEC X

20

21

22

23

24

25

26

5

4

6

7

8

9

2 DEC [expr]

2 DEC [X+expr]

3 LCALL

2 AND A, expr

2 AND A, [expr]

2 AND A, [X+expr]

2 AND [expr], A

2 AND [X+expr], A

3 AND [expr], expr

3 AND [X+expr], expr

1 ROMX

Z

1 MOV X, SP

7C 13

7D

7E 10

2 MOV A, expr

Z

7

3 LJMP

2 MOV A, [expr]

2 MOV A, [X+expr]

2 MOV [expr], A

2 MOV [X+expr], A

3 MOV [expr], expr

3 MOV [X+expr], expr

2 MOV X, expr

1 RETI

C, Z

7F

8x

8

5

1 RET

2 JMP

27 10

28 11

9x 11

2 CALL

Ax

Bx

Cx

Dx

Ex

5

7

2 JZ

29

2A

2B

2C

4

6

7

2 OR A, expr

2 JNZ

2 OR A, [expr]

2 OR A, [X+expr]

2 OR [expr], A

2 JC

2 MOV X, [expr]

2 MOV X, [X+expr]

2 JNC

2 JACC

Fx 13

2 INDEX

Z

Notes

1. Interrupt routines take 13 cycles before execution resumes at interrupt vector table.

2. The number of cycles required by an instruction is increased by one for instructions that span 256-byte boundaries in the Flash memory space.

Document Number: 001-07552 Rev. *G

Page 18 of 85

CYRF69213

Memory Organization

Flash Program Memory Organization

Table 22. Program Memory Space with Interrupt Vector Table

after reset

16-bit PC

Address

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0040

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x005C

0x0060

0x0064

0x0068

Program execution begins here after a reset

POR/LVD

INT0

SPI Transmitter Empty

SPI Receiver Full

GPIO Port 0

GPIO Port 1

INT1

EP0

EP1

EP2

USB Reset

USB Active

1 ms Interval Timer

Programmable Interval Timer

Reserved

16-bit Free Running Timer Wrap

INT2

Reserved

GPIO Port 2

Reserved

Sleep Timer

Program Memory begins here (if below interrupts not used,

program memory can start lower)

0x1FFF

8 KB ends here

Document Number: 001-07552 Rev. *G

Page 19 of 85

CYRF69213

Data Memory Organization

The MCU function has 256 bytes of data RAM.

Table 23. Data Memory Organization

after reset

8-bit PSP

Address

0x00

Stack begins here and grows upward.

Top of RAM Memory

0xFF

Flash

SROM

This section describes the Flash block of the CYRF69213. Much

of the user-visible Flash functionality, including programming

and security, are implemented in the M8C Supervisory Read

Only Memory (SROM). CYRF69213 Flash has an endurance of

1000 cycles and 10 year data retention.

The SROM holds code that is used to boot the part, calibrate

circuitry, and perform Flash operations. (Table 24 lists the SROM

functions.) The functions of the SROM may be accessed in

normal user code or operating from Flash. The SROM exists in

a separate memory space from user code. The SROM functions

are accessed by executing the Supervisory System Call

instruction (SSC), which has an opcode of 00h. Prior to

executing the SSC, the M8C’s accumulator needs to be loaded

with the desired SROM function code from Table 24. Undefined

functions causes a HALT if called from user code. The SROM

functions are executing code with calls; therefore, the functions

require stack space. With the exception of Reset, all of the

SROM functions have a parameter block in SRAM that must be

configured before executing the SSC. Table 25 lists all possible

parameter block variables. The meaning of each parameter, with

regards to a specific SROM function, is described later in this

section.

Flash Programming and Security

All Flash programming is performed by code in the SROM. The

registers that control the Flash programming are only visible to

the M8C CPU when it is executing out of SROM. This makes it

impossible to read, write, or erase the Flash by bypassing the

security mechanisms implemented in the SROM.

Customer firmware can only program the Flash via SROM calls.

The data or code images can be sourced by way of any interface

with the appropriate support firmware. This type of programming

requires a ‘boot-loader’ — a piece of firmware resident on the

Flash. For safety reasons this boot-loader should not be

overwritten during firmware rewrites.

Table 24. SROM Function Codes

The Flash provides four auxiliary rows that are used to hold Flash

block protection flags, boot time calibration values, configuration

tables, and any device values. The routines for accessing these

auxiliary rows are documented in the SROM section. The

auxiliary rows are not affected by the device erase function.

Function Code

Function Name

SWBootReset

ReadBlock

WriteBlock

EraseBlock

EraseAll

Stack Space

00h

01h

02h

03h

05h

06h

07h

0

7

10

9

In-System Programming

Most designs that include an CYRF69213 part have a USB

connector attached to the USB D+/D– pins on the device. These

designs require the ability to program or reprogram a part

through these two pins alone.

11

3

TableRead

CheckSum

3

CYRF69213 device enables this type of in-system programming

by using the D+ and D– pins as the serial programming mode

interface. This allows an external controller to cause the

CYRF69213 part to enter serial programming mode and then to

use the test queue to issue Flash access functions in the SROM.

The programming protocol is not USB.

Two important variables that are used for all functions are KEY1

and KEY2. These variables are used to help discriminate

between valid SSCs and inadvertent SSCs. KEY1 must always

have a value of 3Ah, while KEY2 must have the same value as

the stack pointer when the SROM function begins execution.

This would be the Stack Pointer value when the SSC opcode is

Document Number: 001-07552 Rev. *G

Page 20 of 85

CYRF69213

executed, plus three. If either of the keys do not match the

expected values, the M8C halts (with the exception of the

SWBootReset function). The following code puts the correct

value in KEY1 and KEY2. The code starts with a halt, to force the

program to jump directly into the setup code and not run into it.

SROM Function Descriptions

All SROM functions are described in the following sections.

SWBootReset Function

The SROM function, SWBootReset, is the function that is

responsible for transitioning the device from a reset state to

running user code. The SWBootReset function is executed

whenever the SROM is entered with an M8C accumulator value

of 00h; the SRAM parameter block is not used as an input to the

function. This happens, by design, after a hardware reset,

because the M8C's accumulator is reset to 00h or when user

code executes the SSC instruction with an accumulator value of

00h. The SWBootReset function does not execute when the

SSC instruction is executed with a bad key value and a nonzero

function code. A CYRF69213 device executes the HALT

instruction if a bad value is given for either KEY1 or KEY2.

halt

SSCOP: mov [KEY1], 3ah

mov X, SP

mov A, X

add A, 3

mov [KEY2], A

Table 25. SROM Function Parameters

Variable Name

SRAM Address

0,F8h

Key1/Counter/Return Code

Key2/TMP

BlockID

Pointer

Clock

0,F9h

The SWBootReset function verifies the integrity of the calibration

data by way of a 16-bit checksum, before releasing the M8C to

run user code.

0,FAh

0,FBh

ReadBlock Function

0,FCh

The ReadBlock function is used to read 64 contiguous bytes

from Flash — a block.

Mode

0,FDh

Delay

0,FEh

The first thing this function does is to check the protection bits

and determine if the desired BLOCKID is readable. If read

protection is turned on, the ReadBlock function exits, setting the

accumulator and KEY2 back to 00h. KEY1 has a value of 01h,

indicating a read failure. If read protection is not enabled, the

function reads 64 bytes from the Flash using a ROMX instruction

and store the results in SRAM using an MVI instruction. The first

of the 64 bytes is stored in SRAM at the address indicated by the

value of the POINTER parameter. When the ReadBlock

completes successfully, the accumulator, KEY1, and KEY2 all

have a value of 00h.

PCL

0,FFh

The SROM also features Return Codes and Lockouts.

Return Codes

Return codes aid in the determination of success or failure of a

particular function. The return code is stored in KEY1’s position

in the parameter block. The CheckSum and TableRead functions

do not have return codes because KEY1’s position in the

parameter block is used to return other data.

Table 27. ReadBlock Parameters

Table 26. SROM Return Codes

Name

KEY1

KEY2

Address

0,F8h

Description

Return Code

Description

3Ah

00h

01h

Success

0,F9h

Stack Pointer value, when SSC is

executed

Function not allowed due to level of protection

on block

BLOCKID 0,FAh

POINTER 0,FBh

Flash block number

02h

03h

Software reset without hardware reset

Fatal error, SROM halted

First of 64 addresses in SRAM where

returned data should be stored

Read, write, and erase operations may fail if the target block is

read or write protected. Block protection levels are set during

device programming.

WriteBlock Function

The WriteBlock function is used to store data in the Flash. Data

is moved 64 bytes at a time from SRAM to Flash using this

function. The first thing the WriteBlock function does is to check

the protection bits and determine if the desired BLOCKID is

writable. If write protection is turned on, the WriteBlock function

exits, setting the accumulator and KEY2 back to 00h. KEY1 has

a value of 01h, indicating a write failure. The configuration of the

WriteBlock function is straightforward. The BLOCKID of the

Flash block, where the data is stored, must be determined and

stored at SRAM address FAh.

The EraseAll function overwrites data in addition to leaving the

entire user Flash in the erase state. The EraseAll function loops

through the number of Flash macros in the product, executing

the following sequence: erase, bulk program all zeros, erase.

After all the user space in all the Flash macros are erased, a

second loop erases and then programs each protection block

with zeros.

Document Number: 001-07552 Rev. *G

Page 21 of 85

CYRF69213

The SRAM address of the first of the 64 bytes to be stored in

Flash must be indicated using the POINTER variable in the

parameter block (SRAM address FBh). Finally, the CLOCK and

DELAY values must be set correctly. The CLOCK value

determines the length of the write pulse that is used to store the

data in the Flash. The CLOCK and DELAY values are dependent

on the CPU speed. Refer to ‘Clocking’ Section for additional

information.

ProtectBlock Function

The CYRF69213 device offers Flash protection on

a

block-by-block basis. Table 30 lists the protection modes

available. In the table, ER and EW are used to indicate the ability

to perform external reads and writes. For internal writes, IW is

used. Internal reading is always permitted by way of the ROMX

instruction. The ability to read by way of the SROM ReadBlock

function is indicated by SR. The protection level is stored in two

bits according to Table 30. These bits are bit packed into the 64

bytes of the protection block. Therefore, each protection block

byte stores the protection level for four Flash blocks. The bits are

packed into a byte, with the lowest numbered block’s protection

level stored in the lowest numbered bits.

Table 28. WriteBlock Parameters

Name

KEY1

KEY2

Address

0,F8h

Description

3Ah

0,F9h

Stack Pointer value, when SSC is

executed

The first address of the protection block contains the protection

level for blocks 0 through 3; the second address is for blocks 4

through 7. The 64th byte stores the protection level for blocks

252 through 255.

BLOCKID 0,FAh

POINTER 0,FBh

8 KB Flash block number (00h–7Fh)

4 KB Flash block number (00h–3Fh)

3 KB Flash block number (00h–2Fh)

Table 30. Protection Modes

Firstof64addressesinSRAM, where

the data to be stored in Flash is

located prior to calling WriteBlock

Mode

Settings

Description

Marketing

Unprotected

00b SR ER EW IW Unprotected

01b SR ER EW IW Read protect

CLOCK

DELAY

0,FCh

0,FEh

Clock divider used to set the write

pulse width

Factory upgrade

10b SR ER EW IW Disable external Field upgrade

write

For a CPU speed of 12 MHz set to

56h

11b SR ER EW IW Disable internal Full protection

write

EraseBlock Function

The EraseBlock function is used to erase a block of 64

contiguous bytes in Flash. The first thing the EraseBlock function

does is to check the protection bits and determine if the desired

BLOCKID is writable. If write protection is turned on, the

EraseBlock function exits, setting the accumulator and KEY2

back to 00h. KEY1 has a value of 01h, indicating a write failure.

The EraseBlock function is only useful as the first step in

programming. Erasing a block does not cause data in a block to

be one hundred percent unreadable. If the objective is to

obliterate data in a block, the best method is to perform an

EraseBlock followed by a WriteBlock of all zeros.

7

6

5

4

3

2

1

0

Block n+3

Block n+2

Block n+1

Block n

The level of protection is only decreased by an EraseAll, which

places zeros in all locations of the protection block. To set the

level of protection, the ProtectBlock function is used. This

function takes data from SRAM, starting at address 80h, and

ORs it with the current values in the protection block. The result

of the OR operation is then stored in the protection block. The

EraseBlock function does not change the protection level for a

block. Because the SRAM location for the protection data is fixed

and there is only one protection block per Flash macro, the

ProtectBlock function expects very few variables in the

parameter block to be set prior to calling the function. The

parameter block values that must be set, besides the keys, are

the CLOCK and DELAY values.

To set up the parameter block for the EraseBlock function,

correct key values must be stored in KEY1 and KEY2. The block

number to be erased must be stored in the BLOCKID variable

and the CLOCK and DELAY values must be set based on the

current CPU speed.

Table 29. EraseBlock Parameters

Table 31. ProtectBlock Parameters

Name

KEY1

KEY2

Address

0,F8h

Description

Name

KEY1

Address

0,F8h

Description

3Ah

0,F9h

Stack Pointer value when SSC is

executed

KEY2

0,F9h

Stack Pointer value when SSC is

executed

BLOCKID 0,FAh

Flash block number (00h–7Fh)

CLOCK

DELAY

0,FCh

0,FEh

Clock divider used to set the write

pulse width

CLOCK

0,FCh

Clock divider used to set the erase

pulse width

For a CPU speed of 12 MHz set to

56h

DELAY

0,FEh

For a CPU speed of 12 MHz set to

56h

Document Number: 001-07552 Rev. *G

Page 22 of 85

CYRF69213

EraseAll Function

numbered zero through seven. All user and hidden blocks in the

CYRF69213 parts consist of 64 bytes.

The EraseAll function performs a series of steps that destroy the

user data in the Flash macros and resets the protection block in

each Flash macro to all zeros (the unprotected state). The

EraseAll function does not affect the three hidden blocks above

the protection block in each Flash macro. The first of these four

hidden blocks is used to store the protection table for its eight

Kbytes of user data.

An internal table holds the Silicon ID and returns the Revision ID.

The Silicon ID is returned in SRAM, while the Revision ID is

returned in the CPU_A and CPU_X registers. The Silicon ID is a

value placed in the table by programming the Flash and is

controlled by Cypress Semiconductor Product Engineering. The

Revision ID is hard coded into the SROM. The Revision ID is

discussed in more detail later in this section.

The EraseAll function begins by erasing the user space of the

Flash macro with the highest address range. A bulk program of

all zeros is then performed on the same Flash macro, to destroy

all traces of the previous contents. The bulk program is followed

by a second erase that leaves the Flash macro in a state ready

for writing. The erase, program, erase sequence is then

performed on the next lowest Flash macro in the address space

if it exists. Following the erase of the user space, the protection

block for the Flash macro with the highest address range is

erased. Following the erase of the protection block, zeros are

written into every bit of the protection table. The next lowest

Flash macro in the address space then has its protection block

erased and filled with zeros.

An internal table holds alternate trim values for the device and

returns a one-byte internal revision counter. The internal revision

counter starts out with a value of zero and is incremented each

time one of the other revision numbers is not incremented. It is

reset to zero each time one of the other revision numbers is

incremented. The internal revision count is returned in the

CPU_A register. The CPU_X register is always set to FFh when

trim values are read. The BLOCKID value, in the parameter

block, is used to indicate which table should be returned to the

user. Only the three least significant bits of the BLOCKID

parameter are used by the TableRead function for the

CYRF69213. The upper five bits are ignored. When the function

is called, it transfers bytes from the table to SRAM addresses

F8h–FFh.

The end result of the EraseAll function is that all user data in the

Flash is destroyed and the Flash is left in an unprogrammed

state, ready to accept one of the various write commands. The

protection bits for all user data are also reset to the zero state.

The M8C’s A and X registers are used by the TableRead function

to return the die’s Revision ID. The Revision ID is a 16-bit value

hard coded into the SROM that uniquely identifies the die’s

design.

The parameter block values that must be set, besides the keys,

are the CLOCK and DELAY values.

Checksum Function

Table 32. EraseAll Parameters

The Checksum function calculates a 16-bit checksum over a

user specifiable number of blocks, within a single Flash macro

(Bank) starting from block zero. The BLOCKID parameter is

used to pass in the number of blocks to calculate the checksum

over. A BLOCKID value of 1 calculates the checksum of only

block 0, while a BLOCKID value of 0 calculates the checksum of

all 256 user blocks. The 16-bit checksum is returned in KEY1 and

KEY2. The parameter KEY1 holds the lower eight bits of the

checksum and the parameter KEY2 holds the upper eight bits of

the checksum.

Name

KEY1

Address

0,F8h

Description

3Ah

KEY2

0,F9h

Stack Pointer value when SSC is

executed

CLOCK

DELAY

0,FCh

0,FEh

Clock divider used to set the write

pulse width

For a CPU speed of 12 MHz set to

56h

The checksum algorithm executes the following sequence of

three instructions over the number of blocks times 64 to be

checksummed.

TableRead Function

The TableRead function gives the user access to part specific

data stored in the Flash during manufacturing. It also returns a

Revision ID for the die (not to be confused with the Silicon ID).

romx

add [KEY1], A

adc [KEY2], 0

Table 33. Table Read Parameters

Table 34. Checksum Parameters

Name

KEY1

KEY2

Address

0,F8h

Description

Name

KEY1

KEY2

Address

0,F8h

Description

3Ah

0,F9h

Stack Pointer value when SSC is

executed

0,F9h

Stack Pointer value when SSC is

executed

BLOCKID 0,FAh

Table number to read

BLOCKID 0,FAh

Number of Flash blocks to calculate

checksum on

The table space for the CYRF69213 is simply a 64-byte row

broken up into eight tables of eight bytes. The tables are

Document Number: 001-07552 Rev. *G

Page 23 of 85

CYRF69213

SROM Table Read Description

Figure 7. SROM Table

F8h

F9h

F8h

Silicon ID

[15-8]

Silicon ID

[7-0]

Table 0

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

The Silicon IDs for enCoRe II devices are stored in SROM tables in the part, as shown in Figure 7.

The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated in the following pseudo code. As

mentioned in the section SROM on page 20, the SROM variables occupy address F8h through FFh in the SRAM. Each of the variables

and their definition in given in the section SROM on page 20.

AREA SSCParmBlkA(RAM,ABS)

org F8h // Variables are defined starting at address F8h

SSC_KEY1:

; F8h supervisory key

blk 1 ; F8h result code

blk 1 ;F9h supervisory stack ptr key

blk 1 ; FAh block ID

blk 1 ; FBh pointer to data buffer

blk 1 ; FCh Clock

blk 1 ; FDh ClockW ClockE multiplier

blk 1 ; FEh flash macro sequence delay count

SSC_RETURNCODE:

SSC_KEY2 :

SSC_BLOCKID:

SSC_POINTER:

SSC_CLOCK:

SSC_MODE:

SSC_DELAY:

SSC_WRITE_ResultCode: blk 1 ; FFh temporary result code

_main:

mov

A, 0

[SSC_BLOCKID], A// To read from Table 0 - Silicon ID is stored in Table 0

//Call SROM operation to read the SROM table

mov

add

mov

X, SP

A, X

A, 3

; copy SP into X

; A temp stored in X

; create 3 byte stack frame (2 + pushed A)

; save stack frame for supervisory code

[SSC_KEY2], A

; load the supervisory code for flash operations

mov

[SSC_KEY1], 3Ah ;FLASH_OPER_KEY - 3Ah

mov

SSC

A,6

; load A with specific operation. 06h is the code for Table read Table 24

; SSC call the supervisory ROM

// At the end of the SSC command the silicon ID is stored in F8 (MSB) and F9(LSB) of the SRAM

.terminate:

jmp .terminate

Document Number: 001-07552 Rev. *G

Page 24 of 85

CYRF69213

Clocking

The CYRF69213 internal oscillator outputs two frequencies, the Internal 24 MHz Oscillator and the 32 kHz Low power Oscillator.

The Internal 24 MHz Oscillator is designed such that it may be trimmed to an output frequency of 24 MHz over temperature and voltage

variation. With the presence of USB traffic, the Internal 24 MHz Oscillator can be set to precisely tune to USB timing requirements

(24 MHz ± 1.5%). Without USB traffic, the Internal 24 MHz Oscillator accuracy is 24 MHz ± 5% (between 0 °C–70 °C). No external

components are required to achieve this level of accuracy.

The internal low speed oscillator of nominally 32 KHz provides a slow clock source for the CYRF69213 in suspend mode, particularly

to generate a periodic wakeup interrupt and also to provide a clock to sequential logic during power up and power down events when

the main clock is stopped. In addition, this oscillator can also be used as a clocking source for the Interval Timer clock (ITMRCLK)

and Capture Timer clock (TCAPCLK). The 32 kHz Low power Oscillator can operate in low power mode or can provide a more accurate

clock in normal mode. The Internal 32 kHz Low power Oscillator accuracy ranges (between 0° C–70° C) as follows:

5 V Normal mode: –8% to + 16%

5 V LP mode: +12% to + 48%

When using the 32 kHz oscillator the PITMRL/H should be read until two consecutive readings match before sending/receiving data.

The following firmware example assumes the developer is interested in the lower byte of the PIT.

Read_PIT_counter:

mov A, reg[PITMRL]

mov [57h], A

mov A, reg[PITMRL]

mov [58h], A

mov [59h], A

mov A, reg{PITMRL]

mov [60h], A

;;;Start comparison

mov A, [60h]

mov X, [59h]

sub A, [59h]

jz done

mov A, [59h]

mov X, [58h]

sub A, [58h]

jz done

mov X, [57h]

;;;correct data is in memory location 57h

done:

mov [57h], X

ret

Document Number: 001-07552 Rev. *G

Page 25 of 85

CYRF69213

Figure 8. Clock Block Diagram

CPUCLK

SEL

SCALE (divide by 2ⁿ,

CPU_CLK

n = 0-5,7)

MUX

CLK_24MHz

CLK_USB

MUX

24 MHz

SEL

SCALE

OUT

SCALE

SEL

12 MHz

RESERVED

0

1

X

1

LP OSC

32 KHz

CLK_32

KHz

The Timer Capture clock (TCAPCLK) can be sourced from the

Internal 24 MHz Oscillator, or the Internal 32 kHz Low power

Oscillator except when in sleep mode.

The CLKOUT pin (P0.1) can be driven from one of many

sources. This is used for test and can also be used in some

applications.

Clock Architecture Description

The CYRF69213 clock selection circuitry allows the selection of

independent clocks for the CPU, USB, Interval Timers, and

Capture Timers.

The CPU clock, CPUCLK, can be sourced from the Internal 24

MHz Oscillator. This clock source can optionally be divided by 2ⁿ

where n is 0–5,7 (see Table 38 on page 29).

The sources that can drive the CLKOUT are:

■ CLKIN after the optional EFTB filter

■ Internal 24 MHz Oscillator

USBCLK, which must be 12 MHz for the USB SIE to function

properly, can be sourced by the Internal 24 MHz Oscillator. An

optional divide-by-two allows the use of the 24 MHz source.

The Interval Timer clock (ITMRCLK), can be sourced from the

Internal 24 MHz Oscillator, the Internal 32 kHz Low power

Oscillator, except when in sleep mode, or from the timer capture

clock (TCAPCLK). A programmable prescaler of 1, 2, 3, 4 then

divides the selected source.

■ Internal 32 kHz Low power Oscillator except when in sleep

mode

■ CPUCLK after the programmable divider

Document Number: 001-07552 Rev. *G

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CYRF69213

Table 35. IOSC Trim (IOSCTR) [0x34] [R/W]

Bit #

7

6

foffset[2:0]

R/W

5

4

3

2

Gain[4:0]

R/W

1

0

Field

Read/Write

Default

R/W

0

R/W

0

R/W

D

R/W

D

R/W

D

R/W

D

0

D

The I/OSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM

writes a calibration value that is determined during manufacturing test. This value should not require change during normal use.

This is the meaning of ‘D’ in the Default field

Bits 7:5

foffset [2:0]

This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and is zero. Setting

each of these bits causes the appropriate fine offset in oscillator frequency

foffset bit 0 = 7.5 kHz

foffset bit 1 = 15 kHz

foffset bit 2 = 30 kHz

Bits 4:0

Gain [4:0]

The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases

the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change (KHz/off-

setStep) at each bit, typical conditions (24 MHz operation):

Gain bit 0 = –1.5 kHz

Gain bit 1 = –3.0 kHz

Gain bit 2 = –6 kHz

Gain bit 3 = –12 kHz

Gain bit 4 = –24 kHz

Table 36. LPOSC Trim (LPOSCTR) [0x36] [R/W]

Bit #

7

6

5

4

3

2

1

0

32 kHz Low

Power

Reserved

32 kHz Bias Trim [1:0]

32 kHz Freq Trim [3:0]

Field

Read/Write

Default

R/W

0

–

R/W

D

R/W

D

R/W

D

R/W

D

R/W

D

R/W

D

This register is used to calibrate the 32 kHz Low speed Oscillator. The reset value is undefined, but during boot the SROM writes

a calibration value that is determined during manufacturing test. This value should not require change during normal use. This is

the meaning of ‘D’ in the Default field. If the 32 kHz Low power bit needs to be written, care should be taken not to disturb the 32

kHz Bias Trim and the 32 kHz Freq Trim fields from their factory calibrated values

Bit 7

32 kHz Low Power

0 = The 32 kHz Low speed Oscillator operates in normal mode

1 = The 32 kHz Low speed Oscillator operates in a low power mode. The oscillator continues to function normally but with re-

duced accuracy

Bit 6

Reserved

Bits 5:4

32 kHz Bias Trim [1:0]

These bits control the bias current of the low power oscillator.

0 0 = Mid bias

0 1 = High bias

1 0 = Reserved

1 1 = Reserved

Important Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value, as the oscillator does not oscillate at

all corner conditions with this setting

Bits 3:0

32 kHz Freq Trim [3:0]

These bits are used to trim the frequency of the low power oscillator

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CYRF69213

Table 37. CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]

Bit #

Field

7

6

5

4

3

2

1

0

Reserved

Read/Write

Default

Bit 7

–

0

R/W

0

R/W

0

–

0

–

0

–

0

–

0

R/W

0

Reserved

Bit 6

Bit 5

Bits 4:1

Bit 0

Note The CPU speed selection is configured using the OSC_CR0 Register (Table 38 on page 29)

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CYRF69213

Table 38. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]

Bit #

7

6

5

No Buzz

R/W

0

4

3

2

1

0

Field

Reserved

Sleep Timer [1:0]

CPU Speed [2:0]

Read/Write

Default

Bits 7:6

Bit 5

–

0

–

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Reserved

No Buzz

During sleep (the Sleep bit is set in the CPU_SCR Register — Table 42 on page 33), the LVD and POR detection circuit is turned

on periodically to detect any POR and LVD events on the V pin (the Sleep Duty Cycle bits in the ECO_TR are used to control

CC

the duty cycle — Table 46 on page 38). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the

LVD and POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR

event during sleep at the expense of a slightly higher than average sleep current

0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle

1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled

Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below

Bits 4:3

Sleep Timer [1:0]

SleepTimer Sleep Timer Clock Sleep Period Watchdog Period

[1:0] Frequency (Nominal) (Nominal) (Nominal)

00

01

10

11

512 Hz

64 Hz

8 Hz

1.95 ms

15.6 ms

125 ms

1 sec

6 ms

47 ms

375 ms

3 sec

1 Hz

Note Sleep intervals are approximate

Bits 2:0 CPU Speed [2:0]

The CYRF69213 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the

default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz

Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements

apply. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less

CPU Speed [2:0]

CPU

3 MHz (Default)

6 MHz

000

001

010

011

100

101

110

111

12 MHz

24 MHz

1.5 MHz

750 KHz

187 KHz

Reserved

Important Note Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two

clocks have the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks have different

sources, care must be taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8 across the full

specification range of both clock sources

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CYRF69213

Table 39. USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Fine Tune USBOsclock

Field

Only

R/W

0

Disable

R/W

0

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference. The USB

Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock

Bits 7:2

Reserved

Bit 1

Fine Tune Only

0 = Enable

1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be allowed to

perform a course tuning to tune the oscillator for correct USB SIE operation. After the oscillator is properly tuned this bit can be

set to reduce variance in the internal oscillator frequency that would be caused by course tuning

Bit 0

USB Osclock Disable

0 = Enable. With the presence of USB traffic, the Internal 24 MHz Oscillator precisely tunes to 24 MHz ± 1.5%

1 = Disable. The Internal 24 MHz Oscillator is not trimmed based on USB packets. This setting is useful when the internal oscil-

lator is not sourcing the USBSIE clock

Table 40. Timer Clock Config (TMRCLKCR) [0x31] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

TCAPCL Divider

R/W R/W

TCAPCLK Select

ITMRCLK Divider

ITMRCLK Select

Read/Write

Default

Bits 7:6

R/W

-

R/W

-

R/W

1

R/W

1

R/W

0

R/W

0

-

TCAPCLK Divider

TCAPCLK Divider controls the TCAPCLK divisor

00 = Divide by 2

01 = Divide by 4

10 = Divide by 6

11 = Divide by 8

Bits 5:4

TCAPCLK Select

The TCAPCLK Select field controls the source of the TCAPCLK

0 0 = Internal 24 MHz Oscillator

0 1 = Reserved)

1 0 = Internal 32 kHz Low power Oscillator. However this configuration is not used in sleep mode.

1 1 = TCAPCLK Disabled

Note The 1024-s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency

causes a corresponding change in the 1024 s interval timer frequency

Bits 3:2

ITMRCLK Divider

ITMRCLK Divider controls the ITMRCLK divisor.

0 0 = Divider value of 1

0 1 = Divider value of 2

1 0 = Divider value of 3

1 1 = Divider value of 4

Bits 1:0

ITMRCLK Select

0 0 = Internal 24 MHz Oscillator

0 1 = Reserved

1 0 = Internal 32 kHz Low power Oscillator. However this configuration is not used in sleep mode.

1 1 = TCAPCLK

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CYRF69213

Interval Timer Clock (ITMRCLK)

PITIMER_Divider. The PITIMER_Source is the clock to the timer

and the PITMER_Divider is the value the clock is divided by.

The Interval Timer Clock (ITMRCLK) can be sourced from the

Internal 24 MHz oscillator, the internal 32 kHz low power

oscillator except when in sleep mode, or the timer capture clock.

A programmable prescaler of 1, 2, 3, or 4 then divides the

selected source. The 12-bit Programmable Interval Timer is a

simple down counter with a programmable reload value. It

provides a 1 s resolution by default. When the down counter

reaches zero, the next clock is spent reloading. The reload value

can be read and written while the counter is running, but care

should be taken to ensure that the counter does not

unintentionally reload while the 12-bit reload value is only

partially stored — for example, between the two writes of the

12-bit value. The programmable interval timer generates an

interrupt to the CPU on each reload.

The interval register (PITMR) holds the value that is loaded into

the PIT counter on terminal count. The PIT counter is a down

counter.

The Programmable Interval Timer resolution is configurable. For

example:

TCAPCLK divide by x of CPU clock (for example TCAPCLK

divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz)

ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK

divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 s)

Timer Capture Clock (TCAPCLK)

The Timer Capture clock can be sourced from the internal

24 MHz oscillator or the Internal 332 kHz low power oscillator

except when in sleep mode. A programmable prescaler of 2, 4,

6, or 8 then divides the selected source.

The parameters to be set appears on the device editor view of

PSoC Designer after you place the CYRF69213 Timer User

Module. The parameters are PITIMER_Source and

Figure 9. Programmable Interval Timer Block Diagram

C onfiguration

12-bit

reload

value

System

Status and

C lock

C ontrol

12-bit

reload

counter

12-bit dow n

counter

Interrupt

C ontroller

C lock

Tim er

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CYRF69213

Figure 10. Timer Capture Block Diagram

System Clock

Configuration Status

and Control

Captimer Clock

16-bit counter

Prescale Mux

Capture Registers

1ms

timer

Overflow

Interrupt

Capture0 Int

Capture1 Int

Interrupt Controller

Table 41. Clock I/O Config (CLKIOCR) [0x32] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

CLKOUT Select

R/W

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

R/W

0

Bits 7:2 Reserved

Bits 1:0

CLKOUT Select

0 0 = Internal 24 MHz Oscillator

0 1 = Reserved

1 0 = Internal 32 kHz Low power Oscillator.However this configuration is not used in sleep mode.

1 1 = CPUCLK

initiated, all registers are restored to their default states and all

interrupts are disabled.

CPU Clock During Sleep Mode

When the CPU enters sleep mode the CPUCLK Select (Bit [0],

Table 37) is forced to the internal oscillator, and the oscillator is

stopped. When the CPU comes out of sleep mode it is running

on the internal oscillator. The internal oscillator recovery time is

three clock cycles of the Internal 32 kHz Low power Oscillator.

The occurrence of a reset is recorded in the System Status and

Control Register (CPU_SCR). Bits within this register record the

occurrence of POR and WDR Reset respectively. The firmware

can interrogate these bits to determine the cause of a reset.

The microcontroller resumes execution from Flash address

0x0000 after a reset. The internal clocking mode is active after a

reset.

Reset

The microcontroller supports two types of resets: Power on

Reset (POR) and Watchdog Reset (WDR). When reset is

Note The CPU clock defaults to 3 MHz (Internal 24 MHz

Oscillator divide-by-8 mode) at POR to guarantee operation at

the low V that might be present during the supply ramp.

CC

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CYRF69213

Table 42. System Status and Control Register (CPU_SCR) [0xFF] [R/W]

Bit #

7

GIES

R

6

5

4

3

Sleep

R/W

0

2

1

0

Field

Reserved

WDRS

PORS

Reserved

Stop

R/W

0

[3]

Read/Write

Default

–

0

R/C

–

0

–

0

1

The bits of the CPU_SCR register are used to convey status and control of events for various functions of an CYRF69213 device

Bit 7 GIES

The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which was

used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When this

bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor services

interrupts

0 = Global interrupts disabled

1 = Global interrupt enabled

Bit 6

Bit 5

Reserved

WDRS

The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of

reset that has occurred. The user can clear but not set this bit

0 = No WDR

1 = A WDR event has occurred

Bit 4

PORS

The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of

reset that has occurred. The user can clear but not set this bit

0 = No POR

1 = A POR event has occurred. (Note that WDR events does not occur until this bit is cleared)

Bit 3

SLEEP

Set by the user to enable CPU sleep state. CPU remains in sleep mode until any interrupt is pending. The Sleep bit is covered

in more detail in the Sleep Mode section

0 = Normal operation

1 = Sleep

Bit 2:1

Reserved

STOP

Bit 0

This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset) has taken place.

If an application wants to stop code execution until a reset, the preferred method would be to use the HALT instruction rather than

writing to this bit

0 = Normal CPU operation

1 = CPU is halted (not recommended)

Note

3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware

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CYRF69213

WDT cannot be disabled. The only exception to this is if a POR

event takes place, which disables the WDT.

Power on Reset

POR occurs every time the power to the device is switched on.

POR is released when the supply is typically 2.6 V for the upward

supply transition, with typically 50 mV of hysteresis during the

power on transient. Bit 4 of the System Status and Control

Register (CPU_SCR) is set to record this event (the register

contents are set to 00010000 by the POR). After a POR, the

The sleep timer is used to generate the sleep time period and the

Watchdog time period. The sleep timer is clocked by the Internal

32 kHz Low power Oscillator system clock. The user can

program the sleep time period using the Sleep Timer bits of the

OSC_CR0 Register (Table 38 on page 29). When the sleep time

elapses (sleep timer overflows), an interrupt to the Sleep Timer

Interrupt Vector is generated.

microprocessor is held off for approximately 20 ms for the V

CC

supply to stabilize before executing the first instruction at

The Watchdog Timer period is automatically set to be three

counts of the Sleep Timer overflows. This represents between

two and three sleep intervals depending on the count in the

Sleep Timer at the previous WDT clear. When this timer reaches

three, a WDR is generated.

address 0x00 in the Flash. If the V voltage drops below the

CC

POR downward supply trip point, POR is reasserted. The V

supply needs to ramp linearly from 0 to 4 V in 0 to 200 ms.

CC

Important The PORS status bit is set at POR and can only be

cleared by the user. It cannot be set by firmware.

The user can either clear the WDT, or the WDT and the Sleep

Timer. Whenever the user writes to the Reset WDT Register

(RES_WDT), the WDT is cleared. If the data that is written is the

hex value 0x38, the Sleep Timer is also cleared at the same time.

Watchdog Timer Reset

The user has the option to enable the WDT. The WDT is enabled

by clearing the PORS bit. When the PORS bit is cleared, the

Table 43. Reset Watchdog Timer (RESWDT) [0xE3] [W]

Bit #

7

6

5

4

3

2

1

0

Field

Reset Watchdog Timer [7:0]

Read/Write

Default

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

Any write to this register clears Watchdog Timer, a write of 0x38 also clears the Sleep Timer

Bits 7:0 Reset Watchdog Timer [7:0]

Internal 32 kHz Low power Oscillator. The Internal 24 MHz

Oscillator restarts immediately on exiting Sleep mode.

Sleep Mode

The CPU can only be put to sleep by the firmware. This is accom-

plished by setting the Sleep bit in the System Status and Control

Register (CPU_SCR). This stops the CPU from executing

instructions, and the CPU remains asleep until an interrupt

comes pending, or there is a reset event (either a Power on

Reset, or a Watchdog Timer Reset).

On exiting sleep mode, when the clock is stable and the delay

time has expired, the instruction immediately following the sleep

instruction is executed before the interrupt service routine (if

enabled).

The Sleep interrupt allows the microcontroller to wake up

periodically and poll system components while maintaining very

low average power consumption. The Sleep interrupt may also

be used to provide periodic interrupts during non sleep modes.

The Low voltage Detection circuit (LVD) drops into fully functional

power reduced states, and the latency for the LVD is increased.

The actual latency can be traded against power consumption by

changing the Sleep Duty Cycle field of the ECO_TR Register.

Sleep Sequence

The Internal 32 kHz Low speed Oscillator remains running. Prior

to entering suspend mode, firmware can optionally configure the

32 kHz Low speed Oscillator to operate in a low power mode to

help reduce the overall power consumption (using Bit 7, Table 36

on page 27). This helps save approximately 5 A; however, the

trade off is that the 32 kHz Low speed Oscillator is less accurate.

The SLEEP bit is an input into the sleep logic circuit. This circuit

is designed to sequence the device into and out of the hardware

sleep state. The hardware sequence to put the device to sleep

is shown in Figure 11 and is defined as follows.

1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The

Bus Request (BRQ) signal to the CPU is immediately

asserted. This is a request by the system to halt CPU

operation at an instruction boundary. The CPU samples BRQ

on the positive edge of CPUCLK.

All interrupts remain active. Only the occurrence of an interrupt

wakes the part from sleep. The Stop bit in the System Status and

Control Register (CPU_SCR) must be cleared for a part to

resume out of sleep. The Global Interrupt Enable bit of the CPU

Flags Register (CPU_F) does not have any effect. Any

unmasked interrupt wakes the system up. As a result, any

interrupts not intended for waking must be disabled through the

Interrupt Mask Registers.

2. Due to the specific timing of the register write, the CPU issues

a Bus Request Acknowledge (BRA) on the following positive

edge of the CPU clock. The sleep logic waits for the following

negative edge of the CPU clock and then asserts a

system-wide Power Down (PD) signal. In Figure 11 the CPU

is halted and the system-wide power down signal is asserted.

When the CPU exits sleep mode the CPUCLK Select (Bit 1,

Table 37 on page 28) is forced to the Internal Oscillator. The

internal oscillator recovery time is three clock cycles of the

3. The system-wide PD (power down) signal controls several

major circuit blocks: The Flash memory module, the internal

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CYRF69213

24 MHz oscillator, the EFTB filter and the bandgap voltage

reference. These circuits transition into a zero power state.

The only operational circuits on chip are the Low Power

oscillator, the bandgap refresh circuit, and the supply voltage

monitor (POR/LVD) circuit.

Note To achieve the lowest possible power consumption during

suspend/sleep, the following conditions must be observed in

addition to considerations for the sleep timer.

■ All GPIOs must be set to outputs and driven low

■ The USB pins P1.0 and P1.1 should be configured as inputs

with their pull ups enabled.

Figure 11. Sleep Timing

On the falling edge of

CPUCLK, PD is asserted.

The 24/48 MHz system clock

is halted; the Flash and

CPU

responds

with a BRA

Firmware write to SCR

SLEEP bit causes an

immediate BRQ

CPU captures

BRQ on next

CPUCLK edge

bandgap are powered down

CPUCLK

IOW

SLEEP

BRQ

BRA

PD

4. At the following negative edge of the 32 kHz clock (after about

15 µs nominal), the BRQ signal is negated by the sleep logic

circuit. On the following CPUCLK, BRA is negated by the CPU

and instruction execution resumes. Note that in Figure 12 on

page 36 fixed function blocks, such as Flash, internal

oscillator, EFTB, and bandgap, have about 15 µs start up. The

wakeup times (interrupt to CPU operational) ranges from 75

µs to 105 µs.

Wakeup Sequence

When asleep, the only event that can wake the system up is an

interrupt. The global interrupt enable of the CPU flag register

does not need to be set. Any unmasked interrupt wakes the

system up. It is optional for the CPU to actually take the interrupt

after the wakeup sequence. The wakeup sequence is

synchronized to the 32 kHz clock for purposes of sequencing a

startup delay, to allow the Flash memory module enough time to

power up before the CPU asserts the first read access. Another

reason for the delay is to allow the oscillator, Bandgap, and

LVD/POR circuits time to settle before actually being used in the

system. As shown in Figure 12 on page 36, the wakeup

sequence is as follows:

Low Power in Sleep Mode

The following steps are mandatory before configuring the system

into suspend mode to meet the specifications:

1. Clear P11CR[0], P10CR[0] - during USB and Non-USB

operations

1. The wakeup interrupt occurs and is synchronized by the

negative edge of the 32 kHz clock.

2. Clear the USB Enable USBCR[7] - during USB mode

operations

2. At the following positive edge of the 32 kHz clock, the

system-wide PD signal is negated. The Flash memory

module, internal oscillator, EFTB, and bandgap circuit are all

powered up to a normal operating state.

3. Set P10CR[1] - during non-USB mode operations

4. To avoid current consumption make sure ITMRCLK,

TCPCLK, and USBCLK are not sourced by either low power

32KHz oscillator or 24 MHz crystal-less oscillator.

3. At the following positive edge of the 32 kHz clock, the current

values for the precision POR and LVD have settled and are

sampled.

All the other blocks go to the power down mode automatically on

suspend.

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CYRF69213

The following steps are user configurable and help in reducing the average suspend mode power consumption.

1. Configure the power supply monitor at a large regular intervals, control register bits are 1,EB[7:6] (Power system sleep duty cycle

PSSDC[1:0]).

2. Configure the Low power oscillator into low power mode, control register bit is LOPSCTR[7].

Figure 12. Wakeup Timing

CPU is restarted

after 90 ms

Interrupt is double sampled

by 32K clock and PD is

negated to system

Sleep Timer or GPIO

interrupt occurs

(nominal)

CLK32K

INT

SLEEP

PD

BANDGAP

LVD PPOR

ENABLE

SAMPLE

LVD/POR

CPUCLK/

(Not to Scale)

24MHz

BRQ

BRA

CPU

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CYRF69213

Low Voltage Detect Control

Table 44. Low voltage Control Register (LVDCR) [0x1E3] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

PORLEV[1:0]

Reserved

VM[2:0]

R/W

0

Read/Write

Default

–

0

–

0

R/W

0

R/W

0

–

0

R/W

0

R/W

0

This register controls the configuration of the Power on Reset/Low voltage Detection block

Bits 7:6

Reserved

Bits 5:4

PORLEV[1:0]

This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset

0 0 = 2.7 V Range (trip near 2.6 V)

0 1 = 3 V Range (trip near 2.9 V)

1 0 = 5 V Range, >4.75 V (trip near 4.65 V). This setting must be used when operating the CPU above 12 MHz.

1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 45) give the in-

ternal PPOR comparator state with trip point set to the 3 V range setting

Bit 3

Bits 2:0

Reserved

VM[2:0]

This field controls the level below which the low voltage-detect trips — possibly generating an interrupt and the level at which

the Flash is enabled for operation.

LVD Trip Point (V)

VM[2:0]

000

Min.

Reserved

4.439

Typical

Reserved

4.48

Max.

Reserved

4.528

001

010

011

100

101

4.597

4.64

4.689

110

4.680

4.73

4.774

111

4.766

4.82

4.862

POR Compare State

Table 45. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]

Bit #

7

6

5

4

3

2

1

LVD

R

0

PPOR

R

Field

Reserved

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

This read-only register allows reading the current state of the Low voltage-Detection and Precision-Power-On-Reset comparators

Bits 7:2

Reserved

Bit 1

LVD

This bit is set to indicate that the low voltage-detect comparator has tripped, indicating that the supply voltage has gone below

the trip point set by VM[2:0] (See Table 44)

0 = No low voltage-detect event

1 = A low voltage-detect has tripped

Bit 0

PPOR

This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below

the trip point set by PORLEV[1:0]

0 = No precision-power-on-reset event

1 = A precision-power-on-reset event has tripped

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CYRF69213

ECO Trim Register

Table 46. ECO (ECO_TR) [0x1EB] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Sleep Duty Cycle [1:0]

Reserved

Read/Write

Default

R/W

0

R/W

0

–

0

–

0

–

0

–

0

–

0

–

0

This register controls the ratios (in numbers of 32 kHz clock periods) of ‘on’ time versus ‘off’ time for LVD and POR detection circuit

Bits 7:6 Sleep Duty Cycle [1:0]

0 0 = 1/128 periods of the Internal 32 kHz Low speed Oscillator

0 1 = 1/512 periods of the Internal 32 kHz Low speed Oscillator

1 0 = 1/32 periods of the Internal 32 kHz Low speed Oscillator

1 1 = 1/8 periods of the Internal 32 kHz Low speed Oscillator

General-Purpose I/O Ports

The general purpose I/O ports are discussed in the following sections.

Port Data Registers

Table 47. P0 Data Register (P0DATA)[0x00] [R/W]

Bit #

7

6

Reserved

R/W

5

Reserved

R/W

4

P0.4/INT2

R/W

3

P0.3/INT1

R/W

2

Reserved

R/W

1

0

Reserved

R/W

Field

P0.7

R/W

0

P0.1

R/W

0

Read/Write

Default

0

This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 0 pins

Bit 7

P0.7 Data

Bits 6:5

Reserved

The use of the pins as the P0.6–P0.5 GPIOs and the alternative functions exist in the CYRF69213

Bits 4:3

P0.4–P0.3 Data/INT2 – INT1

In addition to their use as the P0.4–P0.3 GPIOs, these pins can also be used for the alternative functions as the Interrupt pins

(INT0–INT2). To configure the P0.4–P0.3 pins, refer to the P0.3/INT1–P0.4/INT2 Configuration Register (Table 51)

The use of the pins as the P0.4–P0.3 GPIOs and the alternative functions exist in the CYRF69213

Bit 2

Reserved

P0.1

Bit 1

Bit 0

Reserved

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Table 48. P1 Data Register (P1DATA) [0x01] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

P1.7

R/W

0

P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG

P1.1/D–

R/W

0

P1.0/D+

R/W

0

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 1 pins

Bit 7

P1.7 Data

Bits 6:3

P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)

In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI interface

pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 56 on page 43)

The use of the pins as the P1.6–P1.3 GPIOs and the alternative functions exist in all the CYRF69213 parts

Bit 2

P1.2/VREG

This pin is used as the regulator output. The 3.3 V VREG output must be enabled by setting Bit 0 of VREGCR register (Table

80 on page 56). A 1 mF min, 2 mF max capacitor is required on VREG output.

Bits 1:0

P1.1–P1.0/D– and D+

When USB mode is disabled (Bit 7 in Table 81 on page 57 is clear), the P1.1 and P1.0 bits are used to control the state of the

P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins, respectively. If

the USB Force State bit (Bit 0 in Table 79 on page 56) is set, the state of the D– and D+ pins can be controlled by writing to the

D– and D+ bits

Table 49. P2 Data Register (P2DATA) [0x02] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

P2.1–P2.0

Read/Write

Default

–

0

–

0

–

0

–

0

–

0

–

0

R/W

0

R/W

0

This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading

from this register returns the current state of the Port 2 pins

Bits 7:2

Reserved Data [7:2]

Bits 1:0

P2 Data [1:0]

Int Act Low

GPIO Port Configuration

When set, the corresponding interrupt is active on the falling

edge.

All the GPIO configuration registers have common configuration

controls. The following are the bit definitions of the GPIO

configuration registers.

When clear, the corresponding interrupt is active on the rising

edge.

Int Enable

TTL Thresh

When set, the Int Enable bit allows the GPIO to generate

interrupts. Interrupt generate can occur regardless of whether

the pin is configured for input or output. All interrupts are edge

sensitive, however for any interrupt that is shared by multiple

sources (that is, Ports 2, 3, and 4) all inputs must be deasserted

before a new interrupt can occur.

When set, the input has TTL threshold. When clear, the input has

standard CMOS threshold.

High Sink

When set, the output can sink up to 50 mA.

When clear, the output can sink up to 8 mA.

When clear, the corresponding interrupt is disabled on the pin.

It is possible to configure GPIOs as outputs, enable the interrupt

on the pin and then to generate the interrupt by driving the

appropriate pin state. This is useful in test and may have value

in applications as well.

On the CYRF69213, only the P1.7–P1.3 have 50 mA sink drive

capability. Other pins have 8 mA sink drive capability.

Open Drain

When set, the output on the pin is determined by the Port Data

Register. If the corresponding bit in the Port Data Register is set,

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CYRF69213

the pin is in high impedance state. If the corresponding bit in the

Port Data Register is clear, the pin is driven low.

VREG Output/SPI Use

The P1.2 (VREG), P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI)

and P1.6 (SMISO) pins can be used for their dedicated functions

or for GPIO.

When clear, the output is driven LOW or HIGH.

Pull up Enable

To enable the pin for GPIO, clear the corresponding VREG

Output or SPI Use bit. The SPI function controls the output

enable for its dedicated function pins when their GPIO enable bit

is clear.

When set the pin has a 7K pull up to V (or VREG for ports with

CC

V3.3 enabled).

When clear, the pull up is disabled.

3.3 V Drive

Output Enable

The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6

(SMISO) pins have an alternate voltage source from the voltage

regulator. If the 3.3 V Drive bit is set a high level is driven from

When set, the output driver of the pin is enabled.

When clear, the output driver of the pin is disabled.

For pins with shared functions there are some special cases.

the voltage regulator instead of from V

.

CC

Setting the 3.3 V Drive bit does not enable the voltage regulator.

That must be done explicitly by setting the VREG Enable bit in

the VREGCR Register (Table 80 on page 56).

Figure 13. Block Diagram of a GPIO

V_CC

VREG

3.3V Drive

Pull-Up Enable

Output Enable

V_CC

VREG

R_UP

Data Out

Open Drain

Port Data

GPIO

High Sink

V_CCGND

VREG GND

Data In

TTL Threshold

Table 50. P0.1 Configuration (P01CR) [0x06] R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low TTL Thresh

High Sink

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This register is used to configure P0.1 In the CYRF69213, only 8 mA sink drive capability is available on this pin regardless of the

setting of the High Sink bit

Bit 7: Reserved

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Table 51. P0.3/INT1–P0.4/INT2 Configuration (P03CR–P04CR) [0x08–0x09] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Act Low TTL Thresh

Reserved

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

–

0

–

0

R/W

0

R/W

0

–

0

R/W

0

R/W

0

R/W

0

These registers control the operation of pins P0.3–P0.4, respectively. These pins are shared between the P0.3–P0.4 GPIOs and

the INT0–INT2. These registers exist in all CYRF69213 parts. The INT0–INT2 interrupts are different than all the other GPIO

interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent

interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set.

These pins are enabled as interrupt sources in the interrupt controller registers (Table 77 and Table 75)

To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2 pins

are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the P0.3

and P0.4 data bits in the P0 Data Register

Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and Pull

up Enable bits control the behavior of the pin

The P0.3/INT1–P0.4/INT2 pins are individually configured with the P03CR (0x08), and P04CR (0x09), respectively.

Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these interrupt

sources, it is best to follow the following procedure:

1. Disable interrupt source

2. Configure interrupt source

3. Clear any pending interrupts from the source

4. Enable interrupt source

Table 52. P0.7 Configuration (P07CR) [0x0C] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low TTL Thresh

Reserved

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

–

0

R/W

0

R/W

0

R/W

0

–

0

R/W

0

R/W

0

R/W

0

This register controls the operation of pin P0.7.

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Table 53. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low

Reserved

5K pull up

enable

Output

Enable

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

–

0

–

0

–

0

–

0

R/W

0

This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as a

GPIO pin which is pulled up. See Table 81 for information on enabling USB. When USB is enabled, none of the controls in this

register have any effect on the P1.0 pin

Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high

Bit 1

5K Pull up Enable

0 = Disable the 5 Kohm pull up resistors

1 = Enable 5 Kohm pull up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as pulled up

GPIOs

Bit 0This bit enables the output on P1.0/D+. This bit should be cleared in sleep mode.

Table 54. P1.1/D– Configuration (P11CR) [0x0E] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low

Reserved

Open Drain

Reserved

Output

Enable

Field

Read/Write

Default

–

0

R/W

0

R/W

0

–

0

–

0

R/W

0

–

0

R/W

0

This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as a

GPIO. See Table 81 for information on enabling USB. When USB is enabled, none of the controls in this register have any effect

on the P1.1 pin. When USB is disabled, the 5 Kohm pull up resistor on this pin can be enabled by the 5K Pull up Enable bit of the

P10CR Register (Table 53)

Bit 0This bit enables the output on P1.1/D-. This bit should be cleared in sleep mode.

Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at V

OL3

Table 55. P1.2 Configuration (P12CR) [0x0F] [R/W]

Bit #

7

6

5

4

3

2

1

0

CLK Output

Int Enable

Int Act Low

TTL

Threshold

Reserved

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

–

0

R/W

0

R/W

0

R/W

0

This register controls the operation of the P1.2

Bit 7 CLK Output

0 = The internally selected clock is not sent out onto P1.2 pin

1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin

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Table 56. P1.3 Configuration (P13CR) [0x10] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low 3.3 V Drive

High Sink

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

–

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This register controls the operation of the P1.3 pin. This register exists in all CYRF69213 parts

The P1.3 GPIO’s threshold is always set to TTL

When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry. When the SPI

hardware is disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register

Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain, and

Pull up Enable control the behavior of the pin

The 50 mA sink drive capability is only available in the CY7C638xx.

Table 57. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]

Bit #

7

6

5

4

3

2

1

0

SPI Use

Int Enable

Int Act Low 3.3 V Drive

High Sink

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

These registers control the operation of pins P1.4–P1.6, respectively

The P1.4–P1.6 GPIO’s threshold is always set to TTL

When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the

SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit and

the corresponding bit in the P1 data register

Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain, and

Pull up Enable control the behavior of the pin

Bit 7

SPI Use

0 = Disable the SPI alternate function. The pin is used as a GPIO

1 = Enable the SPI function. The SPI circuitry controls the output of the pin

Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 61)

When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins

P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it

must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4

must be configured as an input

Table 58. P1.7 Configuration (P17CR) [0x14] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low TTL Thresh

High Sink

Open Drain

Pull up

Enable

Output

Enable

Field

Read/Write

Default

–

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This register controls the operation of pin P1.7. This register only exists in CY7C638xx

The 50 mA sink drive capability is only available in the CY7C638xx. The P1.7 GPIO’s threshold is always set to TTL

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CYRF69213

Table 59. P2 Configuration (P2CR) [0x15] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Int Enable

Int Act Low TTL Thresh

High Sink

Open Drain Pull up En-

able

Output En-

able

Field

Read/Write

Default

–

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This register only exists in CY7C638xx. This register controls the operation of pins P2.0–P2.1. In the CY7C638xx, only 8 mA sink

drive capability is available on this pin regardless of the setting of the High Sink bit

GPIO Configurations for Low Power Mode:

To ensure low power mode, unbonded GPIO pins in CYRF69213 must be placed in a non floating state. The following assembly code

snippet shows how this is achieved. This snippet can be added as a part of the initialization routine.

//Code Snippet for addressing unbonded GPIOs

mov A, 00h

mov reg[1Fh],A

mov A, 01h

mov reg[16h],A // Port3 Configuration register - Enable ouptut

mov A, 00h

mov reg[03h],A // Asserting P3.0 and P3.1 outputs to '0'

mov A, 01h

mov reg[05h],A // Port0.0 Configuration register - Enable output

mov reg[07h],A // Port0.2 Configuration register - Enable output

mov reg[0Ah],A // Port0.5 Configuration register - Enable output

mov reg[0Bh],A // Port0.6 Configuration register - Enable output

mov A,reg[00h]

mov A,00h

and A,9Ah

mov reg[00h], A // Asserting outputs '0' to pins in port 1

When writing to port 0 , to access GPIOs P0.1,3,4,7 , mask bits 0,2,5,6 .Failing to do so will void the low power.

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CYRF69213

Serial Peripheral Interface (SPI)

The SPI Master/Slave Interface core logic runs on the SPI clock domain, making its functionality independent of system clock speed.

SPI is a four pin serial interface comprised of a clock, an enable and two data pins.

Figure 14. SPI Block Diagram

Register Block

SCK Speed Sel

Master/Slave Sel

SCK Clock Generation

SCK Clock Select

SCK_OE

SCK Polarity

SCK Phase

SCK Clock Phase/Polarity

Select

SCK

LE_SEL

Little Endian Sel

GPIO Block

SS_N

SPI State Machine

SS_N_OE

MISO_OE

SS_N

Data (8 bit)

Load

Output Shift Buffer

Empty

MISO/MOSI

Crossbar

Master/Slave Set

MISO

SCK

Shift Buffer

LE_SEL

MOSI_OE

MOSI

Data (8 bit)

Input Shift Buffer

Load

Full

SCK_OE

SS_N_OE

MISO_OE

MOSI_OE

Sclk Output Enable

Slave Select Output Enable

Master IN, Slave Out OE

Master Out, Slave In, OE

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SPI Data Register

Table 60. SPI Data Register (SPIDATA) [0x3C] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

SPIData[7:0]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register

Bits 7:0 SPI Data [7:0]

When an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty,

firmware has 7 SPI clocks to manage the buffers — to empty the receiver buffer, or to refill the transmit holding register. Failure to

meet this timing requirement results in incorrect data transfer.

SPI Configure Register

Table 61. SPI Configure Register (SPICR) [0x3D] [R/W]

Bit #

7

Swap

R/W

0

6

LSB First

R/W

5

4

3

CPOL

R/W

0

2

CPHA

R/W

0

1

0

Field

Comm Mode

SCLK Select

Read/Write

Default

Bit 7

R/W

0

R/W

0

R/W

0

R/W

0

Swap

0 = Swap function disabled

1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single wire

SPI-like communications

Bit 6

LSB First

0 = The SPI transmits and receives the MSB (Most Significant Bit) first

1 = The SPI transmits and receives the LSB (Least Significant Bit) first.

Bits 5:4

Comm Mode [1:0]

0 0: All SPI communication disabled

0 1: SPI master mode

1 0: SPI slave mode

1 1: Reserved

Bit 3

CPOL

This bit controls the SPI clock (SCLK) idle polarity

0 = SCLK idles low

1 = SCLK idles high

Bit 2

CPHA

The Clock Phase bit controls the phase of the clock on which data is sampled. Table 62 on page 47 shows the timing for the

various combinations of LSB First, CPOL, and CPHA

Bits 1:0

SCLK Select

This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK

Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave):

When configured for SPI, (SPI Use = 1 — Table 57 on page 43), the input/output direction of pins P1.3, P1.5, and P1.6 is set

automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by

firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an

input

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Table 62. SPI Mode Timing vs. LSB First, CPOL and CPHA

LSB First CPHA

CPOL

Diagram

0

1

0

SCLK

SSEL

DAT A

X

MSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

LSB

X

1

0

SC LK

SSEL

D AT A

X

MS B

B it 7

B it 6

B it 5

B it 4

B it 3

B it 2

LS B

X

SCLK

SSEL

DAT A

X

MSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

LSB

X

0

1

SCLK

SSEL

DATA

X

MSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

LSB

X

1

0

1

SCLK

SSEL

DATA

X

LSB

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

MSB

X

SCLK

SSEL

DATA

X

LSB

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

MSB

X

1

0

1

SCLK

SSEL

DATA

X

LSB

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

MSB

X

SCLK

SSEL

DATA

X

LSB

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

MSB

X

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Registers

Table 63. SPI SCLK Frequency

Free-Running Counter

SCLK Frequency

SCLK

Select

CPUCLK

Divisor

The 16-bit free-running counter is clocked by a 4/6 MHz source.

It can be read in software for use as a general purpose time base.

When the low order byte is read, the high order byte is registered.

Reading the high order byte reads this register allowing the CPU

to read the 16-bit value atomically (loads all bits at one time). The

free-running timer generates an interrupt at a 1024 s rate. It can

also generate an interrupt when the free-running counter

overflow occurs — every 16.384 ms. This allows extending the

length of the timer in software.

CPUCLK = 12 MHz CPUCLK = 24 MHz

00

01

10

11

6

2 MHz

1 MHz

4 MHz

2 MHz

12

48

96

250 KHz

125 KHz

500 KHz

250 KHz

Timer Registers

All timer functions of the CYRF69213 are provided by a single

timer block. The timer block is asynchronous from the CPU clock.

Figure 15. 16-Bit Free-Running Counter Block Diagram

Overflow

Interrupt

Timer Capture

Clock

16-bit Free

Running Counter

1024-µs

Timer

Interrupt

Table 64. Free-Running Timer Low Order Byte (FRTMRL) [0x20] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Free-running Timer [7:0]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0Free-running Timer [7:0]

This register holds the low order byte of the 16-bit free-running timer. Reading this register causes the high order byte to be moved

into a holding register allowing an automatic read of all 16 bits simultaneously.

For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle

when the high order is written

When reading the free-running timer, the low order byte should be read first and the high order second. When writing, the low order

byte should be written first then the high order byte

Table 65. Free-Running Timer High Order Byte (FRTMRH) [0x21] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Free-running Timer [15:8]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0Free-running Timer [15:8]

When reading the free-running timer, the low order byte should be read first and the high order second. When writing, the low order

byte should be written first then the high order byte

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CYRF69213

Table 66. Programmable Interval Timer Low (PITMRL) [0x26] [R]

Bit #

7

6

5

4

3

2

1

0

Field

Prog Interval Timer [7:0]

Read/Write

Default

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Bits 7:0 ‘Prog Interval Timer [7:0]

This register holds the low order byte of the 12-bit programmable interval timer. Reading this register causes the high order byte to

be moved into a holding register allowing an automatic read of all 12 bits simultaneously

Table 67. Programmable Interval Timer High (PITMRH) [0x27] [R]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

Prog Interval Timer [11:8]

Read/Write

Default

Bits 7:4

Bits 3:0

–

0

–

0

–

0

–

0

R

0

R

0

R

0

R

0

Reserved

Prog Internal Timer [11:8]

This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order nibble

of the 12-bit timer at the instant that the low order byte was last read

Table 68. Programmable Interval Reload Low (PIRL) [0x28] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Prog Interval [7:0]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 Prog Interval [7:0]

This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble

Table 69. Programmable Interval Reload High (PIRH) [0x29] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

Prog Interval[11:8]

Read/Write

Default

Bits 7:4

Bits 3:0

–

0

–

0

–

0

–

0

R/W

0

R/W

0

R/W

0

R/W

0

Reserved

Prog Interval [11:8]

This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble

Document Number: 001-07552 Rev. *G

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CYRF69213

Figure 16. 16-Bit Free-Running Counter Loading Timing Diagram

clk_sys

write

valid

addr

write data

FRT reload

ready

Clk Timer

12b Prog Timer

12b reload

interrupt

12-bit programmable timer load timing

Capture timer

clk

16b free running

counter load

16b free

running counter

00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0

16-bit free running counter loading timing

Figure 17. Memory Mapped Registers Read/Write Timing Diagram

clk_sys

rd_wrn

Valid

Addr

rdata

wdata

Memory mapped registers Read/Write timing diagram

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CYRF69213

Table 70. Interrupt Numbers, Priorities, Vectors (continued)

Interrupt Controller

The interrupt controller and its associated registers allow the

user’s code to respond to an interrupt from almost every

functional block in the CYRF69213 devices. The registers

associated with the interrupt controller allow interrupts to be

disabled either globally or individually. The registers also provide

a mechanism by which a user may clear all pending and posted

interrupts, or clear individual posted or pending interrupts.

Interrupt Interrupt

Name

Priority

17

Address

0044h

0048h

004Ch

0050h

0054h

0058h

005Ch

0060h

0064h

16-bit Free Running Timer Wrap

INT2

18

19

Reserved

20

GPIO Port 2

Reserved

The following table lists all interrupts and the priorities that are

available in the CYRF69213.

21

22

Reserved

Table 70. Interrupt Numbers, Priorities, Vectors

23

Reserved

Interrupt Interrupt

Name

24

Reserved

Priority

Address

0000h

0004h

0008h

000Ch

0010h

0014h

0018h

001Ch

0020h

0024h

0028h

002Ch

0030h

0034h

0038h

003Ch

0040h

25

Sleep Timer

0

1

Reset

POR/LVD

Architectural Description

2

INT0

An interrupt is posted when its interrupt conditions occur. This

results in the flip-flop in Figure 18 clocking in a ‘1’. The interrupt

remains posted until the interrupt is taken or until it is cleared by

writing to the appropriate INT_CLRx register.

3

SPI Transmitter Empty

SPI Receiver Full

GPIO Port 0

GPIO Port 1

INT1

4

5

A posted interrupt is not pending unless it is enabled by setting

its interrupt mask bit (in the appropriate INT_MSKx register). All

pending interrupts are processed by the Priority Encoder to

determine the highest priority interrupt which is taken by the M8C

if the Global Interrupt Enable bit is set in the CPU_F register.

6

7

8

EP0

9

EP1

Disabling an interrupt by clearing its interrupt mask bit (in the

INT_MSKx register) does not clear a posted interrupt, nor does

it prevent an interrupt from being posted. It simply prevents a

posted interrupt from becoming pending.

10

11

12

13

14

15

16

EP2

USB Reset

USB Active

1 ms Interval timer

Programmable Interval Timer

Reserved

Nested interrupts can be accomplished by re-enabling interrupts

inside an interrupt service routine. To do this, set the IE bit in the

Flag Register.

A block diagram of the CYRF69213 Interrupt Controller is shown

in Figure 18.

Reserved

Figure 18. Interrupt Controller Block Diagram

Priority

Encoder

Interrupt Vector

InterruptTaken

or

INT_CLRxWrite

Posted

Interrupt

Pending

Interrupt

Request

M8C Core

R

1

D

Q

Interrupt

Source

(Timer,

CPU_F[0]

GIE

GPIO,etc.)

INT_MSKx

MaskBit Setting

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CYRF69213

■ The ISR executes. Note that interrupts are disabled because

GIE = 0. In the ISR, interrupts can be re-enabled if desired by

setting GIE = 1 (care must be taken to avoid stack overflow).

Interrupt Processing

The sequence of events that occur during interrupt processing is

as follows:

■ The ISR ends with a RETI instruction which restores the

Program Counter and Flag registers (CPU_PC and CPU_F).

The restored Flag register re-enables interrupts, because

GIE = 1 again.

■ An interrupt becomes active, either because:

a. The interrupt condition occurs (for example, a timer expires).

b. A previously posted interrupt is enabled through an update

of an interrupt mask register.

c. An interrupt is pending and GIE is set from 0 to 1 in the CPU

Flag register.

■ Execution resumes at the next instruction, after the one that

occurred before the interrupt. However, if there are more

pending interrupts, the subsequent interrupts are processed

before the next normal program instruction.

d. The GPIO interrupts are edge triggered.

■ The current executing instruction finishes.

Interrupt Latency

■ The internal interrupt is dispatched, taking 13 cycles. During

this time, the following actions occur:

a. The MSB and LSB of Program Counter and Flag registers

(CPU_PC and CPU_F) are stored onto the program stack

by an automatic CALL instruction (13 cycles) generated

during the interrupt acknowledge process.

The time between the assertion of an enabled interrupt and the

start of its ISR can be calculated from the following equation.

Latency = Time for current instruction to finish + Time for internal

interrupt routine to execute + Time for LJMP instruction in

interrupt table to execute.

For example, if the 5 cycle JMP instruction is executing when an

interrupt becomes active, the total number of CPU clock cycles

before the ISR begins would be as follows:

b. The PCH, PCL, and Flag register (CPU_F) are stored onto

the program stack (in that order) by an automatic CALL

instruction (13 cycles) generated during the interrupt

acknowledge process.

c. The CPU_F register is then cleared. Because this clears the

GIE bit to 0, additional interrupts are temporarily disabled

(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)

+ (7 cycles for LJMP) = 21 to 25 cycles.

In the example above, at 24 MHz, 25 clock cycles take 1.042 s.

d. The PCH (PC[15:8]) is cleared to zero.

Interrupt Registers

e. The interrupt vector is read from the interrupt controller and

its value placed into PCL (PC[7:0]). This sets the program

counter to point to the appropriate address in the interrupt

table (for example, 0004h for the POR/LVD interrupt).

The Interrupt Registers are discussed it the following sections.

Interrupt Clear Register

The Interrupt Clear Registers (INT_CLRx) are used to enable the

individual interrupt sources’ ability to clear posted interrupts.

■ Program execution vectors to the interrupt table. Typically, a

LJMP instruction in the interrupt table sends execution to the

user's Interrupt Service Routine (ISR) for this interrupt.

When an INT_CLRx register is read, any bits that are set

indicates an interrupt has been posted for that hardware

resource. Therefore, reading these registers gives the user the

ability to determine all posted interrupts.

Table 71. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]

Bit #

7

6

5

4

3

2

1

INT0

R/W

0

POR/LVD

R/W

Field

GPIO Port 1 Sleep Timer

INT1

R/W

0

GPIO Port 0 SPI Receive SPI Transmit

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When reading this register,

0 = There’s no posted interrupt for the corresponding hardware

1 = Posted interrupt for the corresponding hardware present

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT

(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt

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CYRF69213

Table 72. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved Prog Interval 1 ms Timer USB Active USB Reset

Timer

USB EP2

USB EP1

USB EP0

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When reading this register,

0 = There’s no posted interrupt for the corresponding hardware

1 = Posted interrupt for the corresponding hardware present

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT

(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt

Bit 7

Reserved

Table 73. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

GPIO Port 2

Reserved

INT2

16-bit

Counter

Wrap

Reserved

Field

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When reading this register,

0 = There’s no posted interrupt for the corresponding hardware

1 = Posted interrupt for the corresponding hardware present

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT

(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt

Bits 7,6,5,3,0Reserved

Interrupt Mask Registers

The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]

determines the way an individual bit value written to an

INT_CLRx register is interpreted. When is cleared, writing 1's to

an INT_CLRx register has no effect. However, writing 0's to an

INT_CLRx register, when ENSWINT is cleared, causes the

corresponding interrupt to clear. If the ENSWINT bit is set, any

0’s written to the INT_CLRx registers are ignored. However, 1’s

written to an INT_CLRx register, while ENSWINT is set, causes

an interrupt to post for the corresponding interrupt.

The Interrupt Mask Registers (INT_MSKx) are used to enable

the individual interrupt sources’ ability to create pending inter-

rupts.

There are four Interrupt Mask Registers (INT_MSK0,

INT_MSK1, INT_MSK2, and INT_MSK3), which may be referred

to in general as INT_MSKx. If cleared, each bit in an INT_MSKx

register prevents a posted interrupt from becoming a pending

interrupt (input to the priority encoder). However, an interrupt can

still post even if its mask bit is zero. All INT_MSKx bits are

independent of all other INT_MSKx bits.

Software interrupts can aid in debugging interrupt service

routines by eliminating the need to create system level

interactions that are sometimes necessary to create

a

If an INT_MSKx bit is set, the interrupt source associated with

that mask bit may generate an interrupt that becomes a pending

interrupt.

hardware-only interrupt.

Table 74. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]

Bit #

7

ENSWINT

R/W

6

5

4

3

2

1

0

Field

Reserved

Read/Write

Default

Bit 7

–

0

–

0

–

0

–

0

–

0

–

0

–

0

Enable Software Interrupt (ENSWINT)

0 = Disable. Writing 0’s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear

1 = Enable. Writing 1’s to an INT_CLRx register, when ENSWINT is set, causes the corresponding interrupt to post

Bits 6:0

Reserved

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CYRF69213

Table 75. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

GPIO Port 2

Int Enable

Reserved

INT2

Int Enable

16-bit

Reserved

Counter

Wrap Int

Enable

Field

Read/Write

Default

Bit 7

–

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Reserved

Bit 6

Reserved

Bit 5

Bit 4

GPIO Port 2 Interrupt Enable

0 = Mask GPIO Port 2 interrupt

1 = Unmask GPIO Port 2 interrupt

Bit 3

Reserved

Bit 2

INT2 Interrupt Enable

0 = Mask INT2 interrupt

1 = Unmask INT2 interrupt

Bit 1 16-bit Counter Wrap Interrupt Enable

0 = Mask 16-bit Counter Wrap interrupt

1 = Unmask 16-bit Counter Wrap interrupt

Bit 0

Reserved

Table 76. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved Prog Interval 1 ms Timer USB Active USB Reset

USB EP2

Int Enable

USB EP1

Int Enable

USB EP0

Int Enable

Timer

Int Enable

Field

Int Enable

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7

Bit 6

Reserved

Prog Interval Timer Interrupt Enable

0 = Mask Prog Interval Timer interrupt

1 = Unmask Prog Interval Timer interrupt

1 ms Timer Interrupt Enable

0 = Mask 1 ms interrupt

1 = Unmask 1 ms interrupt

USB Active Interrupt Enable

0 = Mask USB Active interrupt

1 = Unmask USB Active interrupt

USB Reset Interrupt Enable

0 = Mask USB Reset interrupt

1 = Unmask USB Reset interrupt

USB EP2 Interrupt Enable

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 = Mask EP2 interrupt

1 = Unmask EP2 interrupt

USB EP1 Interrupt Enable

0 = Mask EP1 interrupt

1 = Unmask EP1 interrupt

USB EP0 Interrupt Enable

0 = Mask EP0 interrupt

1 = Unmask EP0 interrupt

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CYRF69213

Table 77. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]

Bit #

7

6

5

4

3

2

1

0

GPIO Port 1 Sleep Timer

INT1

Int Enable

GPIO Port 0 SPI Receive SPI Transmit

INT0

Int Enable

POR/LVD

Int Enable

Field

Int Enable

Read/Write

Default

Bit 7

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIO Port 1 Interrupt Enable

0 = Mask GPIO Port 1 interrupt

1 = Unmask GPIO Port 1 interrupt

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sleep Timer Interrupt Enable

0 = Mask Sleep Timer interrupt

1 = Unmask Sleep Timer interrupt

INT1 Interrupt Enable

0 = Mask INT1 interrupt

1 = Unmask INT1 interrupt

GPIO Port 0 Interrupt Enable

0 = Mask GPIO Port 0 interrupt

1 = Unmask GPIO Port 0 interrupt

SPI Receive Interrupt Enable

0 = Mask SPI Receive interrupt

1 = Unmask SPI Receive interrupt

SPI Transmit Interrupt Enable

0 = Mask SPI Transmit interrupt

1 = Unmask SPI Transmit interrupt

INT0 Interrupt Enable

0 = Mask INT0 interrupt

1 = Unmask INT0 interrupt

POR/LVD Interrupt Enable

0 = Mask POR/LVD interrupt

1 = Unmask POR/LVD interrupt

Interrupt Vector Clear Register

Table 78. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Pending Interrupt [7:0]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and

when written clears all pending interrupts

Bits 7:0

Pending Interrupt [7:0]

8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register clears all pending in-

terrupts

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CYRF69213

USB Transceiver

USB Transceiver Configuration

Table 79. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]

Bit #

7

6

5

4

3

2

1

0

USB Pull up

Enable

Reserved

USB Force

State

Field

Read/Write

Default

Bit 7

R/W

–

0

–

0

–

0

–

0

–

0

–

0

R/W

0

USB Pull up Enable

0 = Disable the pull up resistor on D–

1 = Enable the pull up resistor on D–. This pull up is to V IF VREG is not enabled or to the internally generated 3.3 V when

CC

VREG is enabled. This bit should be cleared in sleep mode.

Bits 6:1

Bit 0

Reserved

USB Force State

This bit allows the state of the USB I/O pins DP and D+ to be forced to a state while USB is enabled

0 = Disable USB Force State

1 = Enable USB Force State. Allows the D– and D+ pins to be controlled by P1.1 and P1.0 respectively when the

USBIO is in USB mode. Refer to Table 48 for more information

Note The USB transceiver has a dedicated 3.3 V regulator for USB signalling purposes and to provide for the 1.5K D– pull up.

Unlike the other 3.3 V regulator, this regulator cannot be controlled/accessed by firmware. When the device is suspended, this

regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D– line is pulled up to

5 V through an alternate 6.5K resistor. During wakeup following a suspend, the band gap and the regulator are switched on in any

order. Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator and the

band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D– line. The host can misinterpret

this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry enabled during sleep.

This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only if the device is put to sleep during

a bus reset condition

VREG Control

Table 80. VREG Control Register (VREGCR) [0x73] [R/W]

Bit #

7

6

5

4

3

2

1

0

Reserved

Keep Alive

VREG

Enable

Field

Read/Write

Default

Bits 7:2

Bit 1

–

0

–

0

–

0

–

0

–

0

–

0

R/W

0

R/W

0

Reserved

Keep Alive

Keep Alive when set allows the voltage regulator to source up to 20 µA of current when voltage regulator is disabled,

P12CR[0],P12CR[7] should be cleared.

0 = Disabled

1 = Enabled

Bit 0

VREG Enable

This bit turns on the 3.3 V voltage regulator. The voltage regulator only functions within specifications when V is

CC

above 4.35 V. This block should not be enabled when V is below 4.35 V — although no damage or irregularities

CC

occurs if it is enabled below 4.35 V

0 = Disable the 3.3 V voltage regulator output on the VREG/P1.2 pin

1 = Enable the 3.3 V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled

Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide the

alternate voltage

Document Number: 001-07552 Rev. *G

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CYRF69213

■ Identifying token type (SETUP, IN, or OUT). Setting the appro-

priate token bit after a valid token is received

USB Serial Interface Engine (SIE)

The SIE allows the microcontroller to communicate with the USB

host at low speed data rates (1.5 Mbps). The SIE simplifies the

interface between the microcontroller and USB by incorporating

hardware that handles the following USB bus activity

independently of the microcontroller:

■ Placing valid received data in the appropriate endpoint FIFOs

■ Sending and updating the data toggle bit (Data1/0)

■ Bit stuffing/unstuffing.

Firmware is required to handle the rest of the USB interface with

the following tasks:

■ Translating the encoded received data and formatting the data

to be transmitted on the bus

■ Coordinate enumeration by decoding USB device requests

■ Fill and empty the FIFOs

■ CRC checking and generation. Flagging the microcontroller if

errors exist during transmission

■ Address checking. Ignoring the transactions not addressed to

the device

■ Suspend/Resume coordination

■ Verify and select Data toggle values

■ Sending appropriate ACK/NAK/STALL handshakes

USB Device

Table 81. USB Device Address (USBCR) [0x40] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

USB Enable

Device Address[6:0]

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The content of this register is cleared when a USB Bus Reset condition occurs

Bit 7

USB Enable

This bit must be enabled by firmware before the serial interface engine (SIE) responds to USB traffic at the address

specified in Device Address [6:0]. When this bit is cleared, the USB transceiver enters power down state. User’s firm-

ware should clear this bit prior to entering sleep mode to save power

0 = Disable USB device address and put the USB transceiver into power down state

1 = Enable USB device address and put the USB transceiver into normal operating mode

Device Address [6:0]

Bits 6:0

These bits must be set by firmware during the USB enumeration process (for example, SetAddress) to the non-zero

address assigned by the USB host

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CYRF69213

Table 82. Endpoint 0, 1, and 2 Count (EP0CNT–EP2CNT) [0x41, 0x43, 0x45] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Data Toggle Data Valid

Reserved

Byte Count[3:0]

R/W R/W

Read/Write

Default

Bit 7

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Data Toggle

This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the trans-

mitted Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Tog-

gle bit.

0 = DATA0

1 = DATA1

Bit 6

Data Valid

This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred.

This bit does not update for some endpoint mode settings

0 = Data is invalid. If enabled, the endpoint interrupt occurs even if invalid data is received

1 = Data is valid

Bits 5:4

Bits 3:0

Reserved

Byte Count Bit [3:0]

Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the

number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or

SETUP transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes.

Valid values are 2–10 inclusive.

For Endpoint 0 Count Register, whenever the count updates from a SETUP or OUT transaction, the count register locks and cannot

be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on it

Document Number: 001-07552 Rev. *G

Page 58 of 85

CYRF69213

Endpoint 0 Mode

Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking

mechanism to prevent accidental overwriting of data.

When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to

this register clears the upper four bits regardless of the value written.

Table 83. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]

Bit #

7

6

5

4

3

2

1

0

Setup

Received

IN Received

OUT

Received

ACK’d Trans

Mode[3:0]

Field

Read/Write

Default

Bit 7

R/C[3]

0

R/C[3]

0

R/C[3]

0

R/C[3]

0

R/W

0

R/W

0

R/W

0

R/W

0

SETUP Received

This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet

phase of the SETUP transactions until the end of the data phase of a control write transfer and cannot be cleared dur-

ing this interval. While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from over-

writing an incoming SETUP transaction before firmware has a chance to read the SETUP data

This bit is cleared by any non-locked writes to the register

0 = No SETUP received

1 = SETUP received

Bit 6

IN Received

This bit, when set, indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowl-

edges an IN data packet.When clear, it indicates that either no IN has been received or that the host didn’t acknowl-

edge the IN data by sending an ACK handshake

This bit is cleared by any non-locked writes to the register.

0 = No IN received

1 = IN received

Bit 5

OUT Received

This bit, when set, indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last

received packet in an OUT transaction. When clear, it indicates no OUT received

This bit is cleared by any non-locked writes to the register

0 = No OUT received

1 = OUT received

Bit 4

ACK’d Transaction

The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes

with a ACK packet

This bit is cleared by any non-locked writes to the register

1 = The transaction completes with an ACK

0 = The transaction does not complete with an ACK

Bits 3:0

Mode [3:0]

The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode

controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of

host packets to the endpoint

Document Number: 001-07552 Rev. *G

Page 59 of 85

CYRF69213

Table 84. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]

Bit #

7

6

5

4

3

2

1

0

Stall

Reserved

NAK Int

Enable

ACK’d

Transaction

Mode[3:0]

Field

Read/Write

Default

Bit 7

R/W

0

R/W

0

R/W

0

R/C (Note 3)

0

R/W

0

R/W

0

R/W

0

R/W

0

Stall

When this bit is set the SIE stalls an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE stalls an IN packet

if the mode bits are set to ACK-IN. This bit must be clear for all other modes

Bit 6

Bit 5

Reserved

NAK Int Enable

This bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike

enCoRe, CYRF69213 family members do not generate an endpoint interrupt under these conditions unless this bit is

set

0 = Disable interrupt on NAK’d transactions

1 = Enable interrupt on NAK’d transaction

Bit 4

ACK’d Transaction

The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes

with an ACK packet

This bit is cleared by any writes to the register

0 = The transaction does not complete with an ACK

1 = The transaction completes with an ACK

Bits 3:0

Mode [3:0]

The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode

controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of

host packets to the endpoint.

Note When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the EP1MODE

registers, respectively (if both writes occur in the same clock cycle). This is because the design employs only one common ‘update’

signal for both EP1MODE and EP2MODE registers. Thus, when SIE writes to the EP1MODE register, the update signal is set and

this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have higher priority than firmware

writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware must read the EP1/2MODE

registers immediately following a firmware write and rewrite if the value read is incorrect

Endpoint Data Buffers

The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values of

the Endpoint Data Registers are unknown. Unlike past enCoRe parts the USB data buffers are only accessible in the I/O space of the

processor.

Table 85. Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Endpoint 0 Data Buffer [7:0]

Read/Write

Default

R/W

Unknown

The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57

Document Number: 001-07552 Rev. *G

Page 60 of 85

CYRF69213

Table 86. Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Endpoint 1 Data Buffer [7:0]

Read/Write

Default

R/W

Unknown

The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F

Table 87. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]

Bit #

7

6

5

4

3

2

1

0

Field

Endpoint 2 Data Buffer [7:0]

Read/Write

Default

R/W

Unknown

The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67

Document Number: 001-07552 Rev. *G

Page 61 of 85

CYRF69213

USB Mode Tables

Mode

Encoding

SETUP

IN

OUT

Comments

DISABLE

0000

Ignore

Ignore all USB traffic to this endpoint. Used by Data and

Control endpoints

NAK IN/OUT

STATUS OUT ONLY

STALL IN/OUT

0001

0010

0011

0110

Accept

NAK

STALL

TX0 byte

NAK

NAK IN and OUT token. Control endpoint only

STALL IN and ACK zero byte OUT. Control endpoint only

STALL IN and OUT token. Control endpoint only

Check

STALL

STATUS IN ONLY

STALL OUT and send zero byte data for IN token. Control

endpoint only

ACK OUT –

STATUS IN

1011

1111

Accept

TX0 byte

TX Count

ACK

ACK the OUT token or send zero byte data for IN token.

Control endpoint only

ACK IN –

Check

Respond to IN data or Status OUT. Control endpoint only

STATUS OUT

NAK OUT

1000

1001

Ignore

NAK

ACK

Send NAK handshake to OUT token. Data endpoint only

ACK OUT (STALL =

0)

This mode is changed by the SIE to mode 1000 on issuance

of ACK handshake to an OUT. Data endpoint only

ACK OUT (STALL =

1)

1001

Ignore

STALL

STALL the OUT transfer

NAK IN

1100

1101

Ignore

NAK

Ignore

Send NAK handshake for IN token. Data endpoint only

ACK IN (STALL = 0)

TX Count

This mode is changed by the SIE to mode 1100 after

receiving ACK handshake to an IN data. Data endpoint only

ACK IN (STALL = 1)

1101

Ignore

STALL

Ignore

STALL the IN transfer. Data endpoint only

Reserved

0101

0111

1010

0100

1110

Ignore

These modes are not supported by SIE. Firmware should

not use this mode in Control and Data endpoints

Mode Column

SETUP, IN, and OUT Columns

The 'Mode' column contains the mnemonic names given to the

modes of the endpoint. The mode of the endpoint is determined

by the four-bit binaries in the 'Encoding' column as discussed in

the following section. The Status IN and Status OUT represent

the status IN or OUT stage of the control transfer.

Depending on the mode specified in the 'Encoding' column, the

'SETUP', 'IN', and 'OUT' columns contain the SIE's responses

when the endpoint receives SETUP, IN, and OUT tokens,

respectively.

A 'Check' in the Out column means that upon receiving an OUT

token the SIE checks to see whether the OUT is of zero length

and has a Data Toggle (Data1/0) of 1. If these conditions are true,

the SIE responds with an ACK. If any of the above conditions is

not met, the SIE responds with either a STALL or Ignore.

Encoding Column

The contents of the 'Encoding' column represent the Mode

Bits [3:0] of the Endpoint Mode Registers (Table 83 on page 59

and Table 84 on page 60). The endpoint modes determine how

the SIE responds to different tokens that the host sends to the

endpoints. For example, if the Mode Bits [3:0] of the Endpoint 0

Mode Register are set to '0001', which is NAK IN/OUT mode, the

SIE sends an ACK handshake in response to SETUP tokens and

NAK any IN or OUT tokens.

A 'TX Count' entry in the IN column means that the SIE transmits

the number of bytes specified in the Byte Count Bit [3:0] of the

Endpoint Count Register (Table 82 on page 58) in response to

any IN token.

Document Number: 001-07552 Rev. *G

Page 62 of 85

CYRF69213

Details of Mode for Differing Traffic Conditions

SIE

Bus Event

SIE

EP0 Mode Register EP0 Count Register

EP0 Interrupt Comments

Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO

Control Endpoint

DISABLED

0000

STALL_IN_OUT

0011 SETUP > 10

x

Ignore All

x

junk

Ignore

0011 SETUP < 10 invalid

Ignore

0011 SETUP < 10

valid

ACK

1

0001 update

1

update data

Yes

ACK SETUP

Stall IN

0011

IN

x

STALL

0011 OUT

NAK_IN_OUT

> 10

Ignore

< 10 invalid

Ignore

< 10

valid

STALL

Stall OUT

0001 SETUP > 10

x

junk

Ignore

0001 SETUP < 10 invalid

Ignore

0001 SETUP < 10

valid

ACK

NAK

1

0001 update

update data

Yes

ACK SETUP

NAK IN

Ignore

0001

IN

x

0001 OUT

>10

< 10 invalid

Ignore

< 10

valid

NAK

NAK OUT

ACK_IN_STATUS_OUT

1111 SETUP > 10

x

junk

Ignore

1111 SETUP < 10 invalid

Ignore

1111 SETUP < 10

valid

x

ACK

TX

1

0001 update

0001

update data

Yes

ACK SETUP

1111

IN

x

Host Not

ACK'd

1111

IN

x

TX

1

Host ACK'd

Ignore

OUT

> 10

< 10 invalid

Ignore

< 10, valid

<>2

STALL

0011

Yes

Bad Status

1111

OUT

2

valid

0

1

STALL

ACK

Yes

Bad Status

1 1 0010

1

2

Good Status

STATUS_OUT

0010 SETUP >10

x

junk

Ignore

0010 SETUP < 10 invalid

Ignore

0010 SETUP < 10

valid

ACK

1

0001 update

0011

update data

Yes

ACK SETUP

Stall IN

0010

IN

x

STALL

0010 OUT

>10

Ignore

< 10 invalid

Ignore

< 10, valid

<>2

STALL

0011

Yes

Bad Status

Document Number: 001-07552 Rev. *G

Page 63 of 85

CYRF69213

Details of Mode for Differing Traffic Conditions (continued)

SIE

Bus Event

SIE

EP0 Mode Register EP0 Count Register

EP0 Interrupt Comments

Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO

0010 OUT

2

valid

0

1

STALL

ACK

0011

Yes

Bad Status

1 1

1

2

Good Status

ACK_OUT_STATUS_IN

1011 SETUP >10

x

junk

Ignore

1011 SETUP < 10 invalid

Ignore

1011 SETUP < 10

valid

x

ACK

TX 0

1

0001 update

0011

update data

Yes

ACK SETUP

1011

IN

x

Host Not

ACK'd

1011

IN

x

TX 0

1

Host ACK'd

Ignore

1011 OUT

STATUS_IN

>10

junk

< 10 invalid

Ignore

< 10

valid

ACK

1 1 0001 update

1

update data

Yes

Good OUT

0110 SETUP >10

x

junk

Ignore

0110 SETUP < 10 invalid

Ignore

0110 SETUP < 10

valid

x

ACK

TX 0

1

0001 update

0011

update data

Yes

ACK SETUP

0110

IN

x

Host Not

ACK'd

0110

IN

x

TX 0

1

Host ACK'd

Ignore

0110 OUT

>10

< 10 invalid

< 10 valid

Ignore

STALL

0011

Yes

Stall OUT

Data Out Endpoints

ACK OUT (STALL Bit = 0)

1001 IN

1001 OUT > MAX

x

Ignore

junk

Ignore

1001 OUT < MAX invalid invalid

1001 OUT < MAX valid valid

ACK OUT (STALL Bit = 1)

Ignore

ACK

STALL

NAK

1

1000 update

1

update data

Yes

ACK OUT

1001

IN

x

Ignore

1001 OUT > MAX

Ignore

1001 OUT < MAX invalid invalid

1001 OUT < MAX valid valid

NAK OUT

Ignore

Stall OUT

1000

IN

x

Ignore

1000 OUT > MAX

Ignore

1000 OUT < MAX invalid invalid

1000 OUT < MAX valid valid

Ignore

If

NAK OUT

Enabled

Document Number: 001-07552 Rev. *G

Page 64 of 85

CYRF69213

Details of Mode for Differing Traffic Conditions (continued)

SIE

Bus Event

SIE

EP0 Mode Register EP0 Count Register

EP0 Interrupt Comments

Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO

Data In Endpoints

ACK IN (STALL Bit = 0)

1101 OUT

x

Ignore

1101

IN

Host Not

ACK'd

1101

IN

x

TX

1

1100

Yes

Host ACK'd

ACK IN (STALL Bit = 1)

1101 OUT

x

Ignore

1101

IN

STALL

NAK

Stall IN

NAK IN

1100 OUT

1100 IN

x

Ignore

If

NAK IN

Enabled

Document Number: 001-07552 Rev. *G

Page 65 of 85

CYRF69213

Register Summary

Addr

Name

7

6

5

4

3

2

1

0

R/W

Default

00

P0DATA

P0.7

Reserved Reserved P0.4 /

INT2

P0.3 / Reserved

INT1

P0.1

Reserved b--bbb--

00000000

01

P1DATA

P1.7

P1.6/SMI P1.5/SM P1.4 /

P1.3 /

SSEL

P1.2 /

VREG

P1.1/D– P1.0/D+ bbbbbbbb 00000000

SO

OSI

SCLK

02

06

P2DATA

P01CR

Res

P2.1–P2.0

bbbbbbbb 00000000

--bbbbbb 00000000

Reserved

Int

Enable

Int Act

Low

TTL

Thresh

High Sink Open

Drain

Pull up

Output

Enable

08–09 P03CR– Reserved Reserved Int Act

TTL

Reserved Open

Drain

Pull up

Enable

Output

Enable

--bbbbbb 00000000

-bbbbbbb 00000000

P04CR

Low

Thresh

0C

0D

0E

0F

10

P07CR

Reserved

Int

Int Act

Low

TTL

Thresh

Reserved Open

Drain

Pull up

Enable

Output

Enable

P10CR

P11CR

P12CR

P13CR

Int

Enable

Int Act

Low

Reserved

5K pull up Output

enable Enable

-bb----b

-bb--b-b

00000000

Int

Enable

Int Act

Low

Reserved

Open Reserved Output

Drain

Enable

CLK

Output

Int

Enable

Int Act

Low

TTL

Thresh

Reserved Open

Drain

Pull up

Enable

Output bbbbbbbb 00000000

Enable

Reserved

Int

Enable

Int Act

Low

3.3 V High Sink Open

Drive Drain

Pull up

Enable

Output

Enable

-bbbbbbb 00000000

11–13 P14CR–

P16CR

SPI Use

Int

Enable

Int Act

Low

3.3 V High Sink Open

Pull up

Enable

Output bbbbbbbb 00000000

Enable

Drive

Drain

14

P17CR

Reserved

Int

Int Act

Low

TTL

High Sink Open

Drain

Pull up

Enable

Output

Enable

-bbbbbbb 00000000

Enable

Thresh

15

P2CR

Int

Enable

Int Act

Low

TTL

Thresh

Reserved Open

Drain

Pull up

Enable

Output

Enable

-bbbbbbb 00000000

20

21

26

27

28

29

30

FRTMRL

FRTMRH

PITMRL

PITMRH

PIRL

Free-Running Timer [7:0]

bbbbbbbb 00000000

Free-Running Timer [15:8]

Prog Interval Timer [7:0]

Reserved

Prog Interval Timer [11:8]

----bbbb

00000000

Prog Interval [7:0]

Reserved

bbbbbbbb 00000000

PIRH

Prog Interval [11:8]

----bbbb

--------

00000000

00010000

CPUCLKC

R

31 ITMRCLKC TCAPCLK Divider

R

TCAPCLK Select

ITMRCLK Divider

ITMRCLK Select

CLKOUT Select

bbbbbbbb 10001111

32

34

35

36

CLKIOCR

IOSCTR

XOSCTR

Reserved

foffset[2:0]

Reserved

---bbbbb 00000000

bbbbbbbb 000ddddd

Gain[4:0]

Reserved

Reserved Mode

---bbb-b

000ddd0d

LPOSCTR 32 kHz Reserved 32 kHz Bias Trim

32 kHz Freq Trim [3:0]

b-bbbbbb dddddddd

Low

[1:0]

Power

39 OSCLCKC

R

Reserved

FineTune

Only

USB

Osclock

Disable

------bb

00000000

3C

3D

40

SPIDATA

SPICR

SPIData[7:0]

bbbbbbbb 00000000

Swap

LSB First

Comm Mode

CPOL

CPHA

SCLK Select

USBCR

USB

Enable

Device Address[6:0]

Document Number: 001-07552 Rev. *G

Page 66 of 85

CYRF69213

Register Summary (continued)

Addr

Name

7

6

5

4

3

2

1

0

R/W

Default

41

EP0CNT

Data

Valid

Reserved

Byte Count[3:0]

Mode[3:0]

bbbbbbbb 00000000

Toggle

42

43

EP1CNT

EP2CNT

Data

Toggle

Data

Valid

Reserved

bbbbbbbb 00000000

ccccbbbb 00000000

b-bcbbbb 00000000

Data

Toggle

Data

Valid

44 EP0MODE

45 EP1MODE

46 EP2MODE

Setup

rcv’d

IN rcv’d

OUT

rcv’d

ACK’d

trans

Stall

Reserved NAK Int

Enable

Ack’d

trans

Mode[3:0]

Stall

Reserved NAK Int

Enable

Ack’d

trans

Mode[3:0]

50–57 EP0DATA

58–5F EP1DATA

60–67 EP2DATA

Endpoint 0 Data Buffer [7:0]

Endpoint 1 Data Buffer [7:0]

Endpoint 2 Data Buffer [7:0]

Reserved

bbbbbbbb ????????

73

VREGCR

Keep

Alive

VREG

Enable

------bb

00000000

74

USBXCR USB Pull

up Enable

Reserved

USB

Force

State

b------b

00000000

DA INT_CLR0 GPIOPort Sleep

INT1

GPIO

Port 0

SPI

INT0 POR/LVD bbbbbbbb 00000000

1

Timer

Receive Transmit

DB INT_CLR1 Reserved

Prog

Interval

Timer

1-ms

Timer

USB

Active

USB

Reset

USB EP2 USB EP1 USB EP0 -bbbbbbb 00000000

DC INT_CLR2 Reserved Reserved Reserved GPIO Reserved INT2

Port 2

16-bit Reserved -bbbbbb- 00000000

Counter

Wrap

DE INT_MSK3 ENSWINT

Reserved

b-------

00000000

DF INT_MSK2 Reserved Reserved Reserved GPIO Reserved INT2

16-bit Reserved ---bbbb-

Port 2

Int

Enable

Int

Enable

Counter

Wrap

Int

Enable

E0 INT_MSK0

GPIO

Port 1

Int Enable

Sleep

Timer

Int

INT1

Int

Enable

GPIO

Port 0

Int

SPI

INT0 POR/LVD bbbbbbbb 00000000

Receive Transmit

Int

Enable

Int

Enable

E1 INT_MSK1 Reserved

Prog

Interval

Timer

Int

1-ms

Timer

Int

USB

Active

Int

USB

Reset

Int

USB EP2 USB EP1 USB EP0 bbbbbbbb 00000000

Int

Enable

E2

E3

INT_VC

Pending Interrupt [7:0]

bbbbbbbb 00000000

RESWDT

Reset Watchdog Timer [7:0]

wwwwwww 00000000

w

--

CPU_A

CPU_X

Temporary Register T1 [7:0]

X[7:0]

--------

00000000

CPU_PCL

CPU_PCH

CPU_SP

CPU_F

Program Counter [7:0]

Program Counter [15:8]

Stack Pointer [7:0]

Reserved

XOI

Super

Carry

Zero

Global IE ---brwww 00000010

FF CPU_SCR

GIES

Reserved WDRS

PORS

Sleep Reserved Reserved

Stop

r-ccb--b

00010000

Document Number: 001-07552 Rev. *G

Page 67 of 85

CYRF69213

Register Summary (continued)

Addr

Name

7

6

5

4

3

2

1

0

R/W

Default

--bbbbbb 00000000

--bb-bbbb 00000000

1E0 OSC_CR0

Reserved

No Buzz Sleep Timer [1:0]

CPU Speed [2:0]

VM[2:0]

1E3

1E4

LVDCR

PORLEV[1:0]

Reserved

VLTCMP

LVD

PPOR

------rr

00000000

1EB ECO_TR

Sleep Duty Cycle

[1:0]

bb------

LEGEND

In the R/W column,

b = Both Read and Write

r = Read Only

w = Write Only

c = Read/Clear

? = Unknown

d = calibration value. Should not change during normal use

Document Number: 001-07552 Rev. *G

Page 68 of 85

CYRF69213

Radio Function Register Descriptions

All registers are read and writeable, except where noted. Registers may be written to or read from either individually or in sequential

groups. A single-byte read or write reads or writes from the addressed register. Incrementing burst read and write is a sequence that

begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible

to repeatedly read (poll) a single register using a non-incrementing burst read. These registers are managed and configured over SPI

by the user firmware running in the microcontroller function.

Table 88. Register Map Summary

[4]

Address

0x00

Mnemonic

CHANNEL_ADR

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

Not Used

Channel

-1001000

00000000

00000011

-bbbbbbb

bbbbbbbb

0x01

TX_LENGTH_ADR

TX_CTRL_ADR

TX_CFG_ADR

TX Length

TXB15

IRQEN

TXB8

IRQEN

TXB0

IRQEN

TXBERR

IRQEN

TXC

IRQEN

TXE

IRQEN

0x02

0x03

0x04

TX GO

TX CLR

DATA CODE

LENGTH

--000101

10111000

00000111

10010-10

00000000

--bbbbbb

rrrrrrrr

bbbbbbbb

bbbbb-bb

brrrrrrr

Not Used

DATA MODE

PA SETTING

OS

IRQ

LV

IRQ

TXB15

IRQ

TXB8

IRQ

TXB0

IRQ

TXBERR IRQ

TXC

IRQ

TXE

IRQ

TX_IRQ_STATUS_ADR

RX_CTRL_ADR

RX_CFG_ADR

RXB16

IRQEN

RXB8

IRQEN

RXB1

IRQEN

RXBERR

IRQEN

RXC

IRQEN

RXE

IRQEN

0x05

0x06

RX GO

RSVD

LNA

FASTTURN

EN

AGC EN

ATT

HILO

Not Used

RXOW EN

VLD EN

RXOW

IRQ

SOFDET

IRQ

RXB16

IRQ

RXB8

IRQ

RXB1

IRQ

RXBERR IRQ

RXC

IRQ

RXE

IRQ

0x07

0x08

0x09

0x0A

0x0B

RX_IRQ_STATUS_ADR

RX_STATUS_ADR

RX_COUNT_ADR

RX_LENGTH_ADR

PWR_CTRL_ADR

RX ACK

PKT ERR

EOP ERR

CRC0

Bad CRC

RX Code

RX Data Mode

00001---

00000000

10100000

rrrrrrrr

bbb-bbbb

RX Count

RX Length

RSVD

PMU EN

LVIRQ EN

PMU MODE

FORCE

LVI TH

PMU OUTV

FREQ

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

XTAL_CTRL_ADR

XOUT FN

XSIRQ EN

MISO OD

PACTL OP

FRC END

LEN EN

Not Used

LNA

Not Used

000--100

00000000

0000----

1-000000

10100101

----0100

---01010

0-100000

10100100

00000000

--------

11111111

00000000

----0000

00000--0

0000000-

00000000

bbb--bbb

bbbbbbbb

bbbbrrrr

b-bbbbbb

bbbbbbbb

----bbbb

---bbbbb

r-rrrrrr

bbbbbbbb

rrrrrrrr

bbbbbbbb

----bbbb

wwwww--w

bbbbbbb-

bbbbbbbb

IO_CFG_ADR

IRQ OD

XOUT OP

ACK EN

SOP EN

Not Used

SOP

IRQ POL

MISO OP

Not Used

SOP LEN

Not Used

XOUT OD PACTL OD PACTL GPIO

SPI 3PIN

PACTL IP

IRQ GPIO

IRQ IP

GPIO_CTRL_ADR

IRQ OP

XOUT IP

MISO IP

XACT_CFG_ADR

END STATE

ACK TO

FRAMING_CFG_ADR

DATA32_THOLD_ADR

DATA64_THOLD_ADR

RSSI_ADR

SOP TH

TH32

Not Used

TH64

RSSI

EOP_CTRL_ADR

HEN

HINT

EOP

CRC_SEED_LSB_ADR

CRC_SEED_MSB_ADR

TX_CRC_LSB_ADR

TX_CRC_MSB_ADR

RX_CRC_LSB_ADR

RX_CRC_MSB_ADR

TX_OFFSET_LSB_ADR

TX_OFFSET_MSB_ADR

MODE_OVERRIDE_ADR

RX_OVERRIDE_ADR

CRC SEED LSB

CRC SEED MSB

CRC LSB

CRC MSB

CRC LSB

CRC MSB

STRIM LSB

Not Used

RSVD

Not Used

RSVD

Not Used

FRC SEN

Not Used

FRC AWAKE

STRIM MSB

Not Used

ACE

RST

ACK RX

RXTX DLY

MAN RXACK FRC RXDR DIS CRC0 DIS RXCRC

MAN

RSVD

Not Used

0x1F

0x27

0x28

0x29

0x32

0x35

0x39

TX_OVERRIDE_ADR

CLK_OVERRIDE_ADR

CLK_EN_ADR

ACK TX

RSVD

FRC PRE

RSVD

TXACK

RSVD

OVRD ACK DIS TXCRC

RSVD

RXF

TX INV

RSVD

00000000

00000011

00000000

wwwwwwww

RSVD

RXF

RX_ABORT_ADR

RSVD

ABORT EN

RSVD

AUTO_CAL_TIME_ADR

AUTO_CAL_OFFSET_ADR

ANALOG_CTRL_ADR

AUTO_CAL_TIME_MAX

AUTO_CAL_OFFSET_MINUS_4

RSVD

ALL SLOW

Register Files

0x20

0x21

0x22

0x23

0x24

0x25

TX_BUFFER_ADR

TX Buffer File

--------

wwwwwwww

rrrrrrrr

bbbbbbbb

rrrrrrrr

RX_BUFFER_ADR

SOP_CODE_ADR

DATA_CODE_ADR

PREAMBLE_ADR

MFG_ID_ADR

RX Buffer File

SOP Code File

Data Code File

Preamble File

MFG ID File

Note

NA

5

6

7

Notes

4. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.

5. SOP_CODE_ADR default = 0x17FF9E213690C782.

6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.

7. PREAMBLE_ADR default = 0x333302;The count value should be great than 4 for DDR and greater than 8 for SDR.

Document Number: 001-07552 Rev. *G

Page 69 of 85

CYRF69213

DC Voltage applied to Outputs

in High Z State ..................................... –0.3 V to V + 0.3 V

Absolute Maximum Ratings

IO

[9]

Storage Temperature ................................. –40 °C to +90 °C

Ambient Temperature with Power Applied ..... 0 °C to +70 °C

Supply Voltage on any power supply

Static Discharge Voltage (Digital)

........................>2000 V

[9]

Static Discharge Voltage (RF)

............................... 1100 V

Latch up Current .....................................+200 mA, –200 mA

Ground Voltage ................................................................ 0 V

pin relative to V ........................................–0.3 V to +3.9 V

SS

[8]

DC Voltage to Logic Inputs

.............. –0.3 V to V + 0.3 V

IO

F

(Crystal Frequency) .......................... 12 MHz ±30 ppm

OSC

DC Characteristics

(T = 25C)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

Radio Function Operating Voltages (For RF activity, V_cc= V_bat= 3.0 V to 3.6 V)

V

Battery Voltage

0C–70 C

2.4

1.8

2.4

–

3.6

V

BAT

IO

V

Voltage

IO

CC

0 C–70 C

CC

MCU Function Operating Voltages

V

Operating Voltage

No USB activity,

4.0

–

5.25

V

DD_MICRO1

CPU speed < 12 MHz

V

Operating Voltage

USB activity,

CPU speed < 12 MHz.

Flash programming

4.35

DD_MICRO2

V

Low voltage Detect Trip Voltage

(8 programmable trip points)

2.68

–

4.87

V

LVD

Device Current (For total current consumption in different modes, for example Radio, active, MCU, sleep, etc., add Radio

Function Current and MCU Function Current)

[10]

I

(GFSK)

Average I , 1 Mbps, slow

channel

PA = 5, 2-way, 4 bytes/10 ms

RadiofunctionandMCUfunction

–

10.87

–

mA

µA

DD

SB

DD

[10]

(32-8DR)

Average I , 250 kbps, fast

11.2

DD

channel

Sleep Mode I

40.1

DD

in Sleep mode, V

Alive.

in Keep

REG

Radio Function Current (V_{DD_Micro}= 5.0 V, V_REGenabled, MCU sleep)

IDLE I

Radio Off, XTAL Active

XOUT disabled

–

2.1

9.8

–

mA

CC

I

during Synth Start

during Transmit

during Receive

synth

CC

TX I

PA = 5 (–5 dBm)

PA = 6 (0 dBm)

PA = 7 (+4 dBm)

LNA off, ATT on

LNA on, ATT off

22.4

27.7

36.6

20.2

23.4

CC

RX I

CC

Notes

8. It is permissible to connect voltages above V to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.

IO

9. Human Body Model (HBM).

10. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK

handshake. Device is in sleep except during this transaction.

Document Number: 001-07552 Rev. *G

Page 70 of 85

CYRF69213

DC Characteristics (continued)

(T = 25C)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

MCU Function Current (V_{DD_Micro}= 5.0 V, V_REGdisabled)

I

V

Operating Supply

No GPIO loading, 6 MHz

–

10

4

–

mA

µA

DD_MICRO1

DD_MICRO

Current

Standby Current

Internal Oscillators, Bandgap,

Flash, CPU Clock, Timer Clock,

USB Clock all disabled

10

SB1

USB Interface

V

Static Output High

15K ± 5% Ohm to V

2.8

–

3.6

0.3

–

V

ON

OFF

DI

SS

Static Output Low

R

is enabled

UP

Differential Input Sensitivity

0.2

0.8

Differential Input Common Mode

Range

2.5

CM

V

Single Ended Receiver

Threshold

0.8

–

2

V

SE

C

Transceiver Capacitance

–

20

10

pF

µA

IN

I

Hi-Z State Data Line Leakage

0 V < V < 3.3 V

–10

IO

IN

Radio Function GPIO Interface

V

Output High Voltage Condition 1 At I = –100.0 µA

V

– 0.1

V

–

V

OH1

OH2

OL

IH

OH

IO

Output High Voltage Condition 2 At I = –2.0 mA

– 0.4

–

OH

IO

Output Low Voltage

Input High Voltage

Input Low Voltage

At I = 2.0 mA

0

0.4

V

OL

0.76 V

–

V

IO

0

–1

–

0.24 V

+1

V

IL

IO

I

Input Leakage Current

Pin Input Capacitance

0 < V < V

IO

0.26

3.5

µA

pF

IL

IN

C

except XTAL, RF , RF , RF

BIAS

10

IN

N

P

MCU Function GPIO Interface

R

Pull up Resistance

4

–

12

K

UP

V

Input Threshold Voltage Low,

CMOS mode

Low to High edge

High to Low edge

40%

65%

V

ICR

CC

Input Threshold Voltage Low,

CMOS mode

30%

3%

–

55%

10%

ICF

HC

Input Hysteresis Voltage, CMOS High to Low edge

Mode

V

Input Low Voltage, TTL Mode

Input High Voltage, TTL Mode

Output Low Voltage,

IO-pin Supply = 2.9–3.6 V

IO-pin Supply = 4.0–5.5 V

–

2.0

–

0.8

–

V

ILTTL

IHTTL

OL1

I

= 50 mA

= 25 mA

= 8 mA

0.8

OL1

OL2

OH

[11]

High Drive

V

Output Low Voltage,

–

0.4

–

V

OL2

OL3

OH

[11]

High Drive

Output Low Voltage,

[11]

Low Drive

[11]

Output High Voltage

= 2 mA

V

– 0.5

CC

Note

11. Except for pins P1.0, P1.1 in GPIO mode.

Document Number: 001-07552 Rev. *G

Page 71 of 85

CYRF69213

DC Characteristics (continued)

(T = 25C)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

3.3 V Regulator

I

Max Regulator Output Current

Keep Alive Current

V

> 4.35 V

CC

–

125

20

mA

µA

VREG

KA

When regulator is disabled with

‘keep alive’ enable

V

Output Voltage

V > 4.35 V, 0 < temp < 40 °C,

CC

3.0

–

3.6

3.45

3.9

V

REG1

REG2

KA

REG

25 mA < I

< 125 mA

VREG

V

> 4.35 V, 0 < temp < 40 °C,

3.15

2.35

CC

1 mA < I

< 25 mA

VREG

Keep Alive Voltage

Keep Alive bit set in VREGCR

Document Number: 001-07552 Rev. *G

Page 72 of 85

CYRF69213

RF Characteristics

Table 89. Radio Parameters

Parameter Description

RF Frequency Range

Conditions

Min.

Typ.

Max.

Unit

Subject to regulations.

2.400

–

2.497

GHz

Receiver (T = 25 °C, V_CC= V_bat= 3.0 V, f_OSC= 12.000 MHz, BER < 10^–3

)

Sensitivity 125 kbps 64-8DR

Sensitivity 250 kbps 32-8DR

Sensitivity

BER 1E-3

CER 1E-3

–

–97

–93

–87

–84

22.8

–31.7

–6

–

dBm

–80

–

dBm

Sensitivity GFSK

LNA gain

BER 1E-3, ALL SLOW = 1

dBm

–

dB

ATT gain

–

dB

Maximum Received Signal

LNA On

–15

–

dBm

[13]

RSSI value for PWR –60 dBm

21

Count

dB/Count

in

RSSI slope

–

1.9

Interference Performance (CER 1E-3)

Co-channel Interference rejection

Carrier-to-Interference (C/I)

C = –60 dBm

–

9

–

dB

Adjacent (±1 MHz) channel selectivity C/I 1 MHz

Adjacent (±2 MHz) channel selectivity C/I 2 MHz

C = –60 dBm

–

3

–

dB

–30

–38

–30

–36

Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm

dB

[12]

Out-of-Band Blocking 30 MHz–12.75 MHz

C = –67 dBm

dBm

Intermodulation

Receive Spurious Emission

800 MHz

C = –64 dBm, f = 5,10 MHz

100 kHz ResBW

–

–79

–71

–65

–

dBm

1.6 GHz

3.2 GHz

Transmitter (T = 25 °C, V_CC= V_bat= 3.0 V, f_OSC= 12.000 MHz)

Maximum RF Transmit Power

RF Power Control Range

PA = 7

PA = 6

PA = 5

PA = 0

+2

–2

–7

–

4

+6

+2

–3

–

dBm

dB

0

–5

–35

39

–

RF Power Range Control Step Size

Frequency Deviation Min

seven steps, monotonic

PN Code Pattern 10101010

PN Code Pattern 11110000

>0 dBm

–

5.6

270

323

10

–

dB

–

kHz

%rms

kHz

Frequency Deviation Max

–

Error Vector Magnitude (FSK error)

Occupied Bandwidth

–

–6 dBc, 100 kHz ResBW

500

876

–

Notes

12. Exceptions F/3 & 5C/3.

13. RSSI value is not guaranteed. Extensive variation from part to part.

Document Number: 001-07552 Rev. *G

Page 73 of 85

CYRF69213

Table 89. Radio Parameters (continued)

Parameter Description

Transmit Spurious Emission (PA = 7)

In-band Spurious Second Channel Power (±2 MHz)

In-band Spurious Third Channel Power (> 3 MHz)

Non-Harmonically Related Spurs (8.000 GHz)

Non-Harmonically Related Spurs (1.6 GHz)

Non-Harmonically Related Spurs (3.2 GHz)

Harmonic Spurs (Second Harmonic)

Conditions

Min.

Typ.

Max.

Unit

–

–38

–44

–38

–34

–47

–43

–48

–59

–

dBm

Harmonic Spurs (Third Harmonic)

Fourth and Greater Harmonics

Power Management (Crystal PN# eCERA GF-1200008)

Crystal start to 10 ppm

–

0.7

0.6

–

1.3

–

ms

µs

Crystal start to IRQ

Synth Settle

XSIRQ EN = 1

Slow channels

270

180

100

30

Synth Settle

Medium channels

Fast channels

GFSK

–

µs

Synth Settle

–

µs

Link turnaround time

Max. packet length

–

µs

250 kbps

–

62

µs

125 kbps

–

94

µs

<125 kbps

–

31

µs

< 60 ppm crystal-to-crystal

all modes except 64-DDR

and 64-SDR

–

40

bytes

Max. packet length

< 60 ppm crystal-to-crystal

64-DDR and 64-SDR

–

16

bytes

AC Test Loads and Waveforms for Digital Pins

Figure 19. AC Test Loads and Waveforms for Digital Pins

AC Test Loads

OUTPUT

DC Test Load

OUTPUT

R1

V

CC

5 pF

30 pF

OUTPUT

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

R2

Max

Typical

ALL INPUT PULSES

V

Parameter

Unit



V

CC

90%

10%

90%

10%

R1

1071

937

500

1.4

GND

R2

R

Fall time: 1 V/ns

Rise time: 1 V/ns

TH

V

TH

CC

THÉVENIN EQUIVALENT

Equivalent to:

OUTPUT

3.00

V

R

TH

V

TH

Document Number: 001-07552 Rev. *G

Page 74 of 85

CYRF69213

AC Electrical Characteristics

Parameter

Clock

Description

Conditions

Min.

Typ.

Max.

Unit

MHz

kHz

F

Internal Main Oscillator

Frequency

No USB present

22.8

23.64

29.44

35.84

–

25.2

24.36

37.12

47.36

IMO

With USB present

Normal Mode

F

Internal Low Power Oscillator

ILO

Low Power Mode

3.3 V Regulator

V

Output Ripple Voltage

45

–

55

%

ORIP

USB Driver

T

Transition Rise Time

C

= 200 pF

= 600 pF

= 200 pF

= 600 pF

75

–

ns

%

V

R1

R2

F1

F2

R

LOAD

T

Transition Rise Time

300

–

Transition Fall Time

75

–

Transition Fall Time

300

125

2.0

Rise/Fall Time Matching

Output Signal Crossover Voltage

80

1.3

V

CRS

USB Data Timing

T

Low speed Data Rate

Ave. Bit Rate (1.5 Mbps ± 1.5%)

To next transition

1.4775

–75

–

1.5225

75

Mbps

ns

DRATE

DJR1

T

Receiver Data Jitter Tolerance

To pair transition

–45

45

ns

DJR2

Differential to EOP Transition

Skew

–40

100

ns

DEOP

T

EOP Width at Receiver

Source EOP Width

Rejects as EOP

Accept as EOP

–

330

–

ns

s

ns

EOPR1

EOPR2

EOPT

UDJ1

UDJ2

LST

675

1.25

–95

–

1.5

95

Differential Driver Jitter

To next transition

To pair transition

95

Width of SE0 during Diff.

Transition

210

Non-USB Mode Driver Characteristics

T

SDATA/SCK Transition Fall Time

50

–

300

ns

FPS2

SPI Timing

T

SPI Master Clock Rate

SPI Slave Clock Rate

SPI Clock High Time

F

/6

–

2

2.2

–

MHz

ns

SMCK

SSCK

SCKH

CPUCLK

T

High for CPOL = 0,

Low for CPOL = 1

125

T

SPI Clock Low Time

Low for CPOL = 0,

High for CPOL = 1

125

–

ns

SCKL

[14]

T

Master Data Output Time

SCK to data valid

–25

100

–

50

–

ns

MDO

Master Data Output Time,

First bit with CPHA = 0

Time before leading SCK edge

MDO1

Note

14. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.

Document Number: 001-07552 Rev. *G

Page 75 of 85

CYRF69213

AC Electrical Characteristics (continued)

Parameter

Description

Conditions

Min.

50

–

Typ.

Max.

–

Unit

ns

T

Master Input Data Setup time

Master Input Data Hold time

Slave Input Data Setup Time

Slave Input Data Hold Time

Slave Data Output Time

–

MSU

MHD

SSU

SHD

SDO

SDO1

–

ns

–

ns

–

ns

SCK to data valid

100

ns

Slave Data Output Time,

First bit with CPHA = 0

Time after SS LOW to data valid

–

ns

T

Slave Select Setup Time

Slave Select Hold Time

Before first SCK edge

After last SCK edge

150

–

ns

SSS

SSH

Figure 20. Clock Timing

T

CYC

T

CH

CLOCK

T

CL

Figure 21. USB Data Signal Timing

T

F

R

D

D

V

oh

90%

V

crs

10%

V

ol

Figure 22. Clock Timing

T

CYC

T

CH

CLOCK

T

CL

Document Number: 001-07552 Rev. *G

Page 76 of 85

CYRF69213

Figure 23. USB Data Signal Timing

T

F

R

D

D

V

oh

90%

V

crs

10%

V

ol

Figure 24. Receiver Jitter Tolerance

T_PERIOD

Differential

Data Lines

T_JR

T_JR1

T_JR2

Consecutive

Transitions

N * T_PERIOD+ T_JR1

Paired

Transitions

N * T_PERIOD+ T_JR2

Figure 25. Differential to EOP Transition Skew and EOP Width

T_PERIOD

Crossover Point

Extended

Crossover

Point

Differential

Data Lines

Diff. Data to

SE0 Skew

N * T_PERIOD+ T_DEOP

Source EOP Width: T_EOPT

Receiver EOP Width: T_EOPR1, T_EOPR2

Document Number: 001-07552 Rev. *G

Page 77 of 85

CYRF69213

Figure 26. Differential Data Jitter

T_PERIOD

Crossover

Points

Differential

Data Lines

Consecutive

Transitions

N * T_PERIOD+ T_xJR1

Paired

Transitions

N * T_PERIOD+ T_xJR2

Figure 27. SPI Master Timing, CPHA = 1

(SS is under firmware control in SPI Master mode)

SS

T

SCKL

SCK (CPOL=0)

T

SCKH

SCK (CPOL=1)

MOSI

T

MDO

MSB

LSB

MSB

LSB

MISO

T

MHD

MSU

Document Number: 001-07552 Rev. *G

Page 78 of 85

CYRF69213

Figure 28. SPI Slave Timing, CPHA = 1

SS

T

SSH

SSS

T

SCKL

SCK (CPOL=0)

T

SCKH

SCK (CPOL=1)

MOSI

MSB

LSB

T

SHD

T

SSU

SDO

MSB

LSB

MISO

Document Number: 001-07552 Rev. *G

Page 79 of 85

CYRF69213

Figure 29. SPI Master Timing, CPHA = 0

(SS is under firmware control in SPI Master mode)

SS

T

SCKL

SCK (CPOL=0)

SCK (CPOL=1)

T

SCKH

T

MDO

T

MDO1

MSB

LSB

MOSI

MISO

MSB

LSB

T

MHD

MSU

Figure 30. SPI Slave Timing, CPHA = 0

SS

T

SSH

SSS

T

SCKL

SCK (CPOL=0)

T

SCKH

SCK (CPOL=1)

MOSI

MSB

LSB

T

SHD

SSU

T

SDO

T

SDO1

MISO

MSB

LSB

Document Number: 001-07552 Rev. *G

Page 80 of 85

CYRF69213

Ordering Information

Package

Ordering Part Number

CYRF69213-40LTXC

Status

40-pin Pb-free QFN 6 × 6 mm (Sawn)

40-pin Pb-free QFN 6 × 6 mm (Punch)

In Production

NRND

CYRF69213-40LFXC

Ordering Code Definitions

C

69213

CY RF

40 L(F,T)X

Temperature range:

Commercial

40-pin package

F = QFN; T = Sawn QFN

X = Pb-free

Part Number

Marketing Code:

RF Wireless

=

(radio frequency) product line

Company ID: Cypress

CY

=

Document Number: 001-07552 Rev. *G

Page 81 of 85

CYRF69213

Package Diagram

Figure 31. 40-pin QFN (6 × 6 × 1.0 mm) LT40B (3.5 × 3.5 mm) E-Pad (Sawn) Package Outline, 001-13190

001-13190 *H

Document Number: 001-07552 Rev. *G

Page 82 of 85

CYRF69213

[15]

Figure 32. 40-pin QFN (6 × 6 × 1.0 mm) LF40A/LY40A (3.50 × 3.50 mm) E-Pad (Punch) Package Outline, 001-12917

SOLDERABLE

EXPOSED

PAD

001-12917 *C

Note

15. Not Recommended for New Design.

Document Number: 001-07552 Rev. *G

Page 83 of 85

CYRF69213

Document History Page

Document Title: CYRF69213, Programmable Radio on Chip Low Power

Document #: 001-07552

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

436355

501280

631538

OYR

BOO

See ECN New advance data sheet.

See ECN Preliminary data sheet.

*A

*B

See ECN Final datasheet. Updated DC Characteristics table with characterization data.

Minor text changes

Removed all residual references to external crystal oscillator and GPIO4

Voltage regulator line/load regulation documented

GPIO capacitance and timing diagram included

Sleep and Wake up sequence documented.

EP1MODE/EP2MODE register issue discussed

Updated radio function register descriptions

Changed L/D pin description

Changed RST Capacitor from 0.1uF to 0.47uF

*C

2447906 VNY / VGT

/ AESA

See ECN Modified figure 1: Vbat changed to Vbat 0,1,2 for pins 36,6 and 9

Drive level changed to 100uW

Figures 1and 3 have a 1 ohm resistor added between Vreg and Vcc

Radio register map summary has PFET disable added to bit 4 of

PWR_CTRL_ADR

Modified register map notes summary for the radio.

Modified P02CR to P03CR

Added a table to include properties of P01CR

Modified the enCoRe II register summary table to include properties of P01CR

Modified section on low power in Sleep mode

Updated Template

*D

2661527

TGE /

PYRS

18/02/09

Changed package spec to 001-12917

Removed Backward Compatibility section

Changed "PFET disable" bit in register 0x0B to "RSVD".

Added text “For RF activity, Vcc=Vbat=3.0 V-3.6 V” to Radio Function

Operating Voltage

*E

*F

2899829

3550855

KKU

03/26/2010 Updated the following sections:

Pinouts, Clock Block Diagram, Clock Architecture Description, CPU Clock

During Sleep Mode, Reset, Sleep Mode, and Register Summary

ANTG

03/15/2012 Added new ordering part number for Sawn type package

Added new package diagram for Sawn type package.

Added a section “Receive Spurious Response”

Added note# 16 and provided reference to it in Table 88

Added ordering code definition

Updated the package diagram for Punch type package

*G

3717153

ANKC

08/18/2012 Updated Ordering Information (No change in part numbers, included a column

“Status”).

Updated PackageDiagram (spec001-13190 (Changed revision from*G to*H),

added Note 15 and referred the same note in Figure 32).

Updated in new template.

Document Number: 001-07552 Rev. *G

Page 84 of 85

CYRF69213

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/psoc

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-07552 Rev. *G

Revised August 18, 2012

Page 85 of 85

WirelessUSB, PSoC, enCoRe and PRoC are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective

holders.


型号：	CYRF69213-40LTXC
厂家：	CYPRESS
描述：	Programmable Radio on Chip Low Power 无线可编程片上低功耗无线
文件：	总85页 (文件大小：843K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYRF69213-40LTXC [CYPRESS]

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