CYUSB3014-FBXCT [CYPRESS]
EZ-USB® FX3: SuperSpeed USB Controller; EZ - USB® FX3 ：超高速USB控制器
| 型号： | CYUSB3014-FBXCT |
| 厂家： | 
CYPRESS |
| 描述： | EZ-USB® FX3: SuperSpeed USB Controller |
| 文件： | 总45页 (文件大小：568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYUSB301X
EZ-USB® FX3: SuperSpeed USB Controller
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
Features
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0
specification 1.0
❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V
■ Package option
❐ 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array
(BGA)
❐ 131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale
package (WLCSP)
■ EZ-USB® software and development kit (DVK) for easy code
development
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐ 8-, 16-, and 32-bit data bus
❐ As many as16 configurable control signals
Applications
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Additional connectivity to the following peripherals
❐ I2C master controller at 1 MHz
■ Scanners
❐ I2S master (transmitter only) at sampling frequencies of
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
32 kHz, 44.1 kHz, and 48 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Portable media players
■ Industrial cameras
Cypress Semiconductor Corporation
Document Number: 001-52136 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised May 31, 2013
CYUSB301X
Logic Block Diagram
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
JTAG
CLKIN_32
XTALIN
Embedded
SRAm
(512kB/
256KB)
ARM926EJ -S
XTALOUT
HS/FS/LS
OTG Host
OTG_ID
DQ[31:0]/
DQ[15:0]
SSRX -
SSRX +
SSTX -
SSTX +
SS
Peripheral
CTL[12:0]
32
EPs
PMODE[2:0
]
GPIF™ II
HS/FS
Peripheral
D+
D-
INT#
RESET #
EZ-Dtect™
UART
SPI
I2S
I2C
Document Number: 001-52136 Rev. *N
Page 2 of 45
CYUSB301X
Contents
Functional Overview ..........................................................4
Pin Description .................................................................15
Absolute Maximum Ratings ............................................22
Operating Conditions .......................................................22
DC Specifications .............................................................22
Application Examples ....................................................4
USB Interface ......................................................................5
OTG ...............................................................................5
ReNumeration ...............................................................6
EZ-Dtect ........................................................................6
VBUS Overvoltage Protection .......................................6
Carkit UART Mode ........................................................6
AC Timing Parameters .....................................................24
GPIF II Timing .............................................................24
Slave FIFO Interface ...................................................27
Synchronous Slave FIFO
Write Sequence Description ...............................................28
Asynchronous Slave FIFO
Read Sequence Description ...............................................29
Asynchronous Slave FIFO
Write Sequence Description ...............................................30
Serial Peripherals Timing ............................................33
GPIF II ..................................................................................7
CPU ......................................................................................7
JTAG Interface ....................................................................8
Other Interfaces ..................................................................8
UART Interface ..............................................................8
I2C Interface ..................................................................8
I2S Interface ..................................................................8
SPI Interface ..................................................................8
Reset Sequence ................................................................38
Package Diagram ..............................................................39
Boot Options .......................................................................9
Ordering Information ........................................................41
Reset ....................................................................................9
Hard Reset ....................................................................9
Soft Reset ......................................................................9
Ordering Code Definitions ...........................................41
Acronyms ..........................................................................42
Document Conventions ...................................................42
Clocking ..............................................................................9
Units of Measure .........................................................42
32-kHz Watchdog Timer Clock Input ...........................10
Document History Page ...................................................43
Power .................................................................................10
Sales, Solutions, and Legal Information ........................45
Worldwide Sales and Design Support .........................45
Products ......................................................................45
PSoC Solutions ...........................................................45
Power Modes ..............................................................10
Configuration Options .....................................................13
Digital I/Os .........................................................................13
GPIOs .................................................................................13
System-level ESD .............................................................13
Pin Configurations ...........................................................13
Document Number: 001-52136 Rev. *N
Page 3 of 45
CYUSB301X
FX3 contains 512 KB or 256 KB of on-chip SRAM (see Ordering
Information on page 41) for code and data. EZ-USB FX3 also
provides interfaces to connect to serial peripherals such as
UART, SPI, I2C, and I2S.
Functional Overview
Cypress’s EZ-USB FX3 is the next-generation USB 3.0
peripheral controller, providing integrated and flexible features.
FX3 comes with application development tools. The software
development kit comes with application examples for
accelerating time to market.
FX3 has a fully configurable, parallel, general programmable
interface called GPIF II, which can connect to any processor,
ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in
FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and
glueless connectivity to popular interfaces, such as
asynchronous SRAM, asynchronous and synchronous address
data multiplexed interfaces, and parallel ATA.
FX3 complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0. It also complies with the
Battery Charging Specification v1.1 and USB 2.0 OTG
Specification v2.0.
FX3 has integrated the USB 3.0 and USB 2.0 physical layers
(PHYs) along with a 32-bit ARM926EJ-S microprocessor for
powerful data processing and for building custom applications. It
implements an architecture that enables 375-MBps data transfer
from GPIF II to the USB interface.
Application Examples
In a typical application (see Figure 1), FX3 functions as a copro-
cessor and connects to an external processor, which manages
system-level functions. Figure 2 shows a typical application
diagram when FX3 functions as the main processor.
An integrated USB 2.0 OTG controller enables applications in
which FX3 may serve dual roles; for example, EZ-USB FX3 may
function as an OTG Host to MSC as well as HID-class devices.
Figure 1. EZ-USB FX3 as a Coprocessor
Power
Subsystem
*
Crystal
External Processor
(Example: MCU/CPU/
EZ- USB FX3
(ARM9 Core)
USB
Port
GPIF II
USB Host
ASIC/FPGA)
Serial Interfaces
( example:I2C)
External Serial Peripheral
(Example::
*
A clock input may be provided on the
CLKIN pin instead of a crystal input
)
EEPROM
Note
1. Assuming that GPIF II is configured for a 32-bit data bus (available with certain part numbers; see Ordering Information on page 41), synchronous interface operating
at 100 MHz. This number also includes protocol overheads.
Document Number: 001-52136 Rev. *N
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CYUSB301X
Figure 2. EZ-USB FX3 as Main Processor
*
Crystal
External Slave Device
(Example: Image sensor)
EZ-USB FX3
(ARM9 Core)
USB
Port
GPIF II
USB Host
I2C
*
A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
Figure 3. USB Interface Signals
USB Interface
EZ-USB FX3
FX3 complies with the following specifications and supports the
following features:
VBATT
■ Supports USB peripheral functionality compliant with USB 3.0
Specification Revision 1.0 and is also backward compatible
with the USB 2.0 Specification.
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
■ Complies with OTG Supplement Revision 2.0. It supports
High-Speed, Full-Speed, andLow-SpeedOTGdual-roledevice
capability. As a peripheral, FX3 is capable of SuperSpeed,
High-Speed, and Full-Speed. As a host, it is capable of
High-Speed, Full-Speed, and Low-Speed.
D+
■ Supports Carkit Pass-Through UART functionality on USB
D+/D– lines based on the CEA-936A specification.
OTG
FX3 is compliant with the OTG Specification Revision 2.0. In
OTG mode, FX3 supports both A and B device modes and
supports Control, Interrupt, Bulk, and Isochronous data
transfers.
■ Supports up to 16 IN and 16 OUT endpoints.
■ Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device-class to optimize mass-storage
access performance.
FX3 requires an external charge pump (either standalone or
integrated into a PMIC) to power VBUS in the OTG A-device
mode.
■ As a USB peripheral, FX3 supports UAS, USB Video Class
(UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral,
all other device classes are supported only in pass-through
mode when handled entirely by a host processor external to
the device.
The Target Peripheral List for OTG host implementation consists
of MSC- and HID-class devices.
FX3 does not support Attach Detection Protocol (ADP).
■ As an OTG host, FX3 supports MSC and HID device classes.
Note When the USB port is not in use, disable the PHY and
transceiver to save power.
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CYUSB301X
OTG Connectivity
VBUS Overvoltage Protection
In OTG mode, FX3 can be configured to be an A, B, or dual-role
device. It can connect to the following:
The maximum input voltage on FX3's VBUS pin is 6 V. A charger
can supply up to 9 V on VBUS. In this case, an external
overvoltage protection (OVP) device is required to protect FX3
from damage on VBUS. Figure 4 shows the system application
diagram with an OVP device connected on VBUS. Refer to
Table 7 for the operating range of VBUS and VBATT.
■ ACA device
■ Targeted USB peripheral
■ SRP-capable USB peripheral
■ HNP-capable USB peripheral
■ OTG host
Figure 4. System Diagram with OVP Device For VBUS
POWER SUBSYSTEM
■ HNP-capable host
■ OTG device
ReNumeration
Because of FX3's soft configuration, one chip can take on the
identities of multiple distinct USB devices.
EZ-USB FX3
When first plugged into USB, FX3 enumerates automatically with
the Cypress Vendor ID (0x04B4) and downloads firmware and
USB descriptors over the USB interface. The downloaded
firmware executes an electrical disconnect and connect. FX3
enumerates again, this time as a device defined by the
downloaded information. This patented two-step process, called
ReNumeration, happens instantly when the device is plugged in.
VBUS
OTG_ID
1
2
OVP device
SSRX-
SSRX+
SSTX-
SSTX+
D-
3
4
5
6
7
8
9
D+
GND
EZ-Dtect
FX3 supports USB Charger and accessory detection (EZ-Dtect).
The charger detection mechanism complies with the Battery
Charging Specification Revision 1.1. In addition to supporting
this version of the specification, FX3 also provides hardware
support to detect the resistance values on the ID pin.
Carkit UART Mode
The USB interface supports the Carkit UART mode (UART over
D+/D–) for non-USB serial data transfer. This mode is based on
the CEA-936A specification.
FX3 can detect the following resistance ranges:
■ Less than 10
In the Carkit UART mode, the output signaling voltage is 3.3 V.
When configured for the Carkit UART mode, TXD of UART
(output) is mapped to the D– line, and RXD of UART (input) is
mapped to the D+ line.
■ Less than 1 k
■ 65 k to 72 k
■ 35 kto 39 k
In the Carkit UART mode, FX3 disables the USB transceiver and
D+ and D– pins serve as pass-through pins to connect to the
UART of the host processor. The Carkit UART signals may be
routed to the GPIF II interface or to GPIO[48] and GPIO[49], as
shown in Figure 5 on page 7.
■ 99.96 k to 104.4 k (102 k2%)
■ 119 k to 132 k
■ Higher than 220 k
In this mode, FX3 supports a rate of up to 9600 bps.
■ 431.2 k to 448.8 k (440 k2%)
FX3's charger detects a dedicated wall charger, Host/Hub
charger, and Host/Hub.
Document Number: 001-52136 Rev. *N
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CYUSB301X
Figure 5. Carkit UART Pass-through Block Diagram
Carkit UART Pass-through
UART_TXD
UART_RXD
TXD
RXD
RXD(DP)
TXD(DM)
(
)
Carkit UART Pass-through
Interface on GPIF II
DP
USB PHY
DM
GPIO[48]
(UART_TX)
Carkit UART Pass-through
Interface on GPIOs
GPIO[49]
(UART_RX)
Note Access to all 32 buffers is also supported over the slave
FIFO interface. For details, contact Cypress Applications
Support.
GPIF II
The high-performance GPIF II interface enables functionality
similar to, but more advanced than, FX2LP’s GPIF and Slave
FIFO interfaces.
Figure 6. Slave FIFO Interface
SLCS#
PKTEND
FLAGB
FLAGA
The GPIF II is a programmable state machine that enables a
flexible interface that may function either as a master or slave in
industry-standard or proprietary interfaces. Both parallel and
serial interfaces may be implemented with GPIF II.
A[1:0]
External
Processor
D[31:0]
SLWR#
SLRD#
Here are a list of GPIF II features:
EZ-USB FX3
■ Functions as master or slave
■ Provides 256 firmware programmable states
■ Supports 8-bit, 16-bit, and 32-bit parallel data bus
■ Enables interface frequencies up to 100 MHz
SLOE#
Note: Multiple Flags may be configured.
■ Supports 14 configurable control pins when a 32- bit data bus
is used. All control pins can be either input/output or bidirec-
tional.
CPU
FX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.
The core has direct access to 16 kB of Instruction Tightly
Coupled Memory (TCM) and 8 kB of Data TCM. The
ARM926EJ-S core provides a JTAG interface for firmware
debugging.
■ Supports 16 configurable control pins when a 16/8 data bus is
used. Allcontrolpins can be either input/outputor bi-directional.
GPIF II state transitions are based on control input signals. The
control output signals are driven as a result of the GPIF II state
transitions. The INT# output signal can be controlled by GPIF II.
Refer to the GPIFII Designer tool. The GPIF II state machine’s
behavior is defined by a GPIF II descriptor. The GPIF II
descriptor is designed such that the required interface specifica-
tions are met. 8 kB of memory (separate from the 512 kB of
embedded SRAM) is dedicated to the GPIF II waveform where
the GPIF II descriptor is stored in a specific format.
FX3 offers the following advantages:
■ Integrates 512 KB of embedded SRAM for code and data and
8 kB of Instruction cache and Data cache.
■ ImplementsefficientandflexibleDMAconnectivitybetweenthe
various peripherals (such as, USB, GPIF II, I2S, SPI, UART),
requiring firmware only to configure data accesses between
peripherals, which are then managed by the DMA fabric.
Cypress’s GPIFII Designer Tool enables fast development of
GPIF II descriptors and includes examples for common inter-
faces.
■ Allows easy application development on industry-standard
development tools for ARM926EJ-S.
Example implementations of GPIF II are the asynchronous slave
FIFO and synchronous slave FIFO interfaces.
Examples of the FX3 firmware are available with the Cypress
EZ-USB FX3 Development Kit. Software APIs that can be ported
to an external processor are available with the Cypress EZ-USB
FX3 Software Development Kit.
Slave FIFO interface
The Slave FIFO interface signals are shown in Figure 6. This
interface allows an external processor to directly access up to
four buffers internal to FX3. Further details of the Slave FIFO
interface are described on page 27.
Document Number: 001-52136 Rev. *N
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CYUSB301X
2
I C Interface
JTAG Interface
FX3’s I2C interface is compatible with the I2C Bus Specification
Revision 3. This I2C interface is capable of operating only as I2C
master; therefore, it may be used to communicate with other I2C
slave devices. For example, FX3 may boot from an EEPROM
connected to the I2C interface, as a selectable boot option.
FX3’s I2C Master Controller also supports multi-master mode
functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This
gives the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock-stretching
feature to enable slower devices to exercise flow control.
FX3’s JTAG interface has a standard five-pin interface to connect
to a JTAG debugger in order to debug firmware through the
CPU-core's on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core
can be used for the FX3 application development.
Other Interfaces
FX3 supports the following serial peripherals:
■ UART
■ I2C
■ I2S
■ SPI
The SPI, UART, and I2S interfaces are multiplexed on the serial
peripheral port.
The I2C interface’s SCL and SDA signals require external pull-up
resistors. The pull-up resistors must be connected to VIO5.
The CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit
Data Bus Width) on page 15 shows details of how these inter-
faces are multiplexed. Note that when GPIF II is configured for a
32-bit data bus width (CYUSB3012 and CYUSB3014), only the
UART interface is available on GPIO[53] to GPIO[56].
2
I S Interface
FX3 has an I2S port to support external audio codec devices.
FX3 functions as I2S Master as transmitter only. The I2S interface
consists of four signals: clock line (I2S_CLK), serial data line
(I2S_SD), word select line (I2S_WS), and master system clock
(I2S_MCLK). FX3 can generate the system clock as an output
on I2S_MCLK or accept an external system clock input on
I2S_MCLK.
UART Interface
The UART interface of FX3 supports full-duplex communication.
It includes the signals noted in Table 1.
Table 1. UART Interface Signals
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
Signal
TX
Description
Output signal
Input signal
Flow control
Flow control
RX
SPI Interface
CTS
RTS
FX3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 36 for details on the
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then FX3's UART only transmits data when the CTS
input is asserted. In addition to this, FX3’s UART asserts the RTS
output signal, when it is ready to receive data.
modes) with the Start-Stop clock. This controller is
a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Document Number: 001-52136 Rev. *N
Page 8 of 45
CYUSB301X
Boot Options
Clocking
FX3 can load boot images from various sources, selected by the
configuration of the PMODE pins. Following are the FX3 boot
options:
FX3 allows either a crystal to be connected between the XTALIN
and XTALOUT pins or an external clock to be connected at the
CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins
can be left unconnected if they are not used.
■ Boot from USB
■ Boot from I2C
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),
M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents
FX3 has an on-chip oscillator circuit that uses an external
19.2-MHz (±100 ppm) crystal (when the crystal option is used).
An appropriate load capacitance is required with a crystal. Refer
to the specification of the crystal used to determine the appro-
priate load capacitance. The FSLC[2:0] pins must be configured
appropriately to select the crystal- or clock-frequency option. The
configuration options are shown in Table 3.
■ Boot from GPIF II ASync ADMux mode
■ Boot from GPIF II Sync ADMux mode
■ Boot from GPIF II ASync SRAM mode
Clock inputs to FX3 must meet the phase noise and jitter require-
ments specified in Table 4 on page 10.
Table 2. FX3 Booting Options
PMODE[2:0] [2]
Boot From
Sync ADMux (16-bit)
The input clock frequency is independent of the clock and data
rate of the FX3 core or any of the device interfaces (including
P-Port and S-Port). The internal PLL applies the appropriate
clock multiply option depending on the input frequency.
F00
F01
F11
F0F
F1F
1FF
0F1
Async ADMux (16-bit)
USB boot
Async SRAM (16-bit)
I2C, On Failure, USB Boot is Enabled
I2C only
Table 3. Crystal/Clock Frequency Selection
Crystal/Clock
FSLC[2]
FSLC[1]
FSLC[0]
SPI, On Failure, USB Boot is Enabled
Frequency
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
19.2-MHz crystal
19.2-MHz input CLK
26-MHz input CLK
38.4-MHz input CLK
52-MHz input CLK
Reset
Hard Reset
A hard reset is initiated by asserting the Reset# pin on FX3. The
specific reset sequence and timing requirements are detailed in
Figure 19 on page 38 and Table 16 on page 38. All I/Os are
tristated during a hard reset.
Soft Reset
In a soft reset, the processor sets the appropriate bits in the
PP_INIT control register. There are two types of Soft Reset:
■ CPU Reset – The CPU Program Counter is reset. Firmware
does not need to be reloaded following a CPU Reset.
■ Whole Device Reset – This reset is identical to Hard Reset.
■ The firmware must be reloaded following a Whole Device
Reset.
Note
2. F indicates Floating.
Document Number: 001-52136 Rev. *N
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CYUSB301X
Table 4. FX3 Input Clock Specifications
Parameter
Specification
Description
Units
Min
–
Max
–75
–104
–120
–128
–130
150
70
Phase noise
100-Hz offset
1- kHz offset
dB
dB
dB
dB
dB
ppm
%
–
10-kHz offset
100-kHz offset
1-MHz offset
–
–
–
Maximum frequency deviation
Duty cycle
–
30
–
Overshoot
3
%
Undershoot
–
–3
%
Rise time/fall time
–
3
ns
❐ CVDDQ: Clock
32-kHz Watchdog Timer Clock Input
❐ VDD: This is the supply voltage for the logic core. The nominal
supply-voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-
tor, and other core analog circuits
• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-
ages for the USB 3.0 interface.
FX3 includes a watchdog timer. The watchdog timer can be used
to interrupt the ARM926EJ-S core, automatically wake up the
FX3 in Standby mode, and reset the ARM926EJ-S core. The
watchdog timer runs a 32-kHz clock, which may be optionally
supplied from an external source on a dedicated FX3 pin.
The firmware can disable the watchdog timer.
Requirements for the optional 32-kHz clock input are listed in
Table 5.
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through FX3's internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Table 5. 32-kHz Clock Input Requirements
Parameter
Duty cycle
Min
40
–
Max
60
Units
%
Power Modes
Frequency deviation
Rise time/fall time
±200
200
ppm
ns
FX3 supports the following power modes:
–
■ Normal mode: This is the full-functional operating mode. The
internal CPU clock and the internal PLLs are enabled in this
mode.
❐ Normal operating power consumption does not exceed the
sum of ICC Core max and ICC USB max (see Table 7 for
current consumption specifications).
Power
FX3 has the following power supply domains:
■ IO_VDDQ: This is a group of independent supply domains for
digitalI/Os.Thevoltagelevelonthesesuppliesis1.8 Vto3.3 V.
FX3 provides six independent supply domains for digital I/Os
listed as follows (see Table 7 for details on each of the power
domain signals):
❐ VIO1: GPIF II I/O
❐ VIO2: IO2
❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be
turned off when the corresponding interface is not in use.
VIO1 cannot be turned off at any time if the GPIF II interface
is used in the application.
■ Low-power modes (see Table 6 on page 11):
❐ Suspend mode with USB 3.0 PHY enabled (L1)
❐ Suspend mode with USB 3.0 PHY disabled (L2)
❐ Standby mode (L3)
❐ VIO3: IO3
❐ VIO4: UART-/SPI/I2S
❐ VIO5: I2C and JTAG (supports 1.2 V to 3.3 V)
❐ Core power-down mode (L4)
Document Number: 001-52136 Rev. *N
Page 10 of 45
CYUSB301X
Table 6. Entry and Exit Methods for Low-Power Modes
Low-Power Mode Characteristics
Suspend Mode with ■ Thepowerconsumptioninthismodedoes ■ Firmware executing on
Methods of Entry
Methods of Exit
■ D+ transitioning to low
or high
USB 3.0 PHY
Enabled (L1)
not exceed ISB1
ARM926EJ-S core can put FX3 into
suspend mode. For example, on
USB suspend condition, firmware
may decide to put FX3 into suspend
mode
■ USB3.0PHYisenabledandisinU3mode
(one of the suspend modes defined by the
USB 3.0 specification). This one block
alone is operational with its internal clock
while all other clocks are shut down
■ D- transitioning to low
or high
■ Impedance change on
OTG_ID pin
■ External Processor, through the use
of mailbox registers, can put FX3 into
suspend mode
■ Resume condition on
SSRX±
■ All I/Os maintain their previous state
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
■ Detection of VBUS
■ Level detect on
UART_CTS (program-
mable polarity)
■ The states of the configuration registers,
buffer memory, and all internal RAM are
maintained
■ GPIF II interface
assertion of CTL[0]
■ All transactions must be completed before
FX3 enters Suspend mode (state of
outstanding transactions are not
preserved)
■ Assertion of RESET#
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Suspend Mode with ■ Thepowerconsumptioninthismodedoes ■ Firmware executing on
■ D+ transitioning to low
or high
USB 3.0 PHY
Disabled (L2)
not exceed ISB2
ARM926EJ-S core can put FX3 into
suspend mode. For example, on
USB suspend condition, firmware
may decide to put FX3 into suspend
mode
■ USB 3.0 PHY is disabled and the USB
■ D- transitioning to low
or high
interface is in suspend mode
■ The clocks are shut off. The PLLs are
■ Impedance change on
disabled
OTG_ID pin
■ External Processor, through the use
of mailbox registers can put FX3 into
suspend mode
■ All I/Os maintain their previous state
■ Resume condition on
SSRX±
■ USB interface maintains the previous
state
■ Detection of VBUS
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
■ Level detect on
UART_CTS
(programmable
polarity)
■ The states of the configuration registers,
buffer memory and all internal RAM are
maintained
■ GPIF II interface
assertion of CTL[0]
■ Assertion of RESET#
■ All transactions must be completed before
FX3 enters Suspend mode (state of
outstanding transactions are not
preserved)
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Document Number: 001-52136 Rev. *N
Page 11 of 45
CYUSB301X
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low-Power Mode Characteristics
Standby Mode (L3) ■ Thepowerconsumptioninthismodedoes ■ Firmware executing on
Methods of Entry
Methods of Exit
■ Detection of VBUS
not exceed ISB3
ARM926EJ-S core or external
processorconfigurestheappropriate
register
■ Level detect on
UART_CTS
(Programmable
Polarity)
■ All configuration register settings and
program/data RAM contents are
preserved. However, data in the buffers or
other parts of the data path, if any, is not
guaranteed. Therefore, the external
processor should take care that the data
needed is read before putting FX3 into this
Standby Mode
■ GPIF II interface
assertion of CTL[0]
■ Assertion of RESET#
■ The program counter is reset after waking
up from Standby
■ GPIO pins maintain their configuration
■ Crystal oscillator is turned off
■ Internal PLL is turned off
■ USB transceiver is turned off
■ ARM926EJ-S core is powered down.
Upon wakeup, the core re-starts and runs
the program stored in the program/data
RAM
■ Power supply for the wakeup source and
core power must be retained. All other
power domains can be turned on/off
individually
Core Power Down ■ Thepowerconsumptioninthismodedoes ■ Turn off VDD
■ Reapply VDD
Mode (L4)
not exceed ISB4
■ Assertion of RESET#
■ Core power is turned off
■ All buffer memory, configuration registers,
and the program RAM do not maintain
state. After exiting this mode, reload the
firmware
■ In this mode, all other power domains can
be turned on/off individually
Document Number: 001-52136 Rev. *N
Page 12 of 45
CYUSB301X
Similarly, any unused pins on the serial peripheral interfaces may
be configured as GPIOs. See Pin Configurations for pin
configuration options.
Configuration Options
Configuration options are available for specific usage models.
Contact Cypress Applications or Marketing for details.
All GPIF II and GPIO pins support an external load of up to 16 pF
for every pin.
Digital I/Os
EMI
FX3 has internal firmware-controlled pull-up or pull-down
resistors on all digital I/O pins. An internal 50-k resistor pulls
the pins high, while an internal 10-k resistor pulls the pins low
to prevent them from floating. The I/O pins may have the
following states:
FX3 meets EMI requirements outlined by FCC 15B (USA) and
EN55022 (Europe) for consumer electronics. FX3 can tolerate
reasonable EMI, conducted by the aggressor, outlined by these
specifications and continue to function as expected.
■ Tristated (High-Z)
System-level ESD
■ Weak pull-up (via internal 50 k)
FX3 has built-in ESD protection on the D+, D–, and GND pins on
the USB interface. The ESD protection levels provided on these
ports are:
■ Pull-down (via internal 10 k)
■ Hold (I/O hold its value) when in low-power modes
■ ±2.2-KV human body model (HBM) based on JESD22-A114
Specification
■ The JTAG TDI, TMC, and TRST# signals have fixed 50-k
internal pull-ups, and the TCK signal has a fixed 10-k
pull-down resistor.
■ ±6-KV contact discharge and ±8-KV air gap discharge based
on IEC61000-4-2 level 3A
All unused I/Os should be pulled high by using the internal
pull-up resistors. All unused outputs should be left floating. All
I/Os can be driven at full-strength, three-quarter strength,
half-strength, or quarter-strength. These drive strengths are
configured separately for each interface.
■ ± 8-KV Contact Discharge and ±15-KV Air Gap Discharge
based on IEC61000-4-2 level 4C.
This protection ensures the device continues to function after
ESD events up to the levels stated in this section.
GPIOs
The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to
±2.2-KV HBM internal ESD protection.
EZ-USB enables a flexible pin configuration both on the GPIF II
and the serial peripheral interfaces. Any unused control pins
(except CTL[15]) on the GPIF II interface can be used as GPIOs.
Pin Configurations
Figure 7. FX3 121-ball BGA Ball Map (Top View)
1
2
3
4
5
6
7
8
9
10
11
NC
U3VSSQ
VIO4
U3RXVDDQ
FSLC[0]
GPIO[ 55]
GPIO[51]
VSS
SSRXM
R_USB3
VDD
SSRXP
SSTXP
SSTXM
AVDD
VSS
VSS
DP
DM
A
B
C
D
E
F
G
H
J
FSLC[1]
GPIO[ 57]
GPIO[53]
GPIO[49]
GPIO[ 41]
GPIO[30]
GPIO[ 31]
GPIO[34]
VSS
U3TXVDDQ
RESET#
GPIO[56]
GPIO[48]
GPIO[ 46]
GPIO[25]
GPIO[ 29]
GPIO[28]
GPIO[27]
VDD
CVDDQ
XTALIN
CLKIN_32
FSLC[2]
TCK
AVSS
XTALOUT
CLKIN
VSS
VDD
TDO
TRST#
VIO5
O[60]
VBUS
VDD
GPIO[ 54]
GPIO[50]
GPIO[ 47]
VIO2
R_USB2
VSS
OTG_ID
GPIO[52]
VIO3
I2C_GPIO[58] I2C_GPIO[59]
TDI
TMS
VDD
GPIO[ 1]
GPIO[4]
GPIO[ 7]
GPIO[9]
GPIO[13]
VIO1
VBATT
GPIO[ 0]
GPIO[3]
GPIO[ 6]
GPIO[8]
GPIO[12]
GPIO[11]
GPIO[ 45]
GPIO[42]
GPIO[ 39]
GPIO[36]
GPIO[33]
VSS
GPIO[ 44]
GPIO[43]
GPIO[ 40]
GPIO[37]
VSS
GPIO[ 2]
GPIO[21]
GPIO[ 20]
GPIO[19]
GPIO[18]
VDD
GPIO[ 5]
GPIO[15]
GPIO[ 24]
GPIO[14]
GPIO[17]
INT#
VSS
GPIO[22]
GPIO[ 26]
GPIO[16]
GPIO[23]
VSS
VSS
VDD
VIO1
VDD
GPIO[38]
GPIO[35]
VSS
GPIO[10]
VSS
K
L
VSS
GPIO[32]
Document Number: 001-52136 Rev. *N
Page 13 of 45
CYUSB301X
Figure 8. FX3 131-Ball CSP Ball Map (Bottom View)
12
11
10
9
8
7
6
5
4
3
2
1
VSS
VSS
VIO4
VIO3
SSRXM
SSTXM
FSLC[0]
FSLC[2]
CVDDQ
AVSS
AVDD
DP
NC
VSS
VSS
DM
NC
VDD
VDD
TRST#
A
B
C
GPIO[55]
GPIO[56]
SSRXP
R_USB3
U3VSSQ
SSTXP
XTALIN
CLKIN_32
XTALOUT
CLKIN
R_USB2
OTG_ID
U3RXVDDQ
U3TXVDDQ
TDO
I2C_GPIO[58
]
I2C_GPIO[59
]
GPIO[49]
GPIO[50]
GPIO[53]
GPIO[54]
RESET#
VDD
TMS
VIO5
TCK
VSS
D
E
F
G
H
J
GPIO[57]
VSS
GPIO[48]
GPIO[46]
GPIO[43]
GPIO[40]
GPIO[38]
GPIO[34]
VSS
GPIO[51]
GPIO[47]
GPIO[44]
GPIO[41]
GPIO[37]
GPIO[33]
VDD
GPIO[52]
FSLC[1]
O[60]
TDI
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
GPIO[3]
GPIO[4]
GPIO[7]
GPIO[12]
GPIO[15]
GPIO[24]
GPIO[17]
VBATT
GPIO[1]
VBUS
GPIO[0]
GPIO[2]
VIO1
VIO2
GPIO[45]
GPIO[42]
GPIO[36]
GPIO[32]
GPIO[30]
VSS
VSS
VDD
VSS
GPIO[9]
GPIO[14]
GPIO[19]
INT#
GPIO[6]
GPIO[8]
GPIO[10]
GPIO[11]
GPIO[13]
VSS
GPIO[39]
GPIO[31]
GPIO[28]
GPIO[29]
VSS
GPIO[20]
GPIO[25]
GPIO[16]
GPIO[23]
GPIO[18]
GPIO[22]
GPIO[21]
VSS
VIO2
GPIO[27]
GPIO[26]
VIO1
GPIO[5]
VSS
GPIO[35]
VDD
K
L
VIO1
VSS
Note No ball is populated at location A9
Document Number: 001-52136 Rev. *N
Page 14 of 45
CYUSB301X
Pin Description
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width)
BGA
WLCSP
I/O
Name
Description
GPIF II (VIO1 Power Domain)
GPIF II Interface
DQ[0]
Slave FIFO Interface
F10
F9
F1
F2
G1
E3
F3
J1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
CVDDQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
INT#
DQ[0]
DQ[1]
DQ[1]
F7
DQ[2]
DQ[2]
G10
G9
F8
DQ[3]
DQ[3]
DQ[4]
DQ[4]
DQ[5]
DQ[5]
H10
H9
J10
J9
G2
G3
H2
G4
J2
DQ[6]
DQ[6]
DQ[7]
DQ[7]
DQ[8]
DQ[8]
DQ[9]
DQ[9]
K11
L10
K10
K9
J8
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
PCLK
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
CLK
K2
H3
L2
H4
J3
G8
J6
K6
L3
H5
J4
K8
K7
J7
CTL[0]
SLCS#
SLWR#
SLOE#
SLRD#
FLAGA
FLAGB
GPIO
CTL[1]
CTL[2]
H7
G7
G6
K6
H8
G5
H6
K5
J5
H6
K5
J5
CTL[3]
CTL[4]
CTL[5]
L6
K3
J6
CTL[6]
CTL[7]
PKTEND#
GPIO
CTL[8]
K7
J7
CTL[9]
GPIO
CTL[10]
CTL[11]
CTL[12]
PMODE[0]
PMODE[1]
PMODE[2]
INT#/CTL[15]
RESET#
GPIO
K8
L8
L9
J8
A1
H5
G4
H4
L4
A0
PMODE[0]
PMODE[1]
PMODE[2]
CTL[15]
RESET#
K9
K4
D8
L8
C5
RESET#
Note
3. When GPIF II is configured for the 32-bit data bus width, GPIO[50]-GPIO[52] may be configured as GPIOs or I2S, and GPIO[53] to GPIO[56] may be configured as
GPIOs or UART interface only.
Document Number: 001-52136 Rev. *N
Page 15 of 45
CYUSB301X
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued)
BGA
WLCSP
I/O
Name
Description
IO2 (VIO2 Power Domain)
GPIF II (32-bit data mode)
K2
J4
K10
K11
K12
J9
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
GPIO[38]
GPIO[39]
GPIO[40]
GPIO[41]
GPIO[42]
GPIO[43]
GPIO[44]
GPIO[45]
DQ[16]
DQ[17]
DQ[18]
DQ[19]
DQ[20]
DQ[21]
DQ[22]
DQ[23]
DQ[24]
DQ[25]
DQ[26]
DQ[27]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
K1
J2
J3
J10
J11
H8
J1
H2
H3
F4
G2
G3
F3
F2
H11
H10
H9
G11
G10
G09
GPIO
IO3 (VIO3 Power Domain)
GPIO + SPI
GPIO
GPIO + UART
GPIO
GPIO
only
GPIF II - 32b +
GPIO +
I2S
UART +
I2S + UART[3]
DQ[28]
SPI + I2S
F5
E1
F11
F10
VIO3
VIO3
I/O
I/O
GPIO[46]
GPIO[47]
GPIO
GPIO
UART_RT
S
GPIO
GPIO
GPIO
DQ[29]
GPIO
UART_CT
S
E5
E4
E11
D12
VIO3
VIO3
I/O
I/O
GPIO[48]
GPIO[49]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DQ[30]
DQ[31]
GPIO
GPIO
UART_TX
UART_R
X
D1
D2
D3
D11
E10
E9
VIO3
VIO3
VIO3
I/O
I/O
I/O
GPIO[50]
GPIO[51]
GPIO[52]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I2S_CLK
I2S_SD
I2S_WS
GPIO
GPIO
GPIO
I2S_CLK
I2S_SD
I2S_WS
IO4 (VIO4) Power Domain
D4
C1
C2
D10
D9
VIO4
VIO4
VIO4
I/O
I/O
I/O
GPIO[53]
GPIO[54]
GPIO[55]
SPI_SCK
SPI_SSN
SPI_MISO
UART_RTS
UART_CTS
UART_TX
GPIO
GPIO
GPIO
UART_RTS
GPIO
I2S_CLK
I2S_SD
SPI_SCK
SPI_SSN
UART_CTS
UART_TX
B12
SPI_MIS
O
D5
C4
C12
E12
VIO4
VIO4
I/O
I/O
GPIO[56]
GPIO[57]
SPI_MOSI
GPIO
UART_RX
GPIO
GPIO
GPIO
UART_RX
I2S_MCLK
I2S_WS
SPI_MOS
I
I2S_MCL
K
I2S_MCL
K
USB Port (VBATT/VBUS Power Domain)
C9
C3
VBUS/
VBATT
I
OTG_ID
OTG_ID
USB Port (U3TXVDDQ/U3RXVDDQ Power Domain)
A3
A4
A6
A5
A10
B10
A8
U3RXVD
DQ
I
SSRXM
SSRXP
SSTXM
SSTXP
SSRX-
U3RXVD
DQ
I
SSRX+
SSTX-
SSTX+
U3TXVD
DQ
O
O
B8
U3TXVD
DQ
Document Number: 001-52136 Rev. *N
Page 16 of 45
CYUSB301X
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued)
BGA
WLCSP
I/O
Name
Description
USB Port (VBATT/VBUS Power Domain)
A9
A4
A2
VBUS/V
BATT
I/O
I/O
DP
D+
A10
VBUS/V
BATT
DM
D–
B4
B2
NC
NC
No connect
A11
No connect
Crystal/Clocks (CVDDQ Power Domain)
B2
C6
C7
B4
E6
D7
D6
A7
B6
B5
F9
B7
C5
C6
CVDDQ
AVDD
I
FSLC[0]
XTALIN
FSLC[0]
I/O
XTALIN
AVDD
I/O
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
XTALOUT
CVDDQ
CVDDQ
CVDDQ
CVDDQ
I
I
I
I
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
CLKIN_32
I2C and JTAG (VIO5 Power Domain)
D9
D10
E7
D6
D2
F8
C2
C1
D5
D3
E8
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
I/O
I2C_GPIO[58]
I2C_GPIO[59]
TDI
I2C_SCL
I/O
I2C_SDA
I
O
I
TDI
C10
B11
E8
TDO
TDO
TRST#
TRST#
TMS
I
TMS
F6
I
TCK
TCK
D11
O
O[60]
Charger detect output
Power
E10
B10
E2
B1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VBATT
VDD
A1
VDD
A1
E11
D8
C9
U3VSSQ
VBUS
VSS
E1
C4
H11
E2
H1
VIO1
VSS
K1
L9
L4
VIO1
VSS
G1
L5
L7
VIO1
VSS
L1
F1
J12
H12
G12
C11
F12
B11
A11
A12
C7
VIO2
VSS
G11
VIO2
E3
PWR
VIO3
L1
B1
L6
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VSS
VIO4
VSS
VSS
B6
B5
CVDDQ
U3TXVDDQ
U3RXVDDQ
VIO5
C8
A2
C10
D4
C11
Document Number: 001-52136 Rev. *N
Page 17 of 45
CYUSB301X
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued)
BGA
L11
A7
WLCSP
A3
I/O
Name
VSS
AVDD
AVSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
Description
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
A5
B7
A6
C3
F4
B8
D1
F5
E9
B9
E4
F11
F6
E5
GND
F7
E6
GND
GND
E7
H1
L7
G6
D7
J11
L5
L10
L12
H7
G7
L11
G8
G5
K4
L3
K3
L2
A8
Precision Resistors
C8
B3
B3
B9
VBUS/V
BATT
I/O
I/O
R_usb2
R_usb3
Precision resistor for USB 2.0 (Connect a 6.04 k±1% resistor between this pin and GND)
U3TXVD
DQ
Precision resistor for USB 3.0 (Connect a 200 ±1% resistor between this pin and GND)
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width)
Pin
I/O
Name
Description
GPIF II (VIO1 Power Domain)
GPIF II Interface
DQ[0]
Slave FIFO Interface
F10
F9
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
DQ[0]
DQ[1]
DQ[2]
DQ[3]
DQ[4]
DQ[5]
DQ[6]
DQ[7]
DQ[8]
DQ[9]
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
DQ[1]
F7
DQ[2]
G10
G9
F8
DQ[3]
DQ[4]
DQ[5]
H10
H9
DQ[6]
DQ[7]
J10
J9
DQ[8]
DQ[9]
K11
L10
K10
K9
DQ[10]
DQ[11]
DQ[12]
DQ[13]
DQ[14]
DQ[15]
J8
G8
Document Number: 001-52136 Rev. *N
Page 18 of 45
CYUSB301X
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued)
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Name
Description
J6
K8
K7
J7
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
VIO1
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
INT#
PCLK
CTL[0]
CLK
SLCS#
SLWR#
SLOE#
SLRD#
FLAGA
FLAGB
GPIO
CTL[1]
CTL[2]
H7
G7
G6
K6
H8
G5
H6
K5
J5
CTL[3]
CTL[4]
CTL[5]
CTL[6]
CTL[7]
PKTEND#
GPIO
CTL[8]
CTL[9]
GPIO
CTL[10]
CTL[11]
CTL[12]
PMODE[0]
PMODE[1]
PMODE[2]
INT#/CTL[15]
RESET#
GPIO
A1
H5
G4
H4
L4
A0
PMODE[0]
PMODE[1]
PMODE[2]
CTL[15]
RESET#
L8
C5
CVDDQ
RESET#
IO2 (VIO2 Power Domain)
K2
J4
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
VIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[33]
GPIO[34]
GPIO[35]
GPIO[36]
GPIO[37]
GPIO[38]
GPIO[39]
GPIO[40]
GPIO[41]
GPIO[42]
GPIO[43]
GPIO[44]
GPIO[45]
GPIO
GPIO
K1
J2
GPIO
GPIO
J3
GPIO
J1
GPIO
H2
H3
F4
G2
G3
F3
F2
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO3 (VIO3 Power Domain)
F5
E1
E5
E4
D1
D2
D3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
VIO3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I2S_CLK
I2S_SD
I2S_WS
GPIO
GPIO
GPIO
I2S_CLK
I2S_SD
I2S_WS
IO4 (VIO4) Power Domain
D4
C1
C2
D5
VIO4
VIO4
VIO4
VIO4
I/O
I/O
I/O
I/O
GPIO[53]
GPIO[54]
GPIO[55]
GPIO[56]
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
UART_RTS
UART_CTS
UART_TX
UART_RX
GPIO
GPIO
GPIO
GPIO
UART_RTS
UART_CTS
UART_TX
UART_RX
GPIO
SPI_SCK
SPI_SSN
SPI_MISO
SPI_MOSI
I2S_CLK
UART_TX
UART_RX
Document Number: 001-52136 Rev. *N
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CYUSB301X
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued)
Pin
I/O
Name
Description
GPIO I2S_MCLK
C4
C9
VIO4
I/O
GPIO[57]
GPIO
GPIO
I2S_MCLK
I2S_MCLK
USB Port (VBATT/VBUS Power Domain)
VBUS/
VBATT
I
OTG_ID
OTG_ID
USB Port (U3TXVDDQ/U3RXVDDQ Power Domain)
A3
A4
A6
A5
U3RXVDDQ
U3RXVDDQ
U3TXVDDQ
U3TXVDDQ
I
I
SSRXM
SSRXP
SSTXM
SSTXP
SSRX-
SSRX+
O
O
SSTX-
SSTX+
USB Port (VBATT/VBUS Power Domain)
A9
VBUS/VBATT
VBUS/VBATT
I/O
I/O
DP
DM
NC
D+
A10
A11
D–
No connect
Crystal/Clocks (CVDDQ Power Domain)
B2
C6
C7
B4
E6
D7
D6
CVDDQ
AVDD
I
FSLC[0]
XTALIN
FSLC[0]
I/O
XTALIN
AVDD
I/O
XTALOUT
FSLC[1]
FSLC[2]
CLKIN
XTALOUT
CVDDQ
CVDDQ
CVDDQ
CVDDQ
I
I
I
I
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
CLKIN_32
I2C and JTAG (VIO5 Power Domain)
D9
D10
E7
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
VIO5
I/O
I2C_GPIO[58]
I2C_GPIO[59]
TDI
I2C_SCL
I/O
I2C_SDA
I
O
I
TDI
C10
B11
E8
TDO
TDO
TRST#
TRST#
TMS
I
TMS
F6
I
TCK
TCK
D11
O
O[60]
Charger detect output
Power
E10
B10
A1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VBATT
VDD
U3VSSQ
VBUS
VSS
E11
D8
H11
E2
VIO1
VSS
L9
VIO1
VSS
G1
F1
VIO2
VSS
G11
E3
PWR
VIO3
L1
B1
L6
PWR
PWR
PWR
VSS
VIO4
VSS
Document Number: 001-52136 Rev. *N
Page 20 of 45
CYUSB301X
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued)
Pin
I/O
Name
CVDDQ
U3TXVDDQ
U3RXVDDQ
VIO5
Description
B6
B5
A2
C11
L11
A7
B7
C3
B8
E9
B9
F11
H1
L7
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VSS
AVDD
AVSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
J11
L5
VDD
VDD
K4
L3
VSS
VSS
K3
L2
VSS
VSS
A8
VSS
Precision Resistors
C8
B3
VBUS/VBATT
U3TXVDDQ
I/O
I/O
R_usb2
R_usb3
Precision resistor for USB 2.0 (Connect a 6.04 k±1% resistor between this pin and GND)
Precision resistor for USB 3.0 (Connect a 200 ±1% resistor between this pin and GND)
Document Number: 001-52136 Rev. *N
Page 21 of 45
CYUSB301X
■ ± 6-KV contact discharge, ± 8-KV air gap discharge based on
IEC61000-4-2 level 3A, ± 8-KV contact discharge, and ± 15-KV
air gap discharge based on IEC61000-4-2 level 4C
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device.
Latch-up current .........................................................> 200 mA
Storage temperature .................................... –65 °C to +150 °C
Maximum output short-circuit current
for all I/O configurations. (Vout = 0 V) ........................ –100 mA
Ambient temperature with
power supplied (Industrial) ............................ –40 °C to +85 °C
Operating Conditions
Ambient temperature with
power supplied (Commercial) ............................. 0 °C to +70 °C
TA (ambient temperature under bias)
Supply voltage to ground potential
Industrial ........................................................ –40 °C to +85 °C
Commercial ....................................................... 0 °C to +70 °C
VDD, AVDDQ ......................................................................1.25 V
VIO1,VIO2, VIO3, VIO4, VIO5 ................................................3.6 V
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
U3TXVDDQ, U3RXVDDQ ...................................................1.25 V
DC input voltage to any input pin ........................... .VCC + 0.3 V
Supply voltage ..................................................1.15 V to 1.25 V
V
BATT supply voltage ...............................................3.2 V to 6 V
IO1, VIO2, VIO3, VIO4, CVDDQ
DC voltage applied to
outputs in high Z state ............................................ VCC + 0.3 V
V
Supply voltage ......................................................1.7 V to 3.6 V
IO5 supply voltage ............................................ 1.15 V to 3.6 V
(VCC is the corresponding I/O voltage)
V
Static discharge voltage ESD protection levels:
■ ± 2.2-KV HBM based on JESD22-A114
■ Additional ESD protectionlevels on D+, D–, and GND pins, and
serial peripheral pins
DC Specifications
Parameter
VDD
Description
Core voltage supply
Min
1.15
1.15
1.7
Max
1.25
1.25
3.6
3.6
3.6
3.6
6
Units
V
Notes
1.2-V typical
1.2-V typical
AVDD
VIO1
Analog voltage supply
V
GPIF II I/O power supply domain
IO2 power supply domain
IO3 power supply domain
UART/SPI/I2S power supply domain
USB voltage supply
V
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
1.8-, 2.5-, and 3.3-V typical
3.7-V typical
VIO2
1.7
V
VIO3
1.7
V
VIO4
1.7
V
VBATT
VBUS
U3TXVDDQ
3.2
V
USB voltage supply
4.0
6
V
5-V typical
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass capacitor is
required on this power supply.
U3RXVDDQ
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass capacitor is
required on this power supply.
CVDDQ
VIO5
Clock voltage supply
I2C and JTAG voltage supply
1.7
3.6
3.6
V
V
V
1.8-, 3.3-V typical
1.15
1.2-, 1.8-, 2.5-, and 3.3-V typical
VIH1
Input HIGH voltage 1
0.625 ×
VCC
VCC + 0.3
For 2.0 V VCC 3.6 V (except USB
port).VCC is the corresponding I/O
voltage supply.
VIH2
Input HIGH voltage 2
VCC – 0.4 VCC + 0.3
V
For 1.7 V VCC 2.0 V
(except USB port).VCC is the corre-
sponding I/O voltage supply.
VIL
Input LOW voltage
–0.3
0.25 × VCC
–
V
V
VCC is the corresponding I/O voltage
supply.
VOH
Output HIGH voltage
0.9 × VCC
IOH (max) = –100 µA tested at quarter
drive strength. VCC is the corresponding
I/O voltage supply.
Document Number: 001-52136 Rev. *N
Page 22 of 45
CYUSB301X
DC Specifications (continued)
Parameter
VOL
Description
Min
Max
Units
Notes
Output LOW voltage
–
0.1 × VCC
V
IOL (min) = +100 µA tested at quarter
drive strength. VCC is the corresponding
I/O voltage supply.
IIX
Input leakage current for all pins except
SSTXP/SSXM/SSRXP/SSRXM
–1
1
µA All I/O signals held at VDDQ
(For I/Os with a pull-up or pull-down
resistor connected, the leakage current
increases by VDDQ/Rpu or VDDQ/RPD
IOZ
Output High-Z leakage current for all pins
except SSTXP/ SSXM/ SSRXP/SSRXM
–1
–
1
µA All I/O signals held at VDDQ
mA Total current through AVDD, VDD
mA
ICC Core
Core and analog voltage operating
current
200
ICC USB
ISB1
USB voltage supply operating current
–
–
60
–
Total suspend current during suspend
mode with USB 3.0 PHY enabled (L1)
mA Core current: 1.5 mA
I/O current: 20 µA
USB current: 2 mA
For typical PVT (typical silicon, all power
supplies at their respective nominal
levels at 25 °C.)
ISB2
ISB3
ISB4
Total suspend current during suspend
mode with USB 3.0 PHY disabled (L2)
–
–
–
–
–
–
mA Core current: 250 µA
I/O current: 20 µA
USB current: 1.2 mA
For typical PVT (Typical silicon, all power
supplies at their respective nominal
levels at 25 °C.)
Total standby current during standby
mode (L3)
µA Core current: 60 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (typical silicon, all power
supplies at their respective nominal
levels at 25 °C.)
Total standby current during core
power-down mode (L4)
µA Core current: 0 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (typical silicon, all power
supplies at their respective nominal
levels at 25 °C.)
VRAMP
VN
Voltage ramp rate on core and I/O
supplies
0.2
–
50
100
20
V/ms Voltage ramp must be monotonic
Noise level permitted on VDD and I/O
supplies
mV Max p-p noise level permitted on all
supplies except AVDD
VN_AVDD
Noise level permitted on AVDD supply
–
mV Max p-p noise level permitted on AVDD
Document Number: 001-52136 Rev. *N
Page 23 of 45
CYUSB301X
AC Timing Parameters
GPIF II Timing
Figure 9. GPIF II Timing in Synchronous Mode
tCLKH tCLKL
CLK
tCLK
tCO
tHZ
tDOH
tCOE
tDS tDH
tDOH
tLZ
tLZ
Data1
( OUT)
Data2
( OUT)
DQ- [31:0]
Data(IN)
tS tH
CTL(IN)
tCTLO
tCOH
CTL( OUT)
Table 9. GPIF II Timing Parameters in Synchronous Mode [4]
Parameter Description
Frequency
Min
–
Max
100
–
Units
MHz
ns
Interface clock frequency
Interface clock period
Clock high time
tCLK
tCLKH
tCLKL
tS
10
4
–
ns
Clock low time
4
–
ns
CTL input to clock setup time
CTL input to clock hold time
Data in to clock setup time
Data in to clock hold time
2
–
ns
tH
0.5
2
–
ns
tDS
–
ns
tDH
tCO
0.5
–
–
ns
Clock to data out propagation delay when DQ bus is already in
output direction
8
ns
tCOE
Clock to data out propagation delay when DQ lines change to
output from tristate and valid data is available on the DQ bus
-
9
tCTLO
tDOH
tCOH
tHZ
Clock to CTL out propagation delay
Clock to data out hold
Clock to CTL out hold
Clock to high-Z
–
2
0
–
0
8
–
–
8
–
ns
ns
ns
ns
ns
tLZ
Clock to low-Z
Note
4. All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N
Page 24 of 45
CYUSB301X
Figure 10. GPIF II Timing in Asynchronous Mode
tAH
tDH/
tDS/ tAS
DATA/ ADDR
DATA IN
tCHZ
tCTLassert_DQlatch
tCTLdeassert_DQlatch
CTL#
(I/P, ALE/ DLE)
tAA/tDO
tCHZ/tOEHZ
tCLZ/ tOELZ
DATA OUT
DATA OUT
CTL#
(I/P, non ALE/ DLE
tCTLdeassert
tCTLassert
tCTLalpha
tCTLbeta
ALPHA
O/P
BETA
O/P
1
1
tCTLassert
tCTLdeassert
tCTL#
(O/P)
1. n is an integer >= 0
tDST
tDHT
DATA/
ADDR
tCTLdeassert_DQassert
tCTLassert_DQassert
CTL#
I/P (non DLE/ALE)
Figure 11. GPIF II Timing in Asynchronous DDR Mode
tDS
tCTLdeassert_DqlatchDDR
tCTLassert_DQlatchDDR
CTL#
(I/P)
tDS
tDH
tDH
DATA IN
Document Number: 001-52136 Rev. *N
Page 25 of 45
CYUSB301X
[5, 6]
Table 10. GPIF II Timing in Asynchronous Mode
Note The following parameters assume one state transition
Parameter Description
Min
2.3
2
Max
Units
ns
tDS
tDH
tAS
tAH
Data In to DLE setup time. Valid in DDR async mode.
Data In to DLE hold time. Valid in DDR async mode.
Address In to ALE setup time
–
–
–
–
–
ns
2.3
2
ns
Address In to ALE hold time
ns
tCTLassert
CTL I/O asserted width for CTRL inputs without DQ input association
and for outputs.
7
ns
tCTLdeassert
CTL I/O deasserted width for CTRL inputs without DQ input associ-
ation and for outputs.
7
–
–
ns
ns
tCTLassert_DQassert
CTL asserted pulse width for CTL inputs that signify DQ inputs valid
at the asserting edge but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
20
tCTLdeassert_DQassert
tCTLassert_DQdeassert
CTL deasserted pulse width for CTL inputs that signify DQ input valid
at the asserting edge but do not employ in-built latches (ALE/DLE) for
those DQ inputs.
7
7
–
–
–
–
–
ns
ns
ns
ns
ns
CTL asserted pulse width for CTL inputs that signify DQ inputs valid
at the deasserting edge but do not employ in-built latches (ALE/DLE)
for those DQ inputs.
tCTLdeassert_DQdeassert CTL deasserted pulse width for CTL inputs that signify DQ inputs valid
at the deasserting edge but do not employ in-built latches (ALE/DLE)
for those DQ inputs.
20
7
tCTLassert_DQlatch
CTL asserted pulse width for CTL inputs that employ in-built latches
(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built
latches are always close at the deasserting edge.
tCTLdeassert_DQlatch
tCTLassert_DQlatchDDR
CTL deasserted pulse width for CTL inputs that employ in-built latches
(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built
latches always close at the deasserting edge.
10
CTL asserted pulse width for CTL inputs that employ in-built latches
(DLE) to latch the DQ inputs in DDR mode.
10
10
–
–
–
ns
ns
ns
tCTLdeassert_DQlatchDDR CTL deasserted pulse width for CTL inputs that employ in-built latches
(DLE) to latch the DQ inputs in DDR mode.
tAA
DQ/CTL input to DQ output time when DQ change or CTL change
needs to be detected and affects internal updates of input and output
DQ lines.
30
tDO
CTL to data out when the CTL change merely enables the output flop
update whose data was already established.
–
0
25
–
ns
ns
tOELZ
CTL designated as OE to low-Z. Time when external devices should
stop driving data.
tOEHZ
tCLZ
CTL designated as OE to high-Z
8
0
8
–
ns
ns
CTL (non-OE) to low-Z. Time when external devices should stop
driving data.
tCHZ
CTL (non-OE) to high-Z
30
–
30
25
30
–
ns
ns
ns
ns
ns
tCTLalpha
tCTLbeta
tDST
CTL to alpha change at output
CTL to beta change at output
–
Addr/data setup when DLE/ALE not used
Addr/data hold when DLE/ALE not used
2
tDHT
20
–
Notes
5. All parameters guaranteed by design and validated through characterization.
6. "alpha" output corresponds to "early output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs.
Document Number: 001-52136 Rev. *N
Page 26 of 45
CYUSB301X
PCLK), the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
must also be asserted.
Slave FIFO Interface
Synchronous Slave FIFO Sequence Description
The same sequence of events is shown for a burst read.
■ FIFO address is stable and SLCS is asserted
Note For burst mode, the SLRD# and SLOE# are asserted
during the entire duration of the read. When SLOE# is asserted,
the data bus is driven (with data from the previously addressed
FIFO). For each subsequent rising edge of PCLK, while the
SLRD# is asserted, the FIFO pointer is incremented and the next
data value is placed on the data bus.
■ SLOE is asserted. SLOE is an output-enable only, whose sole
function is to drive the data bus.
■ SLRD is asserted
■ The FIFO pointer is updated on the rising edge of the PCLK,
while the SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tco (measured from the rising edge of
Figure 12. Synchronous Slave FIFO Read Mode
Synchronous Read Cycle Timing
tCYC
PCLK
tCH tCL
2-cycle latency
from SLRD to data
cycle latency
3-
from addr to data
SLCS
t
AS tAH
FIFO ADDR
An
Am
tRDH
tRDS
SLRD
SLOE
2
cycle latency from
tCFLG
SLRD to FLAG
FLAGA
(dedicated thread Flag for An)
( 1 = Not Empty0 = Empty)
tCFLG
FLAGB
(dedicated thread Flag for Am)
( 1 = Not Empty0= Empty)
tCDH
tOEZ
tOELZ
tOEZ
tCO
tOELZ
High-Z
Data
driven:DN(An)
DN+2(Am)
DN+1(Am)
DN+1(An)
DN(Am)
Data Out
SLWR (HIGH)
Document Number: 001-52136 Rev. *N
Page 27 of 45
CYUSB301X
edge of PCLK. The FIFO pointer is updated on each rising edge
of PCLK.
Synchronous Slave FIFO Write Sequence Description
■ FIFO address is stable and the signal SLCS# is asserted
■ External master or peripheral outputs the data to the data bus
■ SLWR# is asserted
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device or processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines must be held constant during the PKTEND#
assertion.
■ While the SLWR# is asserted, data is written to the FIFO and
on the rising edge of the PCLK, the FIFO pointer is incremented
Zero-Length Packet: The external device or processor can
signal a Zero-Length Packet (ZLP) to FX3 simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in Figure 13 on page 28.
■ The FIFO flag is updated after a delay of t
edge of the clock
from the rising
WFLG
The same sequence of events is also shown for burst write
Note For the burst mode, SLWR# and SLCS# are asserted for
the entire duration, during which all the required data values are
written. In this burst write mode, after the SLWR# is asserted, the
data on the FIFO data bus is written to the FIFO on every rising
FLAG Usage: The FLAG signals are monitored for flow control
by the external processor. FLAG signals are outputs from FX3
that may be configured to show empty, full, or partial status for a
dedicated thread or the current thread that is addressed.
Figure 13. Synchronous Slave FIFO Write Mode
Synchronous Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
Am
An
tWRS
FIFO ADDR
SLWR
tWRH
tCFLG
3 cycle latency from SLWR# to FLAG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
tCFLG
3 cycle latency from SLWR # to FLAG
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
tDS tDH
tDS tDH
DN(Am) DN+1(Am) DN+2(Am)
tPES
tDH
DN(An)
Data IN
High-Z
tPEH
PKTEND
SLOE
(HIGH)
Synchronous ZLP Write Cycle Timing
tCYC
PCLK
tCH tCL
SLCS
tAH
tAS
An
FIFO ADDR
SLWR
(HIGH)
t
PES tPEH
PKTEND
tCFLG
FLAGA
dedicated thread FLAG for An
(1 = Not Full 0= Full)
FLAGB
current thread FLAG for Am
(1 = Not Full 0= Full)
High-Z
Data IN
SLOE
(HIGH)
Document Number: 001-52136 Rev. *N
Page 28 of 45
CYUSB301X
[7]
Table 11. Synchronous Slave FIFO Parameters
Parameter
Description
Min
–
Max
100
–
Units
MHz
ns
FREQ
tCYC
tCH
Interface clock frequency
Clock period
10
4
Clock high time
–
ns
tCL
Clock low time
4
–
ns
tRDS
tRDH
tWRS
tWRH
tCO
SLRD# to CLK setup time
SLRD# to CLK hold time
SLWR# to CLK setup time
SLWR# to CLK hold time
Clock to valid data
2
–
ns
0.5
2
–
ns
–
ns
0.5
–
–
ns
8
ns
tDS
Data input setup time
CLK to data input hold
2
–
ns
tDH
0.5
2
–
ns
tAS
Address to CLK setup time
CLK to address hold time
SLOE# to data low-Z
–
ns
tAH
0.5
0
–
ns
tOELZ
tCFLG
tOEZ
tPES
tPEH
tCDH
–
ns
CLK to flag output propagation delay
SLOE# deassert to Data Hi Z
PKTEND# to CLK setup
CLK to PKTEND# hold
–
8
ns
–
8
ns
2
–
ns
0.5
2
–
CLK to data output hold
–
ns
Note Three-cycle latency from ADDR to DATA/FLAGS
In Figure 14, data N is the first valid data read from the FIFO. For
data to appear on the data bus during the read cycle, SLOE#
must be in an asserted state. SLRD# and SLOE# can also be
tied.
Asynchronous Slave FIFO Read Sequence
Description
■ FIFO address is stable and the SLCS# signal is asserted.
■ SLOE# is asserted. This results in driving the data bus.
■ SLRD # is asserted.
The same sequence of events is also shown for a burst read.
Note In the burst read mode, during SLOE# assertion, the data
bus is in a driven state (data is driven from a previously
addressed FIFO). After assertion of SLRD# data from the FIFO
is driven on the data bus (SLOE# must also be asserted). The
FIFO pointer is incremented after deassertion of SLRD#.
■ Data from the FIFO is driven after assertion of SLRD#. This
data is valid after a propagation delay of tRDO from the falling
edge of SLRD#.
■ FIFO pointer is incremented on deassertion of SLRD#
Note
7. All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N
Page 29 of 45
CYUSB301X
Figure 14. Asynchronous Slave FIFO Read Mode
SLCS
tAS
tAH
An
Am
FIFO ADDR
tRDl tRDh
SLRD
SLOE
tFLG
tRFLG
FLAGA
dedicated thread Flag for An
(1=Not empty 0 = Empty)
FLAGB
dedicated thread Flag for Am
(1=Not empty 0 = Empty)
tRDO
tRDO
tOH
tOE
tLZ
tOE
tRDO
tOH
DN(An)
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
Data Out
High-Z
SLWR
(HIGH)
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device or processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines must be held constant during the PKTEND#
assertion.
Asynchronous Slave FIFO Write Sequence
Description
■ FIFO address is driven and SLCS# is asserted
■ SLWR# is asserted. SLCS# must be asserted with SLWR# or
before SLWR# is asserted
Zero-Length Packet: The external device or processor can
signal a zero-length packet (ZLP) to FX3 simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and the address
must be driven as shown in Figure 15 on page 31.
■ Data must be present on the tWRS bus before the deasserting
edge of SLWR#
■ Deassertion of SLWR# causes the data to be written from the
data bus to the FIFO, and then the FIFO pointer is incremented
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are FX3 outputs that
can be configured to show empty, full, and partial status for a
dedicated address or the current address.
■ The FIFO flag is updated after the tWFLG from the deasserting
edge of SLWR.
The same sequence of events is shown for a burst write.
Note that in the burst write mode, after SLWR# deassertion, the
data is written to the FIFO, and then the FIFO pointer is incre-
mented.
Document Number: 001-52136 Rev. *N
Page 30 of 45
CYUSB301X
Figure 15. Asynchronous Slave FIFO Write Mode
Asynchronous Write Cycle Timing
SLCS
tAS
tAH
An
FIFO ADDR
Am
tWRl
tWRh
SLWR
tFLG
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
tWFLG
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
tWR
tWR
tWRH
tWRH
S
S
High-Z
DN(An)
DN(Am)
DN+1(Am)
DN+2(Am)
DATA In
tWRPE
tPEh
PKTEND
SLOE
(HIGH)
tWRPE: SLWR# de-assert to PKTEND deassert = 2ns min (This means that PKTEND should not be be deasserted before SLWR#)
Note: PKTEND must be asserted at the same time as SLWR#.
Asynchronous ZLP Write Cycle Timing
SLCS
tAS
tAH
An
FIFO ADDR
SLWR
(HIGH)
tPEl
tPEh
PKTEND
tWFLG
FLAGA
dedicated thread Flag for An
(1=Not Full 0 = Full)
FLAGB
dedicated thread Flag for Am
(1=Not Full 0 = Full)
High-Z
DATA In
SLOE
(HIGH)
Document Number: 001-52136 Rev. *N
Page 31 of 45
CYUSB301X
[8]
Table 12. Asynchronous Slave FIFO Parameters
Parameter
Description
Min
20
10
7
Max
–
Units
ns
tRDI
SLRD# low
SLRD# high
tRDh
tAS
–
ns
Address to SLRD#/SLWR# setup time
SLRD#/SLWR#/PKTEND to address hold time
SLRD# to FLAGS output propagation delay
ADDR to FLAGS output propagation delay
SLRD# to data valid
–
ns
tAH
2
–
ns
tRFLG
tFLG
tRDO
tOE
–
35
22.5
25
25
–
ns
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE# low to data valid
tLZ
OE# low to data low-Z
0
tOH
SLOE# deassert data output hold
SLWR# low
–
22.5
–
tWRI
tWRh
tWRS
tWRH
tWFLG
tPEI
20
10
7
SLWR# high
–
Data to SLWR# setup time
SLWR# to Data Hold time
–
2
–
SLWR#/PKTEND to Flags output propagation delay
PKTEND low
–
35
–
20
7.5
2
tPEh
tWRPE
PKTEND high
–
SLWR# deassert to PKTEND deassert
–
Note
8. All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N
Page 32 of 45
CYUSB301X
Serial Peripherals Timing
I2C Timing
Figure 16. I2C Timing Definition
Document Number: 001-52136 Rev. *N
Page 33 of 45
CYUSB301X
[9]
Table 13. I2C Timing Parameters
Parameter
Description
Min
Max
Units
I2C Standard Mode Parameters
fSCL
SCL clock frequency
0
4
100
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
HIGH period of the SCL
4.7
4
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
–
Setup time for a repeated START condition
Data hold time
4.7
0
–
–
Data setup time
250
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
1000
300
–
tf
–
tSU:STO
tBUF
4
4.7
–
–
tVD:DAT
tVD:ACK
tSP
3.45
3.45
n/a
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
I2C Fast Mode Parameters
n/a
fSCL
SCL clock frequency
0
0.6
1.3
0.6
0.6
0
400
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
HIGH period of the SCL
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
100
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Data valid time
300
300
–
tf
–
tSU:STO
tBUF
0.6
1.3
–
–
tVD:DAT
tVD:ACK
tSP
0.9
0.9
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
Note
9. All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N
Page 34 of 45
CYUSB301X
[9]
Table 13. I2C Timing Parameters (continued)
Parameter
Description
I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2 V)
SCL clock frequency
Min
Max
Units
fSCL
0
0.26
0.5
0.26
0.26
0
1000
–
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHD:STA
tLOW
Hold time START condition
LOW period of the SCL
–
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
HIGH period of the SCL
–
Setup time for a repeated START condition
Data hold time
–
–
Data setup time
50
–
–
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus-free time between a STOP and START condition
Data valid time
120
120
–
tf
–
tSU:STO
tBUF
0.26
0.5
–
–
tVD:DAT
tVD:ACK
tSP
0.45
0.55
50
Data valid ACK
–
Pulse width of spikes that must be suppressed by input filter
0
I2S Timing Diagram
Figure 17. I2S Transmit Cycle
tT
tTR tTF
tTH
tTL
SCK
tThd
SA,
WS (output)
tTd
[10]
Table 14. I2S Timing Parameters
Parameter
Description
Min
Ttr
Max
Units
2
tT
I S transmitter clock cycle
–
ns
ns
ns
ns
ns
ns
ns
2
tTL
tTH
tTR
tTF
tThd
tTd
I S transmitter cycle LOW period
0.35 Ttr
–
–
2
I S transmitter cycle HIGH period
0.35 Ttr
2
I S transmitter rise time
–
–
0
–
0.15 Ttr
0.15 Ttr
–
2
I S transmitter fall time
2
I S transmitter data hold time
2
I S transmitter delay time
0.8tT
Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
10. All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N
Page 35 of 45
CYUSB301X
SPI Timing Specification
Figure 18. SPI Timing
SSN
(output)
tssnh
tsck
tlag
tlead
SCK
(CPOL=0,
Output)
trf
twsck
twsck
SCK
(CPOL=1,
Output)
tsdi
thoi
LSB
MISO
(input)
MSB
MSB
td
tdis
tsdd
tdi
v
MOSI
(output)
LSB
SPI Master Timing for CPHA = 0
SSN
(output)
tssnh
tsck
tlag
tlead
trf
SCK
(CPOL=0,
Output)
twsck
twsck
SCK
(CPOL=1,
Output)
thoi
LSB
tsdi
MISO
(input)
MSB
MSB
tdis
tdi
tdv
MOSI
(output)
LSB
SPI Master Timing for CPHA = 1
Document Number: 001-52136 Rev. *N
Page 36 of 45
CYUSB301X
[11]
Table 15. SPI Timing Parameters
Parameter
Description
Min
0
Max
33
–
Units
MHz
ns
fop
Operating frequency
tsck
twsck
tlead
tlag
trf
Cycle time
30
Clock high/low time
SSN-SCK lead time
Enable lag time
Rise/fall time
13.5
–
ns
[12 ]
[12]
1/2 tsck
-5
1.5 tsck + 5
ns
[12]
0.5
–
1.5 tsck +5
ns
8
5
5
–
–
–
–
–
ns
tsdd
tdv
Output SSN to valid data delay time
Output data valid time
–
ns
–
ns
tdi
Output data invalid
0
ns
tssnh
tsdi
thoi
tdis
Minimum SSN high time
Data setup time input
10
8
ns
ns
Data hold time input
0
ns
Disable data output on SSN high
0
ns
Notes
11. All parameters guaranteed by design and validated through characterization.
12. Depends on LAG and LEAD setting in the SPI_CONFIG register.
Document Number: 001-52136 Rev. *N
Page 37 of 45
CYUSB301X
Reset Sequence
FX3’s hard reset sequence requirements are specified in this section.
Table 16. Reset and Standby Timing Parameters
Parameter
Definition
Conditions
Clock Input
Crystal Input
–
Min (ms)
Max (ms)
tRPW
Minimum RESET# pulse width
1
1
5
1
5
–
–
–
–
–
tRH
tRR
Minimum high on RESET#
Reset recovery time (after which Boot loader begins
firmware download)
Clock Input
Crystal Input
–
tSBY
tWU
Time to enter standby/suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
1
Time to wakeup from standby
Clock Input
Crystal Input
–
1
5
5
–
–
–
tWH
Minimum time before Standby/Suspend source may
be reasserted
Figure 19. Reset Sequence
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
tRh
tRR
Mandatory
Reset Pulse
Hard Reset
RESET #
tWH
tWU
tRPW
tSBY
Standby/
Suspend
Source
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Standby/Suspend
source Is deasserted
Document Number: 001-52136 Rev. *N
Page 38 of 45
CYUSB301X
Package Diagram
Figure 20. 121-ball FBGA Package Diagram
001-54471 *D
Document Number: 001-52136 Rev. *N
Page 39 of 45
CYUSB301X
Figure 21. 131-ball WLCSP Package Diagram
1
2
3
4
5
6
7
8
9 10 11 12
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
001-62221 *B
Note Underfill is required on the board design. Contact Cypress Applications for details.
Document Number: 001-52136 Rev. *N
Page 40 of 45
CYUSB301X
Ordering Information
Table 17. Ordering Information
Ordering Code
CYUSB3011-BZXC
CYUSB3012-BZXC
CYUSB3013-BZXC
CYUSB3014-BZXC
CYUSB3014-BZXI
CYUSB3014-FBXCT
CYUSB3014-FBXIT
SRAM (kB)
GPIF II Data Bus Width
Operating Temperature
0 °C to +70 °C
Package Type
256
256
512
512
512
512
512
16-bit
32-bit
16-bit
32-bit
32-bit
32-bit
32-bit
121-ball BGA
0 °C to +70 °C
121-ball BGA
121-ball BGA
121-ball BGA
121-ball BGA
131-ball CSP
131-ball CSP
0 °C to +70 °C
0 °C to +70 °C
–40°C to +85°C
0 °C to +70 °C
–40 °C to +85 °C
Ordering Code Definitions
Document Number: 001-52136 Rev. *N
Page 41 of 45
CYUSB301X
Acronyms
Document Conventions
Units of Measure
Acronym
DMA
HNP
Description
direct memory access
Symbol
°C
Unit of Measure
host negotiation protocol
multimedia card
degree Celsius
microamperes
microseconds
milliamperes
Megabits per second
Megabytes per second
mega hertz
MMC
MTP
µA
media transfer protocol
phase locked loop
power management IC
secure digital
µs
PLL
mA
Mbps
MBps
MHz
ms
ns
PMIC
SD
SD
secure digital
SDIO
SLC
secure digital input / output
single-level cell
milliseconds
nanoseconds
ohms
SLCS
SLOE
SLRD
SLWR
SPI
Slave Chip Select
Slave Output Enable
Slave Read
pF
pico Farad
V
volts
Slave Write
serial peripheral interface
session request protocol
universal serial bus
wafer level chip scale package
SRP
USB
WLCSP
Document Number: 001-52136 Rev. *N
Page 42 of 45
CYUSB301X
Document History Page
Document Title: CYUSB301X, EZ-USB® FX3: SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2669761 VSO/PYRS
2758370 VSO
03/06/09
09/01/09
New data sheet
*A
Updated the part# from CYX01XXBB to CYUSB3011-BZXI
Changed the title from “ADVANCE” to “ADVANCE INFORMATION”
In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz” to
first sub bullet.
In page 1, changed the second bullet “Flexible Host Interface” to General
Programmable Interface”.
In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave
Support” and "MMC Slave support with Pass through Boot" sub bullets.
In page 1, third bullet, changed "50 A with Core Power" to "60 A with Core
Power"
In page 1, fifth bullet, added "at 1 MHz"
In page 1, seventh bullet, added "up to 4MHz" to UART
In page 1, Applications Section, move “Digital Still Cameras” to second line.
In page 1, Applications Section, added “Machine Vision” and Industrial
Cameras”
Added ™ to GPIF and FX3.
In page 1, updated Logic Block Diagram.
In page 2, section of “Functional Overview”, updated the whole section.
In page 2, removed the section of “Product Interface”
In page 2, removed the section of “Processor Interface (P-Port)”
In page 2, removed the section of “USB Interface (U-Port)”
In page 2, removed the section of “Other Interfaces”
In page 2, added a section of "GPIF II"
In page 2, added a section of "CPU"
In page 2, added a section of "JTAG Interface"
In page 2, added a section of "Boot Options"
In page 2, added a section of "ReNumeration"
In page 2, added a section of "Power"
In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3.
In the section of “Package”, added 0.8 mm pitch in front of BGA.
Added Pin List (Table 1)
*B
2779196 VSO/PYRS
09/29/09
12/08/09
Features:
Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of
embedded SRAM”
Added the thrid line “EZ USB™ Software and DVK for easy code development”
Table 1: Pin 74, corrected to NC - No Connect.
Changed title to EZ-USB™ FX3: SuperSpeed USB Controller
*C
*D
2823531
3080927
OSG
OSG
Added data sheet to the USB 3.0 EROS spec 001-51884. No technical
updates.
11/08/2010 Changed status from Advance to Preliminary
Changed part number from CYUSB3011 to CYUSB3014
Added the following sections: Power, Configuration Options, Digital I/Os,
System-level ESD, Absolute Maximum Ratings, AC Timing Parameters, Reset
Sequence, Package Diagram
Added DC Specifications table
Updated feature list
Updated Pin List
Added support for selectable clock input frequencies.
Updated block diagram
Updated part number
Updated package diagram
Document Number: 001-52136 Rev. *N
Page 43 of 45
CYUSB301X
Document History Page (continued)
Document Title: CYUSB301X, EZ-USB® FX3: SuperSpeed USB Controller
Document Number: 001-52136
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
3204393
OSG
03/24/2011 Updated Slave FIFO protocol and added ZLP signaling protocol
Changed GPIFII asynchronous tDO parameter
Changed Async Slave FIFO tOE parameter
Changed Async Slave FIFO tRDO parameter
Added tCOE parameter to GPIFII Sync mode timing parameters
Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0
Modified description of GPIFII Sync tCO (previously tDO) parameter
Changed tAH(address hold time) parameter in Async Slave FIFO modes to be
with respect to rising edge of SLWR#/SLRD# instead of falling edge.
Correspondingly, changed the tAH number.
Removed 24 bit data bus support for GPIFII.
*F
*G
*H
3219493
3235250
3217917
OSG
GSZ
OSG
04/07/2011 Minor ECN - Release to web. No content changes.
04/20/2011 Minor updates in Features.
04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option.
Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST#
pull-up/pull-down configuration. Minor updates to block diagrams.
Corrected Synchronous Slave FIFO tDH parameter.
*I
3305568
3369042
DSG
OSG
07/07/2011 Minor ECN - Correct ECN number in revision *F. No content changes.
*J
12/06/2011 Changed tWRPE parameter to 2ns
Updated tRR and tRPW for crystal input
Added clarification regarding I and I
OZ
IX
Updated Sync SLave FIFO Read timing diagram
Updated SPI timing diagram
Removed tGRANULARITY parameter
Updated I2S Timing diagram and tTd parameter
Updated 121-ball FBGA package diagram.
Added clarification regarding VCC in DC Specifications table
In Power Modes description, stated that VIO1 cannot be turned off at any time
if the GPIFII is used in the application
Updated Absolute Maximum Ratings
Added requirement for by-pass capacitor on U3RX
and U3TX
VDDQ
VDDQ
Updated tPEI parameter in Async Slave FIFO timing table
Updated Sync Slave FIFO write and read timing diagrams
Updated I2C interface tVD:ACK parameter for 1MHz operation
Clarified that CTL[15] is not usable as a GPIO
Changed datasheet status from Preliminary to Final.
*K
*L
3534275
3649782
OSG
OSG
02/24/2012 Corrected typo in the block diagram.
08/16/2012 Changed part number to CYUSB301X.
Added 256 KB range for embedded SRAM.
Updated Functional Overview, Other Interfaces, and Clocking sections.
Added Pin List for CYUSB3011 and CYUSB3013 parts.
Updated Ordering Information with new part numbers.
*M
*N
3848148
4016006
OSG
OSG
12/20/2012 Updated 121-ball FBGA package diagram to current revision.
05/31/2013 Updated Features (Added 131-ball WLCSP under Package option).
Updated Pin Configurations (Added FX3 131-ball WLCSP Ball Map (Figure 8)).
Updated Pin Description (Updated Table 7).
Updated Absolute Maximum Ratings (Included Commercial Temperature
Range related information).
Updated Operating Conditions (Included Commercial Temperature Range
related information).
Updated Package Diagram (Added 131-ball WLCSP Package Diagram
(Figure 21)).
Updated Ordering Information (Updated part numbers).
Document Number: 001-52136 Rev. *N
Page 44 of 45
CYUSB301X
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52136 Rev. *N
Revised May 31, 2013
Page 45 of 45
®
EZ-USB™ is a trademark and West Bridge is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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