CYV15G0204RB_技术文档

CYV15G0204RB

Independent Clock Dual HOTLink II™

Reclocking Deserializer

and SMPTE 259 video applications. It supports signaling rates

in the range of 195 to 1500 Mbps per serial link. The two

channels are independent and can simultaneously operate at

different rates. Each receive channel accepts serial data and

converts it to 10-bit parallel characters and presents these

characters to an Output Register. The received serial data can

also be reclocked and retransmitted through the reclocker

serial outputs. Figure 1 illustrates typical connections between

independent video co-processors and corresponding

Features

• Second-generation HOTLink^®technology

• Compliant to SMPTE 292M and SMPTE 259M video

standards

• Dual-channel video reclocking deserializer

— 195- to 1500-Mbps serial data signaling rate

— Simultaneous operation at different signaling rates

CYV15G0204RB

Reclocking

Deserializer

and

• Supportsreceptionofeither1.485or1.485/1.001Gbpsdata

rate with the same training clock

CYV15G0203TB Serializer chips.

The CYV15G0204RB satisfies the SMPTE-259M and

SMPTE-292M compliance as per SMPTE EG34-1999 Patho-

logical Test Requirements.

• Supports half-rate and full-rate clocking

• Internal phase-locked loops (PLLs) with no external PLL

components

As

a

second-generation HOTLink device, the

• Selectable differential PECL-compatible serial inputs

— Internal DC-restoration

CYV15G0204RB extends the HOTLink family with

enhanced levels of integration and faster data rates,

while maintaining serial-link compatibility (data and BIST)

with other HOTLink devices.

• Synchronous LVTTL parallel interface

• JTAG boundary scan

Each channel of the CYV15G0204RB Dual HOTLink II device

accepts a serial bit-stream from one of two selectable

PECL-compatible differential line receivers, and using a

completely integrated Clock and Data Recovery PLL, recovers

the timing information necessary for data reconstruction. The

recovered bit-stream is reclocked and retransmitted through

the reclocker serial outputs. Also, the recovered serial data is

deserialized and presented to the destination host system.

• Built-In Self-Test (BIST) for at-speed link testing

• Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low-power 2W @ 3.3V typical

• Single 3.3V supply

Each channel contains an independent BIST pattern checker.

This BIST hardware allows at-speed testing of the high-speed

serial data paths in each receive section of this device, each

transmit section of a connected HOTLink II device, and across

the interconnecting links.

• Thermally enhanced BGA

• Pb-Free package option available

• 0.25μ BiCMOS technology

Functional Description

The CYV15G0204RB is ideal for SMPTE applications where

different data rates and serial interface standards are

necessary for each channel. Some applications include

multi-format routers, switchers, format converters, SDI

monitors, and camera control units.

The CYV15G0204RB Independent Clock Dual HOTLink II™

Deserializing Reclocker is a point-to-point or point-to-multi-

point communications building block enabling transfer of data

over a variety of high-speed serial links including SMPTE 292

Figure 1. HOTLink II™ System Connections

Reclocked

Output

10

Independent

Channel

Independent

Channel

CYV15G0204RB

Serial Links

CYV15G0203TB

Serializer

Reclocking Deserializer

10

Reclocked

Output

Cypress Semiconductor Corporation

Document #: 38-02103 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 2, 2007

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CYV15G0204RB

CYV15G0204RB Deserializing Reclocker Logic Block Diagram

x10

Deserializer

RX

Reclocker

Document #: 38-02103 Rev. *C

Page 2 of 24

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CYV15G0204RB

= Internal Signal

Reclocking Deserializer Path Block Diagram

RESET

TRST

TRGRATEA

JTAG

Boundary

Scan

TMS

TCLK

TDI

x2

TRGCLKA

Controller

SDASEL[2..1]A[1:0]

LDTDEN

TDO

LFIA

Receive

Signal

INSELA

Monitor

10

RXDA[9:0]

BISTSTA

10

INA1+

INA1–

Clock &

INA2+

INA2–

Data

Recovery

RXCLKA+

RXCLKA–

PLL

÷2

ULCA

SPDSELA

RXBISTA[1:0]

RXRATEA

RXPLLPDA

Recovered Serial Data

Recovered Character Clock

ROE[2..1]A

Reclocker

Output PLL

Clock Multiplier A

ROUTA1+

ROUTA1–

ROE[2..1]A

ROUTA2+

ROUTA2–

RECLKOA

Character-Rate Clock A

REPDOA

TRGRATEB

x2

TRGCLKB

LDTDEN

SDASEL[2..1]B[1:0]

LFIB

Receive

Signal

INSELB

Monitor

10

RXDB[9:0]

BISTSTB

10

INB1+

INB1–

Clock &

Data

Recovery

PLL

INB2+

INB2–

RXCLKB+

RXCLKB–

÷2

ULCB

SPDSELB

RXBISTB[1:0]

RXRATEB

RXPLLPDB

Recovered Serial Data

Recovered Character Clock

ROE[2..1]B

Reclocker

Output PLL

Clock Multiplier B

ROUTB1+

ROUTB1–

ROE[2..1]B

ROUTB2+

ROUTB2–

RECLKOB

REPDOB

Character-Rate Clock B

Document #: 38-02103 Rev. *C

Page 3 of 24

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CYV15G0204RB

Device Configuration and Control Block Diagram

= Internal Signal

RXBIST[A..B]

RXRATE[A..B]

SDASEL[A..B][1:0]

RXPLLPD[A..B]

WREN

Device Configuration

and Control Interface

ADDR[2:0]

DATA[6:0]

ROE[2..1][A..B]

Document #: 38-02103 Rev. *C

Page 4 of 24

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CYV15G0204RB

Pin Configuration (Top View)^[1]

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

C

D

E

IN

B1–

ROUT

B1–

IN

B2–

ROUT

B2–

IN

A1–

ROUT

A1–

IN

A2–

ROUT

A2–

NC

V

GND

V

NC

V

NC

CC

IN

B1+

ROUT

B1+

IN

B2+

ROUT

B2+

IN

A1+

ROUT

A1+

IN

A2+

ROUT

A2+

V

NC

V

NC

V

GND

V

NC

CC

TDI

TMS

ULCB

ULCA

DATA

[6]

DATA

[4]

DATA

[2]

DATA

[0]

SPD

SELB

LDTD TRST

EN

TDO

V

NC

GND

CC

TCLK RESET INSELB INSELA

DATA

[5]

DATA

[3]

DATA

[1]

SCAN TMEN3

EN2

GND GND GND

NC

V

CC

V

CC

F

G

H

J

NC

V

NC

CC

WREN

SPD

SELA

GND

GND GND

NC

GND GND GND GND

NC

K

L

NC

GND GND

NC

GND

NC

GND

M

N

P

R

T

GND GND GND GND

NC

V

CC

V

CC

U

V

W

Y

RX

DB[4]

RX

DB[3]

ADDR

[0]

TRG

CLKB–

RX

DA[4]

BIST

STA

RX

DA[0]

V

GND GND

GND GND GND

V

CC

RX

DB[8]

RX

DB[5]

RX

DB[1]

BIST

STB

TRG

CLKB+ CLKOA

RE

RX

DA[9]

RX

DA[5]

RX

DA[2]

RX

DA[1]

GND

GND GND

LFIB

RX

CLKB–

RX

DB[6]

RX

DB[0]

ADDR ADDR

[2]

RX

RE

LFIA

TRG

CLKA+ DA[6]

RX

DA[3]

GND

GND GND

[1]

CLKA+ PDOA

RX

DB[7]

RX

DB[2]

RE

CLKOB

RX

CLKA–

RE

TRG

RX

DA[7]

NC

GND

DB[9] CLKB+

PDOB CLKA– DA[8]

Note

1. NC = Do not connect.

Document #: 38-02103 Rev. *C

Page 5 of 24

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CYV15G0204RB

Pin Configuration (Bottom View)^[1]

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

ROUT

A2–

IN

A2–

ROUT

A1–

IN

A1–

ROUT

B2–

IN

B2–

ROUT

B1–

IN

B1–

NC

V

NC

V

GND

V

NC

CC

ROUT

A2+

IN

A2+

ROUT

A1+

IN

A1+

ROUT

B2+

IN

B2+

ROUT

B1+

IN

B1+

NC

V

GND

V

NC

V

NC

V

CC

TDO

TRST LDTD

EN

SPD

SELB

DATA

[0]

DATA

[2]

DATA

[4]

DATA

[6]

ULCB

ULCA

TMS

TDI

GND

NC

V

CC

TMEN3 SCAN

EN2

DATA

[1]

DATA

[3]

DATA

[5]

INSELA INSELB RESET TCLK

V

NC

GND GND GND

CC

V

CC

F

G

H

J

NC

V

NC

SPD

SELA

WREN

NC

GND GND

GND

GND GND GND GND

NC

K

L

GND GND

NC

GND

NC

M

N

P

R

T

GND GND GND GND

NC

V

CC

V

CC

U

V

W

Y

RX

DA[0]

BIST

STA

RX

DA[4]

TRG

CLKB–

ADDR

[0]

RX

DB[3]

RX

DB[4]

V

GND GND GND

GND GND

V

CC

RX

DA[1]

RX

DA[2]

RX

DA[5]

RX

DA[9]

RE

TRG

BIST

STB

RX

DB[1]

RX

DB[5]

RX

DB[8]

GND GND

GND

CLKOA CLKB+

RX

DA[3]

RX

TRG

LFIA

RE

RX

ADDR ADDR

[1]

RX

DB[0]

RX

DB[6]

RX

CLKB–

LFIB

GND GND

GND

DA[6] CLKA+

PDOA CLKA+

[2]

RX

DA[7]

RX

TRG

RE

RX

CLKA–

RE

CLKOB

RX

DB[2]

RX

DB[7]

RX

GND

NC

DA[8] CLKA– PDOB

CLKB+ DB[9]

Document #: 38-02103 Rev. *C

Page 6 of 24

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CYV15G0204RB

Pin Definitions

CYV15G0204RB Dual HOTLink II Deserializing Reclocker

Name

I/O Characteristics Signal Description

Receive Path Data and Status Signals

RXDA[9:0]

RXDB[9:0]

LVTTL Output,

Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive

synchronous to the interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are

RXCLK± output

complementary clocks operating at the character rate. The RXDx[9:0] outputs for the

associated receive channels follow rising edge of RXCLKx+ or falling edge of

RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are comple-

mentary clocks operating at half the character rate. The RXDx[9:0] outputs for the

associated receive channels follow both the falling and rising edges of the associated

RXCLKx± clock outputs.

When BIST is enabled on the receive channel, the BIST status is presented on the

RXDx[1:0] and BISTSTx outputs. See Table 5 on page 14 for each status reported

by the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs

should be ignored.

BISTSTA

BISTSTB

LVTTL Output,

BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])

synchronous to the displays the status of the BIST reception. See Table 5 on page 14 for the BIST status

RXCLKx ± output

reported for each combination of BISTSTx and RXDx[1:0].

When RXBISTx[1:0] ≠ 10, BISTSTx should be ignored.

REPDOA

REPDOB

Asynchronous to

reclocker output

channel

Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when the

associated channel’s reclocker output logic is powered down. This occurs when

ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.

enable / disable

Receive Path Clock Signals

TRGCLKA±

TRGCLKB±

Differential LVPECL CDR PLL Training Clock. TRGCLKx± clock inputs are used as the reference source

or single-ended

for the frequency detector (Range Controller) of the associated receive PLL to

reduce PLL acquisition time.

LVTTL input clock

In the presence of valid serial data, the recovered clock output of the receive CDR

PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.

When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock

source to either the true or complement TRGCLKx input, and leave the alternate

TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock

must be a differential clock, using both inputs.

RXCLKA±

RXCLKB±

LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock used to control

timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used

to control timing of data output transfers. These clocks are output continuously at

either the half-character rate (1/20^ththe serial bit-rate) or character rate (1/10^ththe

serial bit-rate) of the data being received, as selected by RXRATEx.

RECLKOA

RECLKOB

LVTTL Output

Reclocker Clock Output. RECLKOx output clock is synthesized by the associated

reclocker output PLL and operates synchronous to the internal recovered character

clock. RECLKOx operates at either the same frequency as RXCLKx± (RXRATEx =

0), or at twice the frequency of RXCLKx± (RXRATEx = 1).The reclocker clock outputs

have no fixed phase relationship to RXCLKx±.

Device Control Signals

RESET LVTTL Input,

Asynchronous Device Reset. RESET initializes all state machines, counters, and

configuration latches in the device to a known state. RESET must be asserted LOW

for a minimum pulse width. When the reset is removed, all state machines, counters

and configuration latches are at an initial state. As per the JTAG specifications the

device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has

to be reset separately. Refer to “JTAG Support” on page 14 for the methods to reset

the JTAG state machine. See Table 3 on page 13 for the initialize values of the device

configuration latches.

asynchronous,

internal pull-up

Document #: 38-02103 Rev. *C

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CYV15G0204RB

Pin Definitions (continued)

CYV15G0204RB Dual HOTLink II Deserializing Reclocker

Name

I/O Characteristics Signal Description

LDTDEN

LVTTL Input,

internal pull-up

Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level

Detector, Range Controller, and Transition Density Detector are all enabled to

determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream.

If the Signal Level Detector, Range Controller, or Transition Density Detector are out

of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx± until

such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure

the trip level of the Signal Level Detector. The Transition Density Detector limit is one

transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range

Controller is used to determine if the RXPLL tracks TRGCLKx± or the selected input

serial data stream. It is recommended to set LDTDEN = HIGH.

ULCA

ULCB

LVTTL Input,

internal pull-up

Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±

instead of the received serial data stream. While ULCx is LOW, the LFIx for the

associated channel is LOW indicating a link fault.

When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on

the input data streams. This function is used in applications in which a stable

RXCLKx± is needed. In cases when there is an absence of valid data transitions for

a long period of time, or the high-gain differential serial inputs (INx±) are left floating,

there may be brief frequency excursions of the RXCLKx± outputs from TRGCLKx±.

SPDSELA

SPDSELB

3-Level Select^[2]

static control input

Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range

of each channel’s receive PLL.

LOW = 195–400 MBd

MID = 400–800 MBd

HIGH = 800–1500 MBd.

INSELA

INSELB

LVTTL Input,

asynchronous

Receive Input Selector. The INSELx input determines which external serial bit

stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx

is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the

associated receive channel. When INSELx is LOW, the Secondary Differential Serial

Data Input, INx2±, is selected for the associated receive channel.

LFIA

LFIB

LVTTL Output,

asynchronous

Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the

logical OR of six internal conditions. LFIx is asserted LOW when any of the following

conditions is true:

• Received serial data rate outside expected range

• Analog amplitude below expected levels

• Transition density lower than expected

• Receive channel disabled

• ULCx is LOW

• Absence of TRGCLKx±.

Device Configuration and Control Bus Signals

WREN

LVTTL input,

asynchronous,

Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into

the latch specified by the address location on the ADDR[2:0] bus.^[3]

internal pull-up

ADDR[2:0]

LVTTL input

asynchronous,

internal pull-up

Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to

configure the device. The WREN input writes the values of the DATA[6:0] bus into

the latch specified by the address location on the ADDR[2:0] bus.^[3]Table 3 on page

13 lists the configuration latches within the device, and the initialization value of the

latches upon the assertion of RESET. Table 4 on page 14 shows how the latches are

mapped in the device.

Notes

2. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually

implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually

SS

CC

implemented by not connecting the input (left floating), which allows it to self bias to the proper level.

3. See “Device Configuration and Control Interface” on page 12 for detailed information on the operation of the Configuration Interface.

Document #: 38-02103 Rev. *C

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CYV15G0204RB

Pin Definitions (continued)

CYV15G0204RB Dual HOTLink II Deserializing Reclocker

Name

I/O Characteristics Signal Description

DATA[6:0]

LVTTL input

asynchronous,

internal pull-up

Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the

device. The WREN input writes the values of the DATA[6:0] bus into the latch

specified by address location on the ADDR[2:0] bus.^[3]Table 3 on page 13 lists the

configuration latches within the device, and the initialization value of the latches upon

the assertion of RESET. Table 4 on page 14 shows how the latches are mapped in

the device.

Internal Device Configuration Latches

RXRATE[A..B]

Internal Latch^[4]

Receive Clock Rate Select.

SDASEL[2..1][A..B] Internal Latch^[4]

[1:0]

Signal Detect Amplitude Select.

RXPLLPD[A..B]

RXBIST[A..B][1:0] Internal Latch^[4]

Internal Latch^[4]

Receive Channel Power Control.

Receive Bist Disabled.

ROE2[A..B]

Internal Latch^[4]

Reclocker Differential Serial Output Driver 2 Enable.

Reclocker Differential Serial Output Driver 1 Enable.

ROE1[A..B]

Factory Test Modes

SCANEN2

LVTTL input,

internal pull-down

Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as

a NO CONNECT, or GND only.

TMEN3

LVTTL input,

internal pull-down

Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a

NO CONNECT, or GND only.

Analog I/O

ROUTA1±

ROUTB1±

CML Differential

Output

Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML

outputs (+3.3V referenced) are capable of driving terminated transmission lines or

standard fiber-optic transmitter modules, and must be AC-coupled for

PECL-compatible connections.

ROUTA2±

ROUTB2±

CML Differential

Output

Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML

outputs (+3.3V referenced) are capable of driving terminated transmission lines or

standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible

connections.

INA1±

INB1±

Differential Input

Primary Differential Serial Data Input. The INx1± input accepts the serial data

stream for deserialization. The INx1± serial stream is passed to the receive CDR

circuit to extract the data content when INSELx = HIGH.

INA2±

INB2±

Secondary Differential Serial Data Input. The INx2± input accepts the serial data

stream for deserialization. The INx2± serial stream is passed to the receiver CDR

circuit to extract the data content when INSELx = LOW.

JTAG Interface

TMS

LVTTL Input,

internal pull-up

Test Mode Select. Used to control access to the JTAG Test Modes. If maintained

high for ≥5 TCLK cycles, the JTAG test controller is reset.

TCLK

TDO

TDI

LVTTL Input,

internal pull-down

JTAG Test Clock.

3-State LVTTL

Output

Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not

selected.

LVTTL Input,

internal pull-up

Test Data In. JTAG data input port.

TRST

LVTTL Input,

internal pull-up

JTAG reset signal. When asserted (LOW), this input asynchronously resets the

JTAG test access port controller.

Note

4. See “Device Configuration and Control Interface” on page 12 for detailed information on the internal latches.

Document #: 38-02103 Rev. *C

Page 9 of 24

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CYV15G0204RB

Pin Definitions (continued)

CYV15G0204RB Dual HOTLink II Deserializing Reclocker

Name

Power

V_CC

I/O Characteristics Signal Description

+3.3V Power.

GND

Signal and Power Ground for all internal circuits.

Analog Amplitude

CYV15G0204RB HOTLink II Operation

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow

operation with highly attenuated signals, or in high-noise

environments. The analog amplitude level detection is set by

the SDASELx latch via device configuration interface. The

SDASELx latch sets the trip point for the detection of a valid

signal at one of three levels, as listed in Table 1. This control

input affects the analog monitors for both receive channels.

The Analog Signal Detect monitors are active for the Line

Receiver as selected by the associated INSELx input.

The CYV15G0204RB is a highly configurable, independent

clocking, dual-channel reclocking deserializer designed to

support reliable transfer of large quantities of digital video

data, using high-speed serial links from multiple sources to

multiple destinations. This device supports two 10-bit

channels.

CYV15G0204RB Receive Data Path

Serial Line Receivers

Table 1. Analog Amplitude Detect Valid Signal Levels^[5]

SDASEL Typical Signal with Peak Amplitudes Above

Two differential Line Receivers, INx1± and INx2±, are

available on each channel for accepting serial data streams.

The active Serial Line Receiver on a channel is selected using

the associated INSELx input. The Serial Line Receiver inputs

are differential, and can accommodate wire interconnect and

filtering losses or transmission line attenuation greater than

16 dB. For normal operation, these inputs should receive a

signal of at least VI_DIFF> 100 mV, or 200 mV peak-to-peak

differential. Each Line Receiver can be DC- or AC-coupled to

+3.3V powered fiber-optic interface modules (any ECL/PECL

family, not limited to 100K PECL) or AC-coupled to +5V

powered optical modules. The common-mode tolerance of

these line receivers accommodates a wide range of signal

termination voltages. Each receiver provides internal

DC-restoration, to the center of the receiver’s common mode

range, for AC-coupled signals.

00

01

10

11

Analog Signal Detector is disabled

140 mV p-p differential

280 mV p-p differential

420 mV p-p differential

Transition Density

The Transition Detection logic checks for the absence of

transitions spanning greater than six transmission characters

(60 bits). If no transitions are present in the data received, the

Detection logic for that channel asserts LFIx.

Range Controls

The CDR circuit includes logic to monitor the frequency of the

PLL Voltage Controlled Oscillator (VCO) used to sample the

incoming data stream. This logic ensures that the VCO

operates at, or near the rate of the incoming data stream for

two primary cases:

Signal Detect/Link Fault

Each selected Line Receiver (i.e., that routed to the clock and

data recovery PLL) is simultaneously monitored for

• analog amplitude above amplitude level selected by

SDASELx

• when the incoming data stream resumes after a time in

which it has been “missing.”

• transition density above the specified limit

• range controls report the received data stream inside

normal frequency range (±1500^[21]ppm)

• when the incoming data stream is outside the acceptable

signaling rate range.

• receive channel enabled

• Presence of reference clock

• ULCx is not asserted.

To perform this function, the frequency of the RXPLL VCO is

periodically compared to the frequency of the TRGCLKx±

input. If the VCO is running at a frequency beyond

±1500 ppm^[21]as defined by the TRGCLKx± frequency, it is

periodically forced to the correct frequency (as defined by

TRGCLKx±, SPDSELx, and TRGRATEx) and then released in

an attempt to lock to the input data stream.

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFIx (Link Fault Indicator) output associated with each

receive channel, which changes synchronous to the receive

interface clock.

The sampling and relock period of the Range Control is calcu-

lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD

= (RECOVERED BYTE CLOCK PERIOD) * (4096).

Note

5. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals

may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase

the values in the table above by approximately 100 mV.

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CYV15G0204RB

During the time that the Range Control forces the RXPLL VCO

to track TRGCLKx±, the LFIx output is asserted LOW. After a

valid serial data stream is applied, it may take up to one

RANGE CONTROL SAMPLING PERIOD before the PLL

locks to the input data stream, after which LFIx will be HIGH.

switched back to the input data stream. If no data is present at

the selected line receiver, this switching behavior may result

in brief RXCLK± frequency excursions from TRGCLKx±.

However, the validity of the input data stream is indicated by

the LFIx output. The frequency of TRGCLKx± is required to be

within ±1500ppm^[21]of the frequency of the clock that drives

the reference clock input of the remote transmitter to ensure a

lock to the incoming data stream. This large ppm tolerance

allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001

Gbps SMPTE HD-SDI data stream with a constant TRGCLK

frequency.

The operating serial signaling-rate and allowable range of

TRGCLK± frequencies are listed in Table 2.

Table 2. Operating Speed Settings

TRGCLKx±

Signaling

SPDSELx TRGRATEx

Frequency

(MHz)

Rate (Mbps)

For systems using multiple or redundant connections, the LFIx

output can be used to select an alternate data stream. When

an LFIx indication is detected, external logic can toggle

selection of the associated INx1± and INx2± input through the

associated INSELx input. When a port switch takes place, it is

necessary for the receive PLL for that channel to reacquire the

new serial stream.

LOW

MID (Open)

HIGH

1

0

1

0

1

0

reserved

19.5–40

20–40

195–400

400–800

40–80

40–75

800–1500

Reclocker

80–150

Each receive channel performs a reclocker function on the

incoming serial data. To do this, the Clock and Data Recovery

PLL first recovers the clock from the data. The data is retimed

by the recovered clock and then passed to an output register.

Also, the recovered character clock from the receive PLL is

passed to the reclocker output PLL which generates the bit

clock that is used to clock the retimed data into the output

register. This data stream is then transmitted through the

differential serial outputs.

Receive Channel Enabled

The CYV15G0204RB contains two receive channels that can

be independently enabled and disabled. Each channel can be

enabled or disabled separately through the RXPLLPDx input

latch as controlled by the device configuration interface. When

the RXPLLPDx latch = 0, the associated PLL and analog

circuitry of the channel is disabled. Any disabled channel

indicates a constant link fault condition on the LFIx output.

When RXPLLPDx = 1, the associated PLL and receive

channel is enabled to receive a serial stream.

Reclocker Serial Output Drivers

The serial output interface drivers use differential Current

Mode Logic (CML) drivers to provide source-matched drivers

for 50Ω transmission lines. These drivers accept data from the

reclocker output register in the reclocker channel. These

drivers have signal swings equivalent to that of standard PECL

drivers, and are capable of driving AC-coupled optical

modules or transmission lines.

Note. When a disabled receive channel is reenabled, the

status of the associated LFIx output and data on the parallel

outputs for the associated channel may be indeterminate for

up to 2 ms.

Clock/Data Recovery

The extraction of a bit-rate clock and recovery of bits from each

received serial stream is performed by a separate CDR block

within each receive channel. The clock extraction function is

performed by an integrated PLL that tracks the frequency of

the transitions in the incoming bit stream and align the phase

of the internal bit-rate clock to the transitions in the selected

serial data stream.

Reclocker Output Channels Enabled

Each driver can be enabled or disabled separately via the

device configuration interface.

When a driver is disabled via the configuration interface, it is

internally powered down to reduce device power. If both

reclocker serial drivers for a channel are in this disabled state,

the associated internal reclocker logic is also powered down.

The deserialization logic and parallel outputs will remain

enabled. A device reset (RESET sampled LOW) disables all

output drivers.

Each CDR accepts a character-rate (bit-rate ÷ 10) or

half-character-rate (bit-rate ÷ 20) training clock from the

associated TRGCLKx± input. This TRGCLKx± input is used to

• ensure that the VCO (within the CDR) is operating at the

correct frequency (rather than a harmonic of the bit-rate)

Note. When the disabled reclocker function (i.e., both outputs

disabled) is re-enabled, the data on the reclocker serial

outputs may not meet all timing specifications for up to 250 μs.

• reduce PLL acquisition time

• limit unlocked frequency excursions of the CDR VCO when

there is no input data present at the selected Serial Line

Receiver.

Output Bus

Each receive channel presents a 10-bit data signal (and a

BIST status signal when RXBISTx[1:0] = 10).

Regardless of the type of signal present, the CDR attempts to

recover a data stream from it. If the signalling rate of the

recovered data stream is outside the limits set by the range

control monitors, the CDR tracks TRGCLKx± instead of the

data stream. Once the CDR output (RXCLK±) frequency

returns back close to TRGCLKx± frequency, the CDR input is

Receive BIST Operation

Each receiver channel contains an internal pattern checker

that can be used to validate both device and link operation.

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CYV15G0204RB

These pattern checkers are enabled by the associated

RXBISTx[1:0] latch via the device configuration interface.

When enabled, a register in the associated receive channel

becomes a signature pattern generator and checker by

logically converting to a Linear Feedback Shift Register

(LFSR). This LFSR generates a 511-character sequence. This

provides a predictable yet pseudo-random sequence that can

be matched to an identical LFSR in the attached Trans-

mitter(s). When synchronized with the received data stream,

the associated Receiver checks each character from the

deserializer with each character generated by the LFSR and

indicates compare errors and BIST status at the RXDx[1:0]

and BISTSTx bits of the Output Register.

down to reduce device power. If both serial drivers for a

channel are in this disabled state, the associated internal logic

for that channel is also powered down. When the reclocker

serial drivers are disabled, the reclocker function will be

disabled, but the deserialization logic and parallel outputs will

remain enabled.

Device Reset State

When the CYV15G0204RB is reset by assertion of RESET, all

state machines, counters, and configuration latches in the

device are initialized to a reset state. Additionally, the JTAG

controller must also be reset for valid operation (even if JTAG

testing is not performed). See “JTAG Support” on page 14 for

JTAG state machine initialization. See Table 3 on page 13 for

the initialize values of the configuration latches.

The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates

010b or 100b for one character period per BIST loop to

indicate loop completion. This status can be used to check test

pattern progress.

Following a device reset, it is necessary to enable the receive

channels used for normal operation. This can be done by

sequencing the appropriate values on the device configuration

interface.^[3]

The specific status reported by the BIST state machine is listed

in Table 5. These same codes are reported on the receive

status outputs.

Device Configuration and Control Interface

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state

machine aborts the compare operations and resets the LFSR

to look for the start of the BIST sequence again.

The CYV15G0204RB is highly configurable via the configu-

ration interface. The configuration interface allows each

channel to be configured independently. Table 3 on page 13

lists the configuration latches within the device including the

initialization value of the latches upon the assertion of RESET.

Table 4 on page 14 shows how the latches are mapped in the

device. Each row in the Table 4 maps to a 7-bit latch bank.

There are 6 such write-only latch banks. When WREN = 0, the

logic value in the DATA[6:0] is latched to the latch bank

specified by the values in ADDR[2:0]. The second column of

Table 4 specifies the channels associated with the corre-

sponding latch bank. For example, the first three latch banks

(0,1 and 2) consist of configuration bits for channel A.

A device reset (RESET sampled LOW) presets the BIST

Enable Latches to disable BIST on both channels.

BIST Status State Machine

When a receive path is enabled to look for and compare the

received data stream with the BIST pattern, the {BISTSTx,

RXDx[0], RXDx[1]} bits identify the present state of the BIST

compare operation.

The BIST state machine has multiple states, as shown in

Figure 2 and Table 5. When the receive PLL detects an

out-of-lock condition, the BIST state is forced to the

Start-of-BIST state, regardless of the present state of the BIST

state machine. If the number of detected errors ever exceeds

the number of valid matches by greater than 16, the state

machine is forced to the WAIT_FOR_BIST state where it

monitors the receive path for the first character of the next

BIST sequence.

Latch Types

There are two types of latch banks: static (S) and dynamic (D).

Each channel is configured by 2 static and 1 dynamic latch

banks. The S type contain those settings that normally do not

change for a given application, whereas the D type controls

the settings that could change during the application's lifetime.

The first and second rows of each channel (address numbers

0, 1, 5, and 6) are the static control latches. The third row of

latches for each channel (address numbers 2, 7) are the

dynamic control latches that are associated with enabling

dynamic functions within the device. Address numbers 3 and

4 are internal test registers.

Power Control

The CYV15G0204RB supports user control of the powered up

or down state of each transmit and receive channel. The

receive channels are controlled by the RXPLLPDx latch via the

device configuration interface. When RXPLLPDx = 0, the

associated PLL and analog circuitry of the channel is disabled.

The transmit channels are controlled by the OE1x and the

OE2x latches via the device configuration interface. The

reclocker function is controlled by the ROE1x and the ROE2x

latches via the device configuration interface. When a driver is

disabled via the configuration interface, it is internally powered

Static Latch Values

There are some latches in the table that have a static value (ie.

1, 0, or X). The latches that have a ‘1’ or ‘0’ must be configured

with their corresponding value each time that their associated

latch bank is configured. The latches that have an ‘X’ are don’t

cares and can be configured with any value.

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CYV15G0204RB

Table 3. Device Configuration and Control Latch Descriptions

Name

Signal Description

RXRATEA

RXRATEB

Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select

the rate of the RXCLKx± clock output.

When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered

clock operating at half the character rate. Data for the associated receive channels should be latched

alternately on the rising edge of RXCLKx+ and RXCLKx–.

When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered

clock operating at the character rate. Data for the associated receive channels should be latched on the

rising edge of RXCLKx+ or falling edge of RXCLKx–.

SDASEL1A[1:0]

SDASEL1B[1:0]

Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the

INx1± Primary Differential Serial Data Inputs.

When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.

When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

SDASEL2A[1:0]

SDASEL2B[1:0]

Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the

INx2± Secondary Differential Serial Data Inputs.

When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled

When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

TRGRATEA

TRGRATEB

Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to

select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0,

the associated TRGCLKx± input is not multiplied before it is passed to the CDR PLL. When TRGRATEx

= 1, the TRGCLKx± input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and

SPDSELx = LOW is an invalid state and this combination is reserved.

RXPLLPDA

RXPLLPDB

Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the

associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive

PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and

analog circuitry are enabled.

RXBISTA[1:0]

RXBISTB[1:0]

Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11.

For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0]

selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception.

When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated channel is set to

receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled and the associated

channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states.

ROE2A

ROE2B

Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the

ROE2x latch = 0. ROE2x selects if the ROUT2± secondary differential output drivers are enabled or

disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be

transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is disabled.

When a driver is disabled via the configuration interface, it is internally powered down to reduce device

power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that

channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers.

ROE1A

ROE1B

Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x

latch = 0. ROE1x selects if the ROUT1± primary differential output drivers are enabled or disabled. When

ROE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the

transmit shifter. When ROE1x = 0, the associated serial data output driver is disabled. When a driver is

disabled via the configuration interface, it is internally powered down to reduce device power. If both serial

drivers for achannel areinthis disabled state, the associated internal logic for that channel is also powered

down. A device reset (RESET sampled LOW) disables all output drivers.

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CYV15G0204RB

Device Configuration Strategy

To ensure valid device operation after power-up (including

non-JTAG operation), the JTAG state machine should also be

initialized to a reset state. This should be done in addition to

the device reset (using RESET). The JTAG state machine can

be initialized using TRST (asserting it LOW and de-asserting

it or leaving it asserted), or by asserting TMS HIGH for at least

5 consecutive TCLK cycles. This is necessary in order to

ensure that the JTAG controller does not enter any of the test

modes after device power-up. In this JTAG reset state, the rest

of the device will be in normal operation.

The following is a series of ordered events needed to load the

configuration latches on a per channel basis:

1. Pulse RESET Low after device power-up. This operation

resets both channels. Initialize the JTAG state machine to

its reset state as detailed in JTAG Support.

2. Set the static latch banks for the target channel. [Optional

step if the default settings match the desired configuration.]

3. Set the dynamic bank of latches for the target channel.

Enable the Receive PLLs and set each channel for SMPTE

data reception (RXBISTx[1:0] = 01) or BIST data reception

(RXBISTx[1:0] = 10). [Required step]

Note. The order of device reset (using RESET) and JTAG

initialization does not matter.

3-Level Select Inputs

JTAG Support

Each 3-Level select inputs reports as two bits in the scan

register. These bits report the LOW, MID, and HIGH state of

the associated input as 00, 10, and 11 respectively

The CYV15G0204RB contains a JTAG port to allow system

level diagnosis of device interconnect. Of the available JTAG

modes, boundary scan, and bypass are supported. This

capability is present only on the LVTTL inputs and outputs and

the TRGCLKx± clock input. The high-speed serial inputs and

outputs are not part of the JTAG test chain.

JTAG ID

The JTAG device ID for the CYV15G0204RB is ‘0C811069’x.

Table 4. Device Control Latch Configuration Table

Reset

Value

ADDR Channel Type

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

0

A

B

S

D

S

D

1

0

X

0

RXRATEA

101111

(000b)

1

SDASEL2A[1]

RXBISTA[1]

1

SDASEL2A[0]

RXPLLPDA

0

SDASEL1A[1]

RXBISTA[0]

X

SDASEL1A[0]

X

ROE2A

0

X

ROE1A

0

TRGRATEA

101011

101100

101111

101011

101100

(001b)

2

X

(010b)

5

X

RXRATEB

TRGRATEB

X

(101b)

6

SDASEL2B[1]

RXBISTB[1]

SDASEL2B[0]

RXPLLPDB

SDASEL1B[1]

RXBISTB[0]

SDASEL1B[0]

X

(110b)

7

ROE2B

ROE1B

(111b)

Table 5. Receive BIST Status Bits

{BISTSTx, RXDx[0], RXDx[1]}

Description

Receive BIST Status

(Receive BIST = Enabled)

000, 001

010

BIST Data Compare. Character compared correctly.

BIST Last Good. Last Character of BIST sequence detected and valid.

Reserved.

011

100

BIST Last Bad. Last Character of BIST sequence detected invalid.

101

BIST Start. Receive BIST is enabled on this channel, but character compares have not yet

commenced. This also indicates a PLL Out of Lock condition.

110

111

BIST Error. While comparing characters, a mismatch was found in one or more of the character

bits.

BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST

character to enable the LFSR.

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CYV15G0204RB

Figure 2. Receive BIST State Machine

Monitor Data

Receive BIST

Received

Detected LOW

{BISTSTx, RXDx[0],

RXDx[1]} =

BIST_START (101)

RX PLL

Out of Lock

{BISTSTx, RXDx[0], RXDx[1]} =

BIST_WAIT (111)

Start of

BIST Detected

No

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_DATA_COMPARE (000, 001)

Compare

Next Character

Mismatch

{BISTSTx, RXDx[0], RXDx[1]} =

BIST_DATA_COMPARE (000, 001)

Match

Auto-Abort

Condition

Yes

No

End-of-BIST

State

End-of-BIST

State

No

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_LAST_BAD (100)

Yes, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_LAST_GOOD (010)

No, {BISTSTx, RXDx[0], RXDx[1]} =

BIST_ERROR (110)

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CYV15G0204RB

Static Discharge Voltage..........................................> 2000 V

(per MIL-STD-883, Method 3015)

Maximum Ratings

Above which the useful life may be impaired. User guidelines

only, not tested

Latch-up Current.....................................................> 200 mA

Power-up Requirements

Storage Temperature ..................................–65°C to +150°C

The CYV15G0204RB requires one power-supply. The Voltage

on any input or I/O pin cannot exceed the power pin during

power-up.

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +3.8V

Operating Range

DC Voltage Applied to LVTTL Outputs

in High-Z State .......................................–0.5V to V_CC+ 0.5V

Range

Ambient Temperature

V_CC

Output Current into LVTTL Outputs (LOW)..................60 mA

DC Input Voltage....................................–0.5V to V_CC+ 0.5V

Commercial

0°C to +70°C

+3.3V ±5%

CYV15G0204RB DC Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL-compatible Outputs

V_OHT

V_OLT

I_OST

I_OZL

Output HIGH Voltage

Output LOW Voltage

I_OH= − 4 mA, V_CC= Min.

I_OL= 4 mA, V_CC= Min.

V_OUT= 0V^[6], V_CC= 3.3V

V_OUT= 0V, V_CC

2.4

V

0.4

–100

20

Output Short Circuit Current

–20

mA

µA

High-Z Output Leakage Current

LVTTL-compatible Inputs

V_IHT

V_ILT

I_IHT

Input HIGH Voltage

2.0

V_CC+ 0.3

0.8

V

Input LOW Voltage

Input HIGH Current

–0.5

V

TRGCLKx Input, V_IN= V_CC

Other Inputs, V_IN= V_CC

TRGCLKx Input, V_IN= 0.0V

Other Inputs, V_IN= 0.0V

1.5

mA

µA

mA

µA

+40

I_ILT

Input LOW Current

–1.5

–40

I_IHPDT

I_ILPUT

Input HIGH Current with internal pull-down V_IN= V_CC

+200

–200

Input LOW Current with internal pull-up

V_IN= 0.0V

LVDIFF Inputs: TRGCLKx±

[7]

V_DIFF

Input Differential Voltage

400

1.2

0.0

1.0

V_CC

mV

V

V_IHHP

Highest Input HIGH Voltage

Lowest Input LOW voltage

Common Mode Range

V_ILLP

V_CC/2

V

[8]

V_COMREF

V_CC– 1.2V

V

3-Level Inputs

V_IHH

V_IMM

V_ILL

I_IHH

I_IMM

I_ILL

Three-Level Input HIGH Voltage

Min. ≤ V_CC≤ Max.

V_IN= V_CC

0.87 * V_CC

0.47 * V_CC

0.0

V_CC

0.53 * V_CC

0.13 * V_CC

200

V

Three-Level Input MID Voltage

Three-Level Input LOW Voltage

Input HIGH Current

V

µA

Input MID current

V_IN= V_CC/2

–50

50

Input LOW current

V_IN= GND

–200

Notes

6. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

7. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the

true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.

8. The common mode range defines the allowable range of TRGCLKx+ and TRGCLKx− when TRGCLKx+ = TRGCLKx−. This marks the zero-crossing between

the true and complement inputs as the signal switches between a logic-1 and a logic-0.

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CYV15G0204RB

CYV15G0204RB DC Electrical Characteristics (continued)

Parameter

Description

Test Conditions

Min.

Max.

Unit

Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±

V_OHC

V_OLC

V_ODIF

Output HIGH Voltage

(V_CCReferenced)

100Ω differential load

150Ω differential load

100Ω differential load

150Ω differential load

100Ω differential load

150Ω differential load

V

_CC– 0.5

V_CC– 0.2

V_CC– 0.7

900

V

V_CC– 0.5

V_CC– 1.4

Output LOW Voltage

(V_CCReferenced)

V

V_CC– 1.4

V

Output Differential Voltage

|(OUT+) − (OUT−)|

450

mV

560

1000

Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±

[7]

V_DIFFs

V_IHE

V_ILE

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

100

1200

V_CC

mV

V

V_CC– 2.0

V

I_IHE

V_IN= V_IHEMax.

V_IN= V_ILEMin.

1350

+3.1

μA

V

I_ILE

Input LOW Current

–700

[9]

VI_COM

Common Mode input range

((V_CC– 2.0V)+0.5)min,

(V_CC– 0.5V) max.

+1.25

Power Supply

Typ.

Max.

720

[10, 11]

I_CC

Max Power Supply Current

TRGCLKx= Commercial

620

mA

MAX

Industrial

1320

700

[10, 11]

I_CC

Typical Power Supply Current

TRGCLKx= Commercial

125 MHz

600

Industrial

1320

AC Test Loads and Waveforms

3.3V

R_L= 100Ω

R

L

R1

R2

R1 = 590Ω

R2 = 435Ω

C_L≤ 7 pF

(Includes fixture and

probe capacitance)

(b) CML Output Test Load^[12]

C_L

(Includes fixture and

probe capacitance)

(a) LVTTL Output Test Load^[12]

V_IHE

3.0V

V_IHE

2.0V

0.8V

2.0V

0.8V

80%

V_th= 1.4V

20%

V_ILE

≤ 270 ps

GND

V_ILE

≤ 270 ps

≤ 1 ns

(c) LVTTL Input Test Waveform^[13]

(d) CML/LVPECL Input Test Waveform

Notes

9. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

10. Maximum I is measured with V = MAX, T = 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and

CC

A

outputs unloaded.

11. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C, with both channels enabled and one Serial Line Driver per transmit channel

CC

A

sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.

12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.

Document #: 38-02103 Rev. *C

Page 17 of 24

[+] Feedback

CYV15G0204RB

CYV15G0204RB AC Electrical Characteristics

Parameter

Description

Min.

Max

Unit

CYV15G0204RB Receiver LVTTL Switching Characteristics Over the Operating Range

f_RS

RXCLKx± Clock Output Frequency

9.75

6.66

150

102.56

+1.0

1.2

MHz

ns

t_RXCLKP

t_RXCLKD

t_RXCLKR

RXCLKx± Period = 1/f_RS

RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)

RXCLKx± Rise Time

–1.0

ns

[14]

0.3

ns

t_RXCLKF

RXCLKx± Fall Time

0.3

1.2

ns

[18]

t_RXDv–

t_RXDv+

f_ROS

Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)

Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)

Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)

Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)

RECLKOx Clock Frequency

5UI–2.0^[19]

5UI–1.3^[19]

5UI–1.8^[19]

5UI–2.6^[19]

19.5

ns

[18]

ns

150

51.28

0

MHz

ns

t_RECLKO

RECLKOx Period=1/f_ROS

6.66

t_RECLKOD

RECLKOx Duty Cycle centered at 60% HIGH time

–1.9

ns

CYV15G0204RB TRGCLKx Switching Characteristics Over the Operating Range

f_TRG

TRGCLKx Clock Frequency

19.5

6.6

150

MHz

ns

%

t_TRGCLK

t_TRGH

TRGCLKx Period = 1/f_REF

51.28

TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)

TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)

TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)

TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)

TRGCLKx Duty Cycle

5.9

2.9^[14]

t_TRGL

5.9

2.9^[14]

30

[20]

t_TRGD

70

2

[14, 15, 16, 17]

t_TRGR

TRGCLKx Rise Time (20%–80%)

ns

%

[14, 15, 16, 17]

[21]

t_TRGF

TRGCLKx Fall Time (20%–80%)

2

t_TRGRX

TRGCLKx Frequency Referenced to Received Clock Frequency

–0.15

+0.15

CYV15G0204RB Bus Configuration Write Timing Characteristics Over the Operating Range

t_DATAH

t_DATAS

t_WRENP

Bus Configuration Data Hold

0

ns

Bus Configuration Data Setup

Bus Configuration WREN Pulse Width

10

CYV15G0204RB JTAG Test Clock Characteristics Over the Operating Range

f_TCLK

t_TCLK

JTAG Test Clock Frequency

JTAG Test Clock Period

20

MHz

ns

50

30

CYV15G0204RB Device RESET Characteristics Over the Operating Range

t_RST

Device RESET Pulse Width

ns

Notes

14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

15. The ratio of rise time to falling time must not vary by greater than 2:1.

16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

17. All transmit AC timing parameters measured with 1ns typical rise time and fall time.

18. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.

19. Receiver UI (Unit Interval) is calculated as 1/(f

* 20) (when TRGRATEx = 1) or 1/(f

* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t .

TRG

T

R

G

B

20. The duty cycle specification is a simultaneous condition with the t

and t

parameters. This means that at faster character rates the TRGCLKx± duty

REFL

REFH

cycle cannot be as large as 30%–70%.

21. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.

TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel

necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be

within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.

Document #: 38-02103 Rev. *C

Page 18 of 24

[+] Feedback

CYV15G0204RB

CYV15G0204RB AC Electrical Characteristics (continued)

Parameter

Description

Min.

Max

Unit

CYV15G0204RB Reclocker Serial Output Characteristics Over the Operating Range

Parameter

Description

Condition

Min.

5128

50

Max.

660

Unit

ps

t_B

t_RISE

Bit Time

[14]

CML Output Rise Time 20−80% (CML Test Load)

SPDSELx = HIGH

SPDSELx = MID

SPDSELx =LOW

SPDSELx = HIGH

SPDSELx = MID

SPDSELx =LOW

270

ps

100

180

50

500

ps

1000

270

ps

[14]

t_FALL

CML Output Fall Time 80−20% (CML Test Load)

ps

100

180

500

ps

1000

ps

PLL Characteristics

Parameter

Description

Condition

Min. Typ.

Max. Unit

CYV15G0204RB Reclocker Output PLL Characteristics

[14, 22]

t_JRGENSD

Reclocker Jitter Generation - SD Data Rate

Reclocker Jitter Generation - HD Data Rate

TRGCLKx = 27 MHz

133

107

ps

[14, 22]

t_JRGENHD

TRGCLKx = 148.5 MHz

CYV15G0204RB Receive PLL Characteristics Over the Operating Range

t_RXLOCK

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL Unlock Rate

376k

46

UI

t_RXUNLOCK

Capacitance ^[14]

Parameter

C_INTTL

Description

Test Conditions

Max.

Unit

TTL Input Capacitance

PECL input Capacitance

T_A= 25°C, f₀= 1 MHz, V_CC= 3.3V

7

4

pF

C_INPECL

Switching Waveforms for the CYV15G0204RB HOTLink II Receiver

Receive Interface

Read Timing

t_RXCLKP

RXRATEx = 0

RXCLKx+

RXCLKx–

t

RXDV

–

RXDx[9:0]

t

RXDV+

Note

22. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The measure-

ment was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.

Document #: 38-02103 Rev. *C

Page 19 of 24

[+] Feedback

CYV15G0204RB

Switching Waveforms for the CYV15G0204RB HOTLink II Receiver (continued)

Receive Interface

Read Timing

t_RXCLKP

RXRATEx = 1

RXCLKx+

RXCLKx–

RXDx[9:0]

t

RXDV

–

t

RXDV+

CYV15G0204RB HOTLink II Bus Configuration Switching Waveforms

Bus Configuration

Write Timing

ADDR[2:0]

DATA[6:0]

t_WRENP

t_DATAS

WREN

t_DATAH

Document #: 38-02103 Rev. *C

Page 20 of 24

[+] Feedback

CYV15G0204RB

Table 6. Package Coordinate Signal Allocation

Ball

ID

Ball

ID

Ball

ID

Signal Name

Signal Type

Signal Name

Signal Type

Signal Name

Signal Type

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C01

C02

C03

NC

NO CONNECT

POWER

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E01

E02

E03

E04

E17

E18

E19

E20

F01

NC

GND

NO CONNECT

GROUND

F17

F18

F19

F20

G01

G02

G03

G04

G17

G18

G19

G20

H01

H02

H03

H04

H17

H18

H19

H20

J01

J02

J03

J04

J17

J18

J19

J20

K01

K02

K03

K04

K17

K18

K19

K20

L01

L02

L03

L04

L17

L18

L19

VCC

NC

POWER

NO CONNECT

GROUND

NC

DATA[6]

DATA[4]

DATA[2]

DATA[0]

GND

LVTTL IN PU

GROUND

NC

VCC

GND

WREN

GND

NC

INB1–

ROUTB1–

GND

CML IN

LVTTL IN PU

GROUND

CML OUT

GROUND

CML IN

NC

NO CONNECT

3-LEVEL SEL

POWER

GROUND

INB2–

ROUTB2–

INA1–

ROUTA1–

GND

SPDSELB

VCC

NO CONNECT

3-LEVEL SEL

NO CONNECT

GROUND

CML OUT

CML IN

NC

LDTDEN

TRST

GND

LVTTL IN PU

GROUND

SPDSELA

NC

CML OUT

GROUND

CML IN

GND

NC

INA2–

ROUTA2–

VCC

TDO

LVTTL 3-S OUT

LVTTL IN PD

LVTTL IN PU

LVTTL IN

GROUND

CML OUT

POWER

TCLK

RESET

INSELB

INSELA

VCC

GROUND

VCC

POWER

GROUND

NC

NO CONNECT

POWER

LVTTL IN

GROUND

VCC

POWER

GROUND

NC

NO CONNECT

POWER

ULCA

NC

LVTTL IN PU

NO CONNECT

GROUND

VCC

GROUND

NC

NO CONNECT

POWER

GND

GROUND

VCC

DATA[5]

DATA[3]

DATA[1]

GND

LVTTL IN PU

GROUND

NC

NO CONNECT

POWER

GROUND

VCC

NO CONNECT

GROUND

INB1+

ROUTB1+

GND

CML IN

NC

CML OUT

GROUND

CML IN

GND

GROUND

NC

GND

GROUND

NC

INB2+

ROUTB2+

INA1+

ROUTA1+

GND

NC

NO CONNECT

POWER

NC

CML OUT

CML IN

VCC

NC

NO CONNECT

POWER

GND

NC

CML OUT

GROUND

CML IN

VCC

GROUND

SCANEN2

TMEN3

VCC

LVTTL IN PD

POWER

NO CONNECT

GROUND

INA2+

ROUTA2+

VCC

NC

CML OUT

POWER

NC

VCC

POWER

NC

NO CONNECT

LVTTL IN PU

POWER

VCC

POWER

NC

VCC

POWER

NC

VCC

POWER

NC

VCC

POWER

GND

NC

TDI

VCC

POWER

NO CONNECT

TMS

VCC

POWER

NC

VCC

NC

NO CONNECT

NC

Document #: 38-02103 Rev. *C

Page 21 of 24

[+] Feedback

CYV15G0204RB

Table 6. Package Coordinate Signal Allocation (continued)

Ball

ID

Ball

ID

Ball

ID

Signal Name

Signal Type

Signal Name

Signal Type

Signal Name

Signal Type

C04

C05

C06

M03

M04

M17

M18

M19

M20

N01

N02

N03

N04

N17

N18

N19

N20

P01

P02

P03

P04

P17

P18

P19

P20

R01

R02

R03

R04

R17

R18

R19

R20

T01

T02

T03

T04

T17

T18

T19

T20

U01

U02

VCC

ULCB

NC

POWER

F02

F03

F04

U03

U04

U05

U06

U07

U08

U09

U10

NC

VCC

NO CONNECT

POWER

L20

M01

M02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

GND

NC

GROUND

NO CONNECT

LVTTL OUT

POWER

LVTTL IN PU

NO CONNECT

GROUND

VCC

POWER

NC

VCC

POWER

LFIB

NC

VCC

POWER

RXCLKB–

VCC

NC

VCC

POWER

NC

RXDB[4]

RXDB[3]

GND

LVTTL OUT

GROUND

LVTTL IN PU

PECL IN

RXDB[6]

RXDB[0]

GND

LVTTL OUT

GROUND

NC

GND

NC

GROUND

GND

ADDR [2]

ADDR [1]

RXCLKA+

REPDOA

GND

LVTTL IN PU

LVTTL OUT

GROUND

ADDR [0]

GROUND

U11 TRGCLKB–

GROUND

U12

U13

U14

U15

U16

U17

U18

U19

U20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

GND

GROUND

POWER

GROUND

GND

GROUND

VCC

POWER

GROUND

VCC

POWER

VCC

POWER

NO CONNECT

GROUND

RXDA[4]

VCC

LVTTL OUT

POWER

LFIA

LVTTL OUT

PECL IN

NC

W18 TRGCLKA+

NC

BISTSTA

RXDA[0]

VCC

LVTTL OUT

POWER

W19

W20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

RXDA[6]

RXDA[3]

VCC

LVTTL OUT

POWER

NC

GND

NC

GROUND

VCC

POWER

VCC

POWER

GROUND

VCC

POWER

RXDB[9]

RXCLKB+

VCC

LVTTL OUT

POWER

GROUND

RXDB[8]

VCC

LVTTL OUT

POWER

NO CONNECT

POWER

NC

RXDB[5]

RXDB[1]

GND

LVTTL OUT

GROUND

LVTTL OUT

GROUND

PECL IN

RXDB[7]

RXDB[2]

GND

LVTTL OUT

GROUND

NC

VCC

BISTSTB

GND

RECLKOB

NC

LVTTL OUT

NO CONNECT

GROUND

POWER

V11 TRGCLKB+

GND

POWER

V12

V13

V14

V15

V16

V17

V18

V19

V20

W01

W02

RECLKOA

GND

LVTTL OUT

GROUND

POWER

RXCLKA–

GND

LVTTL OUT

GROUND

POWER

GND

GROUND

POWER

VCC

POWER

VCC

POWER

VCC

POWER

RXDA[9]

RXDA[5]

RXDA[2]

RXDA[1]

VCC

LVTTL OUT

POWER

REPDOB

LVTTL OUT

PECL IN

POWER

Y18 TRGCLKA–

POWER

Y19

Y20

RXDA[8]

RXDA[7]

LVTTL OUT

POWER

VCC

POWER

Document #: 38-02103 Rev. *C

Page 22 of 24

[+] Feedback

CYV15G0204RB

Ordering Information

Package

Name

Operating

Range

Speed

Ordering Code

Package Type

Standard CYV15G0204RB-BGC

Standard CYV15G0204RB-BGXC

BL256

256-Ball Thermally Enhanced Ball Grid Array

Commercial

Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Commercial

Package Diagram

Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256

TOP VIEW

0.20ꢀ4ꢁX

BOTTOM VIEW ꢀBALL SIDEX

A

27.00 0.13

Ø0.15 M C

Ø0.30 M C

A

B

A1 CORNER I.D.

24.13

Ø0.75 0.15ꢀ256ꢁX

20 18

19

16

14

12

10

8

6

4

2

17

15

13

11

9

7

5

3

1

A

B

C

D

E

F

G

H

J

R 2.5 Max ꢀ4ꢁX

K

L

M

N

P

R

T

A

U

V

W

Y

A

0.50 MIN.

B

1.57 0.175

0.97 REF.

0.15

C

26°

0.15

C

0.60 0.10

0.20 MIN

TOP OF MOLD COMPOUND

TO TOP OF BALLS

TYP.

C

SEATING PLANE

SIDE VIEW

SECTION A-A

51-85123-*E

HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and

company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-02103 Rev. *C

Page 23 of 24

use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to

be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CYV15G0204RB

Document History Page

Document Title: CYV15G0204RB Independent Clock Dual HOTLink II™ Reclocking Deserializer

Document Number: 38-02103

ISSUE

DATE

ORIG. OF

CHANGE

REV.

ECN NO.

DESCRIPTION OF CHANGE

**

246850

338721

384307

1034083

See ECN

FRE

SUA

AGT

UKK

New Data Sheet

*A

*B

*C

Added Pb-Free package option availability

Revised setup and hold times (t_RXDV-t_RXDV+t_RXDV+

)

Added clarification for the necessity of JTAG controller reset and the

methods to implement it.

Document #: 38-02103 Rev. *C

Page 24 of 24

[+] Feedback


型号：	CYV15G0204RB
厂家：	CYPRESS
描述：	Independent Clock Dual HOTLink II⑩ Reclocking Deserializer 独立时钟双的HOTLink II⑩时钟恢复器和解串器时钟
文件：	总24页 (文件大小：705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYV15G0204RB [CYPRESS]

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