CYW2332ZITR [CYPRESS]
PLL Frequency Synthesizer, PDSO20, 0.173 INCH, TSSOP-20;
| 型号： | CYW2332ZITR |
| 厂家： | 
CYPRESS |
| 描述： | PLL Frequency Synthesizer, PDSO20, 0.173 INCH, TSSOP-20 光电二极管 |
| 文件： | 总13页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32
PRELIMINARY
CYW2332
Dual Serial Input PLL with 1.2-GHz and 600-MHz Prescalers
Features
Applications
• Operating voltage 2.7V to 5.5V
• Operating frequency to 1.2 GHz and 600 MHz with in-
puts of –15 dBm and VCC of 3.0V
The Cypress CYW2332 is a dual serial input PLL frequency
synthesizer designed to combine the RF and IF mixer frequen-
cy sections of wireless communications systems. One 1.2-
GHz and one 600-MHz prescaler, each with pulse swallow ca-
pability are included. The device operates from 2.7V and dis-
sipates only 15 mW.
• Lock detect feature
µA typical at 3.0V
• Power-down mode ICC < 1
• Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
• Available in a 24-pin CSP (Chip Scale Package)
• Available in a 20-pin MLF (Mirco Lead Frame Package)
Dual Hi-Lo PLL Block Diagram
GND (4)
GND (7)
VCC1 (1)
VCC2 (20)
VP1 (2)
FIN1 (5)
Prescaler
64/65 or
128/129
fp1
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
DOPLL1 (3)
Phase
Detector
Charge
Pump
FIN1# (6)
19-Bit
Latch
Pwr-dwn
PLL1
OSC_IN (8)
fr fp
fr1
fr2
15-Bit
Monitor
Output
Selector
Reference Counter
FO/LD (10)
20-Bit Latch
Latch
Selector
LE (13)
DATA (12)
20-Bit Latch
Power
Control
15-Bit
Reference Counter
22-Bit
Shift
Cntrl
Reg.
CLOCK (11)
19-Bit
Latch
Pwr-dwn
PLL2
Phase
Detector
Charge
Pump
F
IN2 (16)
Prescaler
8/9 or
16/17
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
DOPLL2 (18)
fp2
FIN2# (15)
GND (14)
GND (9)
GND (17)
VP2 (19)
Pin Configuration
V
1
1
2
20
V
2
CC
CC
21
1
NC
NC
V 1
19
18
17
16
15
14
13
12
11
V 2
P
P
20
2
DoPLL2
Vp1
D PLL1
3
D PLL2
O
O
19
3
GND
DoPLL1
1
15
DoPLL1
GND
GND
4
GND
18
4
Fin2
GND
2
3
4
5
GND
Fin1
14
13
12
11
Fin2
Fin2#
GND
LE
17
5
(Top View)
Fin1
Fin2#
F
1
5
F
F
2
(Top View)
IN
IN
IN
16
6
GND
Fin1#
Fin1#
GND
F
1#
6
2#
IN
15
7
LE
GND
GND
OSC_IN
GND
7
GND
LE
14
8
DATA
OSC_IN
8
13
9
NC
NC
9
DATA
CLOCK
F /LD
10
O
MLF
TSSOP
CSP
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07238 Rev. **
Revised September 27, 2001
PRELIMINARY
CYW2332
Pin Definitions
Pin
No.
(TSSO
P)
Pin
No.
(CSP)
Pin
No.
Pin
Type
Pin Name
(MLF)
Pin Description
VCC
1
1
2
3
24
19
20
1
P
P
O
Power Supply Connection for PLL1 and PLL2: When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
VP1
2
PLL1 Charge Pump Rail Voltage: This voltage accommo-
dates VCO circuits with tuning voltages higher than the VCC of
PLL1.
DOPLL1
3
PLL1 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
FIN1
5
6
5
6
3
4
I
I
Input to PLL1 Prescaler: Maximum frequency 1.2 GHz.
FIN1#
Complementary Input to PLL1 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
OSC_IN
FO/LD
8
8
6
8
I
Oscillator Input: This input has a VCC/2 threshold and CMOS
logic level sensitivity.
10
11
O
Lock Detect Pin of PLL1 Section: This output is HIGH when
the loop is locked. It is multiplexed to the output of the program-
mable counters or reference dividers in the test program mode.
(Refer to Table 3 for configuration.)
CLOCK
11
12
9
I
Data Clock Input: One bit of data is loaded into the Shift Reg-
ister on the rising edge of this signal.
DATA
LE
12
13
14
15
10
11
I
I
Serial Data Input
Load Enable: On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state of
the control bits.
FIN2#
15
17
13
I
Complementary Input to PLL2 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
FIN2
16
18
18
20
14
16
I
Input to PLL2 Prescaler: Maximum frequency 600 MHz.
DOPLL2
O
PLL2 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
VP2
19
20
22
23
17
18
P
P
G
PLL2 Charge Pump Rail Voltage: This voltage accommo-
dates VCO circuits with tuning voltages higher than the VCC of
PLL2.
VCC
2
Power SupplyConnectionsforPLL1andPLL2:When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
GND
4, 7, 9,
14, 17
4,7,10,
16, 19
2, 5, 7,
12, 15
Analog and Digital Ground Connections: This pin must be
grounded.
Document #: 38-07238 Rev. **
Page 2 of 13
PRELIMINARY
CYW2332
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
Parameter
VCC or VP
VOUT
Description
Power Supply Voltage
Rating
–0.5 to +6.5
–0.5 to VCC+0.5
±15
Unit
V
Output Voltage
V
IOUT
Output Current
mA
°C
°C
TL
Lead Temperature
Storage Temperature
+260
TSTG
–55 to +150
Always turn off power before adding or removing devices from
system.
Handling Precautions
Devices should be transported and stored in antistatic con-
tainers.
Protect leads with a conductive sheet when handling or trans-
porting PC boards with devices.
These devices are static sensitive. Ensure that equipment and
personnel contacting the devices are properly grounded.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a mois-
ture free environment for 24 hours prior to assembly in less
than 24 hours.
Cover workbenches with grounded conductive mats.
Recommended Operating Conditions
Parameter
Description
Power Supply Voltage
Test Condition
Rating
Unit
VCC1
,
2.7 to 5.5
V
VCC2
VP
TA
Charge Pump Voltage
Operating Temperature
VCC to +5.5
V
Ambient air at 0 CFM flow
–40 to +85
°C
Document #: 38-07238 Rev. **
Page 3 of 13
PRELIMINARY
CYW2332
Electrical Characteristics: VCC = VP = 2.7V to 5.5V, TA = –40°C to +85°C, Unless otherwise specified
Parameter
Description
Test Condition
Pin
Min.
Typ.
Max.
Unit
ICC
Power Supply Current
PLL1 + PLL2
VCC1 = VCC2 = 3.0V
VCC1,
5.5
mA
VCC
VCC1,
VCC
2
µA
IPD
Power-down Current
Power-down, VCC = 3.0V
1
25
2
FIN1
FIN2
FOSC
Operating Frequency
PLL1
PLL2
FIN1
100
45
5
1200
600
45
MHz
MHz
MHz
FIN2
Oscillator Input Frequen-
cy
OSC_IN
Fφ
Phase Detector Frequen-
cy
10
MHz
PFIN1
Input Sensitivity
VCC = 3.0V, ZIN = 50Ω
FIN1
–15
–10
–10
0.5
4
4
4
dBm
dBm
dBm
VP–P
µA
VCC = 5.0V, ZIN = 50Ω
PFIN2
VOSC
IIH, IIL
VCC = 2.7V to 5.5V, ZIN = 50Ω
FIN2
Oscillator Input Sensitivity VCC = 3.0V
OSC_IN
High/Low Level Input
Current
±50
V
CC = 3.0V
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
DATA,
CLOCK,
LE
VCC * 0.8
V
V
VIL
VCC * 0.2
µA
µA
V
IIH
–10
–10
0.5
0.5
10
10
IIL
VOH
High level Output Voltage VCC = 3.0V, VI = -1 mA
FO/LD
VCC * 0.8
VCC = 3.0V, VI = 1 mA
VOL
Low Level Output Voltage
VCC * 0.2
V
IDOH(SO)
IDOL(SO)
IDOH(SI)
IDOL(SI)
∆IDO
IDO High, Source Current VCC = VP = 3.0V,
DOPLL1
DOPLL2
–3.8
–1.0
3.8
1.0
3
mA
mA
mA
mA
%
DO = VP/2
IDO Low, Source Current
IDO High, Sink Current
IDO Low, Sink Current
IDO Charge Pump Sink
and Source Mismatch
VCC = VP = 3.0V, DO = VP/2
[IDO(SO) – IDO(SI)]/IDO(SI)
T = 25°C
15
nA
IOFF
High-ImpedanceLeakage VCC = VP = 3.0V,
Current Loop locked, between reference
spikes
±2.5
Note:
1. IDOvs T; Charge pump current variation vs. temperature.
[IIDO(SI)@TI - IIDO(SI)@25° CI]/IIDO(SI)@25°CI * 100% and
[IIDO(SO)@TI - IIDO(SO)@25°CI]/IIDO(SO)@25°CI *100%.
Document #: 38-07238 Rev. **
Page 4 of 13
PRELIMINARY
CYW2332
Timing Waveforms
Key:
FC Bit HIGH
FC Bit LOW
Increasing
Voltage
(Refer to Table 2 for meaning of FC bit.)
Increasing Frequency
VCO Characteristics
Phase Comparator Sense
Phase Detector Output Waveform
F
F
R
P
tw
tw
LD
DO Charge Pump Output Current Waveform
F
F
R
P
tw
tw
D
o
ID
O
Hi-Impedance State
Document #: 38-07238 Rev. **
Page 5 of 13
PRELIMINARY
CYW2332
Timing Waveforms (continued)
Serial Data Input Timing Waveform[2, 3, 4, 5]
//
//
//
//
PD = MSB
PRE
B1
A7
CNT2
CNT1 = LSB
DATA
//
//
CLOCK
t5
t4
t3
t2
t1
//
//
//
//
LE
t6
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data into the locations given in Table 1.
Table 1. Control Configuration
CNT1
CNT2
Function
0
0
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.
0
1
1
1
0
1
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1
Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2
to power-down.
Program Counter for PLL1: A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set
PLL1 to power-down.
Notes:
2. t1–t6 = t > 50 ns.
3. CLOCK may remain HIGH after latching in data.
4. DATA is shifted in with the MSB first.
5. For DATA definitions, refer to Table 2.
Document #: 38-07238 Rev. **
Page 6 of 13
PRELIMINARY
CYW2332
Table 2. Shift Register Configuration[6]
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Reference Counter and Configuration Bits
CNT1 CNT2
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 FC IDO TS LD FO
Programmable Counter Bits
CNT1 CNT2
A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PRE PD
Bit(s) Name
CNT1, CNT2
R1–R15
FC
Function
Control Bits: Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
Reference Counter Setting Bits: 15 bits, R = 3 to 32767.[7]
Phase Sense of the Phase Detector: Set to match the VCO polarity, H = + (Positive VCO transfer function).
Charge Pump Setting Bit: IDO HIGH = 3.8 mA, IDO LOW = 1 mA at VP = 3V.
Hi-Impedance State Bit: Makes DO Hi-Impedance for PLL1 and PLL2 when HIGH.
IDO
TS
LD
Lock Detect: Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
FO
Frequency Out: This bit can be set to read out reference or programmable divider at the LD pin for test
purposes.
PRE
PD
Prescaler Divide Bit: For PLL1: LOW = 64/65 and HIGH = 128/129. For PLL2: LOW = 8/9 and HIGH = 16/17.
Power-down: LOW = power-up and HIGH = power-down. FIN is at a high-impedance state, respective B
counter is disabled, forces DO outputs to Hi-Impedance and phase comparators are disabled. The reference
counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be
input and latched in the power-down state.
A1–A7
Swallow Counter Divide Ratio: A = 0 to 127 for PLL1 and 0 to 15 for PLL2.
Programmable Counter Divide Ratio: B = 3 to 2047.[7]
B1–B11
Table 3. FO/LD Pin Truth Table
FO (Bit 22)
LD (Bit 21)
PLL1
PLL2
PLL1
PLL2
FO/LD Pin Output State
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1
X
X
X
X
0
1
1
0
1
0
1
0
0
1
1
1
0
1
Disable
PLL2 Lock Detect
PLL1 Lock Detect
PLL1/PLL2 Lock Detect
PLL2 Reference Divider Output
PLL1 Reference Divider Output
PLL2 Programmable Divider Output
PLL1 Programmable Divider Output
Test PLL2 Counter Reset
Test PLL1 Counter Reset
Test PLL1/PLL2 Counter Reset
Notes:
6. The MSB is loaded in first.
7. Low count ratios may violate frequency limits of the phase detector.
Document #: 38-07238 Rev. **
Page 7 of 13
PRELIMINARY
CYW2332
Table 4. 7-Bit Swallow Counter (A) Truth Table[8]
Divide Ratio A
A7
A6
A5
A4
A3
A2
A1
PLL1 (High Frequency)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:::
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
0
126
127
1
1
1
1
1
1
1
PLL2 (Low Frequency)
0
X
X
:::
X
X
X
X
:::
X
X
X
X
:::
X
X
0
0
0
0
0
0
0
1
1
:::
14
15
:::
1
:::
1
:::
1
:::
0
1
1
1
1
Table 5. 11-Bit Programmable Counter (B) Truth Table[9]
Divide Ratio B
B11
0
B10
0
B9
0
B8
0
B7
0
B6
0
B5
0
B4
0
B3
B2
1
B1
1
3
4
0
1
0
0
0
0
0
0
0
0
0
0
:::
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
0
2046
2047
1
1
1
1
1
1
1
1
1
1
1
Table 6. 15-Bit Programmable Reference Counter (for PLL1 and PLL2) Truth Table[9]
Divide Ratio R
R15 R14 R13 R12 R11 R10
R9
0
R8
0
R7
0
R6
0
R5
R4
0
R3
0
R2
1
R1
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
:::
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
1
:::
0
32766
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ordering Information[10]
Part
Revision
Ordering Code
Package Type
Tape and Reel Option
ZI
BCI
LFI
20-pin Thin Shrink Small Outline Package (0.173” wide)
24-pin Chip Scale Package (3.5 mm X 4.5 mm)
20-pin Micro Lead Frame (4 mm x 4 mm)
CYW2332
TR
Notes:
8. B is greater than or equal to A.
9. Divide ratio less than 3 is prohibited. The divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 127) and the 4-bit swallow counter (0 to 15).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler.
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
The divide ratio N = (P * B) + A.
10. Operating temperature range: –40°C to +85°C.
Document #: 38-07238 Rev. **
Page 8 of 13
PRELIMINARY
CYW2332
Typical Performance Characteristics
Charge Pump Current vs Do Voltage
Icp=Low
Charge Pump Current vs Do Voltage
Icp=High
1.5
1
6
4
Vp=5V
Vp=3V
Vp=5V
Vp=3V
Vp=3V
3
0.5
0
2
0
-0.5
-1
Vp = 5V
-2
-4
-6
Vp=3V
Vp = 5V
-1.5
2
3
4
5
0
1
4
5
Do Voltage (V)
1
2
Do Voltage (V)
0
Figure 3.
Do Output Current Low Mode
Figure 1.
Do Output Current High Mode
ATTEN
RL
10dB
-2.5dBm
VAVG
10dB/
100
MKR
-85.50dB
100.0kHz
85 dBc
1
START
RBW
835.8505MHz
3.0kHz
STOP
836.1505MHz
SWP 84.0ms
2
VBW
3.0kHz
4
3
Figure 3. PLL Reference Spurs
PLL Reference Spurious Level is –85.5 dBc
Marker Reference
Number
Input
Frequency
Real Imaginary
Marker 1
623
21
-823
-120
-55
100 MHz
Marker 2
Marker 3
Marker 4
1 GHz
1.8 GHz
2.2 GHz
14
13
-39
Figure 4.
Input Impedance FIN1, FIN2
VCC = 2.7 to 5.5V, FIN = 75 MHz to 2.6 GHz
Document #: 38-07238 Rev. **
Page 9 of 13
PRELIMINARY
CYW2332
Package Diagram
20-Pin Thin Shrink Small Outline Package (TSSOP, 0.173” wide)
Document #: 38-07238 Rev. **
Page 10 of 13
PRELIMINARY
CYW2332
Package Diagram
24-Pin Chip Scale Package (CSP 3.5 mm X 4.5 mm)
Document #: 38-07238 Rev. **
Page 11 of 13
PRELIMINARY
CYW2332
Package Diagram
20-Pin Micro Lead Frame Package (MLF 4 mm X 4 mm)
Document #: 38-07238 Rev. **
Page 12 of 13
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CYW2332
Document Title: CYW2332 Dual Serial Input PLL with 1.2 GHz and 600-MHz Prescalers
Document Number: 38-07238
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
110503
01/07/02
SZV
Change from Spec number: 38-00965 to 38-07238
Document #: 38-07238 Rev. **
Page 13 of 13
相关型号：
©2020 ICPDF网 联系我们和版权申明