CYW43340XKUBGT_技术文档

PRELIMINARY

CYW43340

Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n

MAC/Baseband/Radio with Integrated Bluetooth 4.0

General Description

The Cypress CYW43340 single–chip quad–radio device provides the highest level of integration for wearables, Internet of Things and

gateway applications, with integrated dual band (2.4 GHz / 5 GHz) IEEE 802.11 a/b/g and single–stream IEEE 802.11n MAC/

baseband/radio, and Bluetooth 4.0. The CYW43340 includes integrated power amplifiers and LNAs for the 2.4 GHz and 5 GHz WLAN

bands, and an integrated 2.4 GHz T/R switch. This greatly reduces the external part count, PCB footprint, and cost of the solution.

Using advanced design techniques and process technology to reduce active and idle power, the CYW43340 is designed to address

the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which

simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life.

The CYW43340 implements the highly sophisticated Enhanced Collaborative Coexistence algorithms and hardware mechanisms,

allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios (such as

cellular and LTE, GPS, WiMAX, and Ultra–Wideband) and a single shared 2.4 GHz antenna for Bluetooth and WLAN. As a result,

enhanced overall quality for simultaneous voice, video, and data transmission in an IoT or wearable application is achieved.

For the WLAN section, two host interface options are included: an SDIO v2.0 interface and a High-Speed Inter-Chip (HSIC) interface

(a USB 2.0 derivative for short-distance on-board connections). An independent, high-speed UART is provided for the Bluetooth host

interface.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM43340

CYW43340

BCM43340XKUBG

BCM43340HKUBG

CYW43340XKUBG

CYW43340HKUBG

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use.

For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary.

Feautures

IEEE 802.11x Key Features

■ Dual–band 2.4 GHz and 5 GHz IEEE 802.11

a/b/g/n

■ Supports IEEE 802.15.2 external coexistence interface to

optimize bandwidth utilization with other co–located wireless

technologies such as GPS, WiMAX, or UWB

■ Single–stream IEEE 802.11n support for 20 MHz and 40 MHz

channels provides PHY layer rates up to 150 Mbps for typical

upper–layer throughput in excess of 90 Mbps.

■ Supports standard SDIO v2.0 host interfaces.

■ Alternative host interface supports HSIC v1.0 (short–distance

■ Supports the IEEE 802.11n STBC (space–time block coding)

RX and LDPC (low–density parity check) TX options for

improved range and power efficiency.

USB device)

■ Integrated ARM® Cortex–M3™ processor and on–chip

memory for complete WLAN subsystem functionality,

minimizing the need to wake up the applications processor for

standard WLAN functions. This allows for further minimization

of power consumption, while maintaining the ability to field

upgrade with future features. On–chip memory includes 512

KB SRAM and 640 KB ROM.

■ Supportsasingle2.4 GHzantennasharedbetweenWLANand

Bluetooth.

■ Shared Bluetoothand 2.4 GHzWLAN receive signal path elimi-

nates the need for an external power splitter while maintaining

excellent sensitivity for both Bluetooth and WLAN.

■ OneDriver™ software architecture for easy migration from

existing embedded WLAN and Bluetooth devices as well as

future devices.

■ Internal fractional nPLL allows support for a wide range of

reference clock frequencies

Cypress Semiconductor Corporation

Document Number: 002-14943 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Tuesday, March 28, 2017

PRELIMINARY

CYW43340

Bluetooth Key Features

■ Complies with Bluetooth Core Specification Version 4.0 with

provisions for supporting future specifications.

■ Interface support: Host Controller Interface (HCI) using a high-

speed UART interface and PCM for audio data

■ Bluetooth Class 1 or Class 2 transmitter operation

■ Low power consumption improves battery life of handheld

devices.

■ Supports extended Synchronous Connections (eSCO), for

enhanced voice quality by allowing for retransmission of

dropped packets.

■ Supports multiple simultaneous Advanced Audio Distribution

Profiles (A2DP) for stereo sound.

■ Adaptive Frequency Hopping (AFH) for reducing radio

frequency interference

■ Automatic frequency detection for standard crystal and TCXO

values

General Features

■ Supports battery voltage range from 2.9V to 4.8V supplies with

■ Security:

internal switching regulator.

❐ WPA™ and WPA2™ (Personal) support for powerful encryp-

tion and authentication

■ Programmable dynamic power management

■ 3072-bit OTP for storing board parameters

❐ AES in WLAN hardware for faster data encryption and IEEE

802.11i compatibility

❐ Reference WLAN subsystem provides Cisco® Compatible

Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0)

■ Routable on low–cost 1x1 PCB stack–ups

❐ Reference WLAN subsystem provides Wi–Fi Protected Set-

up (WPS)

■ 141-ball WLBGA package(5.67 mm × 4.47 mm, 0.4 mm pitch)

■ Worldwide regulatory support: Global products supported with

worldwide homologated design

Figure 1. Functional Block Diagram

VIO

VBAT

5 GHz WLAN Tx

FEM or

WL_REG_ON

WLAN

Host I/F

WL_IRQ

SDIO*

T/R

5 GHz WLAN Rx

Switch

HSIC

2.4 GHz WLAN + Bluetooth Tx/Rx

CYW43340

CBF

CLK_REQ

BT_REG_ON

PCM/I²S

BT_DEV_WAKE

BT_HOST_WAKE

UART

Bluetooth

Host I/F

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/).

Document Number: 002-14943 Rev. *L

Page 2 of 96

PRELIMINARY

CYW43340

Contents

1. Introduction ...................................................................4

1.1 Overview ...............................................................4

1.2 Features ................................................................5

1.3 Standards Compliance ..........................................6

2. Power Supplies and Power Management ...................7

2.1 Power Supply Topology ........................................7

2.2 WLAN Power Management ...................................9

2.3 PMU Sequencing ..................................................9

2.4 Power-Off Shutdown ...........................................10

2.5 Power-Up/Power-Down/Reset Circuits ...............10

3. Frequency References ...............................................11

3.1 Crystal Interface and Clock Generation ..............11

3.2 TCXO ..................................................................11

3.3 Frequency Selection ............................................13

3.4 External 32.768 kHz Low-Power Oscillator .........14

4. Bluetooth Subsystem Overview ................................15

4.1 Features ..............................................................15

4.2 Bluetooth Radio ...................................................16

5. Bluetooth Baseband Core .........................................17

5.1 Bluetooth 4.0 Features ........................................17

5.2 Link Control Layer ...............................................17

5.3 Test Mode Support ..............................................17

5.4 Bluetooth Power Management Unit .....................18

5.5 Adaptive Frequency Hopping ..............................21

5.6 Advanced Bluetooth/WLAN Coexistence ............21

5.7 Fast Connection (Interlaced Page

and Inquiry Scans) ..............................................21

6. Microprocessor and Memory Unit for Bluetooth .....22

6.1 RAM, ROM, and Patch Memory ..........................22

6.2 Reset ...................................................................22

7. Bluetooth Peripheral Transport Unit ........................23

7.1 PCM Interface .....................................................23

7.2 UART Interface ....................................................30

7.3 I²S Interface ........................................................31

8. WLAN Global Functions ............................................34

8.1 WLAN CPU and Memory Subsystem ..................34

8.2 One-Time Programmable Memory ......................34

8.3 GPIO Interface ....................................................34

8.4 External Coexistence Interface ...........................34

8.5 UART Interface ....................................................35

8.6 JTAG Interface ....................................................35

9. WLAN Host Interfaces ................................................36

9.1 SDIO v2.0 ............................................................36

9.2 HSIC Interface .....................................................38

10. Wireless LAN MAC and PHY ...................................39

10.1 MAC Features ...................................................39

10.2 WLAN PHY Description .....................................42

11. WLAN Radio Subsystem ..........................................44

11.1 Receiver Path ....................................................44

11.2 Transmit Path ....................................................44

11.3 Calibration .........................................................44

12. Pinout and Signal Descriptions ..............................45

12.1 Signal Assignments ...........................................45

12.2 Signal Descriptions ............................................45

12.3 I/O States ..........................................................54

13. DC Characteristics ...................................................57

13.1 Absolute Maximum Ratings ...............................57

13.2 Environmental Ratings ......................................57

13.3 Electrostatic Discharge Specifications ..............58

13.4 Recommended Operating Conditions

and DC Characteristics .......................................58

14. Bluetooth RF Specifications ....................................60

15. WLAN RF Specifications ..........................................67

15.1 Introduction ........................................................67

15.2 2.4 GHz Band General RF Specifications .........68

15.3 WLAN 2.4 GHz Receiver

Performance Specifications ................................68

15.4 WLAN 2.4 GHz Transmitter

Performance Specifications ................................72

15.5 WLAN 5 GHz Receiver

Performance Specifications ................................73

15.6 WLAN 5 GHz Transmitter

Performance Specifications ................................75

15.7 General Spurious Emissions Specifications ......76

16. Internal Regulator Electrical Specifications ..........77

16.1 Core Buck Switching Regulator .........................77

16.2 3.3V LDO (LDO3P3) .........................................78

16.3 2.5V LDO (LDO2P5) .........................................79

16.4 HSICDVDD LDO ...............................................79

16.5 CLDO ................................................................80

16.6 LNLDO ..............................................................81

17. System Power Consumption ...................................82

17.1 WLAN Current Consumption .............................82

17.2 Bluetooth, and BLE Current Consumption ........83

18. Interface Timing and AC Characteristics ...............84

18.1 SDIO Timing ......................................................84

18.2 HSIC Interface Specifications ............................86

18.3 JTAG Timing .....................................................86

19. Power-Up Sequence and Timing .............................87

19.1 Sequencing of Reset and

Regulator Control Signals ...................................87

20. Package Information ................................................90

20.1 Package Thermal Characteristics .....................90

20.2 Junction Temperature Estimation

and PSI_JTVersus THETA_JC...............................90

20.3 Environmental Characteristics ...........................90

21. Mechanical Information ...........................................91

22. Ordering Information ................................................93

Document History ...........................................................94

Sales, Solutions, and Legal Information ......................96

Document Number: 002-14943 Rev. *L

Page 3 of 96

PRELIMINARY

CYW43340

1. Introduction

1.1 Overview

The Cypress CYW43340 single-chip device provides the highest level of integration for wearables, audio and IoT applications, with

integrated IEEE 802.1 a/b/g/n MAC/baseband/radio, and Bluetooth 4.0. It provides a small form-factor solution with minimal external

components to drive down cost, flexibility in size, form, and function. Comprehensive power management circuitry and software ensure

the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation.

Figure 2 shows the interconnect of all the major physical blocks in the CYW43340 and their associated external interfaces, which are

described in greater detail in the following sections.

Figure 2. Block Diagram

PMU

FLL

Controller

Analog PMU

Clk rst

JTAG

From

WLAN

BT

To

WLAN

BT

BT/FM

WLAN

CLB

PMU

XTAL/Radio/Pads etc

AXI2APB

From

WLAN

To

WLAN

UART

2

BT

I S

SoCSRAM

GCI

RAM

ROM

LTE

RAM512KB

ROM640KB

PCM

SDIOD

ARMCM3

ARM CM0

AHB

Bridge

USB20D

HSIC

WLAN

Master

Slave

WLAN

BT Access

AXI2AHB

AHB2AXI

Registers

DMA

RAM

ROM

To

GCI

Chip

RX/TX

BLE

JTAG

Master

To

CLB

Common

CLB

UPI

LCU

GPIO

DOT11MAC (D11)

1x1 11N PHY

Shared LNA

Control

APU

Timers

WD

To

CLB

BlueRF

SWP DIG

Pause

Modem

FM

Receiver

2.4 GHz / 5 GHz Dualband Radio

BT RF

Document Number: 002-14943 Rev. *L

Page 4 of 96

PRELIMINARY

CYW43340

1.2 Features

The CYW43340 supports the following WLAN and Bluetooth features:

■ IEEE 802.11a/b/g/n dual-band radio with internal Power Amplifiers, LNAs, and T/R switches

■ Bluetooth v4.0 with integrated Class 1 PA

■ Concurrent Bluetooth, and WLAN operation

■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality

■ Single- and dual-antenna support

❐ Single antenna with shared LNA

❐ Simultaneous BT/WLAN receive with single antenna

■ WLAN host interface options:

❐ SDIO v2.0, including default and high-speed timing.

❐ HSIC (USB device interface for short distance on-board applications)

■ BT host digital interface (can be used concurrently with above interfaces):

❐ UART (up to 4 Mbps)

■ ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives

■ I²S/PCM for BT audio

■ HCI high-speed UART (H4, H5) transport support

■ Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I²S

and PCM interface)

■ Bluetooth SmartAudio^®technology improves voice and music quality to headsets

■ Bluetooth low power inquiry and page scan

■ Bluetooth Low Energy (BLE) support

■ Bluetooth Packet Loss Concealment (PLC)

■ Bluetooth Wideband Speech (WBS)

■ Audio rate-matching algorithms

■ Multiple simultaneous A2DP audio stream

Document Number: 002-14943 Rev. *L

Page 5 of 96

PRELIMINARY

CYW43340

1.3 Standards Compliance

The CYW43340 supports the following standards:

■ Bluetooth 4.0 (including Bluetooth Low Energy)

■ IEEE 802.11n—Handheld Device Class (Section 11)

■ IEEE 802.11a

■ IEEE 802.11b

■ IEEE 802.11g

■ IEEE 802.11d

■ IEEE 802.11h

■ IEEE 802.11i

The CYW43340 will support the following future drafts/standards:

■ IEEE 802.11r—Fast Roaming (between APs)

■ IEEE 802.11k—Resource Management

■ IEEE 802.11w—Secure Management Frames

■ IEEE 802.11 Extensions:

❐ IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported)

❐ IEEE 802.11h 5 GHz Extensions

❐ IEEE 802.11i MAC Enhancements

❐ IEEE 802.11r Fast Roaming Support

❐ IEEE 802.11k Radio Resource Measurement

The CYW43340 supports the following security features and proprietary protocols:

■ Security:

❐ WEP

❐ WPA™ Personal

❐ WPA2™ Personal

❐ WMM

❐ WMM-PS (U-APSD)

❐ WMM-SA

❐ WAPI

❐ AES (Hardware Accelerator)

❐ TKIP (host-computed)

❐ CKIP (SW Support)

■ Proprietary Protocols:

❐ CCXv2

❐ CCXv3

❐ CCXv4

❐ CCXv5

■ IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements

Document Number: 002-14943 Rev. *L

Page 6 of 96

PRELIMINARY

CYW43340

2. Power Supplies and Power Management

2.1 Power Supply Topology

One Buck regulator, multiple LDO regulators, and a Power Management Unit (PMU) are integrated into the CYW43340. All regulators

are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN in embedded designs.

A single VBAT (2.9–4.8V) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in

the CYW43340.

Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of

reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only

when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic

demands of the digital baseband.

The CYW43340 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNDLO

regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO

supply) provide the CYW43340 with all the voltages it requires, further reducing leakage currents.

2.1.1 CYW43340 PMU Features

■ VBAT to 1.35Vout (372 mA maximum) Core-Buck (CBUCK) switching regulator

■ VBAT to 3.3Vout (450 mA maximum) LDO3P3 (external-capacitor)

■ VBAT to 2.5Vout (70 mA maximum) LDO2P5 (external-capacitor)

■ 1.35V to 1.2Vout (100 mA maximum) LNLDO (external-capacitor)

■ 1.35V to 1.2Vout (150 mA maximum) CLDO (external-capacitor)

■ 1.35V to 1.2Vout (80 mA maximum) HSICDVDD LDO (external-capacitor)

■ Additional internal LDOs (not externally accessible)

Figure 3 on page 8 shows the regulators and a typical power topology.

Document Number: 002-14943 Rev. *L

Page 7 of 96

PRELIMINARY

CYW43340

2.2 WLAN Power Management

The CYW43340 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the

chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current

and supply voltages. Additionally, the CYW43340 integrated RAM is a high Vt memory with dynamic clock control. The dominant

supply current consumed by the RAM is leakage current only. Additionally, the CYW43340 includes an advanced WLAN power

management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43340 into various

power management states appropriate to the current environment and activities that are being performed. The power management

unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a

table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are

fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn

on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode.

Slower clock speeds are used wherever possible.

The CYW43340 WLAN power states are described as follows:

■ Active mode— All WLAN blocks in the CYW43340 are powered up and fully functional with active carrier sensing and frame

transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock

speeds are dynamically adjusted by the PMU sequencer.

■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43340 remains

powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum.

The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to

wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.

■ Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic

states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered

off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the HSIC or SDIO bus, logic

states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW re-initialization.

■ Power-down mode—The CYW43340 is effectively powered off by shutting down all internal regulators. The chip is brought out of

this mode by external logic re-enabling the internal regulators.

2.3 PMU Sequencing

The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources

based on a computation of the required resources and a table that describes the relationship between resources and the time needed

to enable and disable them.

Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the Resource Min

register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of

resources required to produce the requested clocks.

Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the

resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value

of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz

PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is

0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go

immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or

the timer load-decrement sequence.

During each clock cycle, the PMU sequencer performs the following actions:

1. Computes the required resource set based on requests and the resource dependency table.

2. Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource

and inverts the ResourceState bit.

3. Compares the request with the current resource status and determines which resources must be enabled or disabled.

4. Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents.

5. Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

Document Number: 002-14943 Rev. *L

Page 9 of 96

PRELIMINARY

CYW43340

2.4 Power-Off Shutdown

The CYW43340 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices

in the system, remain operational. When the CYW43340 is not needed in the system, VDDIO_RF and VDDC are shut down while

VDDIO remains powered. This allows the CYW43340 to be effectively off while keeping the I/O pins powered so that they do not draw

extra current from any other devices connected to the I/O.

During a low-power shut-down state, provided VDDIO remains applied to the CYW43340, all outputs are tristated, and most inputs

signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths

or create loading on any digital signals in the system, and enables the CYW43340 to be fully integrated in an embedded device and

take full advantage of the lowest power-savings modes.

Two signals on the CYW43340, the frequency reference input (WRF_XTAL_CAB_OP) and the LPO_IN input, are designed to be high-

impedance inputs that do not load down the driving signal even if the chip does not have VDDIO power applied to it.

When the CYW43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any information

about its state from before it was powered down.

2.5 Power-Up/Power-Down/Reset Circuits

The CYW43340 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal

regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required

power-up sequences, see Section 19.: “Power-Up Sequence and Timing,” on page 87.

Table 2. Power-Up/Power-Down/Reset Control Signals

Signal

Description

WL_REG_ON

This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the

BT_REG_ON input to control the internal CYW43340 regulators. When this pin is high, the regulators are enabled

and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and

WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that

is enabled by default. It can be disabled through programming.

BT_REG_ON

This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal

CYW43340 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has

an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming.

Document Number: 002-14943 Rev. *L

Page 10 of 96

PRELIMINARY

CYW43340

3. Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency

reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. In addition, a low-power oscillator

(LPO) is provided for lower power mode timing.

Note: The crystal and TCXO implementations have different power supplies (WRF_XTAL_VDD1P2 for crystal,

WRF_TCXO_VDD for TCXO).

3.1 Crystal Interface and Clock Generation

The CYW43340 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator

including all external components is shown in Figure 4. Consult the reference schematics for the latest configuration.

Figure 4. Recommended Oscillator Configuration

C

WRF_XTAL_OP

12–27 pF

C

X ohms*

WRF_XTAL_ON

12–27 pF

* Resistor value

determined by crystal

drive level. See reference

schematics for details.

A fractional-N synthesizer in the CYW43340 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate

using a wide selection of frequency references.

For SDIO and HSIC applications the default frequency reference is a 37.4 MHz crystal or TCXO. The signal characteristics for the

crystal interface are listed in Table 3 on page 12.

Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the

default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further

details.

3.2 TCXO

As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase

Noise requirements listed in Table 3. When the clock is provided by an external TCXO, there are two possible connection methods,

as shown in Figure 5 and Figure 6:

1. If the TCXO is dedicated to driving the CYW43340, it should be connected to the WRF_XTAL_OP pin through an external 1000

pF coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW43340

goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. If the TCXO is to be

shared with another device, such as a GPS receiver, and impedance variation is not allowed, a dedicated external clock buffer will

be needed. Power must be supplied to the WRF_XTAL_VDD1P2 pin.

2. For 2.4 GHz operation only, an alternative is to DC-couple the TCXO to the WRF_TCXO_CK pin, as shown in Figure 6. Use this

method when the same TCXO is shared with other devices and a change in the input impedance is not acceptable because it may

cause a frequency shift that cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer

powered from WRF_TCXO_VDD. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always

on, thereby ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD

is approximately 500 µA.

Document Number: 002-14943 Rev. *L

Page 11 of 96

PRELIMINARY

CYW43340

Figure 5. Recommended Circuit to Use with an External Dedicated TCXO

1000 pF

TCXO

WRF_XTAL_OP

WRF_XTAL_ON

WRF_TCXO_CK

WRF_TCXO_VDD

NC

Figure 6. Recommended Circuit to Use with an External Shared TCXO

To other devices

TCXO

WRF_TCXO_CK

WRF_TCXO_VDD

WRF_XTAL_OP

To always present 1.8V supply

WRF_XTAL_ON

NC

Table 3. Crystal Oscillator and External Clock – Requirements and Performance

Crystal^a

External Frequency

Reference^b,c

Typ

Parameter

Conditions/Notes

Min

Typ

Max

Min

Max

Units

pF

Frequency

–

Between 19.2 MHz and 52 MHz^d,e

Crystal load capacitance

ESR

–

12

–

60

–

Ω

Drive level

External crystal requirement

Resistive

200^f

30k

–

µW

Ω

Input impedance

(WRF_XTAL_OP)

100k

–

30k

–

100k

Capacitive

–

7.5

–

7.5

–

pF

Ω

Input impedance

(WRF_TCXO_IN)

Resistive

–

30k

–

100k

Capacitive

–

4

pF

V

WRF_XTAL_OP

Input low level

DC-coupled digital signal

–

0

0.2

WRF_XTAL_OP

Input high level

DC-coupled digital signal

–

1.0

–

1.26

1200

1980

V

WRF_XTAL_OP

input voltage

AC-coupled analog signal

(see Figure 5)

400

mV_p-p

WRF_TCXO_IN

Input voltage

DC-coupled analog signal

(see Figure 6)

Document Number: 002-14943 Rev. *L

Page 12 of 96

PRELIMINARY

CYW43340

Table 3. Crystal Oscillator and External Clock – Requirements and Performance (Cont.)

Crystal^a

External Frequency

Reference^b,c

Typ

Parameter

Conditions/Notes

Min

–20

Typ

Max

20

Min

–20

Max

20

Units

ppm

Frequency tolerance over Without trimming

the lifetime of the

–

equipment, including

temperature

Duty cycle

37.4 MHz clock

–

40

–

50

–

60

%

Phase Noise

(802.11b/g)

37.4 MHz clock at 10 kHz offset

–131

–138

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

–

Phase Noise

(802.11a)

37.4 MHz clock at 10 kHz offset

–

–139

–146

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

Phase Noise

(802.11n, 2.4 GHz)

37.4 MHz clock at 10 kHz offset

–

–136

–143

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

Phase Noise

(802.11n, 5 GHz)

37.4 MHz clock at 10 kHz offset

–

–144

–151

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

a. (Crystal) Use WRF_XTAL_OP and WRF_XTAL_ON, internal power to pin WRF_XTAL_VDD1P2.

b. (TCXO) See “TCXO” on page 11 for alternative connection methods.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.

d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto-detected

frequency using the LPO clock.

e. The frequency step size is approximately 80 Hz resolution.

f. The crystal should be capable of handling a 200uW drive level from the CYW43340.

3.3 Frequency Selection

Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard

handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with

approximately 80 Hz resolution. The CYW43340 must have the reference frequency set correctly in order for any of the UART or PCM

interfaces to function correctly, since all bit timing is derived from the reference frequency.

Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default

require support to be added in the driver plus additional, extensive system testing. Contact Cypress for further details.

The reference frequency for the CYW43340 may be set in the following ways:

■ Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.

■ Auto-detect any of the standard handset reference frequencies using an external LPO clock.

For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard

frequencies commonly used, the CYW43340 automatically detects the reference frequency and programs itself to the correct

reference frequency. In order for auto frequency detection to work correctly, the CYW43340 must have a valid and stable 32.768 kHz

LPO clock that meets the requirements listed in Table 4 on page 14 and is present during power-on reset.

Document Number: 002-14943 Rev. *L

Page 13 of 96

PRELIMINARY

CYW43340

3.4 External 32.768 kHz Low-Power Oscillator

The CYW43340 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external

32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage,

and temperature, which is adequate for some applications. However, a trade-off caused by this wide LPO tolerance is a small current

consumption increase during WLAN power save mode that is incurred by the need to wake up earlier to avoid missing beacons.

Whenever possible, the preferred approach for WLAN is to use a precision external 32.768 kHz clock that meets the requirements

listed in Table 4.

Note: BT operations require the use of an external LPO that meets the requirements listed in Table 4.

Table 4. External 32.768 kHz Sleep Clock Specifications

Parameter

Nominal input frequency

LPO Clock

Units

kHz

32.768

±200

Frequency accuracy

Duty cycle

ppm

30–70

%

Input signal amplitude

200–1800

mV, p-p

–

Signal type

Square-wave or sine-wave

Input impedance^a

>100k

<5

Ω

pF

Clock jitter (during initial start-up)

<10,000

ppm

a.When power is applied or switched off.

Document Number: 002-14943 Rev. *L

Page 14 of 96

PRELIMINARY

CYW43340

4. Bluetooth Subsystem Overview

The Cypress CYW43340 is a Bluetooth 4.0-compliant, baseband processor/2.4 GHz transceiver.

The CYW43340 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard

Host Controller Interface (HCI) via a high speed UART and PCM for audio. The CYW43340 incorporates all Bluetooth 4.0 features

including BR/EDR and LE.

The CYW43340 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone

temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the

standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, and cellular radios.

The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.

4.1 Features

Major Bluetooth features of the CYW43340 include:

■ Supports key features of upcoming Bluetooth standards

■ Fully supports Bluetooth Core Specification version 4.0 features

■ UART baud rates up to 4 Mbps

■ Supports all Bluetooth 4.0 packet types

■ Supports maximum Bluetooth data rates over HCI UART

■ Multipoint operation with up to seven active slaves

❐ Maximum of seven simultaneous active ACL links

❐ Maximum of three simultaneous active SCO and eSCO connections with scatternet support

■ Trigger Broadcom fast connect (TBFC)

■ Narrowband and wideband packet loss concealment

■ Scatternet operation with up to four active piconets with background scan and support for scatter mode

■ High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see “Host

Controller Power Management” on page 18)

■ Channel quality driven data rate and packet type selection

■ Standard Bluetooth test modes

■ Extended radio and production test mode features

■ Full support for power savings modes

❐ Bluetooth clock request

❐ Bluetooth standard sniff

❐ Deep-sleep modes and software regulator shutdown

■ TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used

during power save mode for better timing accuracy.

Document Number: 002-14943 Rev. *L

Page 15 of 96

PRELIMINARY

CYW43340

4.2 Bluetooth Radio

The CYW43340 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has

been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz

unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the

requirements to provide the highest communication link quality of service.

4.2.1 Transmit

The CYW43340 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block

and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion,

output power amplifier, and RF filtering. The transmitter path also incorporates /4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to

support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be

adjusted to provide Bluetooth class 1 or class 2 operation.

4.2.2 Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4–DQPSK, and 8–DPSK signal. The fully

digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much

more stable than direct VCO modulation schemes.

4.2.3 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-

synchronization algorithm.

4.2.4 Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides

greater flexibility in front-end matching and filtering. Due to the linear nature of the PAcombined with some integrated filtering, external

filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-

cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels

for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)

block to keep the absolute output power variation within a tight range across process, voltage, and temperature.

4.2.5 Receiver

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation

enables the CYW43340 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the

Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the

receiver by the cellular transmit signal.

4.2.6 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

4.2.7 Receiver Signal Strength Indicator

The radio portion of the CYW43340 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the controller

can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

4.2.8 Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.

The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43340 uses an

internal RF and IF loop filter.

4.2.9 Calibration

The CYW43340 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interaction

is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the perfor-

mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters,

matching between key components, and key gain blocks. This takes into account process variation and temperature variation.

Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations

as the device cools and heats during normal operation in its environment.

Document Number: 002-14943 Rev. *L

Page 16 of 96

PRELIMINARY

CYW43340

5. Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation.

The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,

handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages

data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these

functions, it independently handles HCI event types, and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/

RX data before sending over the air:

■ Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),

data decryption, and data dewhitening in the receiver.

■ Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the

transmitter.

5.1 Bluetooth 4.0 Features

The BBC supports all Bluetooth 4.0 features, with the following benefits:

■ Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation.

■ Low Energy Physical Layer

■ Low Energy Link Layer

■ Enhancements to HCI for Low Energy

■ Low Energy Direct Test mode

■ AES encryption

Note: The CYW43340 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic

reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to

provide support for low data rate devices, such as sensors and remote controls.

5.2 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).

This layer consists of the command controller that takes commands from the software, and other controllers that are activated or

configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth Link

Controller.

■ Major states:

❐ Standby

❐ Connection

■ Substates:

❐ Page

❐ Page Scan

❐ Inquiry

❐ Inquiry Scan

❐ Sniff

❐ BLE Adv

❐ BLE Scan/Initiation

5.3 Test Mode Support

The CYW43340 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0.

This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

In addition to the standard Bluetooth Test Mode, the CYW43340 also supports enhanced testing features to simplify RF debugging

and qualification and type-approval testing. These features include:

■ Fixed frequency carrier wave (unmodulated) transmission

❐ Simplifies some type-approval measurements (Japan)

❐ Aids in transmitter performance analysis

Document Number: 002-14943 Rev. *L

Page 17 of 96

PRELIMINARY

CYW43340

■ Fixed frequency constant receiver mode

❐ Receiver output directed to I/O pin

❐ Allows for direct BER measurements using standard RF test equipment

❐ Facilitates spurious emissions testing for receive mode

■ Fixed frequency constant transmission

❐ Eight-bit fixed pattern or PRBS-9

❐ Enables modulated signal measurements with standard RF test equipment

5.4 Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through

power management registers or packet handling in the baseband core. The power management functions provided by the CYW43340

are:

■ RF Power Management

■ Host Controller Power Management

■ BBC Power Management

5.4.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver. The transceiver then processes the power-down functions accordingly.

5.4.2 Host Controller Power Management

When running in UART mode, the CYW43340 may be configured so that dedicated signals are used for power management hand-

shaking between the CYW43340 and the host. The basic power saving functions supported by those hand-shaking signals include

the standard Bluetooth defined power savings modes and standby modes of operation.

Table 5 describes the power-control hand-shake signals used with the UART interface.

Table 5. Power Control Pin Description

Signal

Type

Description

BT_DEV_WAKE

I

Bluetooth device wake-up: Signal from the host to the CYW43340 indicating that the host requires

attention.

■ Asserted: The Bluetooth device must wake-up or remain awake.

■ Deasserted: The Bluetooth device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

BT_HOST_WAKE

CLK_REQ

O

Host wake up. Signal from the CYW43340 to the host indicating that the CYW43340 requires attention.

■ Asserted: host device must wake-up or remain awake.

■ Deasserted: host device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

The CYW43340 asserts CLK_REQ when Bluetooth, or WLAN directs the host to turn on the reference

clock. The CLK_REQ polarity is active-high. Add an external 100 kΩ pull-down resistor to ensure the

signal is deasserted when the CYW43340 powers up or resets when VDDIO is present.

Note: Pad function Control Register is set to 0 for these pins.

Document Number: 002-14943 Rev. *L

Page 18 of 96

PRELIMINARY

CYW43340

Figure 7. Startup Signaling Sequence

LPO

Host I/Os

ƵŶconĮŐƵƌĞĚ

VDDIO

Host I/Os ĐŽŶĮŐƵƌĞĚ

BTH IOs

ƵncoŶĮŐƵƌĞĚ

BTH IOs ĐŽŶĮŐƵƌĞĚ

BT_REG_ON

BT_GPIO_1

(BT_HOST_WAKE)

T_ƐĞƩůĞ

T₁

/ŶĚiĐĂƚĞƐ that BTH

ĚĞǀicĞ is ƌĞĂĚǇ.

BT_UART_RTS_N

BT_UART_CTS_N

T₂

CLK_REQ

T_ƐĞƩůĞ

DƌiǀĞn

PƵůůĞĚ

EŽƚĞƐ͗ꢀꢀ

T₁is ƚŚĞ ƟŵĞ foƌ ƚŚĞ BTH ĚĞǀŝĐĞ to ƐĞƩůĞ its IOs aŌĞƌ a ƌĞƐĞƚ ĂŶĚꢀƌĞĨ ĐůŬ ƐĞƩůŝŶŐ ƟŵĞꢀĞůapsĞĚ.

T₂is ƚŚĞ ƟŵĞ foƌ ƚŚĞ BT ĚĞǀŝĐĞ to ĐŽŵƉůĞtĞ ŝŶŝƟĂůŝǌĂƟon ĂŶĚ ĚƌŝǀĞ BT_UART_RTS_N ůŽǁ͘

T_ƐĞƩůĞis thĞ ƟŵĞ foƌ ƚŚĞ ƌĞf cůŬ siŐŶaů ĨƌŽŵ thĞ host to bĞ ŐƵaƌaŶƚĞĞĚ to haǀĞ ƐĞƩůĞĚ.

5.4.3 BBC Power Management

The following are low-power operations for the BBC:

■ Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

■ Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the CYW43340 runs on the low-power

oscillator and wakes up after a predefined time period.

■ Alow-powershutdownfeatureallowsthedevicetobeturnedoffwhilethehostandanyotherdevicesinthesystemremainoperational.

When the CYW43340 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This

allows the CYW43340 to effectively be off while keeping the I/O pins powered so they do not draw extra current from any other

devices connected to the I/O.

During the low-power shut-down state, provided VDDIO remains applied to the CYW43340, all outputs are tristated, and most input

signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths

or create loading on any digital signals in the system and enables the CYW43340 to be fully integrated in an embedded device to take

full advantage of the lowest power-saving modes.

Two CYW43340 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not

have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the

CYW43340 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about

its state from the time before it was powered down.

Document Number: 002-14943 Rev. *L

Page 19 of 96

PRELIMINARY

CYW43340

5.4.4 Wideband Speech

The CYW43340 provides support for wideband speech (WBS) using on-chip Smart Audio technology. The CYW43340 can perform

subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 Kbps rate) transferred over the PCM

bus.

5.4.5 Packet Loss Concealment

Packet Loss Concealment (PLC) improves apparent audio quality for systems with marginal link performance. Bluetooth messages

are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several

ways:

■ Fill in zeros.

■ Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).

■ Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat).

These techniques cause distortion and popping in the audio stream. The CYW43340 uses a proprietary waveform extension algorithm

to provide dramatic improvement in the audio quality. Figure 8 and Figure 9 show audio waveforms with and without Packet Loss

Concealment. Cypress PLC/BEC algorithms also support wideband speech.

Figure 8. CVSD Decoder Output Waveform Without PLC

Figure 9. CVSD Decoder Output Waveform After Applying PLC

5.4.6 Audio Rate-Matching Algorithms

The CYW43340 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio stream jitter that may

be present when the rate of audio data coming from the host is not the same as the Bluetooth audio data rates.

5.4.7 Codec Encoding

The CYW43340 can support SBC and mSBC encoding and decoding for wideband speech.

5.4.8 Multiple Simultaneous A2DP Audio Stream

The CYW43340 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a

user to share his or her music (or any audio stream) with a friend.

5.4.9 Burst Buffer Operation

The CYW43340 has a data buffer that can buffer data being sent over the HCI and audio transports, then send the data at an increased

rate. This mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current

consumption.

Document Number: 002-14943 Rev. *L

Page 20 of 96

PRELIMINARY

CYW43340

5.5 Adaptive Frequency Hopping

The CYW43340 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map

selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop

map.

5.6 Advanced Bluetooth/WLAN Coexistence

The CYW43340 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution.

These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including appli-

cations such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo.

Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also

supported. The CYW43340 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna

applications. This is possible only via an integrated solution (shared LNAand joint AGC algorithm). It has superior performance versus

implementations that need to arbitrate between Bluetooth and WLAN reception.

The CYW43340 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexis-

tence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement.

The CYW43340 also supports Transmit Power Control on the STA together with standard Bluetooth TPC to limit mutual interference

and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames.

Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimi-

nation of interferers (including non-WLAN 2.4 GHz interference).

The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information.

5.7 Fast Connection (Interlaced Page and Inquiry Scans)

The CYW43340 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection

times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures.

Document Number: 002-14943 Rev. *L

Page 21 of 96

PRELIMINARY

CYW43340

6. Microprocessor and Memory Unit for Bluetooth

The Bluetooth microprocessor core is based on the ARM^®Cortex™-M3 32-bit RISC processor with embedded ICE-RT debug and

JTAG interface units. It runs software from the link control (LC) layer, up to the host controller interface (HCI).

The ARM core is paired with a memory unit that contains 652 KB of ROM memory for program storage and boot ROM, 195 KB of

RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility during power-on reset to enable the same device

to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features additions. These patches

may be downloaded from the host to the CYW43340 through the UART transports. The mechanism for downloading via UART is

identical to the proven interface of the CYW4329 and CYW4330 devices.

6.1 RAM, ROM, and Patch Memory

The CYW43340 Bluetooth core has 195 KB of internal RAM which is mapped between general purpose scratch pad memory and

patch memory and 652 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory

capability enables the addition of code changes for purposes of feature additions and bug fixes to the ROM memory.

6.2 Reset

The CYW43340 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset

(POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the POR circuit is held in reset.

Document Number: 002-14943 Rev. *L

Page 22 of 96

PRELIMINARY

CYW43340

7. Bluetooth Peripheral Transport Unit

7.1 PCM Interface

The CYW43340 supports two independent PCM interfaces that share the pins with the I²S interfaces. The PCM Interface on the

CYW43340 can connect to linear PCM Codec devices in master or slave mode. In master mode, the CYW43340 generates the

PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are

inputs to the CYW43340. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI

commands.

7.1.1 Slot Mapping

The CYW43340 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three

channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample

interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or

1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM

data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow

other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM

clock during the last bit of the slot.

7.1.2 Frame Synchronization

The CYW43340 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization

mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is

synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the

first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization

signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident

with the first bit of the first slot.

7.1.3 Data Formatting

The CYW43340 may be configured to generate and accept several different data formats. For conventional narrowband speech mode,

the CYW43340 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various

data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a

programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

7.1.4 Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM

bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-

bit samples, resulting in a 64 kbps bit rate. The CYW43340 also supports slave transparent mode using a proprietary rate-matching

scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus.

7.1.5 Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and

save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with

an HCI command from the host.

Document Number: 002-14943 Rev. *L

Page 23 of 96

PRELIMINARY

CYW43340

7.1.6 PCM Interface Timing

Short Frame Sync, Master Mode

Figure 10. PCM Timing Diagram (Short Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

7

5

6

PCM_IN

Table 6. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

–

12

–

41

0

ns

–

25

–

0

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14943 Rev. *L

Page 24 of 96

PRELIMINARY

CYW43340

Short Frame Sync, Slave Mode

Figure 11. PCM Timing Diagram (Short Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

9

PCM_OUT

HIGH IMPEDANCE

8

6

7

PCM_IN

Table 7. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

–

12

–

41

8

ns

–

8

–

0

25

–

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14943 Rev. *L

Page 25 of 96

PRELIMINARY

CYW43340

Long Frame Sync, Master Mode

Figure 12. PCM Timing Diagram (Long Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

7

Bit 0

Bit 1

5

6

PCM_IN

Table 8. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

–

12

–

41

0

ns

–

25

–

0

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14943 Rev. *L

Page 26 of 96

PRELIMINARY

CYW43340

Long Frame Sync, Slave Mode

Figure 13. PCM Timing Diagram (Long Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

9

PCM_OUT

PCM_IN

Bit 0

HIGH IMPEDANCE

8

Bit 1

6

7

Bit 1

Table 9. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

–

12

–

41

8

ns

–

8

–

0

25

–

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14943 Rev. *L

Page 27 of 96

PRELIMINARY

CYW43340

Short Frame Sync, Burst Mode

Figure 14. PCM Burst Mode Timing (Receive Only, Short Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

PCM_IN

Table 10. PCM Burst Mode (Receive Only, Short Frame Sync)

Ref No. Characteristics

Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

–

24

–

20.8

8

–

ns

–

8

–

8

–

PCM_IN hold

8

–

Document Number: 002-14943 Rev. *L

Page 28 of 96

PRELIMINARY

CYW43340

Long Frame Sync, Burst Mode

Figure 15. PCM Burst Mode Timing (Receive Only, Long Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

Bit 0

Bit 1

PCM_IN

Table 11. PCM Burst Mode (Receive Only, Long Frame Sync)

Ref No. Characteristics

Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

PCM bit clock frequency

PCM bit clock low

PCM bit clock high

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

–

24

–

20.8

8

–

ns

–

8

–

8

–

PCM_IN hold

8

–

Document Number: 002-14943 Rev. *L

Page 29 of 96

PRELIMINARY

CYW43340

7.2 UART Interface

The CYW43340 uses a UART for Bluetooth. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud

rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection.

Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.

The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through

the AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.0 UART HCI specification: H4 and H5. The

default baud rate is 115.2 Kbaud.

The UART supports the 3-wire H5 UART transport, as described in the Bluetooth specification (“Three-wire UART Transport Layer”).

Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals.

The CYW43340 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP).

It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection,

and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included

through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43340 UARTs

operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2% (see Table 12).

Table 12. Example of Common Baud Rates

Desired Rate

Actual Rate

Error (%)

4000000

3692000

3000000

2000000

1500000

1444444

921600

460800

230400

115200

57600

4000000

3692308

3000000

2000000

1500000

1454544

923077

461538

230796

115385

57692

0.00

0.01

0.00

0.70

0.16

0.17

0.16

0.00

0.16

0.00

0.16

0.00

38400

28800

28846

19200

14400

14423

9600

Document Number: 002-14943 Rev. *L

Page 30 of 96

PRELIMINARY

CYW43340

UART timing is defined in Figure 16 and Table 13.

Figure 16. UART Timing

UART_CTS_N

UART_TXD

1

2

Midpoint of STOP bit

UART_RXD

3

UART_RTS_N

Table 13. UART Timing Specifications

Ref No. Characteristics

Minimum

Typical

Maximum

1.5

Unit

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

–

Bit periods

0.5

2

7.3 I S Interface

The CYW43340 supports an independent I²S digital audio port for high-fidelity Bluetooth audio. The I²S interface supports both master

and slave modes. The I²S signals are:

■ I²S clock: I²S SCK

■ I²S Word Select: I²S WS

■ I²S Data Out: I²S SDO

■ I²S Data In: I²S SDI

I²S SCK and I²S WS become outputs in master mode and inputs in slave mode, while I²S SDO always stays as an output. The channel

word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I²S bus, per the

I²S specification. The MSB of each data word is transmitted one bit clock cycle after the I²S WS transition, synchronous with the falling

edge of bit clock. Left-channel data is transmitted when I²S WS is low, and right-channel data is transmitted when I²S WS is high.

Data bits sent by the CYW43340 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the

rising edge of I2S_SSCK.

The clock rate in master mode is either of the following:

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using a N/M clock divider.

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.

7.3.1 I²S Timing

Note: Timing values specified in Table 14 are relative to high and low threshold levels.

Document Number: 002-14943 Rev. *L

Page 31 of 96

PRELIMINARY

CYW43340

Table 14. Timing for I²S Transmitters and Receivers

Transmitter

Lower LImit Upper Limit

Receiver

Lower Limit Upper Limit

Min Max

Notes

Min

Max

Min

Max

Min

Max

Clock Period T

T

–

T

–

1

tr

r

Master Mode: Clock generated by transmitter or receiver

High t_HC

Low t_LC

0.35T

–

0.35T

–

2

tr

Slave Mode: Clock accepted by transmitter or receiver

High t_HC

–

0.35T

–

0.35T

–

3

4

tr

Low t_LC

tr

Rise time t_RC

0.15T

tr

Transmitter

Delay t_dtr

–

0

–

0.8T

–

5

4

Hold time t_htr

–

Receiver

Setup time t_sr

Hold time t_hr

–

0.2T

0

–

6

r

Note:

■ The system clock period T must be greater than T_trand T_rbecause both the transmitter and receiver have to be able to handle the

data transfer rate.

■ At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason,

t_HCand t_LCare specified with respect to T.

■ In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal.

So long as the minimum periods are greater than 0.35T_r, any clock that meets the requirements can be used.

■ Because the delay (t_dtr) and the maximum transmitter speed (defined by T_tr) are related, a fast transmitter driven by a slow clock

edge can result in t_dtrnot exceeding t_RCwhich means t_htrbecomes zero or negative. Therefore, the transmitter has to guarantee

that t_htris greater than or equal to zero, so long as the clock rise-time t_RCis not more than t_RCmax, where t_RCmaxis not less than 0.15T_tr.

■ To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T,

always giving the receiver sufficient setup time.

■ The data setup and hold time must not be less than the specified receiver setup and hold time.

■ The time periods specified in Figure 17 and Figure 18 on page 33 are defined by the transmitter speed. The receiver specifications

must match transmitter performance.

Document Number: 002-14943 Rev. *L

Page 32 of 96

PRELIMINARY

CYW43340

Figure 17. I²S Transmitter Timing

T

t_RC*

t_LC> 0.35T

t_HC> 0.35T

V_H= 2.0V

V_L= 0.8V

SCK

t_htr> 0

t_otr< 0.8T

SD and WS

T = Clock period

T_tr= Minimum allowed clock period for transmitter

T = T_tr

* t_RCis only relevant for transmitters in slave mode.

Figure 18. I²S Receiver Timing

T

t_LC> 0.35T

t_HC> 0.35

V_H= 2.0V

V_L= 0.8V

SCK

t_sr> 0.2T

t_hr> 0

SD and WS

T = Clock period

T_r= Minimum allowed clock period for transmitter

T > T_r

Document Number: 002-14943 Rev. *L

Page 33 of 96

PRELIMINARY

CYW43340

8. WLAN Global Functions

8.1 WLAN CPU and Memory Subsystem

The CYW43340 includes an integrated ARM Cortex-M3™ processor with internal RAM and ROM. The ARM Cortex-M3 processor is

a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded

applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for

Thumb®-2 instruction set. ARM Cortex-M3 delivers 30% more performance gain over ARM7TDMI®.

At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit

devices on MIPS/µW. It supports integrated sleep modes.

ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced

silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-

M3 supports extensive debug features including real time trace of program execution.

On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.

8.2 One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal 3072-bit One-Time Programmable (OTP) memory, which is

read by the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the

MAC address can be stored, depending on the specific board design.

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.

The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test

tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state

can be altered during each programming cycle.

Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the

reference board design package.

8.3 GPIO Interface

On the WLBGA package, there are 8 GPIO pins available on the WLAN section of the CYW43340 that can be used to connect to

various external devices.

Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via

the GPIO control register.

8.4 External Coexistence Interface

An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such

as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance. The coexistence signals in Figure 19

and Table 15 can be enabled by software on the indicated GPIO pins.

Figure 19. LTE Coexistence Interface

GPIO5

WLAN_PRIORITY

GPIO3

WLAN

ERCX

LTE_TX

LTE_RX

GPIO2

BT

CYW4334X

LTE Chip

Document Number: 002-14943 Rev. *L

Page 34 of 96

PRELIMINARY

CYW43340

Table 15. External Coexistence Interface

Coexistence Signal

ERCX_TX_CONF/WLAN_PRIORITY

ERCX_FREQ/LTE_TX

GPIO Name

Type

Output

Comment

Notify LTE of request to sleep

GPIO_5

GPIO_3

GPIO_2

Input

Notify WLAN RX of requirement to sleep

Notify WLAN TX to reduce TX power

ERCX_RF_ACTIVE/LTE_RX

8.5 UART Interface

One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_5. Provided primarily

for debugging during development, this UART enables the CYW43340 to operate as RS-232 data termination equipment (DTE) for

exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO

size of 64 × 8 in each direction.

8.6 JTAG Interface

The CYW43340 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing

during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-

ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test

points or a header on all PCB designs.

Document Number: 002-14943 Rev. *L

Page 35 of 96

PRELIMINARY

CYW43340

9. WLAN Host Interfaces

9.1 SDIO v2.0

The CYW43340 WLAN section supports SDIO version 2.0, including the following modes:

DS:

HS:

Default speed up to 25 MHz, including 1- and 4-bit modes (3.3V signaling)

High speed up to 50 MHz (3.3V signaling)

It also has the ability to map the interrupt signal onto a GPIO pin for applications requiring an interrupt different than what is provided

by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled

using the strapping option pins strap_host_ifc_[3:1].

Three functions are supported:

■ Function 0 standard SDIO function (Max BlockSize/ByteCount = 32B)

■ Function 1 backplane function to access the internal system-on-chip (SoC) address space (Max BlockSize/ByteCount = 64B)

■ Function 2 WLAN function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B)

9.1.1 SDIO Pin Descriptions

Table 16. SDIO Pin Description

SD 4-Bit Mode

Data line 0

SD 1-Bit Mode

DATA0

DATA1

DATA2

DATA3

CLK

DATA

IRQ

Data line

Interrupt

Data line 1 or Interrupt

Data line 2 or Read Wait

Data line 3

RW

Read Wait

Not used

Clock

N/C

Clock

CLK

CMD

Command line

Figure 20. Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK

CMD

SD Host

CYW43340

DAT[3:0]

Document Number: 002-14943 Rev. *L

Page 36 of 96

PRELIMINARY

CYW43340

Figure 21. Signal Connections to SDIO Host (SD 1-Bit Mode)

CLK

CMD

DATA

SD Host

CYW43340

IRQ

RW

Figure 22. SDIO Pull-Up Requirements

VDDIO_SD

47k

(see note)

CLK

CMD

SD Host

CYW43340

DATA[3:0]

Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD line. This

requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO

Host pull-ups. The CYW43340 does not have internal pull-ups on these lines.

Document Number: 002-14943 Rev. *L

Page 37 of 96

PRELIMINARY

CYW43340

9.2 HSIC Interface

As an alternative to SDIO, an HSIC host interface can be enabled using the strapping option pins strap_host_ifc_[3:1]. HSIC is a

simplified derivative of the USB2.0 interface designed to replace a standard USB PHY and cable for short distances (up to 10 cm) on

board point-to-point connections. Using two signals, a bidirectional data strobe (STROBE) and a bidirectional DDR data signal (DATA),

it provides high-speed serial 480 Mbps data transfers that are 100% host driver compatible with traditional USB 2.0 cable-connected

topologies.

Figure 23 shows the blocks in the HSIC device core.

Key features of HSIC include:

■ High-speed 480 Mbps data rate

■ Source-synchronous serial interface using 1.2V LVCMOS signal levels

■ No power consumed except when a data transfer is in progress

■ Maximum trace length of 10 cm.

■ No Plug-n-Play support, no hot attach/removal

Figure 23. HSIC Device Block Diagram

32-Bit On-Chip Communication System

DMA Engines

s

F I F O T X

F O F I T X

F O F s I T X

F I F O T X

s

RX FIFO

TX FIFOs

Endpoint Management Unit

USB 2.0 Protocol Engine

HSIC PHY

Strobe

Data

Document Number: 002-14943 Rev. *L

Page 38 of 96

PRELIMINARY

CYW43340

10. Wireless LAN MAC and PHY

10.1 MAC Features

The CYW43340 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended

by IEEE 802.11n. The salient features are listed below:

■ Transmission and reception of aggregated MPDUs (A-MPDU)

■ Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP

operation

■ Support for immediate ACK and Block-ACK policies

■ Interframe space timing support, including RIFS

■ Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges

■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification

■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)

generation in hardware

■ Hardware offload for AES-CCMP, legacy WEP ciphers, WAPI, and support for key management

■ Support for coexistence with Bluetooth and other external radios

■ Programmable independent basic service set (IBSS) or infrastructure basic service set functionality

■ Statistics counters for MIB support

10.1.1 MAC Description

The CYW43340 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without

compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several

power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing

synchronization. The architecture diagram of the MAC is shown in Figure 24 on page 40.

The following sections provide an overview of the important modules in the MAC.

Document Number: 002-14943 Rev. *L

Page 39 of 96

PRELIMINARY

CYW43340

Figure 24. WLAN MAC Architecture

Embedded CPU Interface

Host Registers, DMA Engines

TX-FIFO

32 KB

RX-FIFO

10 KB

PSM

PMQ

PSM

UCODE

Memory

IFS

Backoff, BTCX

WEP

TKIP, AES, WAPI

TSF

SHM

BUS

IHR

NAV

BUS

Shared Memory

6 KB

RXE

RX A-MPDU

TXE

TX A-MPDU

EXT- IHR

MAC-PHY Interface

PSM

The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to

implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predom-

inant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which

allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving

IEEE 802.11 specifications.

The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data

store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratchpad

memory (similar to a register bank) to store frequently accessed and temporary variables.

The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs

are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus.

The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,

or a program stack. For ALU operations the operands are obtained from shared memory, scratchpad, IHRs, or instruction literals, and

the results are written into the shared memory, scratchpad, or IHRs.

There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points

in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition

signals are available to the PSM without polling the IHRs), or on the results of ALU operations.

WEP

The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and

MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-

CCMP.

The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies

the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on

transmit frames, and the RXE to decrypt and verify the MIC on receive frames.

Document Number: 002-14943 Rev. *L

Page 40 of 96

PRELIMINARY

CYW43340

TXE

The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames

in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the

appropriate time determined by the channel access mechanisms.

The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic

streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule

a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a

precise timing trigger received from the IFS module.

The TXE module also contains the hardware that allows the rapid assembly of MPDUs into anA-MPDU for transmission. The hardware

module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.

RXE

The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames

from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The

decrypted data is stored in the RXFIFO.

The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria

such as receiver address, BSSID, and certain frame types.

The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate

them into component MPDUS.

IFS

The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple

backoff engines required to support prioritized access to the medium as specified by WMM.

The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers

provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform

transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).

The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or

pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission.

In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies

provided by the PSM.

The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power

save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by

the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer

expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF

is synchronized to the network.

The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.

TSF

The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon trans-

mission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon

and probe response frames in order to maintain synchronization with the network.

The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink

transmission times used in PSMP.

NAV

The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration

field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.

The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.

This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.

MAC-PHY Interface

The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an

programming interface, which can be controlled either by the host or the PSM to configure and control the PHY.

Document Number: 002-14943 Rev. *L

Page 41 of 96

PRELIMINARY

CYW43340

10.2 WLAN PHY Description

The CYW43340 WLAN Digital PHY is designed to comply with IEEE 802.11a/b/g/n single-stream to provide wireless LAN connectivity

supporting data rates from 1 Mbps to 150 Mbps for low-power, high-performance handheld applications.

The PHY has been designed to work with interference, radio nonlinearity, and impairments. It incorporates efficient implementations

of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and

reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and

tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high

throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed for shared single antenna

systems between WL and BT to support simultaneous RX-RX.

10.2.1 PHY Features

■ Supports IEEE 802.11a, 11b, 11g, and 11n single-stream PHY standards.

■ IEEE 802.11n single-stream operation in 20 MHz and 40 MHz channels

■ Supports Optional Short GI and Green Field modes in TX and RX.

■ Supports optional space-time block code (STBC) receive of two space-time streams.

■ TX LDPC for improved range and power efficiency

■ Supports IEEE 802.11h/k for worldwide operation.

■ Advanced algorithms for low power, enhanced sensitivity, range, and reliability

■ Algorithms to improve performance in presence of Bluetooth

■ Simultaneous RX-RX (WL-BT) architecture

■ Automatic gain control scheme for blocking and non blocking application scenario for cellular applications

■ Closed loop transmit power control

■ Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities

■ On-the-fly channel frequency and transmit power selection

■ Supports per packet RX antenna diversity.

■ Designed to meet FCC and other worldwide regulatory requirements.

Document Number: 002-14943 Rev. *L

Page 42 of 96

PRELIMINARY

CYW43340

Figure 25. WLAN PHY Block Diagram

CCK/DSSS Demodulate

Filters and Radio

Comp

Frequency and

Timing Synch

Descramble and

Deframe

OFDM Demodulate

Viterbi Decoder

Carrier Sense, AGC, and

Rx FSM

Buffers

MAC

Radio Control Block

FFT/IFFT

Interface

AFE and

Radio

Tx FSM

Modulation and

Coding

Common Logic Block

Frame and

Scramble

Filters and Radio Comp

PA Comp

Modulate/Spread

COEX

One of the key features of the PHY is its space-time block coding (STBC) capability. The STBC scheme can obtain diversity gains in

a fading channel environment. On a connection with an access point that uses multiple transmit antennas and supports STBC, the

CYW43340 can process two space-time streams to improve receiver performance. Figure 26 is a block diagram showing the STBC

implementation in the receive path.

Figure 26. STBC Implementation in the Receive Path

Descramble and

Deframe

Equalizer

Demod Combine

Demapper

Viterbi

FFT of 2 Symbols

h_old

Transmitter

h_new

Weighted

Averaging

Channel h

h_upd

Symbol

Memory

Estimate

Channel

In STBC mode, symbols are processed in pairs. Equalized output symbols are linearly combined and decoded. The channel estimate is

refined on every pair of symbols using the received symbols and reconstructed symbols.

Document Number: 002-14943 Rev. *L

Page 43 of 96

PRELIMINARY

CYW43340

11. WLAN Radio Subsystem

The CYW43340 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz

Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating

in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering,

mixing, and gain control functions.

11.1 Receiver Path

The CYW43340 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel filtering to ensure reliable

operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. Control signals are available that can support the use of

optional external low noise amplifiers (LNA), which can increase the receive sensitivity by several dB.

11.2 Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. The CYW43340 includes an

on-chip regulator which regulates VBAT down to 3.3V for the CYW43340 on-chip linear Power Amplifiers. Closed-loop output power

control is provided by means of internal a-band and g-band power detectors.

11.3 Calibration

The CYW43340 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations

across components. This enables the CYW43340 to be used in high-volume applications, because calibration routines are not

required during manufacturing testing. These calibration routines are performed periodically in the course of normal radio operation.

Examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance

and LOFT calibration for carrier leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-

chip. No per-board calibration is required in manufacturing test, which helps to minimize test time and cost during large volume

production.

Document Number: 002-14943 Rev. *L

Page 44 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions

WLBGA Ball

Signal Name

Type

Description

WLAN RF Signal Interface

A5

C1

A4

A2

D2

WRF_RFIN_2G

I

2.4G RF input

5G RF input

2.4G RF output

5G RF output

–

WRF_RFIN_5G

I

WRF_RFOUT_2G

WRF_RFOUT_5G

WRF_GPIO_OUT

O

I/O

RF Control Signals

L6

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

O

RF switch enable

H6

G6

G8

H8

O

SDIO Bus Interface

M6

M5

L5

SDIO_CLK

I

SDIO clock input

SDIO_CMD

I/O

SDIO command line

SDIO data line 0

SDIO_DATA_0

SDIO_DATA_1

L4

SDIO data line 1. Also used as a strapping

option (see Table 18 on page 53).

K5

K4

SDIO_DATA_2

SDIO_DATA_3

I/O

SDIO data line 2. Also used as a strapping

option (see Table 18 on page 53).

SDIO data line 3

Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD

line. This requirement must be met during all operating states by using external pull-up resistors or properly

programming internal SDIO Host pull-ups.

JTAG Interface

M4

JTAG_SEL

I/O

JTAG select: Connect this pin high (VDDIO) in

order to use GPIO_2 through GPIO_5 and

GPIO_12 as JTAG signals. Otherwise, if this pin

is left as a NO_CONNECT, its internal pull-down

selects the default mode that allows GPIOs 2,

3, 4, 5, and 12 to be used as GPIOs.

Note: See “WLAN GPIO Interface” on

page 47 for the JTAG signal pins.

HSIC Interface

L2

K2

K3

HSIC_STROBE

HSIC_DATA

RREFHSIC

I

HSIC Strobe

HSIC Data

I/O

I

HSIC reference resistor input. If HSIC is used,

connect this pin to ground via a 51Ω 5% resistor.

Document Number: 002-14943 Rev. *L

Page 46 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

Signal Name

WLAN GPIO Interface

I/O

Type

Description

G3

F3

WL_GPIO_0

WL_GPIO_1

This pin can be programmed by software to be

a GPIO.

I/O

This pin can be programmed by software to be

a GPIO or an AP_READY or

HSIC_HOST_READY input from the host

indicating that it is awake.

G4

WL_GPIO_2

I/O

This pin can be programmed by software to be

a GPIO, the JTAG TCK or an HSIC_READY

output to the host, indicating that the device is

ready to respond with a CONNECTwhen it sees

IDLE on the HSIC bus.

H4

J7

WL_GPIO_3

WL_GPIO_4

I/O

This pin can be programmed by software to be

a GPIO or the JTAG TMS signal.

This pin can be programmed by software to be

a GPIO, the JTAG TDI signal, the UART RX

signal, or as the

WLAN_HOST_WAKE output indicating

that host wake-up should be performed.

H5

G5

WL_GPIO_5

WL_GPIO_6

I/O

This pin can be programmed by software to be

a GPIO, the JTAG TDO signal or the UART TX

signal.

GPIO pin.

Note: Some GPIOs are also used as

strapping options (see Table 18 on page

53).

J5

WL_GPIO_12

I/O

This pin can be programmed by software to be

a GPIO or the JTAG TRST_L signal. GPIO12

has an internal pull-down by default if

JTAG_SEL is low. When JTAG_SEL is high,

GPIO12 is used as JTAG_TRST_Land is pulled

up.

This pin is also used as WLAN_DEV_WAKE, an

out-of- band wake-up signal when the host

wants to wake WLAN from the deep sleep

mode.

Note: Some GPIOs are also used as

strapping options (see Table 18 on page

53).

Document Number: 002-14943 Rev. *L

Page 47 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

Signal Name

Type

Description

Clocks

H1

G1

J3

WRF_XTAL_CAB_XON

O

XTAL oscillator output

XTAL oscillator input

WRF_XTAL_CAB_XOP

WRF_TCXO_CKIN2V

I

TCXO buffered input. When not using a TCXO

this pin should be connected to ground.

E11

CLK_REQ

O

External system clock request—Used when the

system clock is not provided by a dedicated

crystal (for example, when a shared TCXO is

used). Asserted to indicate to the host that the

clock is required. Shared by BT, and WLAN.

Can also be programmed as the BT_I2S_DI

input pin if CLK_REQ functionality is not

required.

F11

LPO_IN

I

External sleep clock input (32.768 kHz)

Bluetooth/FM Receiver

A7

BT_RF

I/O

Bluetooth transceiver RF antenna port

FM analog output 1

D11

C11

A10

FM_AOUT1

FM_AOUT2

FM_RFIN

O

FM analog output 2

I

Bluetooth PCM

I/O

FM radio antenna port

F8

BT_PCM_CLK

PCM clock; can be master (output) or slave

(input)

F9

E8

F7

BT_PCM_IN

I

PCM data input sensing

PCM data output

BT_PCM_OUT

BT_PCM_SYNC

O

I/O

PCM sync; can be master (output) or slave

(input)

Document Number: 002-14943 Rev. *L

Page 48 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

Signal Name

Type

Description

Bluetooth UART and Wake

G11

H11

H10

G10

E10

F10

BT_UART_CTS_N

BT_UART_RTS_N

BT_UART_RXD

BT_UART_TXD

BT_DEV_WAKE

BT_HOST_WAKE

I

UART clear-to-send. Active-low clear-to-send

signal for the HCI UART interface.

O

UART request-to-send. Active-low request-to-

send signal for the HCI UART interface.

I

UART serial input. Serial data input for the HCI

UART interface.

O

UART serial output. Serial data output for the

HCI UART interface.

I/O

DEV_WAKE or general-purpose

I/O signal

HOST_WAKE or general-purpose I/O signal

Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART

functionality. Through software configuration, the PCM interface can also be routed over the

BT_WAKE/UART signals as follows:

■ PCM_CLK on the UART_RTS_N pin

■ PCM_OUT on the UART_CTS_N pin

■ PCM_SYNC on the BT_HOST_WAKE pin

■ PCM_IN on the BT_DEV_WAKE pin

In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire

UART Transport.

Bluetooth/FM I²S

D7

E7

D8

BT_I2S_CLK

BT_I2S_DO

BT_I2S_WS

I/O

I²S clock; can be master (output) or slave (input)

I²S data output

I²S WS; can be master (output) or slave (input)

Miscellaneous

J1

WL_REG_ON

I

Used by PMU to power up or power down the

internal CYW43340 regulators used by the

WLAN section. Also, when deasserted, this pin

holds the WLAN section in reset. This pin has

an internal 200 k pull-down resistor that is

enabled by default. It can be disabled through

programming.

J2

BT_REG_ON

I

Used by PMU to power up or power down the

internal CYW43340 regulators used by the

Bluetooth/FM section. Also, when deasserted,

this pin holds the Bluetooth/FM section in reset.

This pin has an internal 200 k pull-down

resistor that is enabled by default. It can be

disabled through programming.

Document Number: 002-14943 Rev. *L

Page 49 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

Signal Name

Type

Description

Integrated Voltage Regulators

N2

P2

N1

SR_VDDBATA5V

SR_VDDBATP5V

SR_VLX

I

Quiet VBAT

Power VBAT

I

O

CBUCK switching regulator output. See Table

35 on page 77 for details of the inductor and

capacitor required on this output.

P3

LDO_VDD1P5

I

Input for the LNLDO, CLDO, and HSIC LDOs. It

is also the voltage feedback pin for the CBUCK

regulator.

P4

N3

VOUT_LNLDO

VOUT_CLDO

O

Output of low-noise LNLDO

Output of core LDO

O

Bluetooth Power Supplies

A6

A8

C8

B8

A9

BT_PAVDD

BT_LNAVDD

BT_IFVDD

I

Bluetooth PA power supply

Bluetooth LNA power supply

Bluetooth IF block power supply

Bluetooth RF PLL power supply

Bluetooth RF power supply

I

BT_PLLVDD

BT_VCOVDD

I

FM Receiver Power Supplies

D10

A11

FM_PLLVDD

I

FM PLL power supply

FM_LNAVCOVDD

I

FM VCO and receiver power supply pin

WLAN Power Supplies

F4

WRF_BUCK_VDD1P5

I

Internal LDO supply from CBUCK for VCO,

AFE, TX, and RX

B3

B5

D4

A1

A3

F2

H3

WRF_CBUCK_PAVDD1P5

WRF_PA2G_VBAT_VDD3P3

WRF_PADRV_VBAT_VDD3P3

WRF_PAPMU_VBAT_VDD5P0

WRF_PAPMU_VOUT_LDO3P3

WRF_SYNTH_VDD1P2

I

NO_CONNECT

I

2G PA 3.3V Supply

I

3.3V supply for A/G band PAD

PAPMU VBAT power supply

PAPMU 3.3V LDO output voltage

Synth VDD 1.2V input

I

O

I

WRF_TCXO_VDD1P8

I

Supply to the WRF_TCXO_CKIN input buffer.

When not using a TCXO, this pin should be

connected to ground.

F1

WRF_XTAL_CAB_VDD1P2

I

XTAL oscillator supply

Document Number: 002-14943 Rev. *L

Page 50 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

Signal Name

Type

Description

Miscellaneous Power Supplies

L3

HSIC_DVDD1P2_OUT

O

1.2V supply for HSIC interface. This pin can be

NO_CONNECT when HSIC is not used.

E9

H7

K1

P5

H9

J4

VDDC_E9

VDDC_H7

VDDC_K1

VDDC_P5

VDDIO_H9

VDDIO_J4

I

Core supply for WLAN and BT.

I/O supply (1.8–3.3V). For the WLBGA

package, this is the supply for both SDIO and

other I/O pads.

J6

VDDIO_RF

VOUT_2P5

I

I/O supply for RF switch control pads (3.3V)

2.5V LDO output

N4

O

Ground

B7

B6

C7

B9

B11

B10

C9

L1

BT_PAVSS

I

Bluetooth PA ground

1.2V Bluetooth IF block ground

Bluetooth RF PLL ground

1.2V Bluetooth RF ground

FM VCO ground

BT_IFVSS

BT_PLLVSS

BT_VCOVSS

FM_VCOVSS

FM_LNAVSS

FM receiver ground

FM PLL ground

FM_PLLVSS

HSIC_AGND12PLL

PMU_AVSS

HSIC PLL ground

M1

P1

D6

G7

M2

N6

G2

F5

Quiet ground

SR_PVSS

Power ground

VSSC_D6

Core ground for WLAN and BT

VSSC_G7

VSSC_M2

VSSC_N6

WRF_SYNTH_GND1P2

WRF_AFE_GND1P2

WRF_LNA_2G_GND1P2

WRF_LNA_5G_GND1P2

WRF_PA2G_VBAT_GND3P3

Synth ground

AFE ground

D5

D1

C4

C2

C3

B1

D3

E5

E4

E1

H2

J8

2 GHz internal LNA ground

5 GHz internal LNA ground

2.4 GHz PA ground

5 GHz PA ground

WRF_PA5G_VBAT_GND3P3_C2

WRF_PA5G_VBAT_GND3P3_C3

WRF_PAPMU_GND

WRF_PADRV_VBAT_GND3P3

WRF_RX_GND1P2

I

PMU ground

PA driver ground

RX ground

WRF_TX_GND1P2

TX ground

WRF_VCO_GND1P2

WRF_XTAL_CAB_GND1P2

VSS_J8

VCO/LOGEN ground

XTAL ground

Ground

J10

VSS_J10

Ground

Document Number: 002-14943 Rev. *L

Page 51 of 96

PRELIMINARY

CYW43340

Table 17. WLBGA Signal Descriptions (Cont.)

WLBGA Ball

K8

Signal Name

Type

Description

VSS_K8

VSS_K10

VSS_K11

VSS_L8

VSS_L9

VSS_L10

VSS_L11

VSS_M8

VSS_M9

VSS_M10

VSS_M11

VSS_N7

VSS_N8

VSS_N9

VSS_N10

VSS_N11

VSS_P6

VSS_P7

VSS_P8

VSS_P9

VSS_P10

VSS_P11

I

Ground

K10

K11

L8

L9

L10

L11

M8

M9

M10

M11

N7

N8

N9

N10

N11

P6

P7

P8

P9

P10

P11

No Connect

G9

J9

NC_G9

NC_J9

NC_J11

NC_K7

NC_K9

NC_L7

NC_M7

–

No Connect

J11

K7

K9

L7

M7

Document Number: 002-14943 Rev. *L

Page 52 of 96

PRELIMINARY

CYW43340

12.2.1 WLAN GPIO Signals and Strapping Options

The pins listed in Table 18 on page 53 are sampled at power-on reset (POR) to determine the various operating modes. Sampling

occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or

alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD)

resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND,

using a 10 kΩ resistor or less.

Note: Refer to the reference board schematics for more information.

Table 18. WLAN GPIO Functions and Strapping Options (Advance Information)

WLBGA

Pin Name

Default

Function

Description

Pin #

SDIO_DATA_1

F9

0

strap_host_ifc_1

The three strap pins strap_host_ifc_[3:1] select the

host interface^ato enable:

■ 0XX: SDIO

■ 10X: xx

■ 110: normal HSIC

■ 111: bootloader-less HSIC

■ 1: select SDIO mode

■ 0: select SDIO mode

■ 1: select HSIC mode

SDIO_DATA_2

G8

J6

0

strap_host_ifc_2

strap_host_ifc_3

GPIO_6/

MODE_SEL

JTAG_SEL

M4

N/A

JTAG select

■ JTAGselect:Connectthispinhigh(VDDIO)inorder

to use GPIO_2 through GPIO_5 and GPIO_12 as

JTAG signals. Otherwise, if this pin is left as a

NO_CONNECT, its internal Pull-down selects the

default mode that allows GPIOs 2, 3, 4, 5, and 12

to be used as GPIOs.

Note: See “WLAN GPIO Interface” on page 47

for the JTAG signal pins.

a.The unused host interface is tristated. However, the SDIO lines have internal pulls activated when in HSIC mode (see Table 20: “I/O States,” on page 54).

There are no bus-keepers on the HSIC interface when it is not in use.

Document Number: 002-14943 Rev. *L

Page 53 of 96

PRELIMINARY

CYW43340

13. DC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device

characterization.

13.1 Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 21 indicate levels where permanent damage to the device can occur,

even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions.

Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 21. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

DC supply for VBAT and PA

driver supply:

VBAT

–0.5 to +6.0

V

DC supply voltage for digital I/O VDDIO

–0.5 to 3.9

V

DC supply voltage for RF switch VDDIO_RF

I/Os

DC input supply voltage for

CLDO and LNLDO1

–

–0.5 to 1.575

V

DC supply voltage for RF analog VDDRF

–0.5 to 1.32

–0.5 to 3.63

–0.5

V

DC supply voltage for core

WRF_TCXO_VDD

VDDC

–

Maximum undershoot voltage V_undershoot

for I/O

Maximum overshoot voltage for V_overshoot

I/O

0.5

V

Maximum Junction

Temperature

T_j

125

°C

13.2 Environmental Ratings

The environmental ratings are shown in Table 22.

Table 22. Environmental Ratings

Characteristic

Value

–30 to +85

–40 to +125

Units

Conditions/Comments

Functional operation^a

Ambient Temperature (T_A)

Storage Temperature

Relative Humidity

°C

%

–

Less than 60

Less than 85

Storage

Operation

a.Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details.

Document Number: 002-14943 Rev. *L

Page 57 of 96

PRELIMINARY

CYW43340

13.3 Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps

to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.

Table 23. ESD Specifications

Pin Type

ESD

Rating

Symbol

Condition

Unit

ESD, Handling Reference: ESD_HAND_HBM

NQY00083, Section 3.4,

Human body model contact discharge per

JEDEC EID/JESD22-A114

2000

V

Group D9, Table B

Machine Model (MM)

CDM

ESD_HAND_MM

ESD_HAND_CDM

Machine model contact

100

V

Charged device model contact discharge per JEDEC EIA/ 500

JESD22-C101

13.4 Recommended Operating Conditions and DC Characteristics

Caution! Functional operation is not guaranteed outside of the limits shown in Table 24 and operation outside these

limits for extended periods can adversely affect long-term reliability of the device.

Table 24. Recommended Operating Conditions and DC Characteristics

Value

Parameter

Symbol

Unit

Minimum

2.9^a

Typical

Maximum

4.8^b

DC supply voltage for VBAT

VBAT

VDD

–

V

DC supply voltage for core

1.14

1.2

1.8

–

1.26

1.98

3.63

3.46

0.7

DC supply voltage for RF blocks in chip

DC supply voltage for TCXO input buffer

DC supply voltage for digital I/O

DC supply voltage for RF switch I/Os

Internal POR threshold

VDDRF

WRF_TCXO_VDD 1.62

VDDIO, VDDIO_SD 1.71

VDDIO_RF

Vth_POR

3.13

0.4

3.3

–

SDIO Interface I/O Pins

For VDDIO_SD = 1.8V:

Input high voltage

VIH

VIL

1.27

–

V

Input low voltage

0.58

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO_SD = 3.3V:

Input high voltage

VOH

VOL

1.40

–

0.45

VIH

0.625 × VDDIO

–

V

Input low voltage

VIL

–

0.25 × VDDIO

Output high voltage @ 2 mA

Output low voltage @ 2 mA

VOH

VOL

0.75 × VDDIO

–

-

0.125 × VDDIO

Document Number: 002-14943 Rev. *L

Page 58 of 96

PRELIMINARY

CYW43340

Table 24. Recommended Operating Conditions and DC Characteristics (Cont.)

Value

Parameter

Symbol

Unit

Minimum

Typical

Maximum

Other Digital I/O Pins

For VDDIO = 1.8V:

Input high voltage

VIH

0.65 × VDDIO

–

V

Input low voltage

VIL

-

0.35 × VDDIO

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO = 3.3V:

VOH

VOL

VDDIO – 0.45

–

0.45

Input high voltage

VIH

2.00

–

V

Input low voltage

VIL

–

0.80

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

VOH

VDDIO – 0.4

VOL

–

0.40

RF Switch Control Output Pins^c

For VDDIO_RF = 3.3V:

Output high voltage

Output low voltage

Input capacitance

VOH

VOL

C_IN

VDDIO – 0.4

–

V

–

0.40

5

V

pF

a. The CYW43340 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.0V < VBAT

< 4.8V.

b. The maximum continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Volt-

ages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

Document Number: 002-14943 Rev. *L

Page 59 of 96

PRELIMINARY

CYW43340

14. Bluetooth RF Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device

characterization.

Unless otherwise stated, limit values apply for the conditions specified in Table 22: “Environmental Ratings,” on page 57 and

Table 24: “Recommended Operating Conditions and DC Characteristics,” on page 58. Typical values apply for the following condi-

tions:

■ VBAT = 3.6V

■ Ambient temperature +25°C

Figure 28. RF Port Location for Bluetooth Testing

CYW43340

2.4 GHz WLAN

+

Filter

BT Tx/Rx

Chip

Port

Antenna

Port

Note: All Bluetooth specifications are measured at the Chip port unless otherwise specified.

Document Number: 002-14943 Rev. *L

Page 60 of 96

PRELIMINARY

CYW43340

Table 25. Bluetooth Receiver RF Specifications

Parameter Conditions

Minimum

Typical

Maximum

Unit

Note: The specifications in this table are measured at the Chip port output unless otherwise specified.

General

Frequency range

RX sensitivity

–

2402

–

2480

MHz

dBm

GFSK, 0.1% BER, 1 Mbps

–

–92.5

–94.5

–

/4–DQPSK, 0.01% BER,

2 Mbps

8–DPSK, 0.01% BER, 3 Mbps

–

–88.5

–

dBm

Input IP3

–

–16

–

Maximum input at antenna

–

–20

Interference Performance^a

GFSK, 0.1% BER

C/I co-channel

–

11

dB

C/I 1-MHz adjacent channel

C/I 2-MHz adjacent channel

C/I  3-MHz adjacent channel

C/I image channel

GFSK, 0.1% BER

0.0

–30

–40

–9

C/I 1-MHz adjacent to image channel GFSK, 0.1% BER

–20

13

C/I co-channel

/4–DQPSK, 0.1% BER

C/I 1-MHz adjacent channel

C/I 2-MHz adjacent channel

C/I  3-MHz adjacent channel

C/I image channel

/4–DQPSK, 0.1% BER

0.0

–30

–40

–7

C/I 1-MHz adjacent to image channel /4–DQPSK, 0.1% BER

–20

21

C/I co-channel

8–DPSK, 0.1% BER

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I  3-MHz adjacent channel

C/I Image channel

5.0

–25

–33

0.0

–13

C/I 1-MHz adjacent to image channel 8–DPSK, 0.1% BER

Out-of-Band Blocking Performance (CW)

30–2000 MHz

0.1% BER

–

–10.0

–27

–

dBm

2000–2399 MHz

2498–3000 MHz

3000 MHz–12.75 GHz

0.1% BER

–27

–10.0

Out-of-Band Blocking Performance, Modulated Interferer (LTE)

GFSK (1 Mbps)

2310Mhz

2330MHz

2350MHz

2370MHz

LTE band40 TDD 20M BW

–

–20

–21

–22

–23

–

dBm

Document Number: 002-14943 Rev. *L

Page 61 of 96

PRELIMINARY

CYW43340

Table 25. Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum

Typical

–26

Maximum

Unit

2510MHz

2530MHz

2550MHz

2570MHz

LTE band7 FDD 20M BW

–

dBm

–25

–24

/4 DPSK (2 Mbps)

2310Mhz

2330MHz

2350MHz

2370MHz

2510MHz

2530MHz

2550MHz

2570MHz

LTE band40 TDD 20M BW

–

–20

–22

–23

–26

–25

–24

–

dBm

LTE band40 TDD 20M BW

LTE band7 FDD 20M BW

8DPSK (3 Mbps)

2310Mhz

2330MHz

2350MHz

2370MHz

2510MHz

2530MHz

2550MHz

2570MHz

LTE band40 TDD 20M BW

–

–21

–23

–24

–26

–25

–24

–

dBm

LTE band40 TDD 20M BW

LTE band7 FDD 20M BW

Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE)

a

GFSK (1 Mbps)

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–13

–19

–20

–21

–23

–

dBm

776–849 MHz

824–849 MHz

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD–SCDMA

WCDMA

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

Document Number: 002-14943 Rev. *L

Page 62 of 96

PRELIMINARY

CYW43340

Table 25. Bluetooth Receiver RF Specifications (Cont.)

Parameter Conditions

Minimum

Typical

Maximum

Unit

a

/4 DPSK (2 Mbps)

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–11

–

dBm

776–794 MHz

–11

–12

–17

–19

–18

–19

–21

–23

824–849 MHz

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

a

8DPSK (3 Mbps)

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–13

–12

–13

–18

–20

–19

–20

–21

–24

–

dBm

776–794 MHz

–

824–849 MHz

–

824–849 MHz

–

880–915 MHz

–

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

–

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

–

RX LO Leakage

–

2.4 GHz band

–

–90.0

–80.0

dBm

Spurious Emissions

30 MHz–1 GHz

1–12.75 GHz

–

–95

–62

–47

–

dBm

–70

869–894 MHz

925–960 MHz

1805–1880 MHz

1930–1990 MHz

–147

dBm/Hz

–

Document Number: 002-14943 Rev. *L

Page 63 of 96

PRELIMINARY

CYW43340

Table 25. Bluetooth Receiver RF Specifications (Cont.)

Parameter Conditions

2110–2170 MHz

Minimum

Typical

–147

Maximum

Unit

–

dBm/Hz

a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level.

Document Number: 002-14943 Rev. *L

Page 64 of 96

PRELIMINARY

CYW43340

Table 26. Bluetooth Transmitter RF Specifications^a

Parameter Conditions

General

Minimum

Typical

Maximum

Unit

Frequency range

2402

–

2480

MHz

Basic rate (GFSK) TX power at Bluetooth

QPSK TX Power at Bluetooth

8PSK TX Power at Bluetooth

Power control step

–

2

11.0

8.0

4

–

8

dBm

dB

GFSK In-Band Spurious Emissions

–20 dBc BW

–

.93

1

MHz

EDR In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

|M – N|  2.5 MHz^b

M – N = the frequency range for which –

–38

–31

–43

–26.0

–20.0

–40.0

dBc

the spurious emission is measured

relative to the transmit center

–

dBm

–

frequency.

Out-of-Band Spurious Emissions

30 MHz to 1 GHz

–

–36.0 ^c,d

–30.0 ^d,e,f

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–

–47.0

GPS Band Spurious Emissions

Spurious emissions

–

–103

–

dBm

Out-of-Band Noise Floor^g

65–108 MHz

FM RX

–

–147

–146

–145

–144

–141

–

dBm/Hz

776–794 MHz

869–960 MHz

925–960 MHz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

CDMA2000

–

cdmaOne, GSM850

E-GSM

GPS

GSM1800

GSM1900, cdmaOne, WCDMA

WCDMA

a. Unless otherwise specified, the specifications in this table are measured at the chip output port, and output power specifications are with the temperature

correction algorithm and TSSI enabled.

b. Typically measured at an offset of ±3 MHz.

c. The maximum value represents the value required for Bluetooth qualification as defined in the v4.0 specification.

d. The spurious emissions during Idle mode are the same as specified in Table 26 on page 65.

e. Specified at the Bluetooth Antenna port.

f. Meets this specification using a front-end band-pass filter.

g. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 28 on page 60 for location of the port.

Document Number: 002-14943 Rev. *L

Page 65 of 96

PRELIMINARY

CYW43340

Table 27. Local Oscillator Performance

Parameter

Minimum

Typical

Maximum

Unit

LO Performance

Lock time

–

72

–

s

Initial carrier frequency tolerance

–

±25

±75

kHz

Frequency Drift

DH1 packet

DH3 packet

DH5 packet

Drift rate

–

±8

5

±25

±40

20

kHz

kHz/50 µs

Frequency Deviation

00001111 sequence in payload^a

10101010 sequence in payload^b

Channel spacing

140

115

–

155

140

1

175

–

kHz

MHz

–

a. This pattern represents an average deviation in payload.

b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

Table 28. BLE RF Specifications

Parameter

Frequency range

RX sense^a

Conditions

Minimum

2402

Typical

Maximum

Unit

MHz

dBm

kHz

–

2480

GFSK, 0.1% BER, 1 Mbps

–

–94.5

8.5

–

TX power^b

–

Mod Char: delta f1 average

Mod Char: delta f2 max^c

Mod Char: ratio

225

99.9

0.8

255

–

275

–

%

0.95

–

%

a.The Bluetooth tester is set so that Dirty TX is on.

b.BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, and so forth). The output is capped at 12 dBm out. The

BLE TX power at the antenna port cannot exceed the 10 dBm specification limit.

c.At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

Document Number: 002-14943 Rev. *L

Page 66 of 96

PRELIMINARY

CYW43340

15. WLAN RF Specifications

15.1 Introduction

The CYW43340 includes an integrated dual-band direct conversion radio that supports either the 2.4 GHz band or the 5 GHz band.

The CYW43340 does not provide simultaneous 2.4 GHz and 5 GHz operation. This section describes the RF characteristics of the

2.4 GHz and 5 GHz portions of the radio.

Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Unless otherwise stated, limit values apply for the conditions specified inTable 22: “Environmental Ratings,” on page 57 and

Table 24: “Recommended Operating Conditions and DC Characteristics,” on page 58. Typical values apply for the following condi-

tions:

■ VBAT = 3.6V

■ Ambient temperature +25°C

Figure 29. WLAN Port Locations (5 GHz)

CYW43340

FEM or

T/R

5 GHz WLAN

Switch

Chip

Port

Antenna

Port

Figure 30. WLAN Port Locations (2.4 GHz)

CYW43340

2.4 GHz WLAN

+

Filter

BT Tx/Rx

Chip

Port

Antenna

Port

Note: All WLAN specifications are measured at the chip port, unless otherwise specified.

Document Number: 002-14943 Rev. *L

Page 67 of 96

PRELIMINARY

CYW43340

15.2 2.4 GHz Band General RF Specifications

Table 29. 2.4 GHz Band General RF Specifications

Item

Condition

Minimum

Typical

Maximum

Unit

TX/RX switch time

Including TX ramp down

Including TX ramp up

DSSS/CCK modulations

–

5

µs

RX/TX switch time

2

Power-up and power-down ramp time

< 2

15.3 WLAN 2.4 GHz Receiver Performance Specifications

Note: The specifications in Table 30 are measured at the chip port, unless otherwise specified.

Table 30. WLAN 2.4 GHz Receiver Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum

2400

Typical

Maximum

Unit

–

2500

–

MHz

dBm

RX sensitivity

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps CCK

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–

–99

–95

–93

–89

–92

–89

–87

–84

–82

–78

–77

(8% PER for 1024 octet PSDU)^a

–

RX sensitivity

–

(10% PER for 1024 octet

–

PSDU)^a

–

RX sensitivity

20 MHz channel spacing for all MCS rates

MCS0

(GF)

–

(10% PER for 4096 octet

–92

–88

–86

–84

–81

–76

–75

–73

–

dBm

PSDU)^a,b.Defined for default

parameters: GF, 800 ns GI, and 13 Mbps MCS 1

–

non-STBC.

6.5 Mbps MCS 2

–

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

–

Document Number: 002-14943 Rev. *L

Page 68 of 96

PRELIMINARY

CYW43340

Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

RX sensitivity

Condition/Notes

40 MHz channel spacing for all MCS rates

MCS 0

Minimum

(GF)

Typical

Maximum

Unit

(10% PER for 4096 octet

–

–89

–

dBm

PSDU)^a,b.Defined for default

parameters: GF, 800 ns GI, and MCS 1

non-STBC.

–85

–83

–81

–78

–74

–71

–69

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

RX sensitivity

20 MHz channel spacing for all MCS rates (Mixed mode)

(10% PER for 4096 octet

MCS0

–

–91.0

–87.9

–85.5

–82.8

–79.9

–76.2

–74.6

–72.6

–

dBm

PSDU)^a,c.Defined for default

parameters: Mixed mode, 800 MCS 1

ns GI, and

non-STBC.

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

RX sensitivity

40 MHz channel spacing for all MCS rates (Mixed mode)

(10% PER for 4096 octet

MCS 0

–

–89.0

–85.4

–83.2

–80.6

–77.4

–72.3

–70.6

–69.0

–

dBm

PSDU)^a,b.Defined for default

parameters: Mixed mode, 800 MCS 1

ns GI, and

non-STBC.

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

Document Number: 002-14943 Rev. *L

Page 69 of 96

PRELIMINARY

CYW43340

Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

CDMA2000

Minimum

–12.3

Typical

Maximum

Unit

dBm

Blocking level for 3dB RX sensi- 776–794 MHz

–

tivity degradation (without

824–849 MHz^e

cdmaOne

–9.4

external filtering)^d

824–849 MHz

GSM850

–2.7

880–915 MHz

E-GSM

–3.4

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

2496–2690 MHz

2300–2400 MHz

2300–2370 MHz

2570–2620 MHz

2545–2575 MHz

GSM1800

–9

GSM1800

–8.8

cdmaOne

–22.4

–18.6

–22.5

–37.2

–80

WCDMA

LTE + 3 dB desense

In-band static CW jammer

immunity

RX PER < 1%, 54 Mbps OFDM,

1000 octet PSDU for:

(fc – 8 MHz < fcw < + 8 MHz)

(RxSens + 23 dB < Rxlevel < max input level)

Input In-Band IP3^a

Maximum LNA gain

–

–15.5

–

dBm

MHz

Minimum LNA gain

–

–1.5

Maximum Receive Level

@ 2.4 GHz

@ 1, 2 Mbps (8% PER, 1024 octets)

@ 5.5, 11 Mbps (8% PER, 1024 octets)

@ 6–54 Mbps (10% PER, 1024 octets)

@ MCS0–7 rates (10% PER, 4095 octets)

–

–3.5

–9.5

–19.5

9

–

LPF 3 dB Bandwidth

10

Adjacent channel rejection-

DSSS

(Difference between interfering

Desired and interfering signal 30 MHz apart

1 Mbps DSSS

–74 dBm

35

–

dB

and desired signal at 8% PER 2 Mbps DSSS

for 1024 octet PSDU with

desired signal level as specified

Desired and interfering signal 25 MHz apart

in Condition/Notes)

5.5 Mbps DSSS

11 Mbps DSSS

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

–70 dBm

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

35

16

15

13

11

8

–

dB

Adjacent channel rejection-

OFDM

(Difference between interfering

and desired signal (25 MHz

apart) at 10% PER for 1024

octet PSDU with desired signal

level as specified in Condition/ 24 Mbps OFDM

Notes)

36 Mbps OFDM

4

48 Mbps OFDM

54 Mbps OFDM

0

–1

Document Number: 002-14943 Rev. *L

Page 70 of 96

PRELIMINARY

CYW43340

Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

–61 dBm

–62 dBm

–63 dBm

–67 dBm

–71 dBm

–74 dBm

–76 dBm

–79 dBm

–

Minimum

–2

Typical

Maximum

Unit

dB

Adjacent channel rejection

MCS0–7 (Difference between

interfering and desired signal

(25 MHz apart) at 10% PER for MCS5

4096 octet PSDU with desired

MCS7

MCS6

–

5

8

–

–1

0

dB

MCS4

4

signal level as specified in

Condition/Notes)

MCS3

MCS2

MCS1

MCS0

–

8

11

13

16

–

Maximum receiver gain

Gain control step

RSSI accuracy^f

105

3

–

Range –98 dBm to –30 dBm

Range above –30 dBm

–5

–8

6

–

Return loss

Z_o= 50Ω, across the dynamic range

At maximum gain

10

3.5

Receiver cascaded NF

–

a.Derate by 1.5 dB for –30 °C to –10°C and 55°C to 85°C.

b.Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, SGI: 2 dB drop, and STBC: 0.75 dB drop.

c.Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, SGI: 2 dB drop, and STBC: 0.75 dB

drop.

d.The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test.

It is not intended to indicate any specific usage of each band in any specific country.

e.The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 × 824 MHz) falling

within band.)

f.The minimum and maximum values shown have a 95% confidence level.

Document Number: 002-14943 Rev. *L

Page 71 of 96

PRELIMINARY

CYW43340

15.4 WLAN 2.4 GHz Transmitter Performance Specifications

Note: The specifications in Table 31 are measured at the chip port output, unless otherwise specified.

Table 31. WLAN 2.4 GHz Transmitter Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum

Typical Maximum

Unit

–

2400

–

2500

MHz

Transmitted power in cellular 76–108 MHz

FM RX

–

–166

–165

–

dBm/Hz

and FM bands

776–794 MHz

CDMA2000

(–18 dBm at the antenna port,

90% duty cycle, OFDM)^a

869–960 MHz

cdmaOne,

GSM850

925–960 MHz

E-GSM

GPS

–

–165

–155

–147

–141

–

dBm/Hz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

GSM1800

GSM1900,

cdmaOne,

WCDMA

2010–2170 MHz

2400–2483 MHz

2.4 GHz

WCDMA

–

–138

–

dBm/Hz

dBm/MHz

dBm/Hz

dBm/1 MHz

dBm

BT/WLAN

GPS/GLONASS

2170 MHz band

LTE Band 40

LTE Band 7

LTE Band 38

LTE Band 41

LTE Band XGP

2nd harmonic

3rd harmonic

0 dBm

–147

–131

–109

–121

–115

–104

–110

–

2.4 GHz

Harmonic level (at 18 dBm with 4.8–5.0 GHz

–48.4

100% duty cycle)

7.2–7.5 GHz

–

–56.9

TX power at chip port for

highest power level setting at

25°C,

1 Mbps DSSS

6 Mbps

20

–

–3 dBm

19.5

18

dBm

VBAT = 3.6V, spectral mask

54 Mbps

–6 dBm

dBm

and EVM compliance^b

MCS7 (20 MHz)

MCS7 (40 MHz)

MCS7 (20 MHz, SGI)

MCS7 (40 MHz, SGI)

16.5

0.5

dBm

Phase noise

37.4 MHz Crystal, Integrated from 10 kHz to –

10 MHz

Degrees

TX power control dynamic

range

–

30

–

dB

Carrier suppression

Gain control step

–

15

–

dBc

dB

–

0.25

6

Return loss at Chip port TX

Z_o= 50Ω

4

dB

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands.

b. Derate by 2 dB for –30°C to –10°C and 55°C to 85°C.

Document Number: 002-14943 Rev. *L

Page 72 of 96

PRELIMINARY

CYW43340

15.5 WLAN 5 GHz Receiver Performance Specifications

Note: The specifications in Table 32 are measured at the chip port input, unless otherwise specified.

Table 32. WLAN 5 GHz Receiver Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum

4900

Typical

Maximum

Unit

MHz

–

5845

RX sensitivity

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–

–90.5

–87.5

–85.5

–82.5

–80.5

–76.5

–73.5

–

dBm

(10% PER for 1000 octet

PSDU)^a

RX sensitivity

20 MHz channel spacing for all MCS rates (GF)

MCS 0

(10% PER for 4096 octet

–

–90.5

–86.5

–84.5

–82.5

–78.5

–73.5

–71.5

–70.5

–

dBm

PSDU)^a

Defined for default parameters: MCS 1

GF, 800 ns GI, and non-STBC.

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

RX sensitivity

40 MHz channel spacing for all MCS rates (GF)

MCS 0

(10% PER for 4096 octet

–

–87.5

–84.5

–81.5

–80.5

–76.5

–71.5

–69.5

–68.5

–

dBm

PSDU)^a

Defined for default parameters: MCS 1

GF, 800 ns GI, and non-STBC.

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

RX sensitivity

20 MHz channel spacing for all MCS rates (Mixed mode)

(10% PER for 4096 octet

MCS 0

–

–89.5

–86.4

–84.0

–81.3

–78.4

–74.7

–73.1

–71.1

–

dBm

PSDU)^a

Defined for default parameters: MCS 1

Mixed mode, 800 ns GI, and

non-STBC.

MCS 2

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

Document Number: 002-14943 Rev. *L

Page 73 of 96

PRELIMINARY

CYW43340

Table 32. WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

RX sensitivity

Condition/Notes

Minimum

Typical

Maximum

Unit

40 MHz channel spacing for all MCS rates (Mixed mode)

(10% PER for 4096 octet

MCS 0

–

–87.5

–

18

–

dBm

PSDU)^a

Defined for default parameters: MCS 1

Mixed mode, 800 ns GI, and

non-STBC.

–

–83.9

dBm

MHz

dB

MCS 2

–

–81.7

MCS 3

MCS 4

MCS 5

MCS 6

MCS 7

–

–79.1

–

–75.9

–

–70.8

–

–69.1

–

–67.5

Blocking level for 1 dB RX

sensitivity degradation (without

external filtering)^b

776–794 MHz

CDMA2000

cdmaOne

GSM850

E-GSM

–21

–20

–12

–15

–20

–24

–

824–849 MHz

–

824–849 MHz

–

880–915 MHz

–

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

Maximum LNA gain

Minimum LNA gain

@ 6, 9, 12 Mbps

GSM1800

cdmaOne

WCDMA

–

Input In-Band IP3^a

–15.5

–

–1.5

–

Maximum receive level

@ 5.24 GHz

–29.5

9

@ 18, 24, 36, 48, 54 Mbps

–

LPF 3 dB bandwidth

–

Adjacent channel rejection

(Difference between interfering

and desired signal (20 MHz

apart) at 10% PER for 1000

octet PSDU with desired signal

level as specified in Condition/

Notes)

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

–79 dBm

16

15

13

11

8

–

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–61 dBm

–

dB

–

dB

–

dB

–

dB

4

–

dB

0

–

dB

–1

–2

–

dB

–

dB

Document Number: 002-14943 Rev. *L

Page 74 of 96

PRELIMINARY

CYW43340

Table 32. WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

–78.5 dBm

Minimum

32

Typical

Maximum

Unit

dB

Alternate adjacent channel

rejection

(Difference between interfering

and desired signal (40 MHz

apart) at 10% PER for 1000^c

octet PSDU with desired signal

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

–

5

8

–

–77.5 dBm

–75.5 dBm

–73.5 dBm

–70.5 dBm

–66.5 dBm

–62.5 dBm

–61.5 dBm

–60.5 dBm

31

29

27

24

20

16

15

14

–

dB

–

level as specified in Condition/ 24 Mbps OFDM

–

Notes)

36 Mbps OFDM

–

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

–

Maximum receiver gain

Gain control step

RSSI accuracy^d

–

100

3

–

Range –98 dBm to –30 dBm

Range above –30 dBm

Z_o= 50Ω

–5

–8

6

–

Return loss

10

5.0

Receiver cascaded noise figure At maximum gain

–

a.Derate by 1.5 dB for –30 °C to –10°C and 55°C to 85°C.

b.The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test.

It is not intended to indicate any specific usage of each band in any specific country.

c.For 65 Mbps, the size is 4096.

d.The minimum and maximum values shown have a 95% confidence level.

15.6 WLAN 5 GHz Transmitter Performance Specifications

Note: The specifications in Table 33 are measured at the chip port, unless otherwise specified.

Table 33. WLAN 5 GHz Transmitter Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum Typical Maximum

Unit

MHz

–

4900

–

5845

Transmitted power in cellular

and FM bands (–18 dBm at the

antenna port, >90% duty cycle,

OFDM)^a

76–108 MHz

776–794 MHz

869–960 MHz

925–960 MHz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

FM RX

–

< –168

–168

–170

–168

–169

–

dBm/Hz

cdmaOne, GSM850

E-GSM

GPS

GSM1800

GSM1900,

cdmaOne,

WCDMA

2110–2170 MHz

2400–2483 MHz

2300–2690

WCDMA

BT/WLAN

LTE

–

–169

–166

–167

–48.6

–

dBm/Hz

dBm/MHz

Harmonic level

(at 17 dBm)

9.8–11.570 GHz

2nd harmonic

Document Number: 002-14943 Rev. *L

Page 75 of 96

PRELIMINARY

CYW43340

Table 33. WLAN 5 GHz Transmitter Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum Typical Maximum

Unit

dBm

TX power at chip port for

highest power level setting at

25°C,

6 Mbps

–

19

–

54 Mbps

17

dBm

MCS0 (20 MHz)

19.5

16.5

0.7

dBm

VBAT = 3.6V, spectral mask

and EVM compliance^b

MCS7 (20 MHz)

dBm

MCS7 (40 MHz)

dBm

MCS7 (20 MHz, SGI)

MCS7 (40 MHz, SGI)

dBm

Phase noise

37.4 MHz crystal, Integrated from 10 kHz to 10 –

MHz

Degrees

TX power control dynamic

range

–

30

–

dB

Carrier suppression

Gain control step

Return loss

–

15

–

dBc

dB

–

0.25

6

Z_o= 50Ω

–

dB

a.The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands.

b.Derate by 2 dB for –30°C to –10°C and 55°C to 85°C.

15.7 General Spurious Emissions Specifications

Table 34. General Spurious Emissions Specifications

Parameter

Frequency range

Condition/Notes

Min

Typ

Max

2500

Unit

–

2400

–

MHz

General Spurious Emissions

TX Emissions

30 MHz < f < 1 GHz

RBW = 100 kHz

RBW = 1 MHz

RBW = 100 kHz

RBW = 1 MHz

–

–62

–47

–53

–63

–53

dBm

1 GHz < f < 12.75 GHz

1.8 GHz < f < 1.9 GHz

5.15 GHz < f < 5.3 GHz

30 MHz < f < 1 GHz

–

RX/standby Emissions

–78

–68.5^a

1 GHz < f < 12.75 GHz

1.8 GHz < f < 1.9 GHz

5.15 GHz < f < 5.3 GHz

–96

a.For frequencies other than 3.2 GHz, the emissions value is –96 dBm. The value presented in table is the result of LO leakage at 3.2 GHz.

Document Number: 002-14943 Rev. *L

Page 76 of 96

PRELIMINARY

CYW43340

16. Internal Regulator Electrical Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of device

characterization.

Functional operation is not guaranteed outside of the specification limits provided in this section.

16.1 Core Buck Switching Regulator

Table 35. Core Buck Switching Regulator (CBUCK) Specifications

Specification

Notes

Min

2.9

Typ

3.6

Max

4.8^a

Units

Input supply voltage (DC),

VBAT

DC voltage range inclusive of disturbances.

V

PWM mode switching

frequency, Fsw

Forced PWM without FLL enabled.

2.8

3.6

–

4

5.2

4.4

372^b

–

MHz

mA

Forced PWM with FLL enabled.

4

PWM output current

Output current limit

Output voltage range

–

1390

1.35

mA

Programmable, 30 mV steps.

Default = 1.35V (bits = 0000).

1.2

1.5

Volts

PWM output voltage DC accuracy

Includes load and line regulation.

Forced PWM mode.

–4

–

4

%

Total DC accuracy after trim.

–2

–

7

2

%

PWM ripple voltage, static

Measure with 20 MHz BW limit.

Static Load. Max ripple based on:

VBAT < 4.8V, Vout = 1.35V, Fsw = 4 MHz, 2.2 µH

inductor, L > 1.05 µH,

20

mVpp

capacitor + Board total-ESR < 20 mΩ, Cout >

1.9 µF, ESL < 200 pH.

PWM mode peak efficiency

2.5 x 2 mm LQM2HPN2R2NG0,

L = 2 µH, DCR = 80 mΩ ±25%,

79

78

74

67

85

84

81

77

–

%

(Peak efficiency is at 200 mAload. The ACR < 1Ω.

following conditions apply to all

inductor types: Forced PWM, 200 mA,

Vout = 1.35V, VBAT = 3.6V, Fsw = 4

MHz, at 25°C.)

0805-size LQM21PN2R2NGC,

L = 2.1 µH, DCR=230 mΩ ±25%,

ACR < 2Ω.

0603-size MIPSTZ1608D2R2B,

L = 1 µH, DCR = 240 mΩ ±25%,

ACR < 2Ω.

PFM mode efficiency

LPOM efficiency

10 mA load current, Vout = 1.35V,

VBAT = 3.6V,

20C Cap + Board total-ESR < 20 mΩ, Cout =

4.7 µF, ESL < 200 pH, FLL= OFF

0603-size MIPSTZ1608D2R2B,

L = 2.2 µH, DCR = 240 mΩ ±25%,

ACR < 2Ω.

1 mA load current, Vout = 1.35V,

VBAT = 3.6V,

55

65

–

%

20C Cap + board total-ESR < 20 mΩ, Cout =

4.7 µF, ESL < 200 pH, FLL = OFF

0603-size MIPSTZ1608D2R2B,

L = 2.2 µH, DCR = 240Ω ±25%,

ACR < 2Ω.

Start-up time from power down

VIO already on and steady.

Time from REG_ON rising edge to CLDO

reaching 1.2V.

–

903

1106

µs

Includes 256 µsec typical Vddc_ok_o delay.

Document Number: 002-14943 Rev. *L

Page 77 of 96

PRELIMINARY

CYW43340

Table 35. Core Buck Switching Regulator (CBUCK) Specifications (Cont.)

Specification

External inductor, L^c

External output capacitor, Cout^c

Notes

Min

Typ

2.2

Max

Units

µH

–

Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz, 2^d

±20%, 6.3V, 4.7 µF,

4.7

µF

Murata^®GRM155R60J475M

External input capacitor, Cin^c

For SR_VDDBATP5V pin.

Ceramic, X5R, 0603, ESR < 30 mΩ at 4 MHz,

0.67^d

4.7

–

µF

±20%, 6.3V, 4.7 µF,

Murata GRM155R60J475M.

Input supply voltage ramp-up time

0 to 4.3V

40

–

100,000

µs

a.The maximum continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Volt-

ages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

b.At junction temperature 125°C.

c.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.

d.The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.

16.2 3.3V LDO (LDO3P3)

Table 36. LDO3P3 Specifications

Parameters

Input supply voltage, Vin Minimum = Vo+0.2V = 3.5V (for Vo = 3.3V)

dropout voltage requirement must be met under max load for perfor-

Conditions

Min.

2.9

Typ.

3.6

Max.

4.8

Units

V

mance specs.

Nominal output voltage, Default = 3.3V

Vo

–

3.3

–

V

Output voltage program- Range

2.4

3.4

+5

mability

Accuracy at any step (including Line/Load regulation), load > 0.1 mA –5

%

Dropout voltage

Output current

Quiescent current

At maximum load

–

200

450

mV

mA

0.001

–

No load; Vin = Vo + 0.2V

Maximum load @ 450mA; Vin = Vo + 0.2V

66

4

85

4.5

µA

mA

Leakage current

Line regulation

Load regulation

Load step error

Powerdown mode (at 85°C junction temperature)

Vin from (Vo + 0.2V) to 4.8V, maximum load

load from 1–450 mA, Vin = 3.6V

–

1.5

5

µA

3.5

0.45

70

mV/V

mV/mA

mV

0.3

–

Load from 1mA-200mA-400mA in 1 q5s and

400mA-200mA-1mA in 1 µs; Vin ≥ (Vo + 0.2V);

Co = 4.7 µF

PSRR

VBAT ≥ 3.6V, Vo = 3.3V, Co = 4.7 µF,

maximum load, 100 Hz to 100 kHz

20

–

dB

LDO turn-on time

Output current limit

In-rush current

LDO turn-on time when rest of chip is up

–

160

800

250

µs

–

mA

µF

Vin = Vo + 0.2V to 4.8V, Co = 4.7 µF, no load

–

280

External output

capacitor, Co

Ceramic, X5R, 0402,

(ESR: 5m-240mohm), ±10%, 10V

1.0

4.7

5.64

External input capacitor For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R,

0402, ±10%, 10V.

–

µF

Not needed if sharing VBAT cap 4.7 µF with SR_VDDBATP5V.

Document Number: 002-14943 Rev. *L

Page 78 of 96

PRELIMINARY

CYW43340

16.3 2.5V LDO (LDO2P5)

Table 37. LDO2P5 Specifications

Specification

Notes

Min.

2.9

Typ.

3.6

Max.

4.8

Unit

Input supply voltage

Min= 2.52+0.15=2.67V

V

Dropout voltage requirement must be met under the maximum load

for performance specifications.

Output current

–

70

mA

V

Output voltage, Vo

Dropout voltage

default = 2.52V

2.4

2.52

3.4

150

+5

at max load

mV

%

Output voltage DC

Accuracy

include Line/Load regulation

–5

Quiescent current

No load

–

8

–

µA

Line regulation

Vin from (Vo + 0.15V) to 4.8V, maximum load

–11

11

31

mV

Load Regulation

Load from 1–70 mA (subject to parasitic resistance of package and –

board). Vin = 2.52 + 0.15V to 4.8V

15

Leakage current

PSRR

Powerdown mode. At Junction Temp 85°C

–

5

–

µA

dB

VBAT ≥ 3.6V, Vo = 2.52V, Co = 2.2 µF,

maximum load, 100 Hz to 100 kHz

20

LDO turn-on time

LDO turn-on time when rest of chip is up

–

260

100

µs

In-rush current during

turn-on

from its output capacitor in fully-discharged state

mA

External output

capacitor, Co

Ceramic, X5R, 0402,

(ESR: 5m-240mohm), ±20%, 6.3V

0.7^a

–

2.2

1

2.64

–

µF

External input capacitor For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R,

0402, ±10%, 10V. Not needed if sharing the VBAT capacitor 4.7 µF

with SR_VDDBATP5V.

a.Minimum cap value refers to residual cap value after taking into account part–to–part tolerance, DC–bias, temperature, aging

16.4 HSICDVDD LDO

Table 38. HISCDVDD LDO Specifications

Specification

Input supply voltage

Notes

Min

1.3

Typ

1.35

Max

1.5

Units

Min = 1.2V + 0.1V = 1.3V.

V

Dropout voltage requirement must be met

under maximum load for performance specifi-

cations.

Output current

–

80

mA

V

Output voltage, V_o

Dropout voltage

Step size 25 mV. Default = 1.2V.

1.1

–

1.2

–

1.275

100

At maximum load. Includes 100 mΩ routing

mV

resistors at input and output.

Output voltage DC accuracy

Quiescent current

Including line/load regulation.

–4

–

4

–

%

No load. Dependent on programming.

ldo_cntl_i[43], ldo_cntl_i[41] to support

different external capacitor loads.

182

µA

PSRR at 1 kHz

Input ≥ 1.35V, 50 to 300 pF, V_o= 1.2V

Load: 80 mA

Load: 40 mA

–

24

39

dB

Document Number: 002-14943 Rev. *L

Page 79 of 96

PRELIMINARY

CYW43340

Table 38. HISCDVDD LDO Specifications (Cont.)

Specification

PSRR at 10 kHz

Notes

Min

24

Typ

Max

Units

Input ≥ 1.35V, 50 to 300 pF, V_o= 1.2V

Load: 80 mA

–

dB

Load: 40 mA

38

PSRR at 100 kHz

Input ≥ 1.35V, 50 to 300 pF, V_o= 1.2V

Load: 80 mA

15

27

dB

Load: 40 mA

Output Capacitor, C_o

Internal capacitor = Sum of supply decoupling –

caps and supply-to-ground routing parasitic

capacitance.

1000

pF

Output capacitor dependent on programming.

16.5 CLDO

Table 39. CLDO Specifications

Specification

Notes

Min

Typ

1.35

Max

1.5

Units

Input supply voltage, V_in

Min = 1.2 + 0.1V = 1.3V.

1.3

V

Dropout voltage requirement must be met under

maximum load.

Output current

–

0.1

1.1

–

150

mA

Output voltage, V_o

Programmable in 25 mV steps.

1.2

1.275

V

Default = 1.2V, load from 0.1–150 mA

Dropout voltage

Output voltage DC accuracy^a

At max load

–

100

+4

mV

%

Includes line/load regulation

–4

After trim, load from 0.1–150 mA, includes line/load –2

+2

%

regulation.

V_in> V_o+ 0.1V.

Quiescent current

Line regulation

Load regulation

Leakage current

PSRR

No load

–

10

–

µA

V_infrom (V_o+ 0.1V) to 1.5V, maximum load

Load from 1 mA to 150 mA

Power-down

–

7

mV/V

µV/mA

µA

–

15

–

25

10

–

@1 kHz, Vin ≥ 1.5V, C_o= 1 µF

20

–

dB

Start-up time of PMU

VIO up and steady. Time from the REG_ON rising

edge to the CLDO reaching 1.2V. Includes 256 µs

vddc_ok_o delay.

–

1106

µs

LDO turn-on time

Chip already powered up.

–

1

180

150

–

µs

In-rush current during turn-on

From its output capacitor in a fully-discharged state

Total ESR: 30 mΩ–200 mΩ

–

mA

µF

b

External output capacitor, C_o

0.67^c

External input capacitor

Only use an external input capacitor at the VDD_LDO –

pin if it is not supplied from the CBUCK output. Total

ESR (trace/capacitor): 30 mΩ–200 mΩ

–

a.Load from 0.1 to 150 mA.

b.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.

c.The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: 002-14943 Rev. *L

Page 80 of 96

PRELIMINARY

CYW43340

16.6 LNLDO

Table 40. LNLDO Specifications

Specification

Notes

Min

1.3

Typ

1.35

Max

1.5

Units

Input supply voltage, Vin

Min = 1.2V_o+ 0.1V = 1.3V.

V

Dropout voltage requirement must be met under

maximum load.

Output current

–

0.1

1.1

–

104

mA

V

Output voltage, V_o

Programmable in 25 mV steps.

Default = 1.2V

1.2

1.275

Dropout voltage

At maximum load

–

100

+4

mV

%

Output voltage DC

accuracy^a

includes line/load regulation, load from 0.1 to

150 mA

–4

Quiescent current

Line regulation

Load regulation

Leakage current

Output noise

No load

–

44

–

µA

V

_infrom (V_o+ 0.1V) to 1.5V, max load

7

mV/V

µV/mA

µA

Load from 1 mA to 104 mA

Power-down

15

–

25

10

@30 kHz, 60 mA load, C_o= 1 µF

@100 kHz, 60 mA load, C_o= 1 µF

–

60

35

nV/root-Hz

PSRR

@ 1kHz, input > 1.3V, C_o= 1 µF,

V_o= 1.2V

20

–

dB

Start-up time of PMU

VIO up and steady. Time from the REG_ON rising –

edge to the LNLDO reaching 1.2V. Includes 256

µs vddc_ok_o delay.

1106

µs

LDO turn-on time

Chip already powered up.

–

180

150

µs

In-rush current during turn-on

From its output capacitor in a fully-discharged

state

mA

External output capacitor,

C_o

Total ESR (trace/capacitor): 30–200 mΩ

0.67^c

–

1

–

µF

b

External input capacitor

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from the CBUCK

output.

Total ESR (trace/capacitor): 30–200 mΩ

a.Load from 0.1 to 104 mA.

b.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.

c.The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

Document Number: 002-14943 Rev. *L

Page 81 of 96

PRELIMINARY

CYW43340

17. System Power Consumption

Note: Values in this data sheet are design goals and are subject to change based on the results of device

characterization.

■ Unless otherwise stated, these values apply for the conditions specified in Table 24: “Recommended Operating Conditions and DC

Characteristics,” on page 58.

17.1 WLAN Current Consumption

The WLAN current consumption measurements are shown in Table 41.

All values in Table 41 are with the Bluetooth core in reset (that is, Bluetooth is off).

Table 41. Typical WLAN Power Consumption

VBAT = 3.6V, VDDIO = 1.8V, T_A25°C

Bandwidth

(MHz)

Band

(GHz)

Mode

VBAT (mA)

Vio^a(µA)

Sleep Modes

Leakage (OFF)

SLEEP^b

IEEE Power Save, DTIM 1^c

IEEE Power Save DTIM 3^d

–

0.004

220

–

0.005

1.06

–

0.321

Active Modes

RX (Listen)^{e, f}

RX (Active)^{f, g, h}

–

44.4

57.7

325

254

270

263

261

283

271

200

TX CCK, 11 Mbps (20.5 dBm @ chip)^{h, i, j}

TX, MCS7 (17.5 dBm @ chip)^{h, i, j}

TX OFDM, 54 Mbps (18 dBm @ chip)^{h, i, j}

TX, MCS7 (15 dBm @ chip)^{h, i, j}

TX OFDM, 54 Mbps (16 dBm @ chip)^{h, i, j}

HT20

HT40

HT20

HT40

HT20

2.4

5

a.Vio is specified with all pins idle and not driving any loads.

b.Idle between beacons.

c.Beacon interval = 100 ms; beacon duration = 1.9 ms @ 1Mbps (Integrated Sleep + wakeup + beacon)

d.Beacon interval = 300 ms; beacon duration = 1.9 ms @ 1Mbps (Integrated Sleep + wakeup + beacon)

e.Carrier sense (CCA) when no carrier present.

f.Carrier sense (CS) detect/packet RX.

g.Applicable to all supported rates.

h.Duty Cycle = 100%

i.TX output power is measured at the chip-out side.

j.The items of active modes are measured under the real association/throughput with the wireless AP.

Document Number: 002-14943 Rev. *L

Page 82 of 96

PRELIMINARY

CYW43340

17.2 Bluetooth and BLE Current Consumption

The Bluetooth current consumption measurements are shown in Table 42.

■ The WLAN core is in reset (WL_REG_ON = low) for all measurements provided in Table 42.

The BT current consumption numbers are measured based on GFSK TX output power = 8 dBm.

Table 42. Bluetooth Current Consumption

Operating Mode

VBAT (3.6V)

VDDIO (1.8V)

Unit

µA

Sleep

6

133

–

SCO HV3 master

3DH5/3DH1 master

DM1/DH1 master

DM3/DH3 master

DM5/DH5 master

2EV3

10.1

18.1

22.9

27.0

28.3

7.5

mA

–

mA

–

mA

–

mA

–

mA

0.1

131

132

mA

BLE scan^a

169

43

µA

BLE connected (1 second)

µA

a.No devices present; 1.28 second interval with a scan window of 11.25 ms.

Document Number: 002-14943 Rev. *L

Page 83 of 96

PRELIMINARY

CYW43340

18. Interface Timing and AC Characteristics

18.1 SDIO Timing

18.1.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 31 and Table 43.

Figure 31. SDIO Bus Timing (Default Mode)

f_PP

t_WL

t_WH

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

(max)

(min)

Table 43. SDIO Bus Timing^aParameters (Default Mode)

Parameter

Symbol

Minimum

Typical

Maximum

Unit

SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)

Frequency – Data Transfer mode

Frequency – Identification mode

Clock low time

fPP

0

–

25

400

–

MHz

fOD

tWL

tWH

tTLH

tTHL

0

kHz

ns

10

–

Clock high time

–

ns

Clock rise time

10

ns

Clock low time

–

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

Input hold time

tISU

tIH

5

–

ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer mode

Output delay time – Identification mode

a.Timing is based on CL  40pF load on CMD and Data.

b.min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.

tODLY

0

–

14

50

ns

Document Number: 002-14943 Rev. *L

Page 84 of 96

PRELIMINARY

CYW43340

18.1.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 32 and Table 44.

Figure 32. SDIO Bus Timing (High-Speed Mode)

f_PP

t_WL

t_WH

50% VDD

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

t_OH

Table 44. SDIO Bus Timing^aParameters (High-Speed Mode)

Parameter Symbol

SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)

Minimum

Typical

Maximum

Unit

Frequency – Data Transfer Mode

Frequency – Identification Mode

Clock low time

fPP

0

7

–

50

400

–

MHz

fOD

tWL

tWH

tTLH

tTHL

kHz

ns

Clock high time

–

ns

Clock rise time

3

ns

Clock low time

3

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup Time

tISU

tIH

6

2

–

ns

Input hold Time

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

Output hold time

tODLY

tOH

–

14

–

ns

pF

2.5

–

Total system capacitance (each line)

a.Timing is based on CL  40pF load on CMD and Data.

b.min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.

CL

40

Document Number: 002-14943 Rev. *L

Page 85 of 96

PRELIMINARY

CYW43340

18.2 HSIC Interface Specifications

Table 45. HSIC Timing Parameters

Parameter

HSIC signaling voltage

I/O voltage input low

I/O Voltage input high

I/O voltage output low

I/O voltage output high

I/O pad drive strength

Symbol

Minimum

1.1

Typical

Maximum

1.3

Unit

Comments

V_DD

V_IL

1.2

–

V

Ω

–

–0.3

0.35 × V_DD

V_DD+ 0.3

0.25 × V_DD

–

V_IH

V_OL

V_OH

O_D

0.65 × V_DD

–

0.75 × V_DD

40

–

60

Controlled output

impedance driver

I/O weak keepers

I_L

20

100

3

–

70

–

μA

kΩ

pF

Ω

–

I/O input impedance

Total capacitive load^a

Z_I

C_L

–

14

55

10

15

Characteristic trace impedance T_I

Circuit board trace length T_L

45

–

50

–

cm

ps

Circuit board trace propagation T_S

skew^b

–

STROBE frequency^c

F_STROBE

239.988

240

1.0

240.012

1.2

MHz

V/ns

± 500 ppm

Slew rate (rise and fall) STROBE T_slew

and DATA^C

0.60 × V_DD

Averaged from

30% ~ 70% points

Receiver data setup time (with

respect to STROBE)^c

T_s

300

–

ps

Measured at the 50%

point

Receiver data hold time (with

respect to STROBE)^c

T_b

Measured at the 50%

point

a.Total Capacitive Load (C_L), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with a length of 10 cm.

b.Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be matched between STROBE and DATA to ensure

that the signal timing is within specification limits at the receiver.

c.Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the table above.

18.3 JTAG Timing

Table 46. JTAG Timing Characteristics

Output

Minimum

Signal Name

Period

125 ns

Setup

Hold

Maximum

TCK

TDI

–

20 ns

–

0 ns

–

TMS

TDO

–

100 ns

–

0 ns

–

JTAG_TRST

250 ns

–

Document Number: 002-14943 Rev. *L

Page 86 of 96

PRELIMINARY

CYW43340

19. Power-Up Sequence and Timing

19.1 Sequencing of Reset and Regulator Control Signals

The CYW43340 has three signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN,

and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing

of the signals for various operational states (see Figure 33, Figure 34 on page 88, and Figure 35 and Figure 36 on page 89). The

timing values indicated are minimum required values; longer delays are also acceptable.

■ The WL_REG_ON and BT_REG_ON signals are ORed in the CYW43340. The diagrams show both signals going high at the same

time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used

(one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW43340

regulators.

■ The CYW43340 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC

and VDDIO have both passed the POR threshold (see Table 24: “Recommended Operating Conditions and DC Characteristics,”

on page 58). Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses.

VBAT should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present

first or be held high before VBAT is high.

19.1.1 Description of Control Signals

■ WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the

internal CYW43340 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this

pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled.

■ BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW43340 regulators. If both the

BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT

section is in reset.

Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 msec time delay between

consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to

discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next

PMU cold start.

19.1.2 Control Signal Timing Diagrams

Figure 33. WLAN = ON, Bluetooth = ON

32.678 kHz Sleep Clock

VBAT*

90% of VH

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds.

2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be

present first or be held high before VBAT is high.

Document Number: 002-14943 Rev. *L

Page 87 of 96

PRELIMINARY

CYW43340

Figure 34. WLAN = OFF, Bluetooth = OFF

32.678 kHz Sleep Clock

VBAT*

VDDIO

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first

or be held high before VBAT is high.

Figure 35. WLAN = ON, Bluetooth = OFF

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds.

2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first

or be held high before VBAT is high .

Document Number: 002-14943 Rev. *L

Page 88 of 96

PRELIMINARY

CYW43340

Figure 36. WLAN = OFF, Bluetooth = ON

32.678 kHz Sleep Clock

VBAT

90% of VH

VDDIO

~ 2 Sleep cycles

W L_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise faster than 40 m icroseconds or slower than 100 m illiseconds.

2. VBAT should be up before or at the sam e time as VDDIO . VDDIO should NOT be present first

or be held high before VBAT is high .

Document Number: 002-14943 Rev. *L

Page 89 of 96

PRELIMINARY

CYW43340

20. Package Information

20.1 Package Thermal Characteristics

Table 47. Package Thermal Characteristics^a

Characteristic

WLBGA



_JA(°C/W) (value in still air)

36.8

_JB(°C/W)

5.93

_JC(°C/W)

2.82



_JT(°C/W)

_JB(°C/W)

9.26



16.93

114.08

1.198

Maximum Junction Temperature T_j

Maximum Power Dissipation (W)

a. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = 1.198W

continuous dissipation.

20.2 Junction Temperature Estimation and PSI Versus THETA

JT

JC

Package thermal characterization parameter PSI–J_T(_JT) yields a better estimation of actual junction temperature (T_J) versus using

the junction-to-case thermal resistance parameter Theta–J_C(_JC). The reason for this is that _JCassumes that all the power is

dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom

and sides of the package. _JTtakes into account power dissipated through the top, bottom, and sides of the package. The equation

for calculating the device junction temperature is:

T = T + P x 

J

T

JT

Where:

■ T_J= Junction temperature at steady-state condition (°C)

■ T_T= Package case top center temperature at steady-state condition (°C)

■ P = Device power dissipation (Watts)

■ _JT= Package thermal characteristics; no airflow (°C/W)

20.3 Environmental Characteristics

For environmental characteristics data, see Table 22: “Environmental Ratings,” on page 57.

Document Number: 002-14943 Rev. *L

Page 90 of 96

PRELIMINARY

CYW43340

21. Mechanical Information

Figure 37. 141-Ball WLBGA Package Mechanical Information

Document Number: 002-14943 Rev. *L

Page 91 of 96

PRELIMINARY

CYW43340

Figure 38. WLBGA Keep-Out Areas for PCB Layout—Bottom View

Note: No top-layer metal is allowed in keep-out areas.

Document Number: 002-14943 Rev. *L

Page 92 of 96

PRELIMINARY

CYW43340

22. Ordering Information

Operating Ambi-

ent Temperature

Part Number

Package

Description

CYW43340XKUBG

CYW43340HKUBG

141 ball WLBGA

(5.67 mm × 4.47 mm, 0.4 mm pitch)

Dual-band 2.4 GHz and 5 GHz WLAN –30°C to +85°C

+ BT 4.0

141 ball WLBGA

(5.67 mm × 4.47 mm, 0.4 mm pitch)

Dual-band 2.4 GHz and 5 GHz WLAN –30°C to +85°C

+ BT 4.0 + BSP

Document Number: 002-14943 Rev. *L

Page 93 of 96

PRELIMINARY

CYW43340

Document History

Document Title: CYW43340 Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Inte-

grated Bluetooth 4.0

Document Number: 002-14943

Revision

ECN

Orig. of Change

Submission Date

Description of Change

07/09/2012

43340–DS100-R:

• Initial Release

**

-

12/21/2012

43340–DS101-R:

Updated:

• HCI high-speed UART: H4+ mode no longer supported.

• General Description on page 1.

• “IEEE 802.11x Key Features” on page 5: shared Bluetooth and 2.4 GHz

WLAN signal path.

• Figure 11: “Startup Signaling Sequence,” on page 54.

• “External Coexistence Interface” on page 80.

• Table 26: “WLBGA and WLCSP Signal Descriptions,” on page 127.

*A

-

• Table 27: “WLAN GPIO Functions and Strapping Options (Advance In-

formation),” on page 140.

• Table 31: “I/O States,” on page 145

.

• Table 32: “Absolute Maximum Ratings,” on page 149.

• Table 36: “Bluetooth Receiver RF Specifications,” on page 154.

• Table 37: “Bluetooth Transmitter RF Specifications,” on page 158.

• Table 53: “Typical WLAN Power Consumption,” on page 185.

• Table 54: “Bluetooth and FM Current Consumption,” on page 187.

04/22/2013

43340–DS102-R:

Updated:

• Figure 1: “Functional Block Diagram,” on page 1.

• AES feature description on page 5.

• VBAT voltage range changed from 2.3–4.8V to 2.9–4.8V.

• Figure 4: “Typical Power Topology,” on page 29.

• “Link Control Layer” on page 51: substates.

• Table 33: “Bluetooth Receiver RF Specifications,” on page 131.

• Figure 52: “WLAN Port Locations (5 GHz),” on page 142.

*B

-

• Table 34: “Bluetooth Transmitter RF Specifications,” on page 135: Power

control step.

• Table 36: “BLE RF Specifications,” on page 136: Rx sense.

• Table 37: “FM Receiver Specifications,” on page 137.

• Table 39: “WLAN 2.4 GHz Receiver Performance Specifications,” on

page 144.

• Table 40: “WLAN 2.4 GHz Transmitter Performance Specifications,” on

page 148.

• Table 42: “WLAN 5 GHz Transmitter Performance Specifications,” on

page 153.

• Table 50: “Typical WLAN Power Consumption,” on page 162.

08/30/0213

12/03/2013

43340–DS103-R:

• Removed ‘Preliminary’ from the document type.

*C

*D

-

43340–DS104-R:

Updated:

• Proprietary protocols in “Standards Compliance” on page 21.

• Table 24: “ESD Specifications,” on page 102.

• Table 33: “WLAN 2.4 GHz Transmitter Performance Specifications,” on

page 124.

• Table 35: “WLAN 5 GHz Transmitter Performance Specifications,” on

page 129.

-

02/14/2014

43340–DS105-R:

Updated:

*E

-

• Section 26: “Ordering Information,” on page 194.

Document Number: 002-14943 Rev. *L

Page 94 of 96

PRELIMINARY

CYW43340

Document Title: CYW43340 Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Inte-

grated Bluetooth 4.0

Document Number: 002-14943

03/04/0214

43340–DS106-R:

• Figure 38: “141-Bump CYW43340 WLBGA Ball Map (Bottom View),” on

page 58 and Table 18: “WLBGA Signal Descriptions,” on page 59: Up-

dated signal names for No Connect, VDDC, VDDIO, VSS, VSSC, and

WRF_PA5G_VBAT_GND3P3 pins.

*F

-

04/07/2014

43340–DS107-R:

Updated:

• [43341]Figure 48: “NFC Boot-Up Sequence (Secure Patch Download)

from Snooze,” on page 117

• [43341]“NFC Operation Requirement” on page 119

*G

-

• Table 28: “WLAN GPIO Functions and Strapping Options (Advance In-

formation),” on page 144

• Title change (2.5 GHz to 2.4 GHz) for Figure 55 on page 169

07/07/2014

43340–DS108-R:

Updated:

*H

*I

-

• Figure 65: “WLBGA Keep-Out Areas for PCB Layout — Bottom View,”

on page 177

43340–DS109-R:

Updated:

• Table 18: “WLBGA Signal Descriptions,” on page 59

01/28/2015

09/10/2015

43340–DS110-R:

Updated:

*J

• Table 32: “WLAN 2.4 GHz Receiver Performance Specifications,” on

page 85

*K

*L

5529544

5675330

UTSV

11/23/2016

03/28/2017

Updated to Cypress template

Removed FM and gSPI sections throughout the document.

Document Number: 002-14943 Rev. *L

Page 95 of 96

PRELIMINARY

CYW43340

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

96

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14943 Rev. *L

Revised March 28, 2017

Page 96 of 96


型号：	CYW43340XKUBGT
厂家：	CYPRESS
描述：	Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Integrated Bluetooth 4.0
文件：	总96页 (文件大小：1349K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYW43340XKUBGT [CYPRESS]

相关型号：

CYW43353

CYW43353LIUBG

CYW43362

CYW43362KUBG

CYW43364

CYW43364KUBG

CYW43364KUBGT

CYW4339

CYW4339NKFFBG

CYW4339XKUBG

CYW4339XKWBG

CYW43438