FM22L16 [CYPRESS]
4Mbit Asynchronous F-RAM Memory; 4Mbit的异步F-RAM存储器
| 型号： | FM22L16 |
| 厂家： | 
CYPRESS |
| 描述： | 4Mbit Asynchronous F-RAM Memory |
| 文件： | 总14页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FM22L16
4Mbit Asynchronous F-RAM Memory
Features
Superior to Battery-backed SRAM Modules
4Mbit Ferroelectric Nonvolatile RAM
•
•
•
•
No Battery Concerns
•
•
•
•
•
•
Organized as 256Kx16
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Configurable as 512Kx8 Using /UB, /LB
1014 Read/Write Cycles
NoDelay™ Writes
Page Mode Operation to 40MHz
Advanced High-Reliability Ferroelectric Process
Low Power Operation
•
•
•
2.7V – 3.6V Power Supply
Low Current Mode (5µA) using ZZ pin
Low Active Current (8 mA typ.)
SRAM Compatible
•
•
JEDEC 256Kx16 SRAM Pinout
55 ns Access Time, 110 ns Cycle Time
Industry Standard Configuration
•
•
Industrial Temperature -40° C to +85° C
44-pin “Green”/RoHS TSOP-II package
Advanced Features
Software Programmable Block Write Protect
•
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Description
The FM22L16 is a 256Kx16 nonvolatile memory that
reads and writes like
a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make the
F-RAM superior to other types of memory.
Pin Configuration
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
1
2
A6
A7
A2
3
OE
A1
4
UB
A0
5
LB
CE
6
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
/ZZ
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
In-system operation of the FM22L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM22L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
A17
A16
A15
A14
A13
A8
A9
A10
A11
A12
The FM22L16 includes a low voltage monitor that
blocks access to the memory array when VDD drops
below VDD min. The memory is protected against an
inadvertent access and data corruption under this
condition. The device also features software-
controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be
individually write protected.
Ordering Information
FM22L16-55-TG
55 ns access, 44-pin
“Green”/RoHS TSOP-II
FM22L16-55-TGTR 55 ns access, 44-pin
“Green”/RoHS TSOP-II,
Tape & Reel
This product conforms specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 3.0
May 2010
Page 1 of 14
FM22L16 - 256Kx16 FRAM
Figure 1. Block Diagram
Pin Description
Pin Name
Type Pin Description
A(17:0)
Input
Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is low
and /ZZ is high. The entire address is latched internally on the falling edge of /CE. Subsequent
changes to the A(1:0) address inputs allow page mode operation when /CE is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM22L16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
/CE
Input
/WE
Input
/OE
/ZZ
Input
Input
Output Enable: When /OE is low, the FM22L16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for normal
read/write operation.
DQ(15:0)
/UB
I/O
Input
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. Deasserting /UB high tri-
states the DQ pins. If the user does not perform byte writes and the device is not configured as
a 512Kx8, the /UB and /LB pins may be tied to ground.
/LB
Input
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. Deasserting /LB high tri-
states the DQ pins. If the user does not perform byte writes and the device is not configured as
a 512Kx8, the /UB and /LB pins may be tied to ground.
VDD
VSS
Supply Supply Voltage
Supply Ground
Rev. 3.0
May 2010
Page 2 of 14
FM22L16 - 256Kx16 FRAM
Functional Truth Table 1,2
/CE
X
H
↓
/WE
X
A(17:2)
A(1:0)
/ZZ
L
Operation
X
X
Sleep Mode
X
X
V
X
V
H
Standby/Idle
Read
H
H
L
H
No Change
Change
H
Page Mode Read
Random Read
/CE-Controlled Write
L
H
Change
V
V
V
V
X
H
L
V
H
↓
L
V
No Change
X
H
/WE-Controlled Write 2
Page Mode Write 3
Starts Precharge
↓
L
H
↓
X
H
↑
Notes:
1) H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
2) /WE-controlled write cycle begins as a Read cycle and A(17:2) is latched then.
3) Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.
4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
Byte Select Truth Table
/OE
H
/LB
X
H
H
L
/UB
X
H
L
Operation
Read; Outputs Disabled
X
L
Read; DQ(7:0) Hi-Z
Read; DQ(15:8) Hi-Z
Read
Write; Mask DQ(7:0)
Write; Mask DQ(15:8)
Write
H
L
L
X
H
L
L
H
L
L
The /UB and /LB pins may be grounded if 1) the system does not
perform byte writes and 2) the device is not configured as a 512Kx8.
Simplified Sleep/Standby State Diagram
Rev. 3.0
May 2010
Page 3 of 14
FM22L16 - 256Kx16 FRAM
Overview
The FM22L16 is a wordwide F-RAM memory
logically organized as 262,144 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(17:2) changes.
and /WE-controlled write cycles. In both cases, the
address A(17:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM22L16 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Memory Operation
Users access 262,144 memory locations, each with 16
data bits through a parallel interface. The F-RAM
array is organized as 8 blocks each having 8192 rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to F-RAM called NoDelayTM writes.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is tRC. Note that unlike SRAMs, the
FM22L16’s /CE-initiated access time is faster than
the address cycle time.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The F-RAM array is organized as 8 blocks each
having 8192 rows. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A(1:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins no later than tAAP, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
along with a new column address provides a page
mode write access.
The FM22L16 will drive the data bus when /OE and
at least one of the byte enables (/UB, /LB) is asserted
low. The upper data byte is driven when /UB is low,
and the lower data byte is driven when /LB is low. If
/OE is asserted after the memory access time has been
satisfied, the data bus will be driven with valid data.
If /OE is asserted prior to completion of the memory
access, the data bus will not be driven until valid data
is available. This feature minimizes supply current in
the system by eliminating transients caused by invalid
data being driven onto the bus. When /OE is
deasserted high, the data bus will remain in a high-Z
state.
Write Operation
Writes occur in the FM22L16 in the same time
interval as reads. The FM22L16 supports both /CE-
Rev. 3.0
May 2010
Page 4 of 14
FM22L16 - 256Kx16 FRAM
Precharge Operation
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time tPC.
Precharge is also activated by changing the upper
addess A(17:2). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the tAA address
access time. Refer to the Read Cycle Timing 1
diagram on page 10. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 12. The rate at which
random addresses can be issued is tRC and tWC
respectively.
,
Sleep Mode
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
The device incorporates a sleep mode of operation
which allows the user to achieve the lowest power
supply current condition. It enters a low power sleep
mode by asserting the /ZZ pin low. Read and write
operations must complete prior to the /ZZ pin going
low. Once /ZZ is low, all pins are ignored except the
/ZZ pin. When /ZZ is deasserted high, there is some
time delay (tZZEX) before the user can access the
device.
Write Protect Sectors – 32K x16 blocks
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
3FFFFh – 38000h
37FFFh – 30000h
2FFFFh – 28000h
27FFFh – 20000h
1FFFFh – 18000h
17FFFh – 10000h
0FFFFh – 08000h
07FFFh – 00000h
If Sleep Mode is not used, the /ZZ pin should be tied
to VDD
.
Software Write Protection
The 256Kx16 address space is divided into 8 sectors
(blocks) of 32Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
The write-protect read address sequence follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
24555h *
3AAAAh
02333h
1CCCCh
000FFh
3EF00h
3AAAAh
1CCCCh
0FF00h
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 24555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 1032 chance of randomly accessing
exactly the 1st six addresses. The odds are further
Rev. 3.0
May 2010
Page 5 of 14
FM22L16 - 256Kx16 FRAM
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
Figure 2. Write-Protect State Machine
For example, the following sequence write-protects addresses from 18000hto 27FFFh(sectors 3 & 4):
Address Data
Read 24555h
Read 3AAAAh
Read 02333h
Read 1CCCCh
Read 000FFh
Read 3EF00h
Write 3AAAAh
Write 1CCCCh
Write 0FF00h
Read 00000h
-
-
-
-
-
-
18h
E7h
-
; bits 3 & 4 = 1
; complement of 18h
; Data is don’t care
; return to Normal Operation
-
Rev. 3.0
May 2010
Page 6 of 14
FM22L16 - 256Kx16 FRAM
Software Write Protect Timing
For applications that require the lowest power
consumption, the /CE signal should be active only
during memory accesses. The FM22L16 draws
supply current while /CE is low, even if addresses and
control signals are static. While /CE is high, the
device draws no more than the maximum standby
current ISB.
SRAM Drop-In Replacement
The FM22L16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low indefinitely. While /CE
is low, the device automatically detects address
changes and a new access is begun. This functionality
allows /CE to be grounded as you might with an
SRAM. It also allows page mode operation at speeds
up to 40MHz. Note that if /CE is tied to ground,
the user must be sure /WE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur. Figure 3 shows a pullup resistor on /WE
which will keep the pin high during power cycles
assuming the MCU/MPU pin tri-states during the
reset condition. The pullup resistor value should
be chosen to ensure the /WE pin tracks VDD yet a
high enough value that the current drawn when
/WE is low is not an issue. A 10Kohm resistor
draws 330uA when /WE is low and VDD=3.3V.
The FM22L16 is backward compatible with the
1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM22L16 with /CE toggling
low on every address is perfectly acceptable.
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 512Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(18) may be
available from the system processor.
FM22L16
V
R
CE
MCU/
MPU
WE
OE
A(17:0)
DQ
Figure 4. FM22L16 Wired as 512Kx8
Figure 3. Use of Pullup Resistor on /WE
Rev. 3.0
May 2010
Page 7 of 14
FM22L16 - 256Kx16 FRAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
VDD
VIN
Description
Ratings
Power Supply Voltage with respect to VSS
Voltage on any signal pin with respect to VSS
-1.0V to +4.5V
-1.0V to +4.5V and
V
IN < VDD+1V
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
-55°C to +125°C
260° C
- Human Body Model (JEDEC Std JESD22-A114-D)
- Charged Device Model (JEDEC Std JESD22-C101-C)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
2.5kV
1.5kV
150V
MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
3.3
8
Max
3.6
Units
V
Notes
VDD
IDD
ISB
Power Supply
2.7
Power Supply Current
Standby Current
@ TA = 25°C
12
mA
1
2
90
-
150
270
µA
µA
@ TA = 85°C
IZZ
Sleep Mode Current
3
@ TA = 25°C
-
-
5
8
µA
µA
µA
µA
V
@ TA = 85°C
ILI
ILO
Input Leakage Current
4
4
1
Output Leakage Current
1
VIH
Input High Voltage
Input Low Voltage
Output High Voltage (IOH = -1.0 mA)
Output High Voltage (IOH = -100 µA)
Output Low Voltage (IOL = 2.1 mA)
Output Low Voltage (IOL = 100 µA)
2.2
-0.3
VDD + 0.3
0.6
VIL
V
VOH1
VOH2
VOL1
VOL2
Notes
2.4
V
VDD-0.2
V
0.4
0.2
V
V
1. VDD = 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.
2. VDD = 3.6V, /CE at VDD, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high.
3. VDD = 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or VDD-0.2V).
4. VIN, VOUT between VDD and VSS.
Rev. 3.0
May 2010
Page 8 of 14
FM22L16 - 256Kx16 FRAM
Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tRC
Read Cycle Time
110
-
tCE
Chip Enable Access Time
Address Access Time
55
110
-
tAA
tOH
tAAP
tOHP
tCA
tPC
-
Output Hold Time
20
-
Page Mode Address Access Time
Page Mode Output Hold Time
Chip Enable Active Time
Precharge Time
/UB, /LB Access Time
Address Setup Time (to /CE low)
Address Hold Time (/CE-controlled)
Output Enable Access Time
Chip Enable to Output High-Z
Output Enable High to Output High-Z
/UB, /LB High to Output High-Z
25
-
5
55
55
-
-
-
tBA
tAS
tAH
tOE
20
-
0
55
-
-
15
10
10
10
tHZ
-
ns
ns
ns
1
1
1
tOHZ
-
tBHZ
-
Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol Parameter
Min
110
55
55
55
25
16
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tWC
tCA
Write Cycle Time
-
-
Chip Enable Active Time
tCW
tPC
Chip Enable to Write Enable High
Precharge Time
-
-
tPWC
Page Mode Write Enable Cycle Time
Write Enable Pulse Width
Address Setup Time (to /CE low)
Page Mode Address Setup Time (to /WE low)
Page Mode Address Hold Time (to /WE low)
Write Enable Low to /CE High
/UB, /LB Low to /CE High
-
tWP
-
tAS
-
tASP
tAHP
tWLC
tBLC
tWLA
tAWH
tBS
8
-
15
25
25
25
110
2
-
-
-
Write Enable Low to A(17:2) Change
A(17:2) Change to Write Enable High
/UB, /LB Setup Time (to /CE low)
/UB, /LB Hold Time (to /CE high)
Data Input Setup Time
-
-
-
tBH
0
-
tDS
14
0
-
tDH
Data Input Hold Time
-
tWZ
Write Enable Low to Output High Z
Write Enable High to Output Driven
Write Enable to /CE Low Setup Time
Write Enable to /CE High Hold Time
-
10
-
1
1
2
2
tWX
tWS
10
0
-
-
tWH
Notes
0
1
2
This parameter is characterized but not 100% tested.
The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters tWS and tWH
are not tested.
Capacitance (TA = 25° C , f=1 MHz, VDD = 3.3V)
Symbol
Parameter
Input/Output Capacitance (DQ)
Input Capacitance
Min
Max
Units
pF
Notes
CI/O
CIN
CZZ
-
-
-
8
6
8
pF
Input Capacitance of /ZZ pin
pF
Rev. 3.0
May 2010
Page 9 of 14
FM22L16 - 256Kx16 FRAM
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tPU
Parameter
Min
Max
Units
µs
Notes
Power-Up (after VDD min. is reached) to First Access Time
Last Write (/WE high) to Power Down Time
VDD Rise Time
450
0
-
-
tPD
µs
tVR
tVF
tZZH
tWEZZ
tZZL
tZZEN
tZZEX
50
100
-
-
1,2
1,2
µs/V
µs/V
ns
VDD Fall Time
-
20
-
-
0
450
/ZZ Active to DQ Hi-Z Time
Last Write to Sleep Mode Entry Time
/ZZ Active Low Time
0
µs
1
µs
Sleep Mode Enter Time (/ZZ low to /CE don’t care)
-
µs
Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)
-
µs
Notes
1
2
Slope measured at any point on VDD waveform.
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Data Retention
Min
10
Units
Years
Notes
AC Test Conditions
Input Pulse Levels
0 to 3V
Input and Output Timing Levels
Output Load Capacitance
1.5V
30pF
Input Rise and Fall Times 3 ns
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
tCA
tPC
CE
tAH
tAS
A(17:0)
tOE
tHZ
tOHZ
OE
tCE
tOH
DQ(15:0)
UB / LB
tBA
tBHZ
Rev. 3.0
May 2010
Page 10 of 14
FM22L16 - 256Kx16 FRAM
Page Mode Read Cycle Timing
Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled) Note: /OE (not shown) is low only to show effect of /WE on DQ pins.
Write Cycle Timing 2 (/CE-Controlled)
Rev. 3.0
May 2010
Page 11 of 14
FM22L16 - 256Kx16 FRAM
Write Cycle Timing 3 (/CE low) Note: /OE (not shown) is low only to show effect of /WE on DQ pins.
Page Mode Write Cycle Timing
Although sequential column addressing is shown, it is not required.
Power Cycle and Sleep Mode Enter/Exit Timing
Rev. 3.0
May 2010
Page 12 of 14
FM22L16 - 256Kx16 FRAM
Mechanical Drawing
44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC)
Recommended PCB Footprint
Pin 1
0.45
0.30
18.41
BASIC
0.8
0.5
0.80
BSC
1.50
10.16 BSC
11.96
11.56
12.6
1.20 max
0.20
0.12
0°-8°
0.10 mm
0.6
0.4
0.15
0.05
Note: All dimensions in millimeters.
TSOP-II Package Marking Scheme
Legend:
RAMTRON
XXXXXX= part number, S= speed, P=package
XXXXXXX-S-P
RLLLLLLLL
YYWW
R=rev code, LLLLLLL= lot code, YY=year, WW=work week
Example: FM22L16, 55ns access time, “Green”/RoHS TSOP-II package,
Rev C, Lot 9619110TG, Year 2010, Work Week 19
RAMTRON
FM22L16-55-TG
C9619110TG
1019
Rev. 3.0
May 2010
Page 13 of 14
FM22L16 - 256Kx16 FRAM
Revision History
Revision
1.0
Date
3/9/2007
9/25/2007
Summary
Initial release.
1.1
Added text and drawing to SRAM Drop-in Replacement section. Changed ISB
and IZZ specs. Changed tAAP, tBA, tOE, tPWC timing parameter limits. Changed
t
PU timing parameter and added others to Power Cycle Timing table. Added
pcb footprint and marking scheme to Mechanical Drawing page.
Added ESD and package MSL ratings.
1.2
2.0
12/12/2007
12/22/2009
Changed status to Pre-Production. Lowered IDD limit. Added UB/LB signals
to timing diagrams and added timing parameters to AC table. Expanded
explanation of precharge operation. Updated lead temperature rating in Abs
Max table. Removed VTP spec. Added tape & reel ordering information.
Changed to Production status. Updated package marking scheme.
3.0
5/25/2010
Rev. 3.0
May 2010
Page 14 of 14
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