概述
规格参数
数据手册
替代型号FM25CL64B-G 概述
64Kb Serial 3V F-RAM Memory 64Kb的串行3V F-RAM存储器 存储芯片 其他内存集成电路
FM25CL64B-G 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP8,.25 | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.71 | 风险等级： | 0.8 |
| Samacsys Confidence： | 3 | Samacsys Status： | Released |
| Samacsys PartID： | 306444 | Samacsys Pin Count： | 8 |
| Samacsys Part Category： | Integrated Circuit | Samacsys Package Category： | Small Outline Packages |
| Samacsys Footprint Name： | SOIC 8 | Samacsys Released Date： | 2017-02-23 05:27:28 |
| Is Samacsys： | N | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e3 | 长度： | 4.9 mm |
| 内存密度： | 65536 bit | 内存集成电路类型： | MEMORY CIRCUIT |
| 内存宽度： | 8 | 湿度敏感等级： | 3 |
| 功能数量： | 1 | 端子数量： | 8 |
| 字数： | 8192 words | 字数代码： | 8000 |
| 工作模式： | SYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 8KX8 |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP8,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3.3 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 最大待机电流： | 0.000006 A |
| 子类别： | SRAMs | 最大压摆率： | 0.003 mA |
| 最大供电电压 (Vsup)： | 3.65 V | 最小供电电压 (Vsup)： | 2.7 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Matte Tin (Sn) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 3.9 mm |
| Base Number Matches： | 1 |
FM25CL64B-G 数据手册
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PDF下载FM25CL64B
64Kb Serial 3V F-RAM Memory
Features
Sophisticated Write Protection Scheme
Hardware Protection
64K bit Ferroelectric Nonvolatile RAM
Organized as 8,192 x 8 bits
Software Protection
High Endurance 100 Trillion (1014) Read/Writes
38 Year Data Retention (@ +75ºC)
NoDelay™ Writes
Low Power Consumption
Low Voltage Operation 2.7-3.65V
200 A Active Current (1 MHz)
3 A (typ.) Standby Current
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 20 MHz Frequency
Industry Standard Configuration
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Industrial Temperature -40 C to +85 C
8-pin “Green”/RoHS SOIC and TDFN Packages
Description
Pin Configuration
The FM25CL64B is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
1
2
3
4
8
7
6
5
CS
SO
VDD
HOLD
SCK
SI
WP
VSS
Top View
The FM25CL64B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after each byte has
been successfully transferred to the device. The next
bus cycle may commence immediately without the
need for data polling. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM25CL64B is capable
of supporting 1014 read/write cycles, or 100 million
times more write cycles than EEPROM.
1
2
3
4
8
7
6
5
VDD
/CS
SO
/HOLD
SCK
SI
/WP
VSS
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
These capabilities make the FM25CL64B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
Ordering Information
FM25CL64B-G
FM25CL64B-GTR
The FM25CL64B provides substantial benefits to
users of serial EEPROM as a hardware drop-in
replacement. The FM25CL64B uses the high-speed
SPI bus, which enhances the high-speed write
“Green” 8-pin SOIC
“Green” 8-pin SOIC,
Tape & Reel
FM25CL64B-DG
FM25CL64B-DGTR
“Green”/RoHS 8-pin TDFN
“Green”/RoHS 8-pin TDFN,
Tape & Reel
capability
of
F-RAM
technology.
Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s
internal qualification testing and has reached production status.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 001-84477 Rev. *B
Revised May 29, 2013
FM25CL64B - 64Kb 3V SPI F-RAM
WP
CS
Instruction Decode
Clock Generator
Control Logic
HOLD
SCK
Write Protect
1,024 x 64
FRAM Array
Instruction Register
13
8
Address Register
Counter
SI
SO
Data I/O Register
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
I/O
Description
/CS
Input
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK
Input
Input
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
/HOLD
/WP
SI
Input
Input
Write Protect: This active low pin prevents write operations to the Status Register.
This is critical since other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided on pages 6 & 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
SO
Output
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
VDD
VSS
Supply
Supply
Power Supply (2.7V to 3.65V)
Ground
Document Number: 001-84477 Rev. *B
Page 2 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
high performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25CL64B operates in SPI Mode 0 and 3.
Overview
The FM25CL64B is a serial F-RAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major difference between the FM25CL64B and a
serial EEPROM with the same pinout is the F-
RAM‟s superior write performance.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25CL64B devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25CL64B device.
Memory Architecture
When accessing the FM25CL64B, the user addresses
8,192 locations of 8 data bits each. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code, and
a two-byte address. The upper 3 bits of the address
range are „don‟t care‟ values. The complete address
of 13-bits specifies each byte address uniquely.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins (SI, SO) together and tie
off (high) the /HOLD pin. Figure 3 shows a
configuration that uses only three pins.
Most functions of the FM25CL64B either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25CL64B will begin
monitoring the clock and data lines. The relationship
between the falling edge of /CS, the clock and data is
dictated by the SPI mode. The device will make a
determination of the SPI mode on the falling edge of
each chip select. While there are four such modes, the
FM25CL64B supports Modes 0 and 3. Figure 4
shows the required signal relationships for Modes 0
and 3. For both modes, data is clocked into the
FM25CL64B on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock begins from a high state, it will
fall prior to beginning data transfer in order to create
the first rising edge.
Users expect several obvious system benefits from
the FM25CL64B due to its fast write cycle and high
endurance as compared with EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Note: The FM25CL64B contains no power
management circuits other than a simple internal
power-on reset circuit. It is the user’s
responsibility to ensure that VDD is within
datasheet tolerances to prevent incorrect
operation. It is recommended that the part is not
powered down with chip enable active.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
Serial Peripheral Interface – SPI Bus
The FM25CL64B employs
a Serial Peripheral
Interface (SPI) bus. It is specified to operate at speeds
up to 20 MHz. This high-speed serial bus provides
Document Number: 001-84477 Rev. *B
Page 3 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
SCK
MOSI
MISO
SO SI
FM25CL64B
CS HOLD
SCK
SO SI SCK
FM25CL64B
CS HOLD
SPI
Microcontroller
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0
P1.1
SO SI SCK
FM25CL64B
Microcontroller
CS
HOLD
P1.2
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Document Number: 001-84477 Rev. *B
Page 4 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
WREN - Set Write Enable Latch
Data Transfer
All data transfers to and from the FM25CL64B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
The FM25CL64B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Command Structure
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit – only
the WREN op-code can set this bit. The WEL bit will
be automatically cleared on the rising edge of /S
following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or
the F-RAM array without another WREN command.
Figure 5 below illustrates the WREN command bus
configuration.
There are six commands called op-codes that can be
issued by the bus master to the FM25CL64B. They
are listed in the table below. These op-codes control
the functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
WRDI - Write Disable
Table 1. Op-code Commands
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
Status Register and verifying that WEL=0. Figure 6
illustrates the WRDI command bus configuration.
Name
Description
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Op-code
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
WREN
WRDI
RDSR
WRSR
READ
WRITE
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Document Number: 001-84477 Rev. *B
Page 5 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
WRSR – Write Status Register
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25CL64B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in a later section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25CL64B, /WP only prevents writing
to the Status Register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration (WREN not shown)
never busy. The WPEN, BP1 and BP0 control write
Status Register & Write Protection
protection features. They are nonvolatile (shaded
yellow). The WEL flag indicates the state of the
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
The write protection features of the FM25CL64B are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /WP
pin. The Status Register is organized as follows.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 2. Status Register
Bit
7
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
Table 3. Block Memory Write Protection
Name WPEN
WEL
BP1
BP0 Protected Address Range
0
0
1
1
0
1
0
1
None
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit (“Ready” in EEPROMs) is
unnecessary as the F-RAM writes in real-time and is
1800h to 1FFFh (upper ¼)
1000h to 1FFFh (upper ½)
0000h to 1FFFh (all)
0
Document Number: 001-84477 Rev. *B
Page 6 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and /WP is
set to 0. This occurs because the block protect bits
prevent writing memory and the /WP signal in
hardware prevents altering the block protect bits (if
WPEN is high). Therefore in this condition, hardware
must be involved in allowing a write operation. The
following table summarizes the write protection
conditions.
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the Status Register. Thus the Status
Register is write protected if WPEN=1 and /WP=0.
Table 4. Write Protection
WEL
WPEN
/WP
X
X
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
0
1
1
1
X
0
1
1
Unprotected
(after the 8th clock). This allows any number of bytes
to be written without page buffer delays.
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike SPI-bus
EEPROMs, the FM25CL64B can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following the READ command is
a two-byte address value. The upper 3-bits of the
address are ignored. In total, the 13-bits specify the
address of the first byte of the read operation. This is
the starting address of the first byte of the read
operation. After the op-code and address are issued,
the device drives out the read data on the next 8
clocks. The SI input is ignored during read data
bytes. Subsequent bytes are data bytes, which are
read out sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks and /CS is low. If the last address of 1FFFh is
reached, the counter will roll over to 0000h. Data is
read MSB first. The rising edge of /CS terminates a
READ operation. A read operation is shown in
Figure 10.
Write Operation
All writes to the memory begin with a WREN op-
code with /CS being asserted and deasserted. The
next op-code is WRITE. The WRITE op-code is
followed by a two-byte address value. The upper 3-
bits of the address are ignored. In total, the 13-bits
specify the address of the first data byte of the write
operation. This is the starting address of the first data
byte of the write operation. Subsequent bytes are data
bytes, which are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks and keeps /CS low. If the
last address of 1FFFh is reached, the counter will roll
over to 0000h. Data is written MSB first. The rising
edge of /CS terminates a WRITE operation. A write
operation is shown in Figure 9.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
EEPROMs use page buffers to increase their write
throughput. This compensates for the technology‟s
inherently slow write operations. F-RAM memories
do not have page buffers because each byte is written
to the F-RAM array immediately after it is clocked in
Document Number: 001-84477 Rev. *B
Page 7 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
op-code
13-bit Address
12 11 10
Data
X
X
X
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
0
0
0
0
0
0
1
0
MSB
LSB MSB
LSB
SO
Figure 9. Memory Write (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
op-code
13-bit Address
12 11 10
X
X
X
4
3
2
1
0
0
0
0
0
0
0
1
1
MSB
LSB MSB
7
LSB
0
Data
SO
6
5
4
3
2
1
Figure 10. Memory Read
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Endurance
The FM25CL64B devices are capable of being
accessed at least 1014 times, reads or writes. An F-
RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A12-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 1K rows of
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq Endurance Endurance Years to Reach
(MHz) Cycles/sec. Limit
Cycles/year
20
10
5
37,310
18,660
9,330
1.18 x 1012
5.88 x 1011
2.94 x 1011
85.1
170.2
340.3
Document Number: 001-84477 Rev. *B
Page 8 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
VDD
VIN
Description
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55 C to + 125 C
260 C
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
4kV
1.25kV
300V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units
Notes
VDD
IDD
Power Supply Voltage
2.7
3.3
3.65
V
VDD Supply Current
@ SCK = 1.0 MHz
@ SCK = 20.0 MHz
Standby Current
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output High Voltage
@ IOH = -2 mA
1
-
-
3
0.2
3.0
6
mA
mA
A
A
A
V
V
V
ISB
ILI
ILO
VIH
VIL
VOH
-
-
-
2
3
3
1
1
VDD + 0.3
0.3 VDD
-
0.7 VDD
-0.3
VDD – 0.8
VOL
Output Low Voltage
@ IOL = 2 mA
Input Hysteresis
-
0.4
-
V
V
VHYS
0.05 VDD
4
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD
3. VSS VIN VDD and VSS VOUT VDD
.
.
4. Characterized but not 100% tested in production. Applies only to /CS and SCK pins.
Document Number: 001-84477 Rev. *B
Page 9 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
AC Parameters (TA = -40 C to + 85 C, CL = 30pF, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol
fCK
tCH
Parameter
Min
0
22
22
10
10
Max
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Notes
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
1
1
tCL
tCSU
tCSH
tOD
tODV
tOH
tD
20
20
2
0
60
ns
tR
tF
tSU
tH
Data In Rise Time
Data In Fall Time
Data Setup Time
50
50
ns
ns
ns
ns
2,3
2,3
5
5
Data Hold Time
tHS
tHH
tHZ
/HOLD Setup Time
/HOLD Hold Time
/HOLD Low to Hi-Z
/HOLD High to Data Active
10
10
ns
ns
ns
ns
20
20
2
2
tLZ
Notes
1. tCH + tCL = 1/fCK
.
2. Characterized but not 100% tested in production.
3. Rise and fall times measured between 10% and 90% of waveform.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V)
Symbol Parameter
Min
-
-
Max
8
6
Units
pF
pF
Notes
1
1
CO
CI
Output Capacitance (SO)
Input Capacitance
Notes
1. This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
10% and 90% of VDD
Input rise and fall times
Input and output timing levels
Output Load Capacitance
5 ns
0.5 VDD
30 pF
Data Retention
Symbol
TDR
Parameter
@ +85ºC
@ +80ºC
@ +75ºC
Min
10
19
Max
Units
Notes
-
-
-
Years
Years
Years
38
Document Number: 001-84477 Rev. *B
Page 10 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Serial Data Bus Timing
tD
CS
tCL
tCH
tF
tR
tCSH
tCSU
1/tCK
SCK
tH
tSU
SI
tOH
tOD
tODV
SO
/Hold Timing
Power Cycle Timing
VDD min
VDD
CS
tVF
tVR
tPD
tPU
Power Cycle Timing (TA = -40 C to + 85 C, VDD = 2.7V to 3.65V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
Parameter
VDD(min) to First Access Start
Last Access Complete to VDD(min)
VDD Rise Time
Min
1
0
30
30
Max
Units
ms
s
s/V
s/V
Notes
-
-
-
-
1
1
VDD Fall Time
Notes
1. Slope measured at any point on VDD waveform.
Document Number: 001-84477 Rev. *B
Page 11 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.70
3.90 ±0.10 6.00 ±0.20
2.00
Pin 1
0.65
1.27
0.25
0.50
4.90 ±0.10
1.35
1.75
0.19
0.25
45
0.10 mm
1.27
0.10
0.25
0 - 8
0.40
1.27
0.33
0.51
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXXXXXX-P
R LLLLLZ
RICYYWW
XXXXXXXXX = part number, P = package type
R = rev code, LLLLL = lot code, Z = Package code
RIC = Ramtron Int‟l Corp, YY = year, WW = work week
= Pb-free
Example:
FM25CL64B, “Green”/RoHS SOIC
Rev. A, Lot 67989, SOIC
Year 2013, Work Week 07
Pb-free
FM25CL64B-G
A 67989S
RIC1307
Document Number: 001-84477 Rev. *B
Page 12 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch)
Exposed metal pad
should be left floating.
4.50 ±0.1
3.60 ±0.10
Pin 1 ID
Pin 1
0.30 ±0.1
2.85 REF
0.0 - 0.05
0.75 ±0.05
0.20 REF.
Recommended PCB Footprint
0.95
0.40 ±0.05
4.30
0.60
0.45
0.95
Note: All dimensions in millimeters. The exposed pad should be left floating.
TDFN Package Marking Scheme for Body Size 4.0mm x 4.5mm
Legend:
R=Ramtron, G=”green” TDFN package, XXXX=base part number
LLLL= lot code
YY=year, WW=work week
RGXXXX
LLLL
YYWW
Example: “Green”/RoHS TDFN package, FM25L64B, Lot 0003,
Year 2011, Work Week 07
R5L64B
0003
1107
Document Number: 001-84477 Rev. *B
Page 13 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Revision History
Revision
Date
Summary
1.0
1.1
1.2
11/15/2010
12/15/2010
2/15/2011
Initial Release
Added 4x4.5mm DFN package. Fixed endurance section on pg 8.
Added ESD ratings. Updated DFN package marking. Changed tPU and tVF
timing parameters.
3.0
1/6/2012
Changed to Production status. Changed tVF spec.
Document Number: 001-84477 Rev. *B
Page 14 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Appendix A - Errata for FM25CL64B
Errata Number
Date
001
March 10, 2011 (Updated Jan. 2012)
FM25CL64B
Product
Recent testing has uncovered a problem with the FM25CL64B at cold temperatures.
These parts meet the current datasheet specifications with the following exceptions:
1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum
VDD Fall Time (tVF) of 200µs/V.
There is a design change in process to improve the cold temperature performance. An update will be
issued when the design change has been verified.
UPDATE: Ramtron has implemented a cold test (-40C) such that all devices comply with the datasheet
specifications without exception over the full industrial temperature range -40C to +85C. Therefore the
above errata no longer applies. The starting date code for errata-free devices is 1148. (YY=11, WW=48)
Document Number: 001-84477 Rev. *B
Page 15 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Document History
Document Title: FM25CL64B 64Kb Serial 3V F-RAM Memory
Document Number: 001-84477
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3902952
3924523
4014247
GVCH
GVCH
GVCH
02/25/2013
03/07/2013
05/29/2013
New Spec
*A
*B
Changed tPU spec value from 10ms to 1ms
Updated SOIC package marking scheme
Added Appendix A - Errata for FM25CL64B
Document Number: 001-84477 Rev. *B
Page 16 of 17
FM25CL64B - 64Kb 3V SPI F-RAM
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors.
To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC® Solutions
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psoc.cypress.com/solutions
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Clocks & Buffers
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Cypress Developer Community
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cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
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Community | Forums | Blogs | Video | Training
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Technical Support
Touch Sensing
USB Controllers
cypress.com/go/support
RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress
Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor
does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life
support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore,
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably
be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the
manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to
worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby
grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the
Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product
to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification,
translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission
of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume
any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the
user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in
doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-84477 Rev. *B
Page 17 of 17
FM25CL64B-G CAD模型
引脚图
封装焊盘图
FM25CL64B-G 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| FM24CL64B-G | RAMTRON | Memory Circuit, 8KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8 | 完全替代 |
|
| FM25640B-G | CYPRESS | 64Kb Serial 5V F-RAM Memory | 类似代替 |
|
FM25CL64B-G 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| FM25CL64B-GA | CYPRESS | Automotive Temp. 64Kb Serial 3V F-RAM Memory | 获取价格 |
|
| FM25CL64B-GATR | CYPRESS | Automotive Temp. 64Kb Serial 3V F-RAM Memory | 获取价格 |
|
| FM25CL64B-GTR | RAMTRON | 64Kb Serial 3V F-RAM Memory | 获取价格 |
|
| FM25CL64B-GTR | CYPRESS | 64Kb Serial 3V F-RAM Memory | 获取价格 |
|
| FM25CL64B-GTR | INFINEON | 铁电存储器 (F-RAM) | 获取价格 |
|
| FM25CL64B_13 | CYPRESS | 64Kb Serial 3V F-RAM Memory | 获取价格 |
|
| FM25CL64_07 | RAMTRON | 64Kb FRAM Serial 3V Memory | 获取价格 |
|
| FM25F005 | FM | SPI NOR Flash | 获取价格 |
|
| FM25F01 | FM | SPI NOR Flash | 获取价格 |
|
| FM25G01B | FM | SPI NAND Flash | 获取价格 |
|
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