GVT71256ZB36-7.5I [CYPRESS]
ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | GVT71256ZB36-7.5I |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总31页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1357A
CY7C1355A
256K x 36/512K x 18 Synchronous Flow-Thru
SRAM with NoBL™ Architecture
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (WEN). BWc and BWd apply
to CY7C1355A/GVT71256ZB36 only.
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 133, 117, and 100 MHz
• Fast OE access time: 6.5, 7.0, 7.5, and 8.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data
occurs, either read or write.
A
Clock Enable (CEN) pin allows operation of the
CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
• 3.3V –5% and +5% power supply
• 3.3V or 2.5V I/O supply
• Single WEN (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Automatic Power-down fearture available using ZZ
mode or CE deselect.
There are three Chip Enable pins (CE, CE2, CE3) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in
high-impedance state one cycle after chip is deselected or a
write cycle is initiated.
The
CY7C1355A/GVT71256ZB36
and
CY7C1357A/
GVT71512ZB18 have an on-chip 2-bit burst counter. In the
burst mode, the CY7C1355A/GVT71256ZB36 and
CY7C1357A/GVT71512ZB18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
• JTAG boundary scan
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The
CY7C1355A/GVT71256ZB36
and
CY7C1357A/
GVT71512ZB18 SRAMs are designed to eliminate dead
cycles when transitions from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization
and achieves Zero Bus Latency (ZBL). They integrate 262,144
× 36 and 524,288 × 18 SRAM cells, respectively, with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. These employ high-speed, low
power CMOS designs using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell consists of
Six transistors.
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Selection Guide
7C1355A-133
71256ZB36-6.5
7C1357A-133
71512ZB18-6.5
7C1355A-117
71256ZB36-7
7C1357A-117
71512ZB18-7
7C1355A-100
71256ZB36-7.5
7C1357A-100
71512ZB18-7.5
7C1355A1-100
71256ZB36-8
7C1357A1-100
71512ZB18-8
Unit
ns
Maximum Access Time
6.5
410
30
7
7.5
350
30
8
Maximum Operating Current
Maximum CMOS Standby Current
385
30
350
30
mA
mA
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05265 Rev. **
Revised July 11, 2002
CY7C1357A
CY7C1355A
Functional Block Diagram 256Kx36[1]
ZZ
MODE
Address
Control
CEN
ADV/LD
WE
WEN
BWa, BWb
BWc, BWd
Input
Registers
CE1, CE2,CE3
A0, A1, A
Control Logic
Sel
Mux
CLK
OE
Output Buffers
DQa-DQd
Functional Block Diagram 512Kx18[1]
ZZ
MODE
Address
Control
CEN
ADV/LD
WEN
BWa, BWb
Input
Registers
CE1, CE2,CE3
A0, A1, A
Control Logic
Sel
Mux
CLK
OE
Output Buffers
DQa, DQb
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05265 Rev. **
Page 2 of 31
CY7C1357A
CY7C1355A
Pin Configurations
100-pin TQFP Packages
256Kx36—CY7C1355A/GVT71256ZB36
512Kx18—CY7C1357A/GVT71512ZB18
Top View
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
VSS
VCC
VCC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
VSS
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
A
NC
NC
VCCQ
VSS
NC
2
2
3
3
4
4
5
5
6
6
7
7
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
VSS
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
8
8
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
VCC
VCC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
100-pin TQFP
NC
VSS
VCCQ
NC
NC
NC
VSS
VCCQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-05265 Rev. **
Page 3 of 31
CY7C1357A
CY7C1355A
Pin Configurations (continued)
119-ball Bump BGA
256Kx36—CY7C1355A/GVT71256ZB36
Top View
1
2
3
A
4
NC
5
6
7
A
B
C
D
E
F
VCCQ
A
A
A
VCCQ
NC
NC
NC
CE2
A
A
ADV/LD
VCC
NC
A
CE3
A
A
A
NC
DQc
DQc
VCCQ
DQc
DQc
VCCQ
DQd
DQd
VCCQ
DQd
DQd
NC
DQc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
VSS
A
DQb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQa
A
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
CE1
OE
G
H
J
A
WEN
VCC
CLK
NC
K
L
VSS
BWd
VSS
VSS
VSS
MODE
A
M
N
P
R
T
CEN
A1
A0
VCC
A
NC
NC
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
512Kx18—CY7C1357A/GVT71512ZB18
Top View
1
2
3
A
4
NC
5
6
7
A
B
C
D
E
F
VCCQ
NC
A
A
A
VCCQ
NC
CE2
A
A
ADV/LD
VCC
NC
A
CE3
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VCC
DQb
NC
DQb
NC
DQb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQa
NC
DQa
NC
DQa
VCC
NC
DQa
NC
DQa
NC
A
NC
CE1
OE
DQa
VCCQ
DQa
NC
VCCQ
NC
G
H
J
A
DQb
VCCQ
NC
WEN
VCC
CLK
NC
VCCQ
DQa
NC
K
L
DQb
VCCQ
DQb
NC
M
N
P
R
T
CEN
A1
VCCQ
NC
A0
DQa
NC
NC
VCC
NC
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05265 Rev. **
Page 4 of 31
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A/GVT71256ZB36)
256K × 36
256K × 36
TQFP Pins
PBGA Pins
Name
Type
Description
Synchronous Address Inputs: The address register is triggered by
37,
36,
4P
4N
A0,
A1,
A
Input-
Synchronous a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW
and true chip enables. A0 and A1 are the two least significant bits of
the address field and set the internal burst counter if burst cycle is
initiated.
32, 33, 34, 35, 2A, 3A, 5A, 6A,
44, 45, 46, 47, 3B, 5B, 2C, 3C,
48, 49, 50, 81, 5C, 6C, 4G, 2R,
82, 83, 99, 100 6R, 3T, 4T, 5T
93,
94,
95,
96
5L
5G
3G
3L
BWa,
Input-
Synchronous Byte Write Enables: Each nine-bit byte has its own
BWb, Synchronous active LOW byte write enable. On load write cycles (when WEN and
BWc,
BWd
ADV/LD are sampled LOW), the appropriate byte write signal (BWx)
must be valid. The byte write signal must also be valid on each cycle
of a burst write. Byte write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device one
cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW
if always doing a write to the entire 36-bit word.
87
88
4M
4H
CEN
Input-
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
WEN
CLK
Input-
Read Write: WEN signal is a synchronous input that identifies
Synchronous whether the current loaded cycle and the subsequent burst cycles
initiated by ADV/LD is a Read or Write operation. The data bus activity
for the current cycle takes place one clock cycle later.
89
4K
Input-
Clock
Clock: This is the clock input to CY7C1355A/GVT71256ZB36.
Except for OE, ZZ, and MODE, all timing references for the device
are made with respect to the rising edge of CLK.
98, 92
4E, 6B
CE1,
CE3
Input-
SynchronousActiveLOWChipEnable:CE1 andCE3 areusedwith
Synchronous CE2 to enable the CY7C1355A/GVT71256ZB36. CE1 or CE3
sampled HIGH or CE2 sampled LOW, along with ADV/LD LOW at the
rising edge of clock, initiates a deselect cycle. The data bus will be
High-Z one clock cycle after chip deselect is initiated.
97
86
2B
4F
CE2
OE
Input-
Synchronous Active High Chip Enable: CE2 is used with CE1 and
Synchronous CE3 to enable the chip. CE2 has inverted polarity but otherwise is
identical to CE1 and CE3.
Input
Asynchronous Output Enable: OE must be LOW to read data.
Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE does
not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied LOW.
85
4B
ADV/
LD
Input-
Advance/Load: ADV/LD is a synchronous input that is used to load
Synchronous the internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected.
When ADV/LD is sampled HIGH, then the internal burst counter is
advanced for any burst that was in progress. The external addresses
and WEN are ignored when ADV/LD is sampled HIGH.
31
64
3R
7T
MODE
ZZ
Input-
Static
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
Input-
Sleep Enable: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to
be either LOW or NC.
Document #: 38-05265 Rev. **
Page 5 of 31
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A/GVT71256ZB36) (continued)
256K × 36
TQFP Pins
256K × 36
PBGA Pins
Name
Type
Description
51, 52, 53,
56–59, 62, 63 6N, 6M, 6L, 7L, DQb
(a) 6P, 7P, 7N, DQa
Input/
Output
Data Inputs/Outputs: Both the data input path and data output path
are registered and triggered by the rising edge of CLK. Byte “a” is
68, 69, 72–75,
78, 79, 80
6K, 7K,
(b) 7H, 6H, 7G, DQd
DQc Synchronous DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd
pins.
1, 2, 3, 6–9, 12, 6G, 6F, 6E, 7E,
13 7D, 6D,
18, 19, 22–25, (c) 2D, 1D, 1E,
28, 29, 30
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
38
39
43
2U
3U
4U
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or
be connected to VCC.
42
5U
TDO
Output
Power
IEEE 1149.1 test output: LVTTL-level output. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No Connect).
15, 16, 41, 65, 4C, 2J, 4J, 6J, VCC
91 4R
Supply
Power Supply: +3.3V –5% and +5%.
Ground: GND.
5, 10, 14, 17, 3D, 5D, 3E, 5E, VSS
21, 26, 40, 55, 3F, 5F, 3H, 5H,
60, 66, 67, 71, 3K,5K,3M,5M,
Ground
76, 90
3N, 5N, 3P, 5P,
5R
4,11,20,27,54, 1A, 7A, 1F, 7F, VCCQ
I/O Power Power Supply for the I/O circuitry.
Supply
61, 70, 77
1J, 7J, 1M, 7M,
1U, 7U
84
4A, 1B, 7B, 1C,
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
NC
–
No Connect: These signals are not internally connected. It can be
left floating or be connected to VCC or to GND.
Pin Descriptions (CY7C1357A/GVT71512ZB18)
512K × 18
TQFP Pins
512K × 18
PBGA Pins
Name
Type
Description
37,
36,
4P
4N
A0,
A1,
A
Input-
Synchronous Address Inputs: The address register is
Synchronous triggered by a combination of the rising edge of CLK, ADV/LD
LOW, CEN LOW and true chip enables. A0 and A1 are the two
least significant bits of the address field and set the internal burst
counter if burst cycle is initiated.
32, 33, 34, 35, 2A, 3A, 5A, 6A,
44, 45, 46, 47, 3B, 5B, 6B, 2C,
48, 49, 50, 80, 3C, 5C, 6C, 4G,
81, 82, 83, 99, 2R, 6R, 2T, 3T,
100
5T, 6T
93,
94,
5L
3G
BWa,
BWb
Input-
Synchronous Byte Write Enables: Each nine-bit byte has its
Synchronous own active low byte write enable. On load write cycles (when
WEN and ADV/LD are sampled LOW), the appropriate byte write
signal (BWx) must be valid. The byte write signal must also be
valid on each cycle of a burst write. Byte write signals are ignored
when WEN is sampled HIGH. The appropriate byte(s) of data are
written into the device one cycle later. BWa controls DQa pins;
BWb controls DQb pins. BWx can all be tied LOW if always doing
write to the entire 18-bit word.
Document #: 38-05265 Rev. **
Page 6 of 31
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1357A/GVT71512ZB18) (continued)
512K × 18
512K × 18
TQFP Pins
PBGA Pins
Name
Type
Description
Synchronous Clock Enable Input: When CEN is sampled
87
4M
CEN
Input-
Synchronous HIGH, all other synchronous inputs, including clock are ignored
and outputs remain unchanged. The effect of CEN sampled
HIGH on the device outputs is as if the LOW-to-HIGH clock
transition did not occur. For normal operation, CEN must be
sampled LOW at rising edge of clock.
88
89
4H
WEN
CLK
Input-
Read Write: WEN signal is a synchronous input that identifies
Synchronous whether the current loaded cycle and the subsequent burst
cycles initiated by ADV/LD is a Read or Write operation. The data
bus activity for the current cycle takes place one clock cycle later.
4K
Input-
Clock
Clock: This is the clock input to CY7C1357A/GVT71512ZB18.
Except for OE, ZZ and MODE, all timing references for the device
are made with respect to the rising edge of CLK.
98,
92
4E, 6B
CE1,
CE3
Input-
Synchronous Active Low Chip Enable: CE1 and CE3 are used
Synchronous with CE2 to enable the CY7C1357A/GVT71512ZB18. CE1 or
CE3 sampled HIGH or CE2 sampled LOW, along with ADV/LD
LOW at the rising edge of clock, initiates a deselect cycle. The
data bus will be High-Z one clock cycle after chip deselect is
initiated.
97
86
2B
4F
CE2
OE
Input-
Synchronous Active High Chip Enable: CE2 is used with CE1
Synchronous and CE3 to enable the chip. CE2 has inverted polarity but
otherwise is identical to CE1 and CE3.
Input-
Asynchronous Output Enable: OE must be LOW to read data.
Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE
does not need to be actively controlled for read and write cycles.
In normal operation, OE can be tied LOW.
85
4B
ADV/
LD
Input-
Advance/Load: ADV/LD is a synchronous input that is used to
Synchronous load the internal registers with new address and control signals
when it is sampled LOW at the rising edge of clock with the chip
is selected. When ADV/LD is sampled HIGH, then the internal
burst counter is advanced for any burst that was in progress. The
external addresses and WEN are ignored when ADV/LD is
sampled HIGH.
31
64
3R
7T
MODE
ZZ
Input
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
Input
Sleep Enable: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal operation, this
input has to be either LOW or NC.
58, 59, 62, 63, (a) 6D, 7E, 6F,
68, 69, 72, 73, 7G, 6H, 7K, 6L,
DQa
DQb
Input/
Output-
Data Inputs/Outputs: Both the data input path and data output
path are registered and triggered by the rising edge of CLK. Byte
74
6N, 7P
Synchronous “a” is DQa pins; Byte “b” is DQb pins.
8, 9, 12, 13, 18, (b) 1D, 2E, 2G,
19, 22, 23, 24 1H, 2K, 1L, 2M,
1N, 2P
38
39
43
2U
3U
4U
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs: LVTTL-level inputs. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect) or be connected to VCC
.
42
5U
TDO
Output Power IEEE 1149.1 test output: LVTTL-level output. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect).
15, 16, 41, 65, 4C, 2J, 4J, 6J,
91 4R
VCC
Supply
Power Supply: +3.3V –5% and +5%.
Document #: 38-05265 Rev. **
Page 7 of 31
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1357A/GVT71512ZB18) (continued)
512K × 18
TQFP Pins
512K × 18
PBGA Pins
Name
Type
Description
5, 10, 14, 17, 21, 3D, 5D, 3E, 5E,
26, 40, 55, 60, 3F, 5F, 5G, 3H,
66, 67, 71, 76, 5H, 3K, 5K, 3L,
VSS
Ground
Ground: GND.
90
3M, 5M, 3N, 5N,
3P, 5P
4, 11, 20, 27, 54, 1A, 7A, 1F, 7F,
VCCQ
I/O Power
Supply
Power supply for the I/O circuitry.
61, 70, 77
1J, 7J, 1M, 7M,
1U, 7U
1-3, 6, 7, 25, 4A, 1B, 7B, 1C,
28-30, 7C, 2D, 4D, 7D,
NC
–
No Connect: These signals are not internally connected. It can
be left floating or be connected to VCC or to GND.
51-53, 56, 57, 1E, 6E, 2F, 1G,
75, 78, 79, 84, 6G, 2H, 7H, 3J,
95, 96
5J, 1K, 6K, 2L,
4L, 7L, 6M, 2N,
7N, 1P, 6P, 1R,
7R, 1T, 4T, 6U
Partial Truth Table for Read/Write[2]
Function
WEN
BWa
X
BWb
X
BWc[4]
BWd[4]
Read
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
H
H
L
No Write
H
H
Write Byte a (DQa)[3]
Write Byte b (DQb)[3]
Write Byte c (DQc)[3]
Write Byte d (DQd}[3]
Write all bytes
L
H
H
L
H
H
H
H
H
L
L
L
L
Sleep Mode
Interleaved Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs must remain inactive for the duration of
tZZREC after the ZZ input returns LOW. CEN needs to active
before going into the ZZ mode and before you want to come
back out of the ZZ mode.
(MODE = V or NC)
CC
First
Address (ex-
ternal)
Second
Address
(internal)
Third
Fourth
Address
Address
(internal)
(internal)[5]
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Linear Burst Address Table
(MODE = V
)
SS
First
Address (ex-
ternal)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)[5]
A...A00
A...A01
A...A10
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
A...A11
Notes:
2. L means logic LOW. H means logic HIGH. X means “Don’t Care.”
3. Multiple bytes may be selected during the same cycle.
4. BWc and BWd apply to 256K × 36 device only.
5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
Document #: 38-05265 Rev. **
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CY7C1357A
CY7C1355A
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
10
Unit
mA
ns
IDDZZ
tZZS
Sleep mode standby current ZZ > VDD – 0.2V
Device operation to ZZ
ZZ recovery time
ZZ > VDD – 0.2V
2tCYC
tZZREC
ZZ < 0.2V
2tCYC
ns
Truth Table[9, 10, 11, 12, 13, 14, 15, 16, 17]
Previous Address
DQ
CEN BWx OE (1 cycle later)
Operation
Deselect Cycle
Continue Deselect/NOP[18]
Cycle
Used
WEN ADV/LD
CE
H
X
L
X
Deselect
X
X
X
X
H
X
H
X
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
X
L
X
X
X
X
H
H
X
X
X
X
X
High-Z
High-Z
Q
X
Read Cycle (Begin Burst)
External
Next
Read Cycle (Continue Burst)[18]
Dummy Read (Begin Burst)[19]
Dummy Read (Continue Burst)[18, 19]
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)[18]
Abort Write (Begin Burst)[19]
Abort Write (Continue Burst)[18, 19]
Ignore Clock Edge/NOP[20]
Read
X
H
L
X
L
Q
External
Next
High-Z
High-Z
D
Read
X
H
L
X
L
External
Next
Write
X
X
L
H
L
X
L
L
D
External
Next
H
H
X
High-Z
High-Z
-
Write
X
X
X
H
H
X
X
X
Disabling the JTAG Feature
IEEE 1149.1 Serial Boundary Scan (JTAG)
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
Test Access Port
TCK–Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Notes:
6. This assumes that CEN, CE, CE2, and CE2 are all True.
7. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
8. DQc and DQd apply to 256Kx36 device only.
9. L means logic LOW. H means logic HIGH. X means “Don’t Care.” High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] equals LOW. BWx
= H means [BWa*BWb*BWc*BWd] equals HIGH. BWc and BWd apply to 256K × 36 device only.
10. CE = H means CE and CE2 are LOW along with CE2 being HIGH. CE = L means CE or CE2 is HIGH or CE2 is LOW. CE = X means CE, CE2, and CE2 are
“Don’t Care.”
11. BWa enables WRITE to byte “a” (DQa pins). BWb enables WRITE to byte “b” (DQb pins). BWc enables WRITE to byte “c” (DQc pins). BWd enables WRITE to
byte “d” (DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only.
12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW.
13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The Sleep Mode can only be entered one cycle after the
WRITE cycle, otherwise the WRITE cycle may not be completed.
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
burst cycle.
18. Continue Burst cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the WEN control
signal at the BEGIN BURST cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first.
19. Dummy Read and Abort WRITE cycles can be entered to set up subsequent READ or WRITE cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is
WRITE or Deselect cycle.
Document #: 38-05265 Rev. **
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CY7C1357A
CY7C1355A
TMS–Test Mode Select (INPUT)
Bypass Register
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
TDI–Test Data In (INPUT)
Boundary Scan Register
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer toFigure 1). It is allowable to leave this pin
unconnected if it is not used in an application. The pin is pulled
up internally, resulting in a logic HIGH level. TDI is connected
to the most significant bit (MSB) of any register. (See
Figure 2.)
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
TDO–Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO. TDO is
connected to the least significant bit (LSB) of any register.
(See Figure 2.)
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name and the third column is the
bump number. The third column is the TQFP pin number and
the fourth column is the BGA bump number.
Performing a TAP Reset
Identification (ID) Register
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
performed for the TAP controller by forcing TMS HIGH (VCC
)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TAP Controller Instruction Set
Test Access Port Registers
Overview
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
Document #: 38-05265 Rev. **
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CY7C1357A
CY7C1355A
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP Clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
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CY7C1357A
CY7C1355A
TEST-LOGIC
RESET
1[21]
0
1
1
1
REUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 1. TAP Controller State Diagram
Note:
21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05265 Rev. **
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CY7C1357A
CY7C1355A
ZZ
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register [22]
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
2.0
Max.
VCC + 0.3
0.8
Unit
V
VIH
VIl
Input High (Logic 1) Voltage[23, 24]
Input Low (Logic 0) Voltage[23, 24]
Input Leakage Current
–0.3
–5.0
–30
–5.0
V
ILI
0V < VIN < VCC
5.0
µA
µA
µA
ILI
TMS and TDI Input Leakage Current 0V < VIN < VCC
30
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
5.0
VOLC
VOHC
VOLT
LVCMOS Output Low Voltage[23, 25] IOLC = 100 µA
LVCMOS Output High Voltage[23, 25] IOHC = 100 µA
0.2
0.4
V
V
V
V
VCC – 0.2
LVTTL Output Low Voltage[23]
IOLT = 8.0 mA
IOHT = 8.0 mA
VOHT
LVTTL Output High Voltage[23]
2.4
Notes:
22.X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
23. All Voltage referenced to VSS (GND).
24. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as WEN, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
25. This parameter is sampled.
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CY7C1357A
CY7C1355A
TAP AC Switching Characteristics Over the Operating Range[26, 27]
Parameter
Clock
Description
Min.
Max.
Unit
tTHTH
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
fTF
50
tTHTL
8
8
tTLTH
ns
Output Times
tTLQX
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
tTLQV
10
tDVTH
5
5
tTHDX
Set-up Times
tMVTH
TMS Set-up
TDI Set-up
5
5
5
ns
ns
ns
tTDIS
tCS
Capture Set-up
Hold Times
tTHMX
TMS Hold
TDI Hold
5
5
5
ns
ns
ns
tTDIH
tCH
Capture Hold
Notes:
26.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
27. Test conditions are specified using the load in TAP AC test conditions.
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CY7C1357A
CY7C1355A
TAP Timing and Test Conditions
Vt = 1.5V
50Ω
ALL INPUT PULSES
1.5V
TDO
3.0V
Z = 50Ω
0
C = 20 pF
L
V
SS
1.5 ns
1.5 ns
(a)
(b)
GND
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
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CY7C1357A
CY7C1355A
Identification Register Definitions
Instruction Field
Revision Number
256K × 36
512K × 18
Description
Reserved for revision number.
XXXX
XXXX
(31:28)
Device Depth
(27:23)
00110
00111
00011
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Reserved for future use.
Device Width
(22:18)
00100
Reserved
(17:12)
XXXXXX
XXXXXX
Cypress JEDEC ID CODE (11:1)
ID Register Presence Indicator (0)
00011100100
1
00011100100 Allows unique identification of DEVICE vendor.
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size (x36)
Bit Size (x18)
3
1
3
1
ID
32
70
32
51
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
010
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
100
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
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CY7C1357A
CY7C1355A
Boundary Scan Order (256K × 36) (continued)
Boundary Scan Order (256K × 36)
Bit#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
CE3
BWa
BWb
BWc
BWd
CE2
CE1
A
TQFP
92
93
94
95
96
97
98
99
100
1
Bump ID
6B
5L
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
Bump ID
2R
3T
2
A
5G
3G
3L
3
A
4T
4
A
5T
5
A
6R
3B
5B
6P
7N
6M
7L
2B
4E
3A
2A
2D
1E
2F
6
A
7
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2
3
6K
7P
6N
6L
6
1G
2H
1D
2E
2G
1H
5R
2K
1L
7
8
9
7K
7T
12
13
14
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
37
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
A
NC
A
ADV/LD
OE
A
A
CEN
WEN
CLK
4M
4H
4K
A1
A0
Document #: 38-05265 Rev. **
Page 17 of 31
CY7C1357A
CY7C1355A
Boundary Scan Order (512K x 18) (continued)
Boundary Scan Order (512K x 18)
Bit#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal Name
CLK
CE3
BWa
BWb
CE2
CE1
A
TQFP
89
92
93
94
97
98
99
100
8
Bump ID
4K
Bit#
1
Signal Name
TQFP
44
45
46
47
48
49
50
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
87
88
Bump ID
2R
2T
A
A
6B
2
5L
3
A
3T
3G
2B
4
A
5T
5
A
6R
3B
5B
7P
6N
6L
4E
6
A
3A
7
A
A
2A
8
DQa
DQa
DQa
DQa
ZZ
DQb
DQb
DQb
DQb
NC
1D
2E
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
2G
1H
5R
2K
7K
7T
DQa
DQa
DQa
DQa
DQa
A
6H
7G
6F
DQb
DQb
DQb
DQb
DQb
MODE
A
1L
2M
1N
2P
7E
6D
6T
3R
2C
3C
5C
6C
4N
4P
A
6A
5A
4G
4A
4B
4F
A
A
A
A
NC
ADV/LD
OE
CEN
WEN
A
A1
A0
4M
4H
Document #: 38-05265 Rev. **
Page 18 of 31
CY7C1357A
CY7C1355A
Short Circuit Output Current ....................................... 50 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
Operating Range
VIN ...........................................................–0.5V to VCC+0.5V
Range
Com’l
Ambient Temperature
0°C to +70°C
VCC
VCCQ
Storage Temperature (plastic) ...................... –55°C to +125°
Junction Temperature ..................................................+125°
Power Dissipation .........................................................2.0W
3.3V ±5% 2.5–5 to
3.3+5%
Ind temp
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
VIHD
Description
Input High (Logic 1) Voltage[23, 29]
Test Conditions
Min.
Max.
Unit
V
All other inputs
3.3V I/O
2.0
2.0
VCC + 0.3
VIH
V
2.5V I/O
1.7
V
Input Low (Logic 0) Voltage[23, 29]
Input Leakage Current
VIL
3.3V I/O
–0.3
–0.3
0.8
0.7
5
V
2.5V I/O
V
ILI
0V < VIN < VCC
MODE and ZZ Input Leakage Current[30] 0V < VIN < VCC
µA
µA
µA
V
ILI
–
30
5
ILO
VOH
Output Leakage Current
Output High Voltage[23]
Output(s) disabled, 0V < VOUT < VCC
–
IOH = –5.0 mA for 3.3V I/O
IOH = –1.0 mA for 2.5V I/O
IOL = 8.0 mA for 3.3V I/O
IOL = 1.0 mA for 2.5V I/O
2.4
2.0
V
VOL
Output Low Voltage[23]
0.4
0.4
V
V
VCC
Supply Voltage[23]
I/O Supply Voltage[23]
3.135
3.135
2.375
3.465
3.465
2.9
V
VCCQ
3.3V I/O
2.5V I/O
V
V
Max.
100
133
117
100
MHz/ MHz/ MHz/ MHz/
Parameter
Description
Conditions
Typ.
-6.5
-7
-7.5
-8
Unit
ICC
VCC Operating
Device selected; all inputs < VILor > VIH; 150
cycle time > tKC min.; VCC = Max.;
outputs open, ADV/LD = X, f = fMAX
480
450
410
380
mA
Supply[31, 32, 33, 34]
2
ISB1
Automatic CE
Power-down
Device deselected;
40
250
10
235
10
220
10
210
10
mA
mA
all inputs < VIL or > VIH; VCC = max.;
Current—TTL Inputs[32, CLK cycle time > tKC min.
33, 34]
ISB2
Automatic CE
Power-down
Device deselected; VCC = max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
5
Current—CMOS
Inputs[32, 33, 34]
ISB3
Automatic CE
Max. VDD, Device Deselected, or VIN
<
40
15
190
30
180
30
170
30
170
30
mA
mA
Power-down Current— 0.3V or VIN > VDDQ – 0.3V f= f MAX = 1/t
CMOS Inputs
CYC
ISB4
Automatic CS
Power-down
Device deselected; all inputs < VIL
or > VIH; all inputs static;
Current—TTL Inputs[32, VCC = max.; CLK frequency = 0
33, 34]
Document #: 38-05265 Rev. **
Page 19 of 31
CY7C1357A
CY7C1355A
Capacitance[25]
Parameter
Description
Input Capacitance
Input/Output Capacitance DQ
Test Conditions
Typ.
4
Max.
Unit
pF
CI
TA = 25°C, f = 1 MHz,
VCC = 3.3V
4
CI/O
7
6.5
pF
Thermal Resistance
Parameter
Description
Test Conditions
TQFP Typ.
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 ×1.125 inch, four-layer PCB
25
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
9
°C/W
AC Test Loads and Waveforms
R = 317Ω
V
CCQ
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
V
CCQ
90%
10%
Z =50Ω
0
R = 50Ω
10%
L
5 pF
GND
R = 351Ω
≤ 1 V/ns
≤ 1 V/ns
= 1.5V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Switching Characteristics Over the Operating Range[35]
-6.5
133-MHz
-7
117 MHz
-7.5
100 MHz
-8
100 MHz
Parameter
Clock
Description
Clock Cycle Time
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tKC
7.5
2.5
2.5
8.5
3.0
3.0
10
3.5
3.5
10
3.5
3.5
ns
ns
ns
tKH
Clock HIGH Time
Clock LOW Time
tKL
Output Times
tKQ
Clock to Output Valid
6.5
7.0
7.5
8.0
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
2.0
3.0
2
2.0
3.0
2
2.0
3.0
2
2.0
3.0
2
tKQLZ
tKQHZ
tOEQ
Clock to Output in Low-Z[25, 36, 37]
Clock to Output in High-Z[25, 36, 37]
OE to Output Valid
3.5
3.5
3.5
3.5
3.5
4.0
3.5
4.0
tOELZ
tOEHZ
Set-up Times
tS
OE to Output in Low-Z[25, 36, 37]
OE to Output in High-Z[25, 36, 37]
0
0
0
0
3.5
3.5
3.5
3.5
Address and Controls[38]
Data In[38]
1.5
1.5
1.5
1.5
1.8
1.8
2.0
2.0
ns
ns
tSD
Notes:
28.
TA is the case temperature.
29. Overshoot: VIH < +6.0V for t < tKC /2
Undershoot:VIL < -2.0V for t < tKC /2.
30. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±50 µA.
31. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
32. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
33. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
34. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f = 0 means no input lines are changing.
35. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
36. Output loading is specified with CL=5 pF as in part (a) of AC Test Loads.
37. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
38. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined in the truth table.
Document #: 38-05265 Rev. **
Page 20 of 31
CY7C1357A
CY7C1355A
Switching Characteristics Over the Operating Range[35]
-6.5
133-MHz
-7
-7.5
100 MHz
-8
117 MHz
100 MHz
Parameter
Hold Times
tH
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address and Controls[38]
Data In[38]
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
tHD
Document #: 38-05265 Rev. **
Page 21 of 31
CY7C1357A
CY7C1355A
Switching Waveforms
Read Timing[39, 40, 41, 42, 43]
tKC
tKH
tKL
CLK
tS
tH
tH
tH
CEN
tS
WEN
tS
A
A1
A2
BWx
tS
tH
CE
tS
tH
ADV/LD
OE
(Burst Wraps around
to initial state)
tKQHZ
(CKE# HIGH, eliminates
current L-H clock edge)
tKQ
tKQX
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
DQx
Deselec
Read
Read
BURST READ
t
Notes:
39. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next
output data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined
by the state of the MODE input.
40. CE2 timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE2 is LOW. CE2 timing transitions are identical but
inverted to the CE signal. For example, when CE is LOW on this waveform, CE2 is HIGH.
41. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
42. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN
signal when new address and control are loaded into the SRAM.
43. BWc and BWd apply to 256K × 36 device only.
Document #: 38-05265 Rev. **
Page 22 of 31
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
Write Timing[40, 41, 42, 43, 44, 45]
tKC
tKH
tKL
CLK
tS
tH
CEN
tS
tH
WEN
tS
tH
tH
tH
tH
A1
A2
A
tS
tS
tS
BW(A1)
BW(A2)
BW(A2+1)
BW(A2+2)
BW(A2+3)
BW(A2)
BWx
CE
ADV/LD
OE
(CKE# HIGH, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
tHD
tSD
D(A1)
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A2)
DQx
Write
Write
Burst Write
Deselect
Notes:
44. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2+1) represents the next input data
in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the
state of the MODE input.
45. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when WEN signal is sampled LOW when ADV/LD
is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
Document #: 38-05265 Rev. **
Page 23 of 31
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
Read/Write Timing[40, 43, 45, 46]
tKC
tKH
tKL
CLK
tS
tH
CKE#
R/W#
tS
tH
tH
tH
tH
tH
tS
ADDRESS
A
A
A
A
A
A
A
7
A8
A9
1
2
3
4
5
6
tS
BW(A)
BW(A)
BW(A)
BWa#, BWb#
BWc#, BWd#
2
4
5
tS
CE#
ADV/LD#
tS
OE#
tKQ
tKQHZ
tKQLZ
tKQX
Q(A)
Q(A)
Q(A)
Q(A)
7
DATA Out (Q)
DATA In (D)
1
3
6
Read
Read
Read
D(A)
D(A)
D(A)
2
4
8
Write
Write
Write
Note:
46. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2.
Document #: 38-05265 Rev. **
Page 24 of 31
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
CEN Timing[40, 43, 45, 46, 47]
tKC
tKH
tKL
CLK
tS
tS
tS
tS
tS
tS
tH
CEN
tH
WEN
tH
tH
tH
tH
A
A
A
A
A
4
A5
1
2
3
BWx
C#
CE
ADV/LD
OE
tKQ
tKQHZ
Q(A)
Q(A)
Q(A)
DATA Out (Q)
DATA In (D)
Note:
1
3
4
tSD tHD
tKQLZ
tKQX
D(A)
2
47. CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the
L-H clock transition did not occur. All internal register in the SRAM will retain their previous state.
Document #: 38-05265 Rev. **
Page 25 of 31
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
CE Timing[40, 43, 45, 48, 49]
tKC
tKH
tKL
CLK
tS
tH
CEN
tS
tH
WEN
tS
tH
A
A
A
A
A
4
A5
1
2
3
tS
tH
BWx
tS
tH
CE#
CE
tS
tH
ADV/LD
tOEQ
OE
tKQHZ
tOEHZ
tOELZ
Q(A)
Q(A)
Q(A)
4
DATA Out (Q)
1
2
tSD tHD
D(A)
tKQLZ
tKQ
tKQX
DATA In (D)
3
Notes:
48. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc.
49. When either one of the Chip enables (CE, CE2 or CE2) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z
one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
Document #: 38-05265 Rev. **
Page 26 of 31
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
ZZ Mode Timing [ 50, 51]
CLK
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Note:
50. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
51. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05265 Rev. **
Page 27 of 31
CY7C1357A
CY7C1355A
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
133
CY7C1355A-133AC
GVT71256ZB36-6.5
A101
BG119
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
119-lead BGA (14 × 22 × 2.4 mm) Commercial
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
CY7C1355A-133BGC
GVT71256ZB36B-6.5
117
CY7C1355A-117AC
GVT71256ZB36-7
CY7C1355A-117AI
GVT71256ZB36-7I
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
CY7C1355A-117BGC
GVT71256ZB36B-7
BG119
BG119
A101
CY7C1355A-117BGI
GVT71256ZB36B-7I
119-lead BGA (14 × 22 × 2.4 mm)
100
CY7C1355A-100AC
GVT71256ZB36-7.5
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
CY7C1355A-100AI
GVT71256ZB36-7.5I
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
CY7C1355A-100BGC
GVT71256ZB36B-7.5
BG119
BG119
CY7C1355A-100BGI
GVT71256ZB36B-7.5I
119-lead BGA (14 × 22 × 2.4 mm)
CY7C1355A1-100AC
CY7C1355A1-100AI
CY7C1355A1-100BGC
CY7C1355A1-100BGI
A101
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
BG119
BG119
A101
119-lead BGA (14 × 22 × 2.4 mm)
133
117
CY7C1357A-133AC
GVT71512ZB36-6.5
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
119-lead BGA (14 × 22 × 2.4 mm) Commercial
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
CY7C1357A-133BGC
GVT71512ZB36B-6.5
BG119
A101
CY7C1357A-117AC
GVT71512ZB36-7
CY7C1357A-117AI
GVT71512ZB36-7I
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
CY7C1357A-117BGC
GVT71512ZB36B-7
BG119
BG119
A101
CY7C1357A-117BGI
GVT71512ZB36B-7I
119-lead BGA (14 × 22 × 2.4 mm)
100
CY7C1357A-100AC
GVT71512ZB36-7.5
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
CY7C1357A-100AI
GVT71512ZB36-7.5I
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
CY7C1357A-100BGC
GVT71512ZB36B-7.5
BG119
BG119
CY7C1357A-100BGI
GVT71512ZB36B-7.5I
119-lead BGA (14 × 22 × 2.4 mm)
CY7C1357A1-100AC
CY7C1357A1-100AI
CY7C1357A1-100BGC
CY7C1357A1-100BGI
A101
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
119-lead BGA (14 × 22 × 2.4 mm)
Industrial
Commercial
Industrial
BG119
BG119
119-lead BGA (14 × 22 × 2.4 mm)
Document #: 38-05265 Rev. **
Page 28 of 31
CY7C1357A
CY7C1355A
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Document #: 38-05265 Rev. **
Page 29 of 31
CY7C1357A
CY7C1355A
Package Diagrams (continued)
119-lead BGA (14 × 22 × 2.4) BG119
51-85115-*A
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-05265 Rev. **
Page 30 of 31
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1357A
CY7C1355A
DocumentTitle:CY7C1355A/CY7C1357A256Kx36/512Kx18SynchronousFlow-ThruSRAMwithNoBL™Architecture
Document Number: 38-05265
Orig. of
Issue Date Change
REV
ECN
Description of Change
**
114118
7/16/02
KKV
New Data Sheet
Document #: 38-05265 Rev. **
Page 31 of 31
相关型号：
GVT71256ZB36B-7.5I
ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CYPRESS
GVT71256ZB36B-7I
ZBT SRAM, 256KX36, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CYPRESS
GVT71256ZC36-10
ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256ZC36-5
ZBT SRAM, 256KX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256ZC36B-5
ZBT SRAM, 256KX36, 3.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
GVT71256ZC36B-6
ZBT SRAM, 256KX36, 3.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
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